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1/*
2 * Copyright 2022 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include "../dmub_srv.h"
27#include "dmub_reg.h"
28#include "dmub_dcn32.h"
29
30#include "dcn/dcn_3_2_0_offset.h"
31#include "dcn/dcn_3_2_0_sh_mask.h"
32
33#define DCN_BASE__INST0_SEG2 0x000034C0
34
35#define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg
36#define CTX dmub
37#define REGS dmub->regs_dcn32
38#define REG_OFFSET_EXP(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)
39
40const struct dmub_srv_dcn32_regs dmub_srv_dcn32_regs = {
41#define DMUB_SR(reg) REG_OFFSET_EXP(reg),
42 {
43 DMUB_DCN32_REGS()
44 DMCUB_INTERNAL_REGS()
45 },
46#undef DMUB_SR
47
48#define DMUB_SF(reg, field) FD_MASK(reg, field),
49 { DMUB_DCN32_FIELDS() },
50#undef DMUB_SF
51
52#define DMUB_SF(reg, field) FD_SHIFT(reg, field),
53 { DMUB_DCN32_FIELDS() },
54#undef DMUB_SF
55};
56
57static void dmub_dcn32_get_fb_base_offset(struct dmub_srv *dmub,
58 uint64_t *fb_base,
59 uint64_t *fb_offset)
60{
61 uint32_t tmp;
62
63 if (dmub->fb_base || dmub->fb_offset) {
64 *fb_base = dmub->fb_base;
65 *fb_offset = dmub->fb_offset;
66 return;
67 }
68
69 REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp);
70 *fb_base = (uint64_t)tmp << 24;
71
72 REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp);
73 *fb_offset = (uint64_t)tmp << 24;
74}
75
76static inline void dmub_dcn32_translate_addr(const union dmub_addr *addr_in,
77 uint64_t fb_base,
78 uint64_t fb_offset,
79 union dmub_addr *addr_out)
80{
81 addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset;
82}
83
84void dmub_dcn32_reset(struct dmub_srv *dmub)
85{
86 union dmub_gpint_data_register cmd;
87 const uint32_t timeout = 30;
88 uint32_t in_reset, scratch, i;
89
90 REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &in_reset);
91
92 if (in_reset == 0) {
93 cmd.bits.status = 1;
94 cmd.bits.command_code = DMUB_GPINT__STOP_FW;
95 cmd.bits.param = 0;
96
97 dmub->hw_funcs.set_gpint(dmub, cmd);
98
99 /**
100 * Timeout covers both the ACK and the wait
101 * for remaining work to finish.
102 *
103 * This is mostly bound by the PHY disable sequence.
104 * Each register check will be greater than 1us, so
105 * don't bother using udelay.
106 */
107
108 for (i = 0; i < timeout; ++i) {
109 if (dmub->hw_funcs.is_gpint_acked(dmub, cmd))
110 break;
111 }
112
113 for (i = 0; i < timeout; ++i) {
114 scratch = dmub->hw_funcs.get_gpint_response(dmub);
115 if (scratch == DMUB_GPINT__STOP_FW_RESPONSE)
116 break;
117 }
118
119 /* Clear the GPINT command manually so we don't reset again. */
120 cmd.all = 0;
121 dmub->hw_funcs.set_gpint(dmub, cmd);
122
123 /* Force reset in case we timed out, DMCUB is likely hung. */
124 }
125
126 REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 1);
127 REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0);
128 REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 1);
129 REG_WRITE(DMCUB_INBOX1_RPTR, 0);
130 REG_WRITE(DMCUB_INBOX1_WPTR, 0);
131 REG_WRITE(DMCUB_OUTBOX1_RPTR, 0);
132 REG_WRITE(DMCUB_OUTBOX1_WPTR, 0);
133 REG_WRITE(DMCUB_SCRATCH0, 0);
134}
135
136void dmub_dcn32_reset_release(struct dmub_srv *dmub)
137{
138 REG_WRITE(DMCUB_GPINT_DATAIN1, 0);
139 REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 0);
140 REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF);
141 REG_UPDATE_2(DMCUB_CNTL, DMCUB_ENABLE, 1, DMCUB_TRACEPORT_EN, 1);
142 REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 0);
143}
144
145void dmub_dcn32_backdoor_load(struct dmub_srv *dmub,
146 const struct dmub_window *cw0,
147 const struct dmub_window *cw1)
148{
149 union dmub_addr offset;
150 uint64_t fb_base, fb_offset;
151
152 dmub_dcn32_get_fb_base_offset(dmub, &fb_base, &fb_offset);
153
154 REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);
155
156 dmub_dcn32_translate_addr(&cw0->offset, fb_base, fb_offset, &offset);
157
158 REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
159 REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
160 REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
161 REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,
162 DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top,
163 DMCUB_REGION3_CW0_ENABLE, 1);
164
165 dmub_dcn32_translate_addr(&cw1->offset, fb_base, fb_offset, &offset);
166
167 REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
168 REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
169 REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
170 REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,
171 DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top,
172 DMCUB_REGION3_CW1_ENABLE, 1);
173
174 REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID,
175 0x20);
176}
177
178void dmub_dcn32_backdoor_load_zfb_mode(struct dmub_srv *dmub,
179 const struct dmub_window *cw0,
180 const struct dmub_window *cw1)
181{
182 union dmub_addr offset;
183
184 REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);
185
186 offset = cw0->offset;
187
188 REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
189 REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
190 REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
191 REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0,
192 DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top,
193 DMCUB_REGION3_CW0_ENABLE, 1);
194
195 offset = cw1->offset;
196
197 REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
198 REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
199 REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
200 REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0,
201 DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top,
202 DMCUB_REGION3_CW1_ENABLE, 1);
203
204 REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID,
205 0x20);
206}
207
208void dmub_dcn32_setup_windows(struct dmub_srv *dmub,
209 const struct dmub_window *cw2,
210 const struct dmub_window *cw3,
211 const struct dmub_window *cw4,
212 const struct dmub_window *cw5,
213 const struct dmub_window *cw6)
214{
215 union dmub_addr offset;
216
217 offset = cw3->offset;
218
219 REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part);
220 REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part);
221 REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base);
222 REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0,
223 DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top,
224 DMCUB_REGION3_CW3_ENABLE, 1);
225
226 offset = cw4->offset;
227
228 REG_WRITE(DMCUB_REGION3_CW4_OFFSET, offset.u.low_part);
229 REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part);
230 REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base);
231 REG_SET_2(DMCUB_REGION3_CW4_TOP_ADDRESS, 0,
232 DMCUB_REGION3_CW4_TOP_ADDRESS, cw4->region.top,
233 DMCUB_REGION3_CW4_ENABLE, 1);
234
235 offset = cw5->offset;
236
237 REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part);
238 REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part);
239 REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base);
240 REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0,
241 DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top,
242 DMCUB_REGION3_CW5_ENABLE, 1);
243
244 REG_WRITE(DMCUB_REGION5_OFFSET, offset.u.low_part);
245 REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part);
246 REG_SET_2(DMCUB_REGION5_TOP_ADDRESS, 0,
247 DMCUB_REGION5_TOP_ADDRESS,
248 cw5->region.top - cw5->region.base - 1,
249 DMCUB_REGION5_ENABLE, 1);
250
251 offset = cw6->offset;
252
253 REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part);
254 REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part);
255 REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base);
256 REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0,
257 DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top,
258 DMCUB_REGION3_CW6_ENABLE, 1);
259}
260
261void dmub_dcn32_setup_mailbox(struct dmub_srv *dmub,
262 const struct dmub_region *inbox1)
263{
264 REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, inbox1->base);
265 REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base);
266}
267
268uint32_t dmub_dcn32_get_inbox1_rptr(struct dmub_srv *dmub)
269{
270 return REG_READ(DMCUB_INBOX1_RPTR);
271}
272
273void dmub_dcn32_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset)
274{
275 REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset);
276}
277
278void dmub_dcn32_setup_out_mailbox(struct dmub_srv *dmub,
279 const struct dmub_region *outbox1)
280{
281 REG_WRITE(DMCUB_OUTBOX1_BASE_ADDRESS, outbox1->base);
282 REG_WRITE(DMCUB_OUTBOX1_SIZE, outbox1->top - outbox1->base);
283}
284
285uint32_t dmub_dcn32_get_outbox1_wptr(struct dmub_srv *dmub)
286{
287 /**
288 * outbox1 wptr register is accessed without locks (dal & dc)
289 * and to be called only by dmub_srv_stat_get_notification()
290 */
291 return REG_READ(DMCUB_OUTBOX1_WPTR);
292}
293
294void dmub_dcn32_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)
295{
296 /**
297 * outbox1 rptr register is accessed without locks (dal & dc)
298 * and to be called only by dmub_srv_stat_get_notification()
299 */
300 REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset);
301}
302
303bool dmub_dcn32_is_hw_init(struct dmub_srv *dmub)
304{
305 union dmub_fw_boot_status status;
306 uint32_t is_hw_init;
307
308 status.all = REG_READ(DMCUB_SCRATCH0);
309 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_hw_init);
310
311 return is_hw_init != 0 && status.bits.dal_fw;
312}
313
314bool dmub_dcn32_is_supported(struct dmub_srv *dmub)
315{
316 uint32_t supported = 0;
317
318 REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported);
319
320 return supported;
321}
322
323void dmub_dcn32_set_gpint(struct dmub_srv *dmub,
324 union dmub_gpint_data_register reg)
325{
326 REG_WRITE(DMCUB_GPINT_DATAIN1, reg.all);
327}
328
329bool dmub_dcn32_is_gpint_acked(struct dmub_srv *dmub,
330 union dmub_gpint_data_register reg)
331{
332 union dmub_gpint_data_register test;
333
334 reg.bits.status = 0;
335 test.all = REG_READ(DMCUB_GPINT_DATAIN1);
336
337 return test.all == reg.all;
338}
339
340uint32_t dmub_dcn32_get_gpint_response(struct dmub_srv *dmub)
341{
342 return REG_READ(DMCUB_SCRATCH7);
343}
344
345uint32_t dmub_dcn32_get_gpint_dataout(struct dmub_srv *dmub)
346{
347 uint32_t dataout = REG_READ(DMCUB_GPINT_DATAOUT);
348
349 REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 0);
350
351 REG_WRITE(DMCUB_GPINT_DATAOUT, 0);
352 REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 1);
353 REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 0);
354
355 REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 1);
356
357 return dataout;
358}
359
360union dmub_fw_boot_status dmub_dcn32_get_fw_boot_status(struct dmub_srv *dmub)
361{
362 union dmub_fw_boot_status status;
363
364 status.all = REG_READ(DMCUB_SCRATCH0);
365 return status;
366}
367
368void dmub_dcn32_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params)
369{
370 union dmub_fw_boot_options boot_options = {0};
371
372 boot_options.bits.z10_disable = params->disable_z10;
373
374 REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
375}
376
377void dmub_dcn32_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip)
378{
379 union dmub_fw_boot_options boot_options;
380 boot_options.all = REG_READ(DMCUB_SCRATCH14);
381 boot_options.bits.skip_phy_init_panel_sequence = skip;
382 REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
383}
384
385void dmub_dcn32_setup_outbox0(struct dmub_srv *dmub,
386 const struct dmub_region *outbox0)
387{
388 REG_WRITE(DMCUB_OUTBOX0_BASE_ADDRESS, outbox0->base);
389
390 REG_WRITE(DMCUB_OUTBOX0_SIZE, outbox0->top - outbox0->base);
391}
392
393uint32_t dmub_dcn32_get_outbox0_wptr(struct dmub_srv *dmub)
394{
395 return REG_READ(DMCUB_OUTBOX0_WPTR);
396}
397
398void dmub_dcn32_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)
399{
400 REG_WRITE(DMCUB_OUTBOX0_RPTR, rptr_offset);
401}
402
403uint32_t dmub_dcn32_get_current_time(struct dmub_srv *dmub)
404{
405 return REG_READ(DMCUB_TIMER_CURRENT);
406}
407
408void dmub_dcn32_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data)
409{
410 uint32_t is_dmub_enabled, is_soft_reset, is_sec_reset;
411 uint32_t is_traceport_enabled, is_cw0_enabled, is_cw6_enabled;
412
413 if (!dmub || !diag_data)
414 return;
415
416 memset(diag_data, 0, sizeof(*diag_data));
417
418 diag_data->dmcub_version = dmub->fw_version;
419
420 diag_data->scratch[0] = REG_READ(DMCUB_SCRATCH0);
421 diag_data->scratch[1] = REG_READ(DMCUB_SCRATCH1);
422 diag_data->scratch[2] = REG_READ(DMCUB_SCRATCH2);
423 diag_data->scratch[3] = REG_READ(DMCUB_SCRATCH3);
424 diag_data->scratch[4] = REG_READ(DMCUB_SCRATCH4);
425 diag_data->scratch[5] = REG_READ(DMCUB_SCRATCH5);
426 diag_data->scratch[6] = REG_READ(DMCUB_SCRATCH6);
427 diag_data->scratch[7] = REG_READ(DMCUB_SCRATCH7);
428 diag_data->scratch[8] = REG_READ(DMCUB_SCRATCH8);
429 diag_data->scratch[9] = REG_READ(DMCUB_SCRATCH9);
430 diag_data->scratch[10] = REG_READ(DMCUB_SCRATCH10);
431 diag_data->scratch[11] = REG_READ(DMCUB_SCRATCH11);
432 diag_data->scratch[12] = REG_READ(DMCUB_SCRATCH12);
433 diag_data->scratch[13] = REG_READ(DMCUB_SCRATCH13);
434 diag_data->scratch[14] = REG_READ(DMCUB_SCRATCH14);
435 diag_data->scratch[15] = REG_READ(DMCUB_SCRATCH15);
436
437 diag_data->undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR);
438 diag_data->inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR);
439 diag_data->data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR);
440
441 diag_data->inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR);
442 diag_data->inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR);
443 diag_data->inbox1_size = REG_READ(DMCUB_INBOX1_SIZE);
444
445 diag_data->inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR);
446 diag_data->inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR);
447 diag_data->inbox0_size = REG_READ(DMCUB_INBOX0_SIZE);
448
449 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled);
450 diag_data->is_dmcub_enabled = is_dmub_enabled;
451
452 REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &is_soft_reset);
453 diag_data->is_dmcub_soft_reset = is_soft_reset;
454
455 REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset);
456 diag_data->is_dmcub_secure_reset = is_sec_reset;
457
458 REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled);
459 diag_data->is_traceport_en = is_traceport_enabled;
460
461 REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &is_cw0_enabled);
462 diag_data->is_cw0_enabled = is_cw0_enabled;
463
464 REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &is_cw6_enabled);
465 diag_data->is_cw6_enabled = is_cw6_enabled;
466}
467void dmub_dcn32_configure_dmub_in_system_memory(struct dmub_srv *dmub)
468{
469 /* DMCUB_REGION3_TMR_AXI_SPACE values:
470 * 0b011 (0x3) - FB physical address
471 * 0b100 (0x4) - GPU virtual address
472 *
473 * Default value is 0x3 (FB Physical address for TMR). When programming
474 * DMUB to be in system memory, change to 0x4. The system memory allocated
475 * is accessible by both GPU and CPU, so we use GPU virtual address.
476 */
477 REG_WRITE(DMCUB_REGION3_TMR_AXI_SPACE, 0x4);
478}
479
480void dmub_dcn32_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data)
481{
482 REG_WRITE(DMCUB_INBOX0_WPTR, data.inbox0_cmd_common.all);
483}
484
485void dmub_dcn32_clear_inbox0_ack_register(struct dmub_srv *dmub)
486{
487 REG_WRITE(DMCUB_SCRATCH17, 0);
488}
489
490uint32_t dmub_dcn32_read_inbox0_ack_register(struct dmub_srv *dmub)
491{
492 return REG_READ(DMCUB_SCRATCH17);
493}