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1/*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#include <linux/firmware.h>
25#include <drm/drmP.h>
26#include "amdgpu.h"
27#include "amdgpu_ucode.h"
28#include "amdgpu_trace.h"
29#include "cikd.h"
30#include "cik.h"
31
32#include "bif/bif_4_1_d.h"
33#include "bif/bif_4_1_sh_mask.h"
34
35#include "gca/gfx_7_2_d.h"
36#include "gca/gfx_7_2_enum.h"
37#include "gca/gfx_7_2_sh_mask.h"
38
39#include "gmc/gmc_7_1_d.h"
40#include "gmc/gmc_7_1_sh_mask.h"
41
42#include "oss/oss_2_0_d.h"
43#include "oss/oss_2_0_sh_mask.h"
44
45static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
46{
47 SDMA0_REGISTER_OFFSET,
48 SDMA1_REGISTER_OFFSET
49};
50
51static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev);
52static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev);
53static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev);
54static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev);
55
56MODULE_FIRMWARE("radeon/bonaire_sdma.bin");
57MODULE_FIRMWARE("radeon/bonaire_sdma1.bin");
58MODULE_FIRMWARE("radeon/hawaii_sdma.bin");
59MODULE_FIRMWARE("radeon/hawaii_sdma1.bin");
60MODULE_FIRMWARE("radeon/kaveri_sdma.bin");
61MODULE_FIRMWARE("radeon/kaveri_sdma1.bin");
62MODULE_FIRMWARE("radeon/kabini_sdma.bin");
63MODULE_FIRMWARE("radeon/kabini_sdma1.bin");
64MODULE_FIRMWARE("radeon/mullins_sdma.bin");
65MODULE_FIRMWARE("radeon/mullins_sdma1.bin");
66
67u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev);
68
69/*
70 * sDMA - System DMA
71 * Starting with CIK, the GPU has new asynchronous
72 * DMA engines. These engines are used for compute
73 * and gfx. There are two DMA engines (SDMA0, SDMA1)
74 * and each one supports 1 ring buffer used for gfx
75 * and 2 queues used for compute.
76 *
77 * The programming model is very similar to the CP
78 * (ring buffer, IBs, etc.), but sDMA has it's own
79 * packet format that is different from the PM4 format
80 * used by the CP. sDMA supports copying data, writing
81 * embedded data, solid fills, and a number of other
82 * things. It also has support for tiling/detiling of
83 * buffers.
84 */
85
86/**
87 * cik_sdma_init_microcode - load ucode images from disk
88 *
89 * @adev: amdgpu_device pointer
90 *
91 * Use the firmware interface to load the ucode images into
92 * the driver (not loaded into hw).
93 * Returns 0 on success, error on failure.
94 */
95static int cik_sdma_init_microcode(struct amdgpu_device *adev)
96{
97 const char *chip_name;
98 char fw_name[30];
99 int err = 0, i;
100
101 DRM_DEBUG("\n");
102
103 switch (adev->asic_type) {
104 case CHIP_BONAIRE:
105 chip_name = "bonaire";
106 break;
107 case CHIP_HAWAII:
108 chip_name = "hawaii";
109 break;
110 case CHIP_KAVERI:
111 chip_name = "kaveri";
112 break;
113 case CHIP_KABINI:
114 chip_name = "kabini";
115 break;
116 case CHIP_MULLINS:
117 chip_name = "mullins";
118 break;
119 default: BUG();
120 }
121
122 for (i = 0; i < adev->sdma.num_instances; i++) {
123 if (i == 0)
124 snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma.bin", chip_name);
125 else
126 snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma1.bin", chip_name);
127 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
128 if (err)
129 goto out;
130 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
131 }
132out:
133 if (err) {
134 printk(KERN_ERR
135 "cik_sdma: Failed to load firmware \"%s\"\n",
136 fw_name);
137 for (i = 0; i < adev->sdma.num_instances; i++) {
138 release_firmware(adev->sdma.instance[i].fw);
139 adev->sdma.instance[i].fw = NULL;
140 }
141 }
142 return err;
143}
144
145/**
146 * cik_sdma_ring_get_rptr - get the current read pointer
147 *
148 * @ring: amdgpu ring pointer
149 *
150 * Get the current rptr from the hardware (CIK+).
151 */
152static uint32_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring)
153{
154 u32 rptr;
155
156 rptr = ring->adev->wb.wb[ring->rptr_offs];
157
158 return (rptr & 0x3fffc) >> 2;
159}
160
161/**
162 * cik_sdma_ring_get_wptr - get the current write pointer
163 *
164 * @ring: amdgpu ring pointer
165 *
166 * Get the current wptr from the hardware (CIK+).
167 */
168static uint32_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring)
169{
170 struct amdgpu_device *adev = ring->adev;
171 u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
172
173 return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) & 0x3fffc) >> 2;
174}
175
176/**
177 * cik_sdma_ring_set_wptr - commit the write pointer
178 *
179 * @ring: amdgpu ring pointer
180 *
181 * Write the wptr back to the hardware (CIK+).
182 */
183static void cik_sdma_ring_set_wptr(struct amdgpu_ring *ring)
184{
185 struct amdgpu_device *adev = ring->adev;
186 u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
187
188 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], (ring->wptr << 2) & 0x3fffc);
189}
190
191static void cik_sdma_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
192{
193 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
194 int i;
195
196 for (i = 0; i < count; i++)
197 if (sdma && sdma->burst_nop && (i == 0))
198 amdgpu_ring_write(ring, ring->nop |
199 SDMA_NOP_COUNT(count - 1));
200 else
201 amdgpu_ring_write(ring, ring->nop);
202}
203
204/**
205 * cik_sdma_ring_emit_ib - Schedule an IB on the DMA engine
206 *
207 * @ring: amdgpu ring pointer
208 * @ib: IB object to schedule
209 *
210 * Schedule an IB in the DMA ring (CIK).
211 */
212static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring,
213 struct amdgpu_ib *ib)
214{
215 u32 extra_bits = ib->vm_id & 0xf;
216 u32 next_rptr = ring->wptr + 5;
217
218 while ((next_rptr & 7) != 4)
219 next_rptr++;
220
221 next_rptr += 4;
222 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
223 amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
224 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
225 amdgpu_ring_write(ring, 1); /* number of DWs to follow */
226 amdgpu_ring_write(ring, next_rptr);
227
228 /* IB packet must end on a 8 DW boundary */
229 cik_sdma_ring_insert_nop(ring, (12 - (ring->wptr & 7)) % 8);
230
231 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits));
232 amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */
233 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff);
234 amdgpu_ring_write(ring, ib->length_dw);
235
236}
237
238/**
239 * cik_sdma_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
240 *
241 * @ring: amdgpu ring pointer
242 *
243 * Emit an hdp flush packet on the requested DMA ring.
244 */
245static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring *ring)
246{
247 u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) |
248 SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */
249 u32 ref_and_mask;
250
251 if (ring == &ring->adev->sdma.instance[0].ring)
252 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA0_MASK;
253 else
254 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA1_MASK;
255
256 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
257 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
258 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
259 amdgpu_ring_write(ring, ref_and_mask); /* reference */
260 amdgpu_ring_write(ring, ref_and_mask); /* mask */
261 amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
262}
263
264static void cik_sdma_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
265{
266 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
267 amdgpu_ring_write(ring, mmHDP_DEBUG0);
268 amdgpu_ring_write(ring, 1);
269}
270
271/**
272 * cik_sdma_ring_emit_fence - emit a fence on the DMA ring
273 *
274 * @ring: amdgpu ring pointer
275 * @fence: amdgpu fence object
276 *
277 * Add a DMA fence packet to the ring to write
278 * the fence seq number and DMA trap packet to generate
279 * an interrupt if needed (CIK).
280 */
281static void cik_sdma_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
282 unsigned flags)
283{
284 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
285 /* write the fence */
286 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
287 amdgpu_ring_write(ring, lower_32_bits(addr));
288 amdgpu_ring_write(ring, upper_32_bits(addr));
289 amdgpu_ring_write(ring, lower_32_bits(seq));
290
291 /* optionally write high bits as well */
292 if (write64bit) {
293 addr += 4;
294 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
295 amdgpu_ring_write(ring, lower_32_bits(addr));
296 amdgpu_ring_write(ring, upper_32_bits(addr));
297 amdgpu_ring_write(ring, upper_32_bits(seq));
298 }
299
300 /* generate an interrupt */
301 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0));
302}
303
304/**
305 * cik_sdma_gfx_stop - stop the gfx async dma engines
306 *
307 * @adev: amdgpu_device pointer
308 *
309 * Stop the gfx async dma ring buffers (CIK).
310 */
311static void cik_sdma_gfx_stop(struct amdgpu_device *adev)
312{
313 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
314 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
315 u32 rb_cntl;
316 int i;
317
318 if ((adev->mman.buffer_funcs_ring == sdma0) ||
319 (adev->mman.buffer_funcs_ring == sdma1))
320 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
321
322 for (i = 0; i < adev->sdma.num_instances; i++) {
323 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
324 rb_cntl &= ~SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK;
325 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
326 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0);
327 }
328 sdma0->ready = false;
329 sdma1->ready = false;
330}
331
332/**
333 * cik_sdma_rlc_stop - stop the compute async dma engines
334 *
335 * @adev: amdgpu_device pointer
336 *
337 * Stop the compute async dma queues (CIK).
338 */
339static void cik_sdma_rlc_stop(struct amdgpu_device *adev)
340{
341 /* XXX todo */
342}
343
344/**
345 * cik_sdma_enable - stop the async dma engines
346 *
347 * @adev: amdgpu_device pointer
348 * @enable: enable/disable the DMA MEs.
349 *
350 * Halt or unhalt the async dma engines (CIK).
351 */
352static void cik_sdma_enable(struct amdgpu_device *adev, bool enable)
353{
354 u32 me_cntl;
355 int i;
356
357 if (enable == false) {
358 cik_sdma_gfx_stop(adev);
359 cik_sdma_rlc_stop(adev);
360 }
361
362 for (i = 0; i < adev->sdma.num_instances; i++) {
363 me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
364 if (enable)
365 me_cntl &= ~SDMA0_F32_CNTL__HALT_MASK;
366 else
367 me_cntl |= SDMA0_F32_CNTL__HALT_MASK;
368 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], me_cntl);
369 }
370}
371
372/**
373 * cik_sdma_gfx_resume - setup and start the async dma engines
374 *
375 * @adev: amdgpu_device pointer
376 *
377 * Set up the gfx DMA ring buffers and enable them (CIK).
378 * Returns 0 for success, error for failure.
379 */
380static int cik_sdma_gfx_resume(struct amdgpu_device *adev)
381{
382 struct amdgpu_ring *ring;
383 u32 rb_cntl, ib_cntl;
384 u32 rb_bufsz;
385 u32 wb_offset;
386 int i, j, r;
387
388 for (i = 0; i < adev->sdma.num_instances; i++) {
389 ring = &adev->sdma.instance[i].ring;
390 wb_offset = (ring->rptr_offs * 4);
391
392 mutex_lock(&adev->srbm_mutex);
393 for (j = 0; j < 16; j++) {
394 cik_srbm_select(adev, 0, 0, 0, j);
395 /* SDMA GFX */
396 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
397 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
398 /* XXX SDMA RLC - todo */
399 }
400 cik_srbm_select(adev, 0, 0, 0, 0);
401 mutex_unlock(&adev->srbm_mutex);
402
403 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
404 adev->gfx.config.gb_addr_config & 0x70);
405
406 WREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0);
407 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
408
409 /* Set ring buffer size in dwords */
410 rb_bufsz = order_base_2(ring->ring_size / 4);
411 rb_cntl = rb_bufsz << 1;
412#ifdef __BIG_ENDIAN
413 rb_cntl |= SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK |
414 SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK;
415#endif
416 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
417
418 /* Initialize the ring buffer's read and write pointers */
419 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
420 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
421
422 /* set the wb address whether it's enabled or not */
423 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
424 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
425 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
426 ((adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC));
427
428 rb_cntl |= SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK;
429
430 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
431 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
432
433 ring->wptr = 0;
434 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
435
436 /* enable DMA RB */
437 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i],
438 rb_cntl | SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK);
439
440 ib_cntl = SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK;
441#ifdef __BIG_ENDIAN
442 ib_cntl |= SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK;
443#endif
444 /* enable DMA IBs */
445 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
446
447 ring->ready = true;
448
449 r = amdgpu_ring_test_ring(ring);
450 if (r) {
451 ring->ready = false;
452 return r;
453 }
454
455 if (adev->mman.buffer_funcs_ring == ring)
456 amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
457 }
458
459 return 0;
460}
461
462/**
463 * cik_sdma_rlc_resume - setup and start the async dma engines
464 *
465 * @adev: amdgpu_device pointer
466 *
467 * Set up the compute DMA queues and enable them (CIK).
468 * Returns 0 for success, error for failure.
469 */
470static int cik_sdma_rlc_resume(struct amdgpu_device *adev)
471{
472 /* XXX todo */
473 return 0;
474}
475
476/**
477 * cik_sdma_load_microcode - load the sDMA ME ucode
478 *
479 * @adev: amdgpu_device pointer
480 *
481 * Loads the sDMA0/1 ucode.
482 * Returns 0 for success, -EINVAL if the ucode is not available.
483 */
484static int cik_sdma_load_microcode(struct amdgpu_device *adev)
485{
486 const struct sdma_firmware_header_v1_0 *hdr;
487 const __le32 *fw_data;
488 u32 fw_size;
489 int i, j;
490
491 /* halt the MEs */
492 cik_sdma_enable(adev, false);
493
494 for (i = 0; i < adev->sdma.num_instances; i++) {
495 if (!adev->sdma.instance[i].fw)
496 return -EINVAL;
497 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
498 amdgpu_ucode_print_sdma_hdr(&hdr->header);
499 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
500 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
501 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
502 if (adev->sdma.instance[i].feature_version >= 20)
503 adev->sdma.instance[i].burst_nop = true;
504 fw_data = (const __le32 *)
505 (adev->sdma.instance[i].fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
506 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
507 for (j = 0; j < fw_size; j++)
508 WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
509 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
510 }
511
512 return 0;
513}
514
515/**
516 * cik_sdma_start - setup and start the async dma engines
517 *
518 * @adev: amdgpu_device pointer
519 *
520 * Set up the DMA engines and enable them (CIK).
521 * Returns 0 for success, error for failure.
522 */
523static int cik_sdma_start(struct amdgpu_device *adev)
524{
525 int r;
526
527 r = cik_sdma_load_microcode(adev);
528 if (r)
529 return r;
530
531 /* unhalt the MEs */
532 cik_sdma_enable(adev, true);
533
534 /* start the gfx rings and rlc compute queues */
535 r = cik_sdma_gfx_resume(adev);
536 if (r)
537 return r;
538 r = cik_sdma_rlc_resume(adev);
539 if (r)
540 return r;
541
542 return 0;
543}
544
545/**
546 * cik_sdma_ring_test_ring - simple async dma engine test
547 *
548 * @ring: amdgpu_ring structure holding ring information
549 *
550 * Test the DMA engine by writing using it to write an
551 * value to memory. (CIK).
552 * Returns 0 for success, error for failure.
553 */
554static int cik_sdma_ring_test_ring(struct amdgpu_ring *ring)
555{
556 struct amdgpu_device *adev = ring->adev;
557 unsigned i;
558 unsigned index;
559 int r;
560 u32 tmp;
561 u64 gpu_addr;
562
563 r = amdgpu_wb_get(adev, &index);
564 if (r) {
565 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
566 return r;
567 }
568
569 gpu_addr = adev->wb.gpu_addr + (index * 4);
570 tmp = 0xCAFEDEAD;
571 adev->wb.wb[index] = cpu_to_le32(tmp);
572
573 r = amdgpu_ring_alloc(ring, 5);
574 if (r) {
575 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
576 amdgpu_wb_free(adev, index);
577 return r;
578 }
579 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
580 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
581 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
582 amdgpu_ring_write(ring, 1); /* number of DWs to follow */
583 amdgpu_ring_write(ring, 0xDEADBEEF);
584 amdgpu_ring_commit(ring);
585
586 for (i = 0; i < adev->usec_timeout; i++) {
587 tmp = le32_to_cpu(adev->wb.wb[index]);
588 if (tmp == 0xDEADBEEF)
589 break;
590 DRM_UDELAY(1);
591 }
592
593 if (i < adev->usec_timeout) {
594 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
595 } else {
596 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
597 ring->idx, tmp);
598 r = -EINVAL;
599 }
600 amdgpu_wb_free(adev, index);
601
602 return r;
603}
604
605/**
606 * cik_sdma_ring_test_ib - test an IB on the DMA engine
607 *
608 * @ring: amdgpu_ring structure holding ring information
609 *
610 * Test a simple IB in the DMA ring (CIK).
611 * Returns 0 on success, error on failure.
612 */
613static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring)
614{
615 struct amdgpu_device *adev = ring->adev;
616 struct amdgpu_ib ib;
617 struct fence *f = NULL;
618 unsigned i;
619 unsigned index;
620 int r;
621 u32 tmp = 0;
622 u64 gpu_addr;
623
624 r = amdgpu_wb_get(adev, &index);
625 if (r) {
626 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
627 return r;
628 }
629
630 gpu_addr = adev->wb.gpu_addr + (index * 4);
631 tmp = 0xCAFEDEAD;
632 adev->wb.wb[index] = cpu_to_le32(tmp);
633 memset(&ib, 0, sizeof(ib));
634 r = amdgpu_ib_get(adev, NULL, 256, &ib);
635 if (r) {
636 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
637 goto err0;
638 }
639
640 ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
641 ib.ptr[1] = lower_32_bits(gpu_addr);
642 ib.ptr[2] = upper_32_bits(gpu_addr);
643 ib.ptr[3] = 1;
644 ib.ptr[4] = 0xDEADBEEF;
645 ib.length_dw = 5;
646 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
647 if (r)
648 goto err1;
649
650 r = fence_wait(f, false);
651 if (r) {
652 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
653 goto err1;
654 }
655 for (i = 0; i < adev->usec_timeout; i++) {
656 tmp = le32_to_cpu(adev->wb.wb[index]);
657 if (tmp == 0xDEADBEEF)
658 break;
659 DRM_UDELAY(1);
660 }
661 if (i < adev->usec_timeout) {
662 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
663 ring->idx, i);
664 goto err1;
665 } else {
666 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
667 r = -EINVAL;
668 }
669
670err1:
671 fence_put(f);
672 amdgpu_ib_free(adev, &ib, NULL);
673 fence_put(f);
674err0:
675 amdgpu_wb_free(adev, index);
676 return r;
677}
678
679/**
680 * cik_sdma_vm_copy_pages - update PTEs by copying them from the GART
681 *
682 * @ib: indirect buffer to fill with commands
683 * @pe: addr of the page entry
684 * @src: src addr to copy from
685 * @count: number of page entries to update
686 *
687 * Update PTEs by copying them from the GART using sDMA (CIK).
688 */
689static void cik_sdma_vm_copy_pte(struct amdgpu_ib *ib,
690 uint64_t pe, uint64_t src,
691 unsigned count)
692{
693 while (count) {
694 unsigned bytes = count * 8;
695 if (bytes > 0x1FFFF8)
696 bytes = 0x1FFFF8;
697
698 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY,
699 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
700 ib->ptr[ib->length_dw++] = bytes;
701 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
702 ib->ptr[ib->length_dw++] = lower_32_bits(src);
703 ib->ptr[ib->length_dw++] = upper_32_bits(src);
704 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
705 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
706
707 pe += bytes;
708 src += bytes;
709 count -= bytes / 8;
710 }
711}
712
713/**
714 * cik_sdma_vm_write_pages - update PTEs by writing them manually
715 *
716 * @ib: indirect buffer to fill with commands
717 * @pe: addr of the page entry
718 * @addr: dst addr to write into pe
719 * @count: number of page entries to update
720 * @incr: increase next addr by incr bytes
721 * @flags: access flags
722 *
723 * Update PTEs by writing them manually using sDMA (CIK).
724 */
725static void cik_sdma_vm_write_pte(struct amdgpu_ib *ib,
726 const dma_addr_t *pages_addr, uint64_t pe,
727 uint64_t addr, unsigned count,
728 uint32_t incr, uint32_t flags)
729{
730 uint64_t value;
731 unsigned ndw;
732
733 while (count) {
734 ndw = count * 2;
735 if (ndw > 0xFFFFE)
736 ndw = 0xFFFFE;
737
738 /* for non-physically contiguous pages (system) */
739 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE,
740 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
741 ib->ptr[ib->length_dw++] = pe;
742 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
743 ib->ptr[ib->length_dw++] = ndw;
744 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
745 value = amdgpu_vm_map_gart(pages_addr, addr);
746 addr += incr;
747 value |= flags;
748 ib->ptr[ib->length_dw++] = value;
749 ib->ptr[ib->length_dw++] = upper_32_bits(value);
750 }
751 }
752}
753
754/**
755 * cik_sdma_vm_set_pages - update the page tables using sDMA
756 *
757 * @ib: indirect buffer to fill with commands
758 * @pe: addr of the page entry
759 * @addr: dst addr to write into pe
760 * @count: number of page entries to update
761 * @incr: increase next addr by incr bytes
762 * @flags: access flags
763 *
764 * Update the page tables using sDMA (CIK).
765 */
766static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib *ib,
767 uint64_t pe,
768 uint64_t addr, unsigned count,
769 uint32_t incr, uint32_t flags)
770{
771 uint64_t value;
772 unsigned ndw;
773
774 while (count) {
775 ndw = count;
776 if (ndw > 0x7FFFF)
777 ndw = 0x7FFFF;
778
779 if (flags & AMDGPU_PTE_VALID)
780 value = addr;
781 else
782 value = 0;
783
784 /* for physically contiguous pages (vram) */
785 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0);
786 ib->ptr[ib->length_dw++] = pe; /* dst addr */
787 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
788 ib->ptr[ib->length_dw++] = flags; /* mask */
789 ib->ptr[ib->length_dw++] = 0;
790 ib->ptr[ib->length_dw++] = value; /* value */
791 ib->ptr[ib->length_dw++] = upper_32_bits(value);
792 ib->ptr[ib->length_dw++] = incr; /* increment size */
793 ib->ptr[ib->length_dw++] = 0;
794 ib->ptr[ib->length_dw++] = ndw; /* number of entries */
795
796 pe += ndw * 8;
797 addr += ndw * incr;
798 count -= ndw;
799 }
800}
801
802/**
803 * cik_sdma_vm_pad_ib - pad the IB to the required number of dw
804 *
805 * @ib: indirect buffer to fill with padding
806 *
807 */
808static void cik_sdma_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
809{
810 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
811 u32 pad_count;
812 int i;
813
814 pad_count = (8 - (ib->length_dw & 0x7)) % 8;
815 for (i = 0; i < pad_count; i++)
816 if (sdma && sdma->burst_nop && (i == 0))
817 ib->ptr[ib->length_dw++] =
818 SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0) |
819 SDMA_NOP_COUNT(pad_count - 1);
820 else
821 ib->ptr[ib->length_dw++] =
822 SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0);
823}
824
825/**
826 * cik_sdma_ring_emit_pipeline_sync - sync the pipeline
827 *
828 * @ring: amdgpu_ring pointer
829 *
830 * Make sure all previous operations are completed (CIK).
831 */
832static void cik_sdma_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
833{
834 uint32_t seq = ring->fence_drv.sync_seq;
835 uint64_t addr = ring->fence_drv.gpu_addr;
836
837 /* wait for idle */
838 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0,
839 SDMA_POLL_REG_MEM_EXTRA_OP(0) |
840 SDMA_POLL_REG_MEM_EXTRA_FUNC(3) | /* equal */
841 SDMA_POLL_REG_MEM_EXTRA_M));
842 amdgpu_ring_write(ring, addr & 0xfffffffc);
843 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
844 amdgpu_ring_write(ring, seq); /* reference */
845 amdgpu_ring_write(ring, 0xfffffff); /* mask */
846 amdgpu_ring_write(ring, (0xfff << 16) | 4); /* retry count, poll interval */
847}
848
849/**
850 * cik_sdma_ring_emit_vm_flush - cik vm flush using sDMA
851 *
852 * @ring: amdgpu_ring pointer
853 * @vm: amdgpu_vm pointer
854 *
855 * Update the page table base and flush the VM TLB
856 * using sDMA (CIK).
857 */
858static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring,
859 unsigned vm_id, uint64_t pd_addr)
860{
861 u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) |
862 SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */
863
864 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
865 if (vm_id < 8) {
866 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
867 } else {
868 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
869 }
870 amdgpu_ring_write(ring, pd_addr >> 12);
871
872 /* flush TLB */
873 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
874 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
875 amdgpu_ring_write(ring, 1 << vm_id);
876
877 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
878 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
879 amdgpu_ring_write(ring, 0);
880 amdgpu_ring_write(ring, 0); /* reference */
881 amdgpu_ring_write(ring, 0); /* mask */
882 amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
883}
884
885static void cik_enable_sdma_mgcg(struct amdgpu_device *adev,
886 bool enable)
887{
888 u32 orig, data;
889
890 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
891 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100);
892 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100);
893 } else {
894 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET);
895 data |= 0xff000000;
896 if (data != orig)
897 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data);
898
899 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET);
900 data |= 0xff000000;
901 if (data != orig)
902 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data);
903 }
904}
905
906static void cik_enable_sdma_mgls(struct amdgpu_device *adev,
907 bool enable)
908{
909 u32 orig, data;
910
911 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
912 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
913 data |= 0x100;
914 if (orig != data)
915 WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
916
917 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
918 data |= 0x100;
919 if (orig != data)
920 WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
921 } else {
922 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
923 data &= ~0x100;
924 if (orig != data)
925 WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
926
927 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
928 data &= ~0x100;
929 if (orig != data)
930 WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
931 }
932}
933
934static int cik_sdma_early_init(void *handle)
935{
936 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
937
938 adev->sdma.num_instances = SDMA_MAX_INSTANCE;
939
940 cik_sdma_set_ring_funcs(adev);
941 cik_sdma_set_irq_funcs(adev);
942 cik_sdma_set_buffer_funcs(adev);
943 cik_sdma_set_vm_pte_funcs(adev);
944
945 return 0;
946}
947
948static int cik_sdma_sw_init(void *handle)
949{
950 struct amdgpu_ring *ring;
951 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
952 int r, i;
953
954 r = cik_sdma_init_microcode(adev);
955 if (r) {
956 DRM_ERROR("Failed to load sdma firmware!\n");
957 return r;
958 }
959
960 /* SDMA trap event */
961 r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq);
962 if (r)
963 return r;
964
965 /* SDMA Privileged inst */
966 r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq);
967 if (r)
968 return r;
969
970 /* SDMA Privileged inst */
971 r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq);
972 if (r)
973 return r;
974
975 for (i = 0; i < adev->sdma.num_instances; i++) {
976 ring = &adev->sdma.instance[i].ring;
977 ring->ring_obj = NULL;
978 sprintf(ring->name, "sdma%d", i);
979 r = amdgpu_ring_init(adev, ring, 256 * 1024,
980 SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), 0xf,
981 &adev->sdma.trap_irq,
982 (i == 0) ?
983 AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1,
984 AMDGPU_RING_TYPE_SDMA);
985 if (r)
986 return r;
987 }
988
989 return r;
990}
991
992static int cik_sdma_sw_fini(void *handle)
993{
994 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
995 int i;
996
997 for (i = 0; i < adev->sdma.num_instances; i++)
998 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
999
1000 return 0;
1001}
1002
1003static int cik_sdma_hw_init(void *handle)
1004{
1005 int r;
1006 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1007
1008 r = cik_sdma_start(adev);
1009 if (r)
1010 return r;
1011
1012 return r;
1013}
1014
1015static int cik_sdma_hw_fini(void *handle)
1016{
1017 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1018
1019 cik_sdma_enable(adev, false);
1020
1021 return 0;
1022}
1023
1024static int cik_sdma_suspend(void *handle)
1025{
1026 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1027
1028 return cik_sdma_hw_fini(adev);
1029}
1030
1031static int cik_sdma_resume(void *handle)
1032{
1033 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1034
1035 return cik_sdma_hw_init(adev);
1036}
1037
1038static bool cik_sdma_is_idle(void *handle)
1039{
1040 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1041 u32 tmp = RREG32(mmSRBM_STATUS2);
1042
1043 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1044 SRBM_STATUS2__SDMA1_BUSY_MASK))
1045 return false;
1046
1047 return true;
1048}
1049
1050static int cik_sdma_wait_for_idle(void *handle)
1051{
1052 unsigned i;
1053 u32 tmp;
1054 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1055
1056 for (i = 0; i < adev->usec_timeout; i++) {
1057 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1058 SRBM_STATUS2__SDMA1_BUSY_MASK);
1059
1060 if (!tmp)
1061 return 0;
1062 udelay(1);
1063 }
1064 return -ETIMEDOUT;
1065}
1066
1067static void cik_sdma_print_status(void *handle)
1068{
1069 int i, j;
1070 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1071
1072 dev_info(adev->dev, "CIK SDMA registers\n");
1073 dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n",
1074 RREG32(mmSRBM_STATUS2));
1075 for (i = 0; i < adev->sdma.num_instances; i++) {
1076 dev_info(adev->dev, " SDMA%d_STATUS_REG=0x%08X\n",
1077 i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i]));
1078 dev_info(adev->dev, " SDMA%d_ME_CNTL=0x%08X\n",
1079 i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]));
1080 dev_info(adev->dev, " SDMA%d_CNTL=0x%08X\n",
1081 i, RREG32(mmSDMA0_CNTL + sdma_offsets[i]));
1082 dev_info(adev->dev, " SDMA%d_SEM_INCOMPLETE_TIMER_CNTL=0x%08X\n",
1083 i, RREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i]));
1084 dev_info(adev->dev, " SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n",
1085 i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i]));
1086 dev_info(adev->dev, " SDMA%d_GFX_IB_CNTL=0x%08X\n",
1087 i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]));
1088 dev_info(adev->dev, " SDMA%d_GFX_RB_CNTL=0x%08X\n",
1089 i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]));
1090 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR=0x%08X\n",
1091 i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i]));
1092 dev_info(adev->dev, " SDMA%d_GFX_RB_WPTR=0x%08X\n",
1093 i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i]));
1094 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n",
1095 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i]));
1096 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n",
1097 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i]));
1098 dev_info(adev->dev, " SDMA%d_GFX_RB_BASE=0x%08X\n",
1099 i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i]));
1100 dev_info(adev->dev, " SDMA%d_GFX_RB_BASE_HI=0x%08X\n",
1101 i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i]));
1102 dev_info(adev->dev, " SDMA%d_TILING_CONFIG=0x%08X\n",
1103 i, RREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i]));
1104 mutex_lock(&adev->srbm_mutex);
1105 for (j = 0; j < 16; j++) {
1106 cik_srbm_select(adev, 0, 0, 0, j);
1107 dev_info(adev->dev, " VM %d:\n", j);
1108 dev_info(adev->dev, " SDMA0_GFX_VIRTUAL_ADDR=0x%08X\n",
1109 RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i]));
1110 dev_info(adev->dev, " SDMA0_GFX_APE1_CNTL=0x%08X\n",
1111 RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i]));
1112 }
1113 cik_srbm_select(adev, 0, 0, 0, 0);
1114 mutex_unlock(&adev->srbm_mutex);
1115 }
1116}
1117
1118static int cik_sdma_soft_reset(void *handle)
1119{
1120 u32 srbm_soft_reset = 0;
1121 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1122 u32 tmp = RREG32(mmSRBM_STATUS2);
1123
1124 if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
1125 /* sdma0 */
1126 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1127 tmp |= SDMA0_F32_CNTL__HALT_MASK;
1128 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1129 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1130 }
1131 if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
1132 /* sdma1 */
1133 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1134 tmp |= SDMA0_F32_CNTL__HALT_MASK;
1135 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1136 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1137 }
1138
1139 if (srbm_soft_reset) {
1140 cik_sdma_print_status((void *)adev);
1141
1142 tmp = RREG32(mmSRBM_SOFT_RESET);
1143 tmp |= srbm_soft_reset;
1144 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1145 WREG32(mmSRBM_SOFT_RESET, tmp);
1146 tmp = RREG32(mmSRBM_SOFT_RESET);
1147
1148 udelay(50);
1149
1150 tmp &= ~srbm_soft_reset;
1151 WREG32(mmSRBM_SOFT_RESET, tmp);
1152 tmp = RREG32(mmSRBM_SOFT_RESET);
1153
1154 /* Wait a little for things to settle down */
1155 udelay(50);
1156
1157 cik_sdma_print_status((void *)adev);
1158 }
1159
1160 return 0;
1161}
1162
1163static int cik_sdma_set_trap_irq_state(struct amdgpu_device *adev,
1164 struct amdgpu_irq_src *src,
1165 unsigned type,
1166 enum amdgpu_interrupt_state state)
1167{
1168 u32 sdma_cntl;
1169
1170 switch (type) {
1171 case AMDGPU_SDMA_IRQ_TRAP0:
1172 switch (state) {
1173 case AMDGPU_IRQ_STATE_DISABLE:
1174 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1175 sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
1176 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1177 break;
1178 case AMDGPU_IRQ_STATE_ENABLE:
1179 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1180 sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK;
1181 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1182 break;
1183 default:
1184 break;
1185 }
1186 break;
1187 case AMDGPU_SDMA_IRQ_TRAP1:
1188 switch (state) {
1189 case AMDGPU_IRQ_STATE_DISABLE:
1190 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1191 sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
1192 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1193 break;
1194 case AMDGPU_IRQ_STATE_ENABLE:
1195 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1196 sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK;
1197 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1198 break;
1199 default:
1200 break;
1201 }
1202 break;
1203 default:
1204 break;
1205 }
1206 return 0;
1207}
1208
1209static int cik_sdma_process_trap_irq(struct amdgpu_device *adev,
1210 struct amdgpu_irq_src *source,
1211 struct amdgpu_iv_entry *entry)
1212{
1213 u8 instance_id, queue_id;
1214
1215 instance_id = (entry->ring_id & 0x3) >> 0;
1216 queue_id = (entry->ring_id & 0xc) >> 2;
1217 DRM_DEBUG("IH: SDMA trap\n");
1218 switch (instance_id) {
1219 case 0:
1220 switch (queue_id) {
1221 case 0:
1222 amdgpu_fence_process(&adev->sdma.instance[0].ring);
1223 break;
1224 case 1:
1225 /* XXX compute */
1226 break;
1227 case 2:
1228 /* XXX compute */
1229 break;
1230 }
1231 break;
1232 case 1:
1233 switch (queue_id) {
1234 case 0:
1235 amdgpu_fence_process(&adev->sdma.instance[1].ring);
1236 break;
1237 case 1:
1238 /* XXX compute */
1239 break;
1240 case 2:
1241 /* XXX compute */
1242 break;
1243 }
1244 break;
1245 }
1246
1247 return 0;
1248}
1249
1250static int cik_sdma_process_illegal_inst_irq(struct amdgpu_device *adev,
1251 struct amdgpu_irq_src *source,
1252 struct amdgpu_iv_entry *entry)
1253{
1254 DRM_ERROR("Illegal instruction in SDMA command stream\n");
1255 schedule_work(&adev->reset_work);
1256 return 0;
1257}
1258
1259static int cik_sdma_set_clockgating_state(void *handle,
1260 enum amd_clockgating_state state)
1261{
1262 bool gate = false;
1263 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1264
1265 if (state == AMD_CG_STATE_GATE)
1266 gate = true;
1267
1268 cik_enable_sdma_mgcg(adev, gate);
1269 cik_enable_sdma_mgls(adev, gate);
1270
1271 return 0;
1272}
1273
1274static int cik_sdma_set_powergating_state(void *handle,
1275 enum amd_powergating_state state)
1276{
1277 return 0;
1278}
1279
1280const struct amd_ip_funcs cik_sdma_ip_funcs = {
1281 .early_init = cik_sdma_early_init,
1282 .late_init = NULL,
1283 .sw_init = cik_sdma_sw_init,
1284 .sw_fini = cik_sdma_sw_fini,
1285 .hw_init = cik_sdma_hw_init,
1286 .hw_fini = cik_sdma_hw_fini,
1287 .suspend = cik_sdma_suspend,
1288 .resume = cik_sdma_resume,
1289 .is_idle = cik_sdma_is_idle,
1290 .wait_for_idle = cik_sdma_wait_for_idle,
1291 .soft_reset = cik_sdma_soft_reset,
1292 .print_status = cik_sdma_print_status,
1293 .set_clockgating_state = cik_sdma_set_clockgating_state,
1294 .set_powergating_state = cik_sdma_set_powergating_state,
1295};
1296
1297static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = {
1298 .get_rptr = cik_sdma_ring_get_rptr,
1299 .get_wptr = cik_sdma_ring_get_wptr,
1300 .set_wptr = cik_sdma_ring_set_wptr,
1301 .parse_cs = NULL,
1302 .emit_ib = cik_sdma_ring_emit_ib,
1303 .emit_fence = cik_sdma_ring_emit_fence,
1304 .emit_pipeline_sync = cik_sdma_ring_emit_pipeline_sync,
1305 .emit_vm_flush = cik_sdma_ring_emit_vm_flush,
1306 .emit_hdp_flush = cik_sdma_ring_emit_hdp_flush,
1307 .emit_hdp_invalidate = cik_sdma_ring_emit_hdp_invalidate,
1308 .test_ring = cik_sdma_ring_test_ring,
1309 .test_ib = cik_sdma_ring_test_ib,
1310 .insert_nop = cik_sdma_ring_insert_nop,
1311 .pad_ib = cik_sdma_ring_pad_ib,
1312};
1313
1314static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev)
1315{
1316 int i;
1317
1318 for (i = 0; i < adev->sdma.num_instances; i++)
1319 adev->sdma.instance[i].ring.funcs = &cik_sdma_ring_funcs;
1320}
1321
1322static const struct amdgpu_irq_src_funcs cik_sdma_trap_irq_funcs = {
1323 .set = cik_sdma_set_trap_irq_state,
1324 .process = cik_sdma_process_trap_irq,
1325};
1326
1327static const struct amdgpu_irq_src_funcs cik_sdma_illegal_inst_irq_funcs = {
1328 .process = cik_sdma_process_illegal_inst_irq,
1329};
1330
1331static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev)
1332{
1333 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1334 adev->sdma.trap_irq.funcs = &cik_sdma_trap_irq_funcs;
1335 adev->sdma.illegal_inst_irq.funcs = &cik_sdma_illegal_inst_irq_funcs;
1336}
1337
1338/**
1339 * cik_sdma_emit_copy_buffer - copy buffer using the sDMA engine
1340 *
1341 * @ring: amdgpu_ring structure holding ring information
1342 * @src_offset: src GPU address
1343 * @dst_offset: dst GPU address
1344 * @byte_count: number of bytes to xfer
1345 *
1346 * Copy GPU buffers using the DMA engine (CIK).
1347 * Used by the amdgpu ttm implementation to move pages if
1348 * registered as the asic copy callback.
1349 */
1350static void cik_sdma_emit_copy_buffer(struct amdgpu_ib *ib,
1351 uint64_t src_offset,
1352 uint64_t dst_offset,
1353 uint32_t byte_count)
1354{
1355 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0);
1356 ib->ptr[ib->length_dw++] = byte_count;
1357 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1358 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1359 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1360 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1361 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1362}
1363
1364/**
1365 * cik_sdma_emit_fill_buffer - fill buffer using the sDMA engine
1366 *
1367 * @ring: amdgpu_ring structure holding ring information
1368 * @src_data: value to write to buffer
1369 * @dst_offset: dst GPU address
1370 * @byte_count: number of bytes to xfer
1371 *
1372 * Fill GPU buffers using the DMA engine (CIK).
1373 */
1374static void cik_sdma_emit_fill_buffer(struct amdgpu_ib *ib,
1375 uint32_t src_data,
1376 uint64_t dst_offset,
1377 uint32_t byte_count)
1378{
1379 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, 0);
1380 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1381 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1382 ib->ptr[ib->length_dw++] = src_data;
1383 ib->ptr[ib->length_dw++] = byte_count;
1384}
1385
1386static const struct amdgpu_buffer_funcs cik_sdma_buffer_funcs = {
1387 .copy_max_bytes = 0x1fffff,
1388 .copy_num_dw = 7,
1389 .emit_copy_buffer = cik_sdma_emit_copy_buffer,
1390
1391 .fill_max_bytes = 0x1fffff,
1392 .fill_num_dw = 5,
1393 .emit_fill_buffer = cik_sdma_emit_fill_buffer,
1394};
1395
1396static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev)
1397{
1398 if (adev->mman.buffer_funcs == NULL) {
1399 adev->mman.buffer_funcs = &cik_sdma_buffer_funcs;
1400 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1401 }
1402}
1403
1404static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = {
1405 .copy_pte = cik_sdma_vm_copy_pte,
1406 .write_pte = cik_sdma_vm_write_pte,
1407 .set_pte_pde = cik_sdma_vm_set_pte_pde,
1408};
1409
1410static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev)
1411{
1412 unsigned i;
1413
1414 if (adev->vm_manager.vm_pte_funcs == NULL) {
1415 adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs;
1416 for (i = 0; i < adev->sdma.num_instances; i++)
1417 adev->vm_manager.vm_pte_rings[i] =
1418 &adev->sdma.instance[i].ring;
1419
1420 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances;
1421 }
1422}
1/*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24
25#include <linux/firmware.h>
26#include <linux/module.h>
27
28#include "amdgpu.h"
29#include "amdgpu_ucode.h"
30#include "amdgpu_trace.h"
31#include "cikd.h"
32#include "cik.h"
33
34#include "bif/bif_4_1_d.h"
35#include "bif/bif_4_1_sh_mask.h"
36
37#include "gca/gfx_7_2_d.h"
38#include "gca/gfx_7_2_enum.h"
39#include "gca/gfx_7_2_sh_mask.h"
40
41#include "gmc/gmc_7_1_d.h"
42#include "gmc/gmc_7_1_sh_mask.h"
43
44#include "oss/oss_2_0_d.h"
45#include "oss/oss_2_0_sh_mask.h"
46
47static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
48{
49 SDMA0_REGISTER_OFFSET,
50 SDMA1_REGISTER_OFFSET
51};
52
53static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev);
54static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev);
55static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev);
56static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev);
57static int cik_sdma_soft_reset(void *handle);
58
59MODULE_FIRMWARE("amdgpu/bonaire_sdma.bin");
60MODULE_FIRMWARE("amdgpu/bonaire_sdma1.bin");
61MODULE_FIRMWARE("amdgpu/hawaii_sdma.bin");
62MODULE_FIRMWARE("amdgpu/hawaii_sdma1.bin");
63MODULE_FIRMWARE("amdgpu/kaveri_sdma.bin");
64MODULE_FIRMWARE("amdgpu/kaveri_sdma1.bin");
65MODULE_FIRMWARE("amdgpu/kabini_sdma.bin");
66MODULE_FIRMWARE("amdgpu/kabini_sdma1.bin");
67MODULE_FIRMWARE("amdgpu/mullins_sdma.bin");
68MODULE_FIRMWARE("amdgpu/mullins_sdma1.bin");
69
70u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev);
71
72
73static void cik_sdma_free_microcode(struct amdgpu_device *adev)
74{
75 int i;
76 for (i = 0; i < adev->sdma.num_instances; i++) {
77 release_firmware(adev->sdma.instance[i].fw);
78 adev->sdma.instance[i].fw = NULL;
79 }
80}
81
82/*
83 * sDMA - System DMA
84 * Starting with CIK, the GPU has new asynchronous
85 * DMA engines. These engines are used for compute
86 * and gfx. There are two DMA engines (SDMA0, SDMA1)
87 * and each one supports 1 ring buffer used for gfx
88 * and 2 queues used for compute.
89 *
90 * The programming model is very similar to the CP
91 * (ring buffer, IBs, etc.), but sDMA has it's own
92 * packet format that is different from the PM4 format
93 * used by the CP. sDMA supports copying data, writing
94 * embedded data, solid fills, and a number of other
95 * things. It also has support for tiling/detiling of
96 * buffers.
97 */
98
99/**
100 * cik_sdma_init_microcode - load ucode images from disk
101 *
102 * @adev: amdgpu_device pointer
103 *
104 * Use the firmware interface to load the ucode images into
105 * the driver (not loaded into hw).
106 * Returns 0 on success, error on failure.
107 */
108static int cik_sdma_init_microcode(struct amdgpu_device *adev)
109{
110 const char *chip_name;
111 char fw_name[30];
112 int err = 0, i;
113
114 DRM_DEBUG("\n");
115
116 switch (adev->asic_type) {
117 case CHIP_BONAIRE:
118 chip_name = "bonaire";
119 break;
120 case CHIP_HAWAII:
121 chip_name = "hawaii";
122 break;
123 case CHIP_KAVERI:
124 chip_name = "kaveri";
125 break;
126 case CHIP_KABINI:
127 chip_name = "kabini";
128 break;
129 case CHIP_MULLINS:
130 chip_name = "mullins";
131 break;
132 default: BUG();
133 }
134
135 for (i = 0; i < adev->sdma.num_instances; i++) {
136 if (i == 0)
137 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
138 else
139 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
140 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
141 if (err)
142 goto out;
143 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
144 }
145out:
146 if (err) {
147 pr_err("cik_sdma: Failed to load firmware \"%s\"\n", fw_name);
148 for (i = 0; i < adev->sdma.num_instances; i++) {
149 release_firmware(adev->sdma.instance[i].fw);
150 adev->sdma.instance[i].fw = NULL;
151 }
152 }
153 return err;
154}
155
156/**
157 * cik_sdma_ring_get_rptr - get the current read pointer
158 *
159 * @ring: amdgpu ring pointer
160 *
161 * Get the current rptr from the hardware (CIK+).
162 */
163static uint64_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring)
164{
165 u32 rptr;
166
167 rptr = *ring->rptr_cpu_addr;
168
169 return (rptr & 0x3fffc) >> 2;
170}
171
172/**
173 * cik_sdma_ring_get_wptr - get the current write pointer
174 *
175 * @ring: amdgpu ring pointer
176 *
177 * Get the current wptr from the hardware (CIK+).
178 */
179static uint64_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring)
180{
181 struct amdgpu_device *adev = ring->adev;
182
183 return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) & 0x3fffc) >> 2;
184}
185
186/**
187 * cik_sdma_ring_set_wptr - commit the write pointer
188 *
189 * @ring: amdgpu ring pointer
190 *
191 * Write the wptr back to the hardware (CIK+).
192 */
193static void cik_sdma_ring_set_wptr(struct amdgpu_ring *ring)
194{
195 struct amdgpu_device *adev = ring->adev;
196
197 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me],
198 (ring->wptr << 2) & 0x3fffc);
199}
200
201static void cik_sdma_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
202{
203 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
204 int i;
205
206 for (i = 0; i < count; i++)
207 if (sdma && sdma->burst_nop && (i == 0))
208 amdgpu_ring_write(ring, ring->funcs->nop |
209 SDMA_NOP_COUNT(count - 1));
210 else
211 amdgpu_ring_write(ring, ring->funcs->nop);
212}
213
214/**
215 * cik_sdma_ring_emit_ib - Schedule an IB on the DMA engine
216 *
217 * @ring: amdgpu ring pointer
218 * @job: job to retrive vmid from
219 * @ib: IB object to schedule
220 * @flags: unused
221 *
222 * Schedule an IB in the DMA ring (CIK).
223 */
224static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring,
225 struct amdgpu_job *job,
226 struct amdgpu_ib *ib,
227 uint32_t flags)
228{
229 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
230 u32 extra_bits = vmid & 0xf;
231
232 /* IB packet must end on a 8 DW boundary */
233 cik_sdma_ring_insert_nop(ring, (4 - lower_32_bits(ring->wptr)) & 7);
234
235 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits));
236 amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */
237 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff);
238 amdgpu_ring_write(ring, ib->length_dw);
239
240}
241
242/**
243 * cik_sdma_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
244 *
245 * @ring: amdgpu ring pointer
246 *
247 * Emit an hdp flush packet on the requested DMA ring.
248 */
249static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring *ring)
250{
251 u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) |
252 SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */
253 u32 ref_and_mask;
254
255 if (ring->me == 0)
256 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA0_MASK;
257 else
258 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA1_MASK;
259
260 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
261 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
262 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
263 amdgpu_ring_write(ring, ref_and_mask); /* reference */
264 amdgpu_ring_write(ring, ref_and_mask); /* mask */
265 amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
266}
267
268/**
269 * cik_sdma_ring_emit_fence - emit a fence on the DMA ring
270 *
271 * @ring: amdgpu ring pointer
272 * @addr: address
273 * @seq: sequence number
274 * @flags: fence related flags
275 *
276 * Add a DMA fence packet to the ring to write
277 * the fence seq number and DMA trap packet to generate
278 * an interrupt if needed (CIK).
279 */
280static void cik_sdma_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
281 unsigned flags)
282{
283 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
284 /* write the fence */
285 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
286 amdgpu_ring_write(ring, lower_32_bits(addr));
287 amdgpu_ring_write(ring, upper_32_bits(addr));
288 amdgpu_ring_write(ring, lower_32_bits(seq));
289
290 /* optionally write high bits as well */
291 if (write64bit) {
292 addr += 4;
293 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
294 amdgpu_ring_write(ring, lower_32_bits(addr));
295 amdgpu_ring_write(ring, upper_32_bits(addr));
296 amdgpu_ring_write(ring, upper_32_bits(seq));
297 }
298
299 /* generate an interrupt */
300 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0));
301}
302
303/**
304 * cik_sdma_gfx_stop - stop the gfx async dma engines
305 *
306 * @adev: amdgpu_device pointer
307 *
308 * Stop the gfx async dma ring buffers (CIK).
309 */
310static void cik_sdma_gfx_stop(struct amdgpu_device *adev)
311{
312 u32 rb_cntl;
313 int i;
314
315 amdgpu_sdma_unset_buffer_funcs_helper(adev);
316
317 for (i = 0; i < adev->sdma.num_instances; i++) {
318 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
319 rb_cntl &= ~SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK;
320 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
321 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0);
322 }
323}
324
325/**
326 * cik_sdma_rlc_stop - stop the compute async dma engines
327 *
328 * @adev: amdgpu_device pointer
329 *
330 * Stop the compute async dma queues (CIK).
331 */
332static void cik_sdma_rlc_stop(struct amdgpu_device *adev)
333{
334 /* XXX todo */
335}
336
337/**
338 * cik_ctx_switch_enable - stop the async dma engines context switch
339 *
340 * @adev: amdgpu_device pointer
341 * @enable: enable/disable the DMA MEs context switch.
342 *
343 * Halt or unhalt the async dma engines context switch (VI).
344 */
345static void cik_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
346{
347 u32 f32_cntl, phase_quantum = 0;
348 int i;
349
350 if (amdgpu_sdma_phase_quantum) {
351 unsigned value = amdgpu_sdma_phase_quantum;
352 unsigned unit = 0;
353
354 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
355 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
356 value = (value + 1) >> 1;
357 unit++;
358 }
359 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
360 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
361 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
362 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
363 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
364 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
365 WARN_ONCE(1,
366 "clamping sdma_phase_quantum to %uK clock cycles\n",
367 value << unit);
368 }
369 phase_quantum =
370 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
371 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
372 }
373
374 for (i = 0; i < adev->sdma.num_instances; i++) {
375 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
376 if (enable) {
377 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
378 AUTO_CTXSW_ENABLE, 1);
379 if (amdgpu_sdma_phase_quantum) {
380 WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i],
381 phase_quantum);
382 WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i],
383 phase_quantum);
384 }
385 } else {
386 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
387 AUTO_CTXSW_ENABLE, 0);
388 }
389
390 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);
391 }
392}
393
394/**
395 * cik_sdma_enable - stop the async dma engines
396 *
397 * @adev: amdgpu_device pointer
398 * @enable: enable/disable the DMA MEs.
399 *
400 * Halt or unhalt the async dma engines (CIK).
401 */
402static void cik_sdma_enable(struct amdgpu_device *adev, bool enable)
403{
404 u32 me_cntl;
405 int i;
406
407 if (!enable) {
408 cik_sdma_gfx_stop(adev);
409 cik_sdma_rlc_stop(adev);
410 }
411
412 for (i = 0; i < adev->sdma.num_instances; i++) {
413 me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
414 if (enable)
415 me_cntl &= ~SDMA0_F32_CNTL__HALT_MASK;
416 else
417 me_cntl |= SDMA0_F32_CNTL__HALT_MASK;
418 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], me_cntl);
419 }
420}
421
422/**
423 * cik_sdma_gfx_resume - setup and start the async dma engines
424 *
425 * @adev: amdgpu_device pointer
426 *
427 * Set up the gfx DMA ring buffers and enable them (CIK).
428 * Returns 0 for success, error for failure.
429 */
430static int cik_sdma_gfx_resume(struct amdgpu_device *adev)
431{
432 struct amdgpu_ring *ring;
433 u32 rb_cntl, ib_cntl;
434 u32 rb_bufsz;
435 int i, j, r;
436
437 for (i = 0; i < adev->sdma.num_instances; i++) {
438 ring = &adev->sdma.instance[i].ring;
439
440 mutex_lock(&adev->srbm_mutex);
441 for (j = 0; j < 16; j++) {
442 cik_srbm_select(adev, 0, 0, 0, j);
443 /* SDMA GFX */
444 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
445 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
446 /* XXX SDMA RLC - todo */
447 }
448 cik_srbm_select(adev, 0, 0, 0, 0);
449 mutex_unlock(&adev->srbm_mutex);
450
451 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
452 adev->gfx.config.gb_addr_config & 0x70);
453
454 WREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0);
455 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
456
457 /* Set ring buffer size in dwords */
458 rb_bufsz = order_base_2(ring->ring_size / 4);
459 rb_cntl = rb_bufsz << 1;
460#ifdef __BIG_ENDIAN
461 rb_cntl |= SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK |
462 SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK;
463#endif
464 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
465
466 /* Initialize the ring buffer's read and write pointers */
467 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
468 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
469 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
470 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
471
472 /* set the wb address whether it's enabled or not */
473 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
474 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
475 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
476 ((ring->rptr_gpu_addr) & 0xFFFFFFFC));
477
478 rb_cntl |= SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK;
479
480 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
481 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
482
483 ring->wptr = 0;
484 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
485
486 /* enable DMA RB */
487 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i],
488 rb_cntl | SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK);
489
490 ib_cntl = SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK;
491#ifdef __BIG_ENDIAN
492 ib_cntl |= SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK;
493#endif
494 /* enable DMA IBs */
495 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
496
497 ring->sched.ready = true;
498 }
499
500 cik_sdma_enable(adev, true);
501
502 for (i = 0; i < adev->sdma.num_instances; i++) {
503 ring = &adev->sdma.instance[i].ring;
504 r = amdgpu_ring_test_helper(ring);
505 if (r)
506 return r;
507
508 if (adev->mman.buffer_funcs_ring == ring)
509 amdgpu_ttm_set_buffer_funcs_status(adev, true);
510 }
511
512 return 0;
513}
514
515/**
516 * cik_sdma_rlc_resume - setup and start the async dma engines
517 *
518 * @adev: amdgpu_device pointer
519 *
520 * Set up the compute DMA queues and enable them (CIK).
521 * Returns 0 for success, error for failure.
522 */
523static int cik_sdma_rlc_resume(struct amdgpu_device *adev)
524{
525 /* XXX todo */
526 return 0;
527}
528
529/**
530 * cik_sdma_load_microcode - load the sDMA ME ucode
531 *
532 * @adev: amdgpu_device pointer
533 *
534 * Loads the sDMA0/1 ucode.
535 * Returns 0 for success, -EINVAL if the ucode is not available.
536 */
537static int cik_sdma_load_microcode(struct amdgpu_device *adev)
538{
539 const struct sdma_firmware_header_v1_0 *hdr;
540 const __le32 *fw_data;
541 u32 fw_size;
542 int i, j;
543
544 /* halt the MEs */
545 cik_sdma_enable(adev, false);
546
547 for (i = 0; i < adev->sdma.num_instances; i++) {
548 if (!adev->sdma.instance[i].fw)
549 return -EINVAL;
550 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
551 amdgpu_ucode_print_sdma_hdr(&hdr->header);
552 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
553 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
554 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
555 if (adev->sdma.instance[i].feature_version >= 20)
556 adev->sdma.instance[i].burst_nop = true;
557 fw_data = (const __le32 *)
558 (adev->sdma.instance[i].fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
559 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
560 for (j = 0; j < fw_size; j++)
561 WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
562 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
563 }
564
565 return 0;
566}
567
568/**
569 * cik_sdma_start - setup and start the async dma engines
570 *
571 * @adev: amdgpu_device pointer
572 *
573 * Set up the DMA engines and enable them (CIK).
574 * Returns 0 for success, error for failure.
575 */
576static int cik_sdma_start(struct amdgpu_device *adev)
577{
578 int r;
579
580 r = cik_sdma_load_microcode(adev);
581 if (r)
582 return r;
583
584 /* halt the engine before programing */
585 cik_sdma_enable(adev, false);
586 /* enable sdma ring preemption */
587 cik_ctx_switch_enable(adev, true);
588
589 /* start the gfx rings and rlc compute queues */
590 r = cik_sdma_gfx_resume(adev);
591 if (r)
592 return r;
593 r = cik_sdma_rlc_resume(adev);
594 if (r)
595 return r;
596
597 return 0;
598}
599
600/**
601 * cik_sdma_ring_test_ring - simple async dma engine test
602 *
603 * @ring: amdgpu_ring structure holding ring information
604 *
605 * Test the DMA engine by writing using it to write an
606 * value to memory. (CIK).
607 * Returns 0 for success, error for failure.
608 */
609static int cik_sdma_ring_test_ring(struct amdgpu_ring *ring)
610{
611 struct amdgpu_device *adev = ring->adev;
612 unsigned i;
613 unsigned index;
614 int r;
615 u32 tmp;
616 u64 gpu_addr;
617
618 r = amdgpu_device_wb_get(adev, &index);
619 if (r)
620 return r;
621
622 gpu_addr = adev->wb.gpu_addr + (index * 4);
623 tmp = 0xCAFEDEAD;
624 adev->wb.wb[index] = cpu_to_le32(tmp);
625
626 r = amdgpu_ring_alloc(ring, 5);
627 if (r)
628 goto error_free_wb;
629
630 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
631 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
632 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
633 amdgpu_ring_write(ring, 1); /* number of DWs to follow */
634 amdgpu_ring_write(ring, 0xDEADBEEF);
635 amdgpu_ring_commit(ring);
636
637 for (i = 0; i < adev->usec_timeout; i++) {
638 tmp = le32_to_cpu(adev->wb.wb[index]);
639 if (tmp == 0xDEADBEEF)
640 break;
641 udelay(1);
642 }
643
644 if (i >= adev->usec_timeout)
645 r = -ETIMEDOUT;
646
647error_free_wb:
648 amdgpu_device_wb_free(adev, index);
649 return r;
650}
651
652/**
653 * cik_sdma_ring_test_ib - test an IB on the DMA engine
654 *
655 * @ring: amdgpu_ring structure holding ring information
656 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
657 *
658 * Test a simple IB in the DMA ring (CIK).
659 * Returns 0 on success, error on failure.
660 */
661static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring, long timeout)
662{
663 struct amdgpu_device *adev = ring->adev;
664 struct amdgpu_ib ib;
665 struct dma_fence *f = NULL;
666 unsigned index;
667 u32 tmp = 0;
668 u64 gpu_addr;
669 long r;
670
671 r = amdgpu_device_wb_get(adev, &index);
672 if (r)
673 return r;
674
675 gpu_addr = adev->wb.gpu_addr + (index * 4);
676 tmp = 0xCAFEDEAD;
677 adev->wb.wb[index] = cpu_to_le32(tmp);
678 memset(&ib, 0, sizeof(ib));
679 r = amdgpu_ib_get(adev, NULL, 256,
680 AMDGPU_IB_POOL_DIRECT, &ib);
681 if (r)
682 goto err0;
683
684 ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE,
685 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
686 ib.ptr[1] = lower_32_bits(gpu_addr);
687 ib.ptr[2] = upper_32_bits(gpu_addr);
688 ib.ptr[3] = 1;
689 ib.ptr[4] = 0xDEADBEEF;
690 ib.length_dw = 5;
691 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
692 if (r)
693 goto err1;
694
695 r = dma_fence_wait_timeout(f, false, timeout);
696 if (r == 0) {
697 r = -ETIMEDOUT;
698 goto err1;
699 } else if (r < 0) {
700 goto err1;
701 }
702 tmp = le32_to_cpu(adev->wb.wb[index]);
703 if (tmp == 0xDEADBEEF)
704 r = 0;
705 else
706 r = -EINVAL;
707
708err1:
709 amdgpu_ib_free(adev, &ib, NULL);
710 dma_fence_put(f);
711err0:
712 amdgpu_device_wb_free(adev, index);
713 return r;
714}
715
716/**
717 * cik_sdma_vm_copy_pte - update PTEs by copying them from the GART
718 *
719 * @ib: indirect buffer to fill with commands
720 * @pe: addr of the page entry
721 * @src: src addr to copy from
722 * @count: number of page entries to update
723 *
724 * Update PTEs by copying them from the GART using sDMA (CIK).
725 */
726static void cik_sdma_vm_copy_pte(struct amdgpu_ib *ib,
727 uint64_t pe, uint64_t src,
728 unsigned count)
729{
730 unsigned bytes = count * 8;
731
732 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY,
733 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
734 ib->ptr[ib->length_dw++] = bytes;
735 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
736 ib->ptr[ib->length_dw++] = lower_32_bits(src);
737 ib->ptr[ib->length_dw++] = upper_32_bits(src);
738 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
739 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
740}
741
742/**
743 * cik_sdma_vm_write_pte - update PTEs by writing them manually
744 *
745 * @ib: indirect buffer to fill with commands
746 * @pe: addr of the page entry
747 * @value: dst addr to write into pe
748 * @count: number of page entries to update
749 * @incr: increase next addr by incr bytes
750 *
751 * Update PTEs by writing them manually using sDMA (CIK).
752 */
753static void cik_sdma_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
754 uint64_t value, unsigned count,
755 uint32_t incr)
756{
757 unsigned ndw = count * 2;
758
759 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE,
760 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
761 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
762 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
763 ib->ptr[ib->length_dw++] = ndw;
764 for (; ndw > 0; ndw -= 2) {
765 ib->ptr[ib->length_dw++] = lower_32_bits(value);
766 ib->ptr[ib->length_dw++] = upper_32_bits(value);
767 value += incr;
768 }
769}
770
771/**
772 * cik_sdma_vm_set_pte_pde - update the page tables using sDMA
773 *
774 * @ib: indirect buffer to fill with commands
775 * @pe: addr of the page entry
776 * @addr: dst addr to write into pe
777 * @count: number of page entries to update
778 * @incr: increase next addr by incr bytes
779 * @flags: access flags
780 *
781 * Update the page tables using sDMA (CIK).
782 */
783static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,
784 uint64_t addr, unsigned count,
785 uint32_t incr, uint64_t flags)
786{
787 /* for physically contiguous pages (vram) */
788 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0);
789 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
790 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
791 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
792 ib->ptr[ib->length_dw++] = upper_32_bits(flags);
793 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
794 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
795 ib->ptr[ib->length_dw++] = incr; /* increment size */
796 ib->ptr[ib->length_dw++] = 0;
797 ib->ptr[ib->length_dw++] = count; /* number of entries */
798}
799
800/**
801 * cik_sdma_ring_pad_ib - pad the IB to the required number of dw
802 *
803 * @ring: amdgpu_ring structure holding ring information
804 * @ib: indirect buffer to fill with padding
805 *
806 */
807static void cik_sdma_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
808{
809 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
810 u32 pad_count;
811 int i;
812
813 pad_count = (-ib->length_dw) & 7;
814 for (i = 0; i < pad_count; i++)
815 if (sdma && sdma->burst_nop && (i == 0))
816 ib->ptr[ib->length_dw++] =
817 SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0) |
818 SDMA_NOP_COUNT(pad_count - 1);
819 else
820 ib->ptr[ib->length_dw++] =
821 SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0);
822}
823
824/**
825 * cik_sdma_ring_emit_pipeline_sync - sync the pipeline
826 *
827 * @ring: amdgpu_ring pointer
828 *
829 * Make sure all previous operations are completed (CIK).
830 */
831static void cik_sdma_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
832{
833 uint32_t seq = ring->fence_drv.sync_seq;
834 uint64_t addr = ring->fence_drv.gpu_addr;
835
836 /* wait for idle */
837 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0,
838 SDMA_POLL_REG_MEM_EXTRA_OP(0) |
839 SDMA_POLL_REG_MEM_EXTRA_FUNC(3) | /* equal */
840 SDMA_POLL_REG_MEM_EXTRA_M));
841 amdgpu_ring_write(ring, addr & 0xfffffffc);
842 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
843 amdgpu_ring_write(ring, seq); /* reference */
844 amdgpu_ring_write(ring, 0xffffffff); /* mask */
845 amdgpu_ring_write(ring, (0xfff << 16) | 4); /* retry count, poll interval */
846}
847
848/**
849 * cik_sdma_ring_emit_vm_flush - cik vm flush using sDMA
850 *
851 * @ring: amdgpu_ring pointer
852 * @vmid: vmid number to use
853 * @pd_addr: address
854 *
855 * Update the page table base and flush the VM TLB
856 * using sDMA (CIK).
857 */
858static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring,
859 unsigned vmid, uint64_t pd_addr)
860{
861 u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) |
862 SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */
863
864 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
865
866 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
867 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
868 amdgpu_ring_write(ring, 0);
869 amdgpu_ring_write(ring, 0); /* reference */
870 amdgpu_ring_write(ring, 0); /* mask */
871 amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
872}
873
874static void cik_sdma_ring_emit_wreg(struct amdgpu_ring *ring,
875 uint32_t reg, uint32_t val)
876{
877 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
878 amdgpu_ring_write(ring, reg);
879 amdgpu_ring_write(ring, val);
880}
881
882static void cik_enable_sdma_mgcg(struct amdgpu_device *adev,
883 bool enable)
884{
885 u32 orig, data;
886
887 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
888 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100);
889 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100);
890 } else {
891 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET);
892 data |= 0xff000000;
893 if (data != orig)
894 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data);
895
896 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET);
897 data |= 0xff000000;
898 if (data != orig)
899 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data);
900 }
901}
902
903static void cik_enable_sdma_mgls(struct amdgpu_device *adev,
904 bool enable)
905{
906 u32 orig, data;
907
908 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
909 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
910 data |= 0x100;
911 if (orig != data)
912 WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
913
914 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
915 data |= 0x100;
916 if (orig != data)
917 WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
918 } else {
919 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
920 data &= ~0x100;
921 if (orig != data)
922 WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
923
924 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
925 data &= ~0x100;
926 if (orig != data)
927 WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
928 }
929}
930
931static int cik_sdma_early_init(void *handle)
932{
933 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
934
935 adev->sdma.num_instances = SDMA_MAX_INSTANCE;
936
937 cik_sdma_set_ring_funcs(adev);
938 cik_sdma_set_irq_funcs(adev);
939 cik_sdma_set_buffer_funcs(adev);
940 cik_sdma_set_vm_pte_funcs(adev);
941
942 return 0;
943}
944
945static int cik_sdma_sw_init(void *handle)
946{
947 struct amdgpu_ring *ring;
948 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
949 int r, i;
950
951 r = cik_sdma_init_microcode(adev);
952 if (r) {
953 DRM_ERROR("Failed to load sdma firmware!\n");
954 return r;
955 }
956
957 /* SDMA trap event */
958 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 224,
959 &adev->sdma.trap_irq);
960 if (r)
961 return r;
962
963 /* SDMA Privileged inst */
964 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 241,
965 &adev->sdma.illegal_inst_irq);
966 if (r)
967 return r;
968
969 /* SDMA Privileged inst */
970 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 247,
971 &adev->sdma.illegal_inst_irq);
972 if (r)
973 return r;
974
975 for (i = 0; i < adev->sdma.num_instances; i++) {
976 ring = &adev->sdma.instance[i].ring;
977 ring->ring_obj = NULL;
978 sprintf(ring->name, "sdma%d", i);
979 r = amdgpu_ring_init(adev, ring, 1024,
980 &adev->sdma.trap_irq,
981 (i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 :
982 AMDGPU_SDMA_IRQ_INSTANCE1,
983 AMDGPU_RING_PRIO_DEFAULT, NULL);
984 if (r)
985 return r;
986 }
987
988 return r;
989}
990
991static int cik_sdma_sw_fini(void *handle)
992{
993 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
994 int i;
995
996 for (i = 0; i < adev->sdma.num_instances; i++)
997 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
998
999 cik_sdma_free_microcode(adev);
1000 return 0;
1001}
1002
1003static int cik_sdma_hw_init(void *handle)
1004{
1005 int r;
1006 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1007
1008 r = cik_sdma_start(adev);
1009 if (r)
1010 return r;
1011
1012 return r;
1013}
1014
1015static int cik_sdma_hw_fini(void *handle)
1016{
1017 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1018
1019 cik_ctx_switch_enable(adev, false);
1020 cik_sdma_enable(adev, false);
1021
1022 return 0;
1023}
1024
1025static int cik_sdma_suspend(void *handle)
1026{
1027 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1028
1029 return cik_sdma_hw_fini(adev);
1030}
1031
1032static int cik_sdma_resume(void *handle)
1033{
1034 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1035
1036 cik_sdma_soft_reset(handle);
1037
1038 return cik_sdma_hw_init(adev);
1039}
1040
1041static bool cik_sdma_is_idle(void *handle)
1042{
1043 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1044 u32 tmp = RREG32(mmSRBM_STATUS2);
1045
1046 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1047 SRBM_STATUS2__SDMA1_BUSY_MASK))
1048 return false;
1049
1050 return true;
1051}
1052
1053static int cik_sdma_wait_for_idle(void *handle)
1054{
1055 unsigned i;
1056 u32 tmp;
1057 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1058
1059 for (i = 0; i < adev->usec_timeout; i++) {
1060 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1061 SRBM_STATUS2__SDMA1_BUSY_MASK);
1062
1063 if (!tmp)
1064 return 0;
1065 udelay(1);
1066 }
1067 return -ETIMEDOUT;
1068}
1069
1070static int cik_sdma_soft_reset(void *handle)
1071{
1072 u32 srbm_soft_reset = 0;
1073 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1074 u32 tmp;
1075
1076 /* sdma0 */
1077 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1078 tmp |= SDMA0_F32_CNTL__HALT_MASK;
1079 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1080 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1081
1082 /* sdma1 */
1083 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1084 tmp |= SDMA0_F32_CNTL__HALT_MASK;
1085 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1086 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1087
1088 if (srbm_soft_reset) {
1089 tmp = RREG32(mmSRBM_SOFT_RESET);
1090 tmp |= srbm_soft_reset;
1091 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1092 WREG32(mmSRBM_SOFT_RESET, tmp);
1093 tmp = RREG32(mmSRBM_SOFT_RESET);
1094
1095 udelay(50);
1096
1097 tmp &= ~srbm_soft_reset;
1098 WREG32(mmSRBM_SOFT_RESET, tmp);
1099 tmp = RREG32(mmSRBM_SOFT_RESET);
1100
1101 /* Wait a little for things to settle down */
1102 udelay(50);
1103 }
1104
1105 return 0;
1106}
1107
1108static int cik_sdma_set_trap_irq_state(struct amdgpu_device *adev,
1109 struct amdgpu_irq_src *src,
1110 unsigned type,
1111 enum amdgpu_interrupt_state state)
1112{
1113 u32 sdma_cntl;
1114
1115 switch (type) {
1116 case AMDGPU_SDMA_IRQ_INSTANCE0:
1117 switch (state) {
1118 case AMDGPU_IRQ_STATE_DISABLE:
1119 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1120 sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
1121 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1122 break;
1123 case AMDGPU_IRQ_STATE_ENABLE:
1124 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1125 sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK;
1126 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1127 break;
1128 default:
1129 break;
1130 }
1131 break;
1132 case AMDGPU_SDMA_IRQ_INSTANCE1:
1133 switch (state) {
1134 case AMDGPU_IRQ_STATE_DISABLE:
1135 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1136 sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
1137 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1138 break;
1139 case AMDGPU_IRQ_STATE_ENABLE:
1140 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1141 sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK;
1142 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1143 break;
1144 default:
1145 break;
1146 }
1147 break;
1148 default:
1149 break;
1150 }
1151 return 0;
1152}
1153
1154static int cik_sdma_process_trap_irq(struct amdgpu_device *adev,
1155 struct amdgpu_irq_src *source,
1156 struct amdgpu_iv_entry *entry)
1157{
1158 u8 instance_id, queue_id;
1159
1160 instance_id = (entry->ring_id & 0x3) >> 0;
1161 queue_id = (entry->ring_id & 0xc) >> 2;
1162 DRM_DEBUG("IH: SDMA trap\n");
1163 switch (instance_id) {
1164 case 0:
1165 switch (queue_id) {
1166 case 0:
1167 amdgpu_fence_process(&adev->sdma.instance[0].ring);
1168 break;
1169 case 1:
1170 /* XXX compute */
1171 break;
1172 case 2:
1173 /* XXX compute */
1174 break;
1175 }
1176 break;
1177 case 1:
1178 switch (queue_id) {
1179 case 0:
1180 amdgpu_fence_process(&adev->sdma.instance[1].ring);
1181 break;
1182 case 1:
1183 /* XXX compute */
1184 break;
1185 case 2:
1186 /* XXX compute */
1187 break;
1188 }
1189 break;
1190 }
1191
1192 return 0;
1193}
1194
1195static int cik_sdma_process_illegal_inst_irq(struct amdgpu_device *adev,
1196 struct amdgpu_irq_src *source,
1197 struct amdgpu_iv_entry *entry)
1198{
1199 u8 instance_id;
1200
1201 DRM_ERROR("Illegal instruction in SDMA command stream\n");
1202 instance_id = (entry->ring_id & 0x3) >> 0;
1203 drm_sched_fault(&adev->sdma.instance[instance_id].ring.sched);
1204 return 0;
1205}
1206
1207static int cik_sdma_set_clockgating_state(void *handle,
1208 enum amd_clockgating_state state)
1209{
1210 bool gate = false;
1211 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1212
1213 if (state == AMD_CG_STATE_GATE)
1214 gate = true;
1215
1216 cik_enable_sdma_mgcg(adev, gate);
1217 cik_enable_sdma_mgls(adev, gate);
1218
1219 return 0;
1220}
1221
1222static int cik_sdma_set_powergating_state(void *handle,
1223 enum amd_powergating_state state)
1224{
1225 return 0;
1226}
1227
1228static const struct amd_ip_funcs cik_sdma_ip_funcs = {
1229 .name = "cik_sdma",
1230 .early_init = cik_sdma_early_init,
1231 .late_init = NULL,
1232 .sw_init = cik_sdma_sw_init,
1233 .sw_fini = cik_sdma_sw_fini,
1234 .hw_init = cik_sdma_hw_init,
1235 .hw_fini = cik_sdma_hw_fini,
1236 .suspend = cik_sdma_suspend,
1237 .resume = cik_sdma_resume,
1238 .is_idle = cik_sdma_is_idle,
1239 .wait_for_idle = cik_sdma_wait_for_idle,
1240 .soft_reset = cik_sdma_soft_reset,
1241 .set_clockgating_state = cik_sdma_set_clockgating_state,
1242 .set_powergating_state = cik_sdma_set_powergating_state,
1243};
1244
1245static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = {
1246 .type = AMDGPU_RING_TYPE_SDMA,
1247 .align_mask = 0xf,
1248 .nop = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0),
1249 .support_64bit_ptrs = false,
1250 .get_rptr = cik_sdma_ring_get_rptr,
1251 .get_wptr = cik_sdma_ring_get_wptr,
1252 .set_wptr = cik_sdma_ring_set_wptr,
1253 .emit_frame_size =
1254 6 + /* cik_sdma_ring_emit_hdp_flush */
1255 3 + /* hdp invalidate */
1256 6 + /* cik_sdma_ring_emit_pipeline_sync */
1257 CIK_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* cik_sdma_ring_emit_vm_flush */
1258 9 + 9 + 9, /* cik_sdma_ring_emit_fence x3 for user fence, vm fence */
1259 .emit_ib_size = 7 + 4, /* cik_sdma_ring_emit_ib */
1260 .emit_ib = cik_sdma_ring_emit_ib,
1261 .emit_fence = cik_sdma_ring_emit_fence,
1262 .emit_pipeline_sync = cik_sdma_ring_emit_pipeline_sync,
1263 .emit_vm_flush = cik_sdma_ring_emit_vm_flush,
1264 .emit_hdp_flush = cik_sdma_ring_emit_hdp_flush,
1265 .test_ring = cik_sdma_ring_test_ring,
1266 .test_ib = cik_sdma_ring_test_ib,
1267 .insert_nop = cik_sdma_ring_insert_nop,
1268 .pad_ib = cik_sdma_ring_pad_ib,
1269 .emit_wreg = cik_sdma_ring_emit_wreg,
1270};
1271
1272static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev)
1273{
1274 int i;
1275
1276 for (i = 0; i < adev->sdma.num_instances; i++) {
1277 adev->sdma.instance[i].ring.funcs = &cik_sdma_ring_funcs;
1278 adev->sdma.instance[i].ring.me = i;
1279 }
1280}
1281
1282static const struct amdgpu_irq_src_funcs cik_sdma_trap_irq_funcs = {
1283 .set = cik_sdma_set_trap_irq_state,
1284 .process = cik_sdma_process_trap_irq,
1285};
1286
1287static const struct amdgpu_irq_src_funcs cik_sdma_illegal_inst_irq_funcs = {
1288 .process = cik_sdma_process_illegal_inst_irq,
1289};
1290
1291static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev)
1292{
1293 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1294 adev->sdma.trap_irq.funcs = &cik_sdma_trap_irq_funcs;
1295 adev->sdma.illegal_inst_irq.funcs = &cik_sdma_illegal_inst_irq_funcs;
1296}
1297
1298/**
1299 * cik_sdma_emit_copy_buffer - copy buffer using the sDMA engine
1300 *
1301 * @ib: indirect buffer to copy to
1302 * @src_offset: src GPU address
1303 * @dst_offset: dst GPU address
1304 * @byte_count: number of bytes to xfer
1305 * @tmz: is this a secure operation
1306 *
1307 * Copy GPU buffers using the DMA engine (CIK).
1308 * Used by the amdgpu ttm implementation to move pages if
1309 * registered as the asic copy callback.
1310 */
1311static void cik_sdma_emit_copy_buffer(struct amdgpu_ib *ib,
1312 uint64_t src_offset,
1313 uint64_t dst_offset,
1314 uint32_t byte_count,
1315 bool tmz)
1316{
1317 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0);
1318 ib->ptr[ib->length_dw++] = byte_count;
1319 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1320 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1321 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1322 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1323 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1324}
1325
1326/**
1327 * cik_sdma_emit_fill_buffer - fill buffer using the sDMA engine
1328 *
1329 * @ib: indirect buffer to fill
1330 * @src_data: value to write to buffer
1331 * @dst_offset: dst GPU address
1332 * @byte_count: number of bytes to xfer
1333 *
1334 * Fill GPU buffers using the DMA engine (CIK).
1335 */
1336static void cik_sdma_emit_fill_buffer(struct amdgpu_ib *ib,
1337 uint32_t src_data,
1338 uint64_t dst_offset,
1339 uint32_t byte_count)
1340{
1341 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, 0);
1342 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1343 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1344 ib->ptr[ib->length_dw++] = src_data;
1345 ib->ptr[ib->length_dw++] = byte_count;
1346}
1347
1348static const struct amdgpu_buffer_funcs cik_sdma_buffer_funcs = {
1349 .copy_max_bytes = 0x1fffff,
1350 .copy_num_dw = 7,
1351 .emit_copy_buffer = cik_sdma_emit_copy_buffer,
1352
1353 .fill_max_bytes = 0x1fffff,
1354 .fill_num_dw = 5,
1355 .emit_fill_buffer = cik_sdma_emit_fill_buffer,
1356};
1357
1358static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev)
1359{
1360 adev->mman.buffer_funcs = &cik_sdma_buffer_funcs;
1361 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1362}
1363
1364static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = {
1365 .copy_pte_num_dw = 7,
1366 .copy_pte = cik_sdma_vm_copy_pte,
1367
1368 .write_pte = cik_sdma_vm_write_pte,
1369 .set_pte_pde = cik_sdma_vm_set_pte_pde,
1370};
1371
1372static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev)
1373{
1374 unsigned i;
1375
1376 adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs;
1377 for (i = 0; i < adev->sdma.num_instances; i++) {
1378 adev->vm_manager.vm_pte_scheds[i] =
1379 &adev->sdma.instance[i].ring.sched;
1380 }
1381 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1382}
1383
1384const struct amdgpu_ip_block_version cik_sdma_ip_block =
1385{
1386 .type = AMD_IP_BLOCK_TYPE_SDMA,
1387 .major = 2,
1388 .minor = 0,
1389 .rev = 0,
1390 .funcs = &cik_sdma_ip_funcs,
1391};