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1// SPDX-License-Identifier: GPL-2.0+
2
3#include <drm/drm_atomic_helper.h>
4#include <drm/drm_simple_kms_helper.h>
5#include <drm/drm_vblank.h>
6
7#include "amdgpu.h"
8#ifdef CONFIG_DRM_AMDGPU_SI
9#include "dce_v6_0.h"
10#endif
11#ifdef CONFIG_DRM_AMDGPU_CIK
12#include "dce_v8_0.h"
13#endif
14#include "dce_v10_0.h"
15#include "dce_v11_0.h"
16#include "ivsrcid/ivsrcid_vislands30.h"
17#include "amdgpu_vkms.h"
18#include "amdgpu_display.h"
19#include "atom.h"
20#include "amdgpu_irq.h"
21
22/**
23 * DOC: amdgpu_vkms
24 *
25 * The amdgpu vkms interface provides a virtual KMS interface for several use
26 * cases: devices without display hardware, platforms where the actual display
27 * hardware is not useful (e.g., servers), SR-IOV virtual functions, device
28 * emulation/simulation, and device bring up prior to display hardware being
29 * usable. We previously emulated a legacy KMS interface, but there was a desire
30 * to move to the atomic KMS interface. The vkms driver did everything we
31 * needed, but we wanted KMS support natively in the driver without buffer
32 * sharing and the ability to support an instance of VKMS per device. We first
33 * looked at splitting vkms into a stub driver and a helper module that other
34 * drivers could use to implement a virtual display, but this strategy ended up
35 * being messy due to driver specific callbacks needed for buffer management.
36 * Ultimately, it proved easier to import the vkms code as it mostly used core
37 * drm helpers anyway.
38 */
39
40static const u32 amdgpu_vkms_formats[] = {
41 DRM_FORMAT_XRGB8888,
42};
43
44static enum hrtimer_restart amdgpu_vkms_vblank_simulate(struct hrtimer *timer)
45{
46 struct amdgpu_crtc *amdgpu_crtc = container_of(timer, struct amdgpu_crtc, vblank_timer);
47 struct drm_crtc *crtc = &amdgpu_crtc->base;
48 struct amdgpu_vkms_output *output = drm_crtc_to_amdgpu_vkms_output(crtc);
49 u64 ret_overrun;
50 bool ret;
51
52 ret_overrun = hrtimer_forward_now(&amdgpu_crtc->vblank_timer,
53 output->period_ns);
54 if (ret_overrun != 1)
55 DRM_WARN("%s: vblank timer overrun\n", __func__);
56
57 ret = drm_crtc_handle_vblank(crtc);
58 if (!ret)
59 DRM_ERROR("amdgpu_vkms failure on handling vblank");
60
61 return HRTIMER_RESTART;
62}
63
64static int amdgpu_vkms_enable_vblank(struct drm_crtc *crtc)
65{
66 struct drm_device *dev = crtc->dev;
67 unsigned int pipe = drm_crtc_index(crtc);
68 struct drm_vblank_crtc *vblank = &dev->vblank[pipe];
69 struct amdgpu_vkms_output *out = drm_crtc_to_amdgpu_vkms_output(crtc);
70 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
71
72 drm_calc_timestamping_constants(crtc, &crtc->mode);
73
74 out->period_ns = ktime_set(0, vblank->framedur_ns);
75 hrtimer_start(&amdgpu_crtc->vblank_timer, out->period_ns, HRTIMER_MODE_REL);
76
77 return 0;
78}
79
80static void amdgpu_vkms_disable_vblank(struct drm_crtc *crtc)
81{
82 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
83
84 hrtimer_cancel(&amdgpu_crtc->vblank_timer);
85}
86
87static bool amdgpu_vkms_get_vblank_timestamp(struct drm_crtc *crtc,
88 int *max_error,
89 ktime_t *vblank_time,
90 bool in_vblank_irq)
91{
92 struct drm_device *dev = crtc->dev;
93 unsigned int pipe = crtc->index;
94 struct amdgpu_vkms_output *output = drm_crtc_to_amdgpu_vkms_output(crtc);
95 struct drm_vblank_crtc *vblank = &dev->vblank[pipe];
96 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
97
98 if (!READ_ONCE(vblank->enabled)) {
99 *vblank_time = ktime_get();
100 return true;
101 }
102
103 *vblank_time = READ_ONCE(amdgpu_crtc->vblank_timer.node.expires);
104
105 if (WARN_ON(*vblank_time == vblank->time))
106 return true;
107
108 /*
109 * To prevent races we roll the hrtimer forward before we do any
110 * interrupt processing - this is how real hw works (the interrupt is
111 * only generated after all the vblank registers are updated) and what
112 * the vblank core expects. Therefore we need to always correct the
113 * timestampe by one frame.
114 */
115 *vblank_time -= output->period_ns;
116
117 return true;
118}
119
120static const struct drm_crtc_funcs amdgpu_vkms_crtc_funcs = {
121 .set_config = drm_atomic_helper_set_config,
122 .destroy = drm_crtc_cleanup,
123 .page_flip = drm_atomic_helper_page_flip,
124 .reset = drm_atomic_helper_crtc_reset,
125 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
126 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
127 .enable_vblank = amdgpu_vkms_enable_vblank,
128 .disable_vblank = amdgpu_vkms_disable_vblank,
129 .get_vblank_timestamp = amdgpu_vkms_get_vblank_timestamp,
130};
131
132static void amdgpu_vkms_crtc_atomic_enable(struct drm_crtc *crtc,
133 struct drm_atomic_state *state)
134{
135 drm_crtc_vblank_on(crtc);
136}
137
138static void amdgpu_vkms_crtc_atomic_disable(struct drm_crtc *crtc,
139 struct drm_atomic_state *state)
140{
141 drm_crtc_vblank_off(crtc);
142}
143
144static void amdgpu_vkms_crtc_atomic_flush(struct drm_crtc *crtc,
145 struct drm_atomic_state *state)
146{
147 unsigned long flags;
148 if (crtc->state->event) {
149 spin_lock_irqsave(&crtc->dev->event_lock, flags);
150
151 if (drm_crtc_vblank_get(crtc) != 0)
152 drm_crtc_send_vblank_event(crtc, crtc->state->event);
153 else
154 drm_crtc_arm_vblank_event(crtc, crtc->state->event);
155
156 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
157
158 crtc->state->event = NULL;
159 }
160}
161
162static const struct drm_crtc_helper_funcs amdgpu_vkms_crtc_helper_funcs = {
163 .atomic_flush = amdgpu_vkms_crtc_atomic_flush,
164 .atomic_enable = amdgpu_vkms_crtc_atomic_enable,
165 .atomic_disable = amdgpu_vkms_crtc_atomic_disable,
166};
167
168static int amdgpu_vkms_crtc_init(struct drm_device *dev, struct drm_crtc *crtc,
169 struct drm_plane *primary, struct drm_plane *cursor)
170{
171 struct amdgpu_device *adev = drm_to_adev(dev);
172 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
173 int ret;
174
175 ret = drm_crtc_init_with_planes(dev, crtc, primary, cursor,
176 &amdgpu_vkms_crtc_funcs, NULL);
177 if (ret) {
178 DRM_ERROR("Failed to init CRTC\n");
179 return ret;
180 }
181
182 drm_crtc_helper_add(crtc, &amdgpu_vkms_crtc_helper_funcs);
183
184 amdgpu_crtc->crtc_id = drm_crtc_index(crtc);
185 adev->mode_info.crtcs[drm_crtc_index(crtc)] = amdgpu_crtc;
186
187 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
188 amdgpu_crtc->encoder = NULL;
189 amdgpu_crtc->connector = NULL;
190 amdgpu_crtc->vsync_timer_enabled = AMDGPU_IRQ_STATE_DISABLE;
191
192 hrtimer_init(&amdgpu_crtc->vblank_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
193 amdgpu_crtc->vblank_timer.function = &amdgpu_vkms_vblank_simulate;
194
195 return ret;
196}
197
198static const struct drm_connector_funcs amdgpu_vkms_connector_funcs = {
199 .fill_modes = drm_helper_probe_single_connector_modes,
200 .destroy = drm_connector_cleanup,
201 .reset = drm_atomic_helper_connector_reset,
202 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
203 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
204};
205
206static int amdgpu_vkms_conn_get_modes(struct drm_connector *connector)
207{
208 struct drm_device *dev = connector->dev;
209 struct drm_display_mode *mode = NULL;
210 unsigned i;
211 static const struct mode_size {
212 int w;
213 int h;
214 } common_modes[] = {
215 { 640, 480},
216 { 720, 480},
217 { 800, 600},
218 { 848, 480},
219 {1024, 768},
220 {1152, 768},
221 {1280, 720},
222 {1280, 800},
223 {1280, 854},
224 {1280, 960},
225 {1280, 1024},
226 {1440, 900},
227 {1400, 1050},
228 {1680, 1050},
229 {1600, 1200},
230 {1920, 1080},
231 {1920, 1200},
232 {2560, 1440},
233 {4096, 3112},
234 {3656, 2664},
235 {3840, 2160},
236 {4096, 2160},
237 };
238
239 for (i = 0; i < ARRAY_SIZE(common_modes); i++) {
240 mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false);
241 drm_mode_probed_add(connector, mode);
242 }
243
244 drm_set_preferred_mode(connector, XRES_DEF, YRES_DEF);
245
246 return ARRAY_SIZE(common_modes);
247}
248
249static const struct drm_connector_helper_funcs amdgpu_vkms_conn_helper_funcs = {
250 .get_modes = amdgpu_vkms_conn_get_modes,
251};
252
253static const struct drm_plane_funcs amdgpu_vkms_plane_funcs = {
254 .update_plane = drm_atomic_helper_update_plane,
255 .disable_plane = drm_atomic_helper_disable_plane,
256 .destroy = drm_plane_cleanup,
257 .reset = drm_atomic_helper_plane_reset,
258 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
259 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
260};
261
262static void amdgpu_vkms_plane_atomic_update(struct drm_plane *plane,
263 struct drm_atomic_state *old_state)
264{
265 return;
266}
267
268static int amdgpu_vkms_plane_atomic_check(struct drm_plane *plane,
269 struct drm_atomic_state *state)
270{
271 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
272 plane);
273 struct drm_crtc_state *crtc_state;
274 int ret;
275
276 if (!new_plane_state->fb || WARN_ON(!new_plane_state->crtc))
277 return 0;
278
279 crtc_state = drm_atomic_get_crtc_state(state,
280 new_plane_state->crtc);
281 if (IS_ERR(crtc_state))
282 return PTR_ERR(crtc_state);
283
284 ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,
285 DRM_PLANE_NO_SCALING,
286 DRM_PLANE_NO_SCALING,
287 false, true);
288 if (ret != 0)
289 return ret;
290
291 /* for now primary plane must be visible and full screen */
292 if (!new_plane_state->visible)
293 return -EINVAL;
294
295 return 0;
296}
297
298static int amdgpu_vkms_prepare_fb(struct drm_plane *plane,
299 struct drm_plane_state *new_state)
300{
301 struct amdgpu_framebuffer *afb;
302 struct drm_gem_object *obj;
303 struct amdgpu_device *adev;
304 struct amdgpu_bo *rbo;
305 uint32_t domain;
306 int r;
307
308 if (!new_state->fb) {
309 DRM_DEBUG_KMS("No FB bound\n");
310 return 0;
311 }
312 afb = to_amdgpu_framebuffer(new_state->fb);
313 obj = new_state->fb->obj[0];
314 rbo = gem_to_amdgpu_bo(obj);
315 adev = amdgpu_ttm_adev(rbo->tbo.bdev);
316
317 r = amdgpu_bo_reserve(rbo, true);
318 if (r) {
319 dev_err(adev->dev, "fail to reserve bo (%d)\n", r);
320 return r;
321 }
322
323 r = dma_resv_reserve_fences(rbo->tbo.base.resv, 1);
324 if (r) {
325 dev_err(adev->dev, "allocating fence slot failed (%d)\n", r);
326 goto error_unlock;
327 }
328
329 if (plane->type != DRM_PLANE_TYPE_CURSOR)
330 domain = amdgpu_display_supported_domains(adev, rbo->flags);
331 else
332 domain = AMDGPU_GEM_DOMAIN_VRAM;
333
334 r = amdgpu_bo_pin(rbo, domain);
335 if (unlikely(r != 0)) {
336 if (r != -ERESTARTSYS)
337 DRM_ERROR("Failed to pin framebuffer with error %d\n", r);
338 goto error_unlock;
339 }
340
341 r = amdgpu_ttm_alloc_gart(&rbo->tbo);
342 if (unlikely(r != 0)) {
343 DRM_ERROR("%p bind failed\n", rbo);
344 goto error_unpin;
345 }
346
347 amdgpu_bo_unreserve(rbo);
348
349 afb->address = amdgpu_bo_gpu_offset(rbo);
350
351 amdgpu_bo_ref(rbo);
352
353 return 0;
354
355error_unpin:
356 amdgpu_bo_unpin(rbo);
357
358error_unlock:
359 amdgpu_bo_unreserve(rbo);
360 return r;
361}
362
363static void amdgpu_vkms_cleanup_fb(struct drm_plane *plane,
364 struct drm_plane_state *old_state)
365{
366 struct amdgpu_bo *rbo;
367 int r;
368
369 if (!old_state->fb)
370 return;
371
372 rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]);
373 r = amdgpu_bo_reserve(rbo, false);
374 if (unlikely(r)) {
375 DRM_ERROR("failed to reserve rbo before unpin\n");
376 return;
377 }
378
379 amdgpu_bo_unpin(rbo);
380 amdgpu_bo_unreserve(rbo);
381 amdgpu_bo_unref(&rbo);
382}
383
384static const struct drm_plane_helper_funcs amdgpu_vkms_primary_helper_funcs = {
385 .atomic_update = amdgpu_vkms_plane_atomic_update,
386 .atomic_check = amdgpu_vkms_plane_atomic_check,
387 .prepare_fb = amdgpu_vkms_prepare_fb,
388 .cleanup_fb = amdgpu_vkms_cleanup_fb,
389};
390
391static struct drm_plane *amdgpu_vkms_plane_init(struct drm_device *dev,
392 enum drm_plane_type type,
393 int index)
394{
395 struct drm_plane *plane;
396 int ret;
397
398 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
399 if (!plane)
400 return ERR_PTR(-ENOMEM);
401
402 ret = drm_universal_plane_init(dev, plane, 1 << index,
403 &amdgpu_vkms_plane_funcs,
404 amdgpu_vkms_formats,
405 ARRAY_SIZE(amdgpu_vkms_formats),
406 NULL, type, NULL);
407 if (ret) {
408 kfree(plane);
409 return ERR_PTR(ret);
410 }
411
412 drm_plane_helper_add(plane, &amdgpu_vkms_primary_helper_funcs);
413
414 return plane;
415}
416
417static int amdgpu_vkms_output_init(struct drm_device *dev, struct
418 amdgpu_vkms_output *output, int index)
419{
420 struct drm_connector *connector = &output->connector;
421 struct drm_encoder *encoder = &output->encoder;
422 struct drm_crtc *crtc = &output->crtc.base;
423 struct drm_plane *primary, *cursor = NULL;
424 int ret;
425
426 primary = amdgpu_vkms_plane_init(dev, DRM_PLANE_TYPE_PRIMARY, index);
427 if (IS_ERR(primary))
428 return PTR_ERR(primary);
429
430 ret = amdgpu_vkms_crtc_init(dev, crtc, primary, cursor);
431 if (ret)
432 goto err_crtc;
433
434 ret = drm_connector_init(dev, connector, &amdgpu_vkms_connector_funcs,
435 DRM_MODE_CONNECTOR_VIRTUAL);
436 if (ret) {
437 DRM_ERROR("Failed to init connector\n");
438 goto err_connector;
439 }
440
441 drm_connector_helper_add(connector, &amdgpu_vkms_conn_helper_funcs);
442
443 ret = drm_simple_encoder_init(dev, encoder, DRM_MODE_ENCODER_VIRTUAL);
444 if (ret) {
445 DRM_ERROR("Failed to init encoder\n");
446 goto err_encoder;
447 }
448 encoder->possible_crtcs = 1 << index;
449
450 ret = drm_connector_attach_encoder(connector, encoder);
451 if (ret) {
452 DRM_ERROR("Failed to attach connector to encoder\n");
453 goto err_attach;
454 }
455
456 drm_mode_config_reset(dev);
457
458 return 0;
459
460err_attach:
461 drm_encoder_cleanup(encoder);
462
463err_encoder:
464 drm_connector_cleanup(connector);
465
466err_connector:
467 drm_crtc_cleanup(crtc);
468
469err_crtc:
470 drm_plane_cleanup(primary);
471
472 return ret;
473}
474
475const struct drm_mode_config_funcs amdgpu_vkms_mode_funcs = {
476 .fb_create = amdgpu_display_user_framebuffer_create,
477 .atomic_check = drm_atomic_helper_check,
478 .atomic_commit = drm_atomic_helper_commit,
479};
480
481static int amdgpu_vkms_sw_init(void *handle)
482{
483 int r, i;
484 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
485
486 adev->amdgpu_vkms_output = kcalloc(adev->mode_info.num_crtc,
487 sizeof(struct amdgpu_vkms_output), GFP_KERNEL);
488 if (!adev->amdgpu_vkms_output)
489 return -ENOMEM;
490
491 adev_to_drm(adev)->max_vblank_count = 0;
492
493 adev_to_drm(adev)->mode_config.funcs = &amdgpu_vkms_mode_funcs;
494
495 adev_to_drm(adev)->mode_config.max_width = XRES_MAX;
496 adev_to_drm(adev)->mode_config.max_height = YRES_MAX;
497
498 adev_to_drm(adev)->mode_config.preferred_depth = 24;
499 adev_to_drm(adev)->mode_config.prefer_shadow = 1;
500
501 adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true;
502
503 adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true;
504
505 r = amdgpu_display_modeset_create_props(adev);
506 if (r)
507 return r;
508
509 /* allocate crtcs, encoders, connectors */
510 for (i = 0; i < adev->mode_info.num_crtc; i++) {
511 r = amdgpu_vkms_output_init(adev_to_drm(adev), &adev->amdgpu_vkms_output[i], i);
512 if (r)
513 return r;
514 }
515
516 r = drm_vblank_init(adev_to_drm(adev), adev->mode_info.num_crtc);
517 if (r)
518 return r;
519
520 drm_kms_helper_poll_init(adev_to_drm(adev));
521
522 adev->mode_info.mode_config_initialized = true;
523 return 0;
524}
525
526static int amdgpu_vkms_sw_fini(void *handle)
527{
528 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
529 int i = 0;
530
531 for (i = 0; i < adev->mode_info.num_crtc; i++)
532 if (adev->mode_info.crtcs[i])
533 hrtimer_cancel(&adev->mode_info.crtcs[i]->vblank_timer);
534
535 drm_kms_helper_poll_fini(adev_to_drm(adev));
536 drm_mode_config_cleanup(adev_to_drm(adev));
537
538 adev->mode_info.mode_config_initialized = false;
539
540 kfree(adev->mode_info.bios_hardcoded_edid);
541 kfree(adev->amdgpu_vkms_output);
542 return 0;
543}
544
545static int amdgpu_vkms_hw_init(void *handle)
546{
547 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
548
549 switch (adev->asic_type) {
550#ifdef CONFIG_DRM_AMDGPU_SI
551 case CHIP_TAHITI:
552 case CHIP_PITCAIRN:
553 case CHIP_VERDE:
554 case CHIP_OLAND:
555 dce_v6_0_disable_dce(adev);
556 break;
557#endif
558#ifdef CONFIG_DRM_AMDGPU_CIK
559 case CHIP_BONAIRE:
560 case CHIP_HAWAII:
561 case CHIP_KAVERI:
562 case CHIP_KABINI:
563 case CHIP_MULLINS:
564 dce_v8_0_disable_dce(adev);
565 break;
566#endif
567 case CHIP_FIJI:
568 case CHIP_TONGA:
569 dce_v10_0_disable_dce(adev);
570 break;
571 case CHIP_CARRIZO:
572 case CHIP_STONEY:
573 case CHIP_POLARIS10:
574 case CHIP_POLARIS11:
575 case CHIP_VEGAM:
576 dce_v11_0_disable_dce(adev);
577 break;
578 case CHIP_TOPAZ:
579#ifdef CONFIG_DRM_AMDGPU_SI
580 case CHIP_HAINAN:
581#endif
582 /* no DCE */
583 break;
584 default:
585 break;
586 }
587 return 0;
588}
589
590static int amdgpu_vkms_hw_fini(void *handle)
591{
592 return 0;
593}
594
595static int amdgpu_vkms_suspend(void *handle)
596{
597 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
598 int r;
599
600 r = drm_mode_config_helper_suspend(adev_to_drm(adev));
601 if (r)
602 return r;
603 return amdgpu_vkms_hw_fini(handle);
604}
605
606static int amdgpu_vkms_resume(void *handle)
607{
608 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
609 int r;
610
611 r = amdgpu_vkms_hw_init(handle);
612 if (r)
613 return r;
614 return drm_mode_config_helper_resume(adev_to_drm(adev));
615}
616
617static bool amdgpu_vkms_is_idle(void *handle)
618{
619 return true;
620}
621
622static int amdgpu_vkms_wait_for_idle(void *handle)
623{
624 return 0;
625}
626
627static int amdgpu_vkms_soft_reset(void *handle)
628{
629 return 0;
630}
631
632static int amdgpu_vkms_set_clockgating_state(void *handle,
633 enum amd_clockgating_state state)
634{
635 return 0;
636}
637
638static int amdgpu_vkms_set_powergating_state(void *handle,
639 enum amd_powergating_state state)
640{
641 return 0;
642}
643
644static const struct amd_ip_funcs amdgpu_vkms_ip_funcs = {
645 .name = "amdgpu_vkms",
646 .early_init = NULL,
647 .late_init = NULL,
648 .sw_init = amdgpu_vkms_sw_init,
649 .sw_fini = amdgpu_vkms_sw_fini,
650 .hw_init = amdgpu_vkms_hw_init,
651 .hw_fini = amdgpu_vkms_hw_fini,
652 .suspend = amdgpu_vkms_suspend,
653 .resume = amdgpu_vkms_resume,
654 .is_idle = amdgpu_vkms_is_idle,
655 .wait_for_idle = amdgpu_vkms_wait_for_idle,
656 .soft_reset = amdgpu_vkms_soft_reset,
657 .set_clockgating_state = amdgpu_vkms_set_clockgating_state,
658 .set_powergating_state = amdgpu_vkms_set_powergating_state,
659};
660
661const struct amdgpu_ip_block_version amdgpu_vkms_ip_block =
662{
663 .type = AMD_IP_BLOCK_TYPE_DCE,
664 .major = 1,
665 .minor = 0,
666 .rev = 0,
667 .funcs = &amdgpu_vkms_ip_funcs,
668};
669