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1/*
2 * GPIO controller in LSI ZEVIO SoCs.
3 *
4 * Author: Fabian Vogt <fabian@ritter-vogt.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/spinlock.h>
12#include <linux/errno.h>
13#include <linux/module.h>
14#include <linux/bitops.h>
15#include <linux/io.h>
16#include <linux/of_device.h>
17#include <linux/of_gpio.h>
18#include <linux/slab.h>
19#include <linux/gpio.h>
20
21/*
22 * Memory layout:
23 * This chip has four gpio sections, each controls 8 GPIOs.
24 * Bit 0 in section 0 is GPIO 0, bit 2 in section 1 is GPIO 10.
25 * Disclaimer: Reverse engineered!
26 * For more information refer to:
27 * http://hackspire.unsads.com/wiki/index.php/Memory-mapped_I/O_ports#90000000_-_General_Purpose_I.2FO_.28GPIO.29
28 *
29 * 0x00-0x3F: Section 0
30 * +0x00: Masked interrupt status (read-only)
31 * +0x04: R: Interrupt status W: Reset interrupt status
32 * +0x08: R: Interrupt mask W: Mask interrupt
33 * +0x0C: W: Unmask interrupt (write-only)
34 * +0x10: Direction: I/O=1/0
35 * +0x14: Output
36 * +0x18: Input (read-only)
37 * +0x20: R: Level interrupt W: Set as level interrupt
38 * 0x40-0x7F: Section 1
39 * 0x80-0xBF: Section 2
40 * 0xC0-0xFF: Section 3
41 */
42
43#define ZEVIO_GPIO_SECTION_SIZE 0x40
44
45/* Offsets to various registers */
46#define ZEVIO_GPIO_INT_MASKED_STATUS 0x00
47#define ZEVIO_GPIO_INT_STATUS 0x04
48#define ZEVIO_GPIO_INT_UNMASK 0x08
49#define ZEVIO_GPIO_INT_MASK 0x0C
50#define ZEVIO_GPIO_DIRECTION 0x10
51#define ZEVIO_GPIO_OUTPUT 0x14
52#define ZEVIO_GPIO_INPUT 0x18
53#define ZEVIO_GPIO_INT_STICKY 0x20
54
55/* Bit number of GPIO in its section */
56#define ZEVIO_GPIO_BIT(gpio) (gpio&7)
57
58struct zevio_gpio {
59 spinlock_t lock;
60 struct of_mm_gpio_chip chip;
61};
62
63static inline u32 zevio_gpio_port_get(struct zevio_gpio *c, unsigned pin,
64 unsigned port_offset)
65{
66 unsigned section_offset = ((pin >> 3) & 3)*ZEVIO_GPIO_SECTION_SIZE;
67 return readl(IOMEM(c->chip.regs + section_offset + port_offset));
68}
69
70static inline void zevio_gpio_port_set(struct zevio_gpio *c, unsigned pin,
71 unsigned port_offset, u32 val)
72{
73 unsigned section_offset = ((pin >> 3) & 3)*ZEVIO_GPIO_SECTION_SIZE;
74 writel(val, IOMEM(c->chip.regs + section_offset + port_offset));
75}
76
77/* Functions for struct gpio_chip */
78static int zevio_gpio_get(struct gpio_chip *chip, unsigned pin)
79{
80 struct zevio_gpio *controller = gpiochip_get_data(chip);
81 u32 val, dir;
82
83 spin_lock(&controller->lock);
84 dir = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_DIRECTION);
85 if (dir & BIT(ZEVIO_GPIO_BIT(pin)))
86 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_INPUT);
87 else
88 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_OUTPUT);
89 spin_unlock(&controller->lock);
90
91 return (val >> ZEVIO_GPIO_BIT(pin)) & 0x1;
92}
93
94static void zevio_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
95{
96 struct zevio_gpio *controller = gpiochip_get_data(chip);
97 u32 val;
98
99 spin_lock(&controller->lock);
100 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_OUTPUT);
101 if (value)
102 val |= BIT(ZEVIO_GPIO_BIT(pin));
103 else
104 val &= ~BIT(ZEVIO_GPIO_BIT(pin));
105
106 zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_OUTPUT, val);
107 spin_unlock(&controller->lock);
108}
109
110static int zevio_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
111{
112 struct zevio_gpio *controller = gpiochip_get_data(chip);
113 u32 val;
114
115 spin_lock(&controller->lock);
116
117 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_DIRECTION);
118 val |= BIT(ZEVIO_GPIO_BIT(pin));
119 zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_DIRECTION, val);
120
121 spin_unlock(&controller->lock);
122
123 return 0;
124}
125
126static int zevio_gpio_direction_output(struct gpio_chip *chip,
127 unsigned pin, int value)
128{
129 struct zevio_gpio *controller = gpiochip_get_data(chip);
130 u32 val;
131
132 spin_lock(&controller->lock);
133 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_OUTPUT);
134 if (value)
135 val |= BIT(ZEVIO_GPIO_BIT(pin));
136 else
137 val &= ~BIT(ZEVIO_GPIO_BIT(pin));
138
139 zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_OUTPUT, val);
140 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_DIRECTION);
141 val &= ~BIT(ZEVIO_GPIO_BIT(pin));
142 zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_DIRECTION, val);
143
144 spin_unlock(&controller->lock);
145
146 return 0;
147}
148
149static int zevio_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
150{
151 /*
152 * TODO: Implement IRQs.
153 * Not implemented yet due to weird lockups
154 */
155
156 return -ENXIO;
157}
158
159static struct gpio_chip zevio_gpio_chip = {
160 .direction_input = zevio_gpio_direction_input,
161 .direction_output = zevio_gpio_direction_output,
162 .set = zevio_gpio_set,
163 .get = zevio_gpio_get,
164 .to_irq = zevio_gpio_to_irq,
165 .base = 0,
166 .owner = THIS_MODULE,
167 .ngpio = 32,
168 .of_gpio_n_cells = 2,
169};
170
171/* Initialization */
172static int zevio_gpio_probe(struct platform_device *pdev)
173{
174 struct zevio_gpio *controller;
175 int status, i;
176
177 controller = devm_kzalloc(&pdev->dev, sizeof(*controller), GFP_KERNEL);
178 if (!controller)
179 return -ENOMEM;
180
181 platform_set_drvdata(pdev, controller);
182
183 /* Copy our reference */
184 controller->chip.gc = zevio_gpio_chip;
185 controller->chip.gc.parent = &pdev->dev;
186
187 status = of_mm_gpiochip_add_data(pdev->dev.of_node,
188 &(controller->chip),
189 controller);
190 if (status) {
191 dev_err(&pdev->dev, "failed to add gpiochip: %d\n", status);
192 return status;
193 }
194
195 spin_lock_init(&controller->lock);
196
197 /* Disable interrupts, they only cause errors */
198 for (i = 0; i < controller->chip.gc.ngpio; i += 8)
199 zevio_gpio_port_set(controller, i, ZEVIO_GPIO_INT_MASK, 0xFF);
200
201 dev_dbg(controller->chip.gc.parent, "ZEVIO GPIO controller set up!\n");
202
203 return 0;
204}
205
206static int zevio_gpio_remove(struct platform_device *pdev)
207{
208 struct zevio_gpio *controller = platform_get_drvdata(pdev);
209
210 of_mm_gpiochip_remove(&controller->chip);
211
212 return 0;
213}
214
215static const struct of_device_id zevio_gpio_of_match[] = {
216 { .compatible = "lsi,zevio-gpio", },
217 { },
218};
219
220MODULE_DEVICE_TABLE(of, zevio_gpio_of_match);
221
222static struct platform_driver zevio_gpio_driver = {
223 .driver = {
224 .name = "gpio-zevio",
225 .of_match_table = zevio_gpio_of_match,
226 },
227 .probe = zevio_gpio_probe,
228 .remove = zevio_gpio_remove,
229};
230module_platform_driver(zevio_gpio_driver);
231
232MODULE_LICENSE("GPL");
233MODULE_AUTHOR("Fabian Vogt <fabian@ritter-vogt.de>");
234MODULE_DESCRIPTION("LSI ZEVIO SoC GPIO driver");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * GPIO controller in LSI ZEVIO SoCs.
4 *
5 * Author: Fabian Vogt <fabian@ritter-vogt.de>
6 */
7
8#include <linux/spinlock.h>
9#include <linux/errno.h>
10#include <linux/init.h>
11#include <linux/bitops.h>
12#include <linux/io.h>
13#include <linux/of_device.h>
14#include <linux/slab.h>
15#include <linux/gpio/driver.h>
16
17/*
18 * Memory layout:
19 * This chip has four gpio sections, each controls 8 GPIOs.
20 * Bit 0 in section 0 is GPIO 0, bit 2 in section 1 is GPIO 10.
21 * Disclaimer: Reverse engineered!
22 * For more information refer to:
23 * http://hackspire.unsads.com/wiki/index.php/Memory-mapped_I/O_ports#90000000_-_General_Purpose_I.2FO_.28GPIO.29
24 *
25 * 0x00-0x3F: Section 0
26 * +0x00: Masked interrupt status (read-only)
27 * +0x04: R: Interrupt status W: Reset interrupt status
28 * +0x08: R: Interrupt mask W: Mask interrupt
29 * +0x0C: W: Unmask interrupt (write-only)
30 * +0x10: Direction: I/O=1/0
31 * +0x14: Output
32 * +0x18: Input (read-only)
33 * +0x20: R: Level interrupt W: Set as level interrupt
34 * 0x40-0x7F: Section 1
35 * 0x80-0xBF: Section 2
36 * 0xC0-0xFF: Section 3
37 */
38
39#define ZEVIO_GPIO_SECTION_SIZE 0x40
40
41/* Offsets to various registers */
42#define ZEVIO_GPIO_INT_MASKED_STATUS 0x00
43#define ZEVIO_GPIO_INT_STATUS 0x04
44#define ZEVIO_GPIO_INT_UNMASK 0x08
45#define ZEVIO_GPIO_INT_MASK 0x0C
46#define ZEVIO_GPIO_DIRECTION 0x10
47#define ZEVIO_GPIO_OUTPUT 0x14
48#define ZEVIO_GPIO_INPUT 0x18
49#define ZEVIO_GPIO_INT_STICKY 0x20
50
51/* Bit number of GPIO in its section */
52#define ZEVIO_GPIO_BIT(gpio) (gpio&7)
53
54struct zevio_gpio {
55 struct gpio_chip chip;
56 spinlock_t lock;
57 void __iomem *regs;
58};
59
60static inline u32 zevio_gpio_port_get(struct zevio_gpio *c, unsigned pin,
61 unsigned port_offset)
62{
63 unsigned section_offset = ((pin >> 3) & 3)*ZEVIO_GPIO_SECTION_SIZE;
64 return readl(IOMEM(c->regs + section_offset + port_offset));
65}
66
67static inline void zevio_gpio_port_set(struct zevio_gpio *c, unsigned pin,
68 unsigned port_offset, u32 val)
69{
70 unsigned section_offset = ((pin >> 3) & 3)*ZEVIO_GPIO_SECTION_SIZE;
71 writel(val, IOMEM(c->regs + section_offset + port_offset));
72}
73
74/* Functions for struct gpio_chip */
75static int zevio_gpio_get(struct gpio_chip *chip, unsigned pin)
76{
77 struct zevio_gpio *controller = gpiochip_get_data(chip);
78 u32 val, dir;
79
80 spin_lock(&controller->lock);
81 dir = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_DIRECTION);
82 if (dir & BIT(ZEVIO_GPIO_BIT(pin)))
83 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_INPUT);
84 else
85 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_OUTPUT);
86 spin_unlock(&controller->lock);
87
88 return (val >> ZEVIO_GPIO_BIT(pin)) & 0x1;
89}
90
91static void zevio_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
92{
93 struct zevio_gpio *controller = gpiochip_get_data(chip);
94 u32 val;
95
96 spin_lock(&controller->lock);
97 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_OUTPUT);
98 if (value)
99 val |= BIT(ZEVIO_GPIO_BIT(pin));
100 else
101 val &= ~BIT(ZEVIO_GPIO_BIT(pin));
102
103 zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_OUTPUT, val);
104 spin_unlock(&controller->lock);
105}
106
107static int zevio_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
108{
109 struct zevio_gpio *controller = gpiochip_get_data(chip);
110 u32 val;
111
112 spin_lock(&controller->lock);
113
114 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_DIRECTION);
115 val |= BIT(ZEVIO_GPIO_BIT(pin));
116 zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_DIRECTION, val);
117
118 spin_unlock(&controller->lock);
119
120 return 0;
121}
122
123static int zevio_gpio_direction_output(struct gpio_chip *chip,
124 unsigned pin, int value)
125{
126 struct zevio_gpio *controller = gpiochip_get_data(chip);
127 u32 val;
128
129 spin_lock(&controller->lock);
130 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_OUTPUT);
131 if (value)
132 val |= BIT(ZEVIO_GPIO_BIT(pin));
133 else
134 val &= ~BIT(ZEVIO_GPIO_BIT(pin));
135
136 zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_OUTPUT, val);
137 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_DIRECTION);
138 val &= ~BIT(ZEVIO_GPIO_BIT(pin));
139 zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_DIRECTION, val);
140
141 spin_unlock(&controller->lock);
142
143 return 0;
144}
145
146static int zevio_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
147{
148 /*
149 * TODO: Implement IRQs.
150 * Not implemented yet due to weird lockups
151 */
152
153 return -ENXIO;
154}
155
156static const struct gpio_chip zevio_gpio_chip = {
157 .direction_input = zevio_gpio_direction_input,
158 .direction_output = zevio_gpio_direction_output,
159 .set = zevio_gpio_set,
160 .get = zevio_gpio_get,
161 .to_irq = zevio_gpio_to_irq,
162 .base = 0,
163 .owner = THIS_MODULE,
164 .ngpio = 32,
165 .of_gpio_n_cells = 2,
166};
167
168/* Initialization */
169static int zevio_gpio_probe(struct platform_device *pdev)
170{
171 struct zevio_gpio *controller;
172 int status, i;
173
174 controller = devm_kzalloc(&pdev->dev, sizeof(*controller), GFP_KERNEL);
175 if (!controller)
176 return -ENOMEM;
177
178 platform_set_drvdata(pdev, controller);
179
180 /* Copy our reference */
181 controller->chip = zevio_gpio_chip;
182 controller->chip.parent = &pdev->dev;
183
184 controller->regs = devm_platform_ioremap_resource(pdev, 0);
185 if (IS_ERR(controller->regs))
186 return dev_err_probe(&pdev->dev, PTR_ERR(controller->regs),
187 "failed to ioremap memory resource\n");
188
189 status = devm_gpiochip_add_data(&pdev->dev, &controller->chip, controller);
190 if (status) {
191 dev_err(&pdev->dev, "failed to add gpiochip: %d\n", status);
192 return status;
193 }
194
195 spin_lock_init(&controller->lock);
196
197 /* Disable interrupts, they only cause errors */
198 for (i = 0; i < controller->chip.ngpio; i += 8)
199 zevio_gpio_port_set(controller, i, ZEVIO_GPIO_INT_MASK, 0xFF);
200
201 dev_dbg(controller->chip.parent, "ZEVIO GPIO controller set up!\n");
202
203 return 0;
204}
205
206static const struct of_device_id zevio_gpio_of_match[] = {
207 { .compatible = "lsi,zevio-gpio", },
208 { },
209};
210
211static struct platform_driver zevio_gpio_driver = {
212 .driver = {
213 .name = "gpio-zevio",
214 .of_match_table = zevio_gpio_of_match,
215 .suppress_bind_attrs = true,
216 },
217 .probe = zevio_gpio_probe,
218};
219builtin_platform_driver(zevio_gpio_driver);