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1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License, version 2
5 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
6 */
7
8#include <linux/module.h>
9#include <linux/init.h>
10#include <linux/platform_device.h>
11#include <linux/slab.h>
12#include <linux/gpio.h>
13#include <linux/interrupt.h>
14#include <linux/of.h>
15#include <linux/mfd/stmpe.h>
16#include <linux/seq_file.h>
17
18/*
19 * These registers are modified under the irq bus lock and cached to avoid
20 * unnecessary writes in bus_sync_unlock.
21 */
22enum { REG_RE, REG_FE, REG_IE };
23
24#define CACHE_NR_REGS 3
25/* No variant has more than 24 GPIOs */
26#define CACHE_NR_BANKS (24 / 8)
27
28struct stmpe_gpio {
29 struct gpio_chip chip;
30 struct stmpe *stmpe;
31 struct device *dev;
32 struct mutex irq_lock;
33 u32 norequest_mask;
34 /* Caches of interrupt control registers for bus_lock */
35 u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
36 u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
37};
38
39static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
40{
41 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
42 struct stmpe *stmpe = stmpe_gpio->stmpe;
43 u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB] - (offset / 8);
44 u8 mask = 1 << (offset % 8);
45 int ret;
46
47 ret = stmpe_reg_read(stmpe, reg);
48 if (ret < 0)
49 return ret;
50
51 return !!(ret & mask);
52}
53
54static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
55{
56 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
57 struct stmpe *stmpe = stmpe_gpio->stmpe;
58 int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;
59 u8 reg = stmpe->regs[which] - (offset / 8);
60 u8 mask = 1 << (offset % 8);
61
62 /*
63 * Some variants have single register for gpio set/clear functionality.
64 * For them we need to write 0 to clear and 1 to set.
65 */
66 if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB])
67 stmpe_set_bits(stmpe, reg, mask, val ? mask : 0);
68 else
69 stmpe_reg_write(stmpe, reg, mask);
70}
71
72static int stmpe_gpio_direction_output(struct gpio_chip *chip,
73 unsigned offset, int val)
74{
75 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
76 struct stmpe *stmpe = stmpe_gpio->stmpe;
77 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
78 u8 mask = 1 << (offset % 8);
79
80 stmpe_gpio_set(chip, offset, val);
81
82 return stmpe_set_bits(stmpe, reg, mask, mask);
83}
84
85static int stmpe_gpio_direction_input(struct gpio_chip *chip,
86 unsigned offset)
87{
88 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
89 struct stmpe *stmpe = stmpe_gpio->stmpe;
90 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
91 u8 mask = 1 << (offset % 8);
92
93 return stmpe_set_bits(stmpe, reg, mask, 0);
94}
95
96static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
97{
98 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
99 struct stmpe *stmpe = stmpe_gpio->stmpe;
100
101 if (stmpe_gpio->norequest_mask & (1 << offset))
102 return -EINVAL;
103
104 return stmpe_set_altfunc(stmpe, 1 << offset, STMPE_BLOCK_GPIO);
105}
106
107static struct gpio_chip template_chip = {
108 .label = "stmpe",
109 .owner = THIS_MODULE,
110 .direction_input = stmpe_gpio_direction_input,
111 .get = stmpe_gpio_get,
112 .direction_output = stmpe_gpio_direction_output,
113 .set = stmpe_gpio_set,
114 .request = stmpe_gpio_request,
115 .can_sleep = true,
116};
117
118static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
119{
120 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
121 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
122 int offset = d->hwirq;
123 int regoffset = offset / 8;
124 int mask = 1 << (offset % 8);
125
126 if (type & IRQ_TYPE_LEVEL_LOW || type & IRQ_TYPE_LEVEL_HIGH)
127 return -EINVAL;
128
129 /* STMPE801 doesn't have RE and FE registers */
130 if (stmpe_gpio->stmpe->partnum == STMPE801)
131 return 0;
132
133 if (type & IRQ_TYPE_EDGE_RISING)
134 stmpe_gpio->regs[REG_RE][regoffset] |= mask;
135 else
136 stmpe_gpio->regs[REG_RE][regoffset] &= ~mask;
137
138 if (type & IRQ_TYPE_EDGE_FALLING)
139 stmpe_gpio->regs[REG_FE][regoffset] |= mask;
140 else
141 stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;
142
143 return 0;
144}
145
146static void stmpe_gpio_irq_lock(struct irq_data *d)
147{
148 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
149 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
150
151 mutex_lock(&stmpe_gpio->irq_lock);
152}
153
154static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
155{
156 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
157 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
158 struct stmpe *stmpe = stmpe_gpio->stmpe;
159 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
160 static const u8 regmap[] = {
161 [REG_RE] = STMPE_IDX_GPRER_LSB,
162 [REG_FE] = STMPE_IDX_GPFER_LSB,
163 [REG_IE] = STMPE_IDX_IEGPIOR_LSB,
164 };
165 int i, j;
166
167 for (i = 0; i < CACHE_NR_REGS; i++) {
168 /* STMPE801 doesn't have RE and FE registers */
169 if ((stmpe->partnum == STMPE801) &&
170 (i != REG_IE))
171 continue;
172
173 for (j = 0; j < num_banks; j++) {
174 u8 old = stmpe_gpio->oldregs[i][j];
175 u8 new = stmpe_gpio->regs[i][j];
176
177 if (new == old)
178 continue;
179
180 stmpe_gpio->oldregs[i][j] = new;
181 stmpe_reg_write(stmpe, stmpe->regs[regmap[i]] - j, new);
182 }
183 }
184
185 mutex_unlock(&stmpe_gpio->irq_lock);
186}
187
188static void stmpe_gpio_irq_mask(struct irq_data *d)
189{
190 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
191 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
192 int offset = d->hwirq;
193 int regoffset = offset / 8;
194 int mask = 1 << (offset % 8);
195
196 stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
197}
198
199static void stmpe_gpio_irq_unmask(struct irq_data *d)
200{
201 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
202 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
203 int offset = d->hwirq;
204 int regoffset = offset / 8;
205 int mask = 1 << (offset % 8);
206
207 stmpe_gpio->regs[REG_IE][regoffset] |= mask;
208}
209
210static void stmpe_dbg_show_one(struct seq_file *s,
211 struct gpio_chip *gc,
212 unsigned offset, unsigned gpio)
213{
214 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
215 struct stmpe *stmpe = stmpe_gpio->stmpe;
216 const char *label = gpiochip_is_requested(gc, offset);
217 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
218 bool val = !!stmpe_gpio_get(gc, offset);
219 u8 dir_reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
220 u8 mask = 1 << (offset % 8);
221 int ret;
222 u8 dir;
223
224 ret = stmpe_reg_read(stmpe, dir_reg);
225 if (ret < 0)
226 return;
227 dir = !!(ret & mask);
228
229 if (dir) {
230 seq_printf(s, " gpio-%-3d (%-20.20s) out %s",
231 gpio, label ?: "(none)",
232 val ? "hi" : "lo");
233 } else {
234 u8 edge_det_reg = stmpe->regs[STMPE_IDX_GPEDR_MSB] + num_banks - 1 - (offset / 8);
235 u8 rise_reg = stmpe->regs[STMPE_IDX_GPRER_LSB] - (offset / 8);
236 u8 fall_reg = stmpe->regs[STMPE_IDX_GPFER_LSB] - (offset / 8);
237 u8 irqen_reg = stmpe->regs[STMPE_IDX_IEGPIOR_LSB] - (offset / 8);
238 bool edge_det;
239 bool rise;
240 bool fall;
241 bool irqen;
242
243 ret = stmpe_reg_read(stmpe, edge_det_reg);
244 if (ret < 0)
245 return;
246 edge_det = !!(ret & mask);
247 ret = stmpe_reg_read(stmpe, rise_reg);
248 if (ret < 0)
249 return;
250 rise = !!(ret & mask);
251 ret = stmpe_reg_read(stmpe, fall_reg);
252 if (ret < 0)
253 return;
254 fall = !!(ret & mask);
255 ret = stmpe_reg_read(stmpe, irqen_reg);
256 if (ret < 0)
257 return;
258 irqen = !!(ret & mask);
259
260 seq_printf(s, " gpio-%-3d (%-20.20s) in %s %s %s%s%s",
261 gpio, label ?: "(none)",
262 val ? "hi" : "lo",
263 edge_det ? "edge-asserted" : "edge-inactive",
264 irqen ? "IRQ-enabled" : "",
265 rise ? " rising-edge-detection" : "",
266 fall ? " falling-edge-detection" : "");
267 }
268}
269
270static void stmpe_dbg_show(struct seq_file *s, struct gpio_chip *gc)
271{
272 unsigned i;
273 unsigned gpio = gc->base;
274
275 for (i = 0; i < gc->ngpio; i++, gpio++) {
276 stmpe_dbg_show_one(s, gc, i, gpio);
277 seq_printf(s, "\n");
278 }
279}
280
281static struct irq_chip stmpe_gpio_irq_chip = {
282 .name = "stmpe-gpio",
283 .irq_bus_lock = stmpe_gpio_irq_lock,
284 .irq_bus_sync_unlock = stmpe_gpio_irq_sync_unlock,
285 .irq_mask = stmpe_gpio_irq_mask,
286 .irq_unmask = stmpe_gpio_irq_unmask,
287 .irq_set_type = stmpe_gpio_irq_set_type,
288};
289
290static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
291{
292 struct stmpe_gpio *stmpe_gpio = dev;
293 struct stmpe *stmpe = stmpe_gpio->stmpe;
294 u8 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB];
295 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
296 u8 status[num_banks];
297 int ret;
298 int i;
299
300 ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status);
301 if (ret < 0)
302 return IRQ_NONE;
303
304 for (i = 0; i < num_banks; i++) {
305 int bank = num_banks - i - 1;
306 unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];
307 unsigned int stat = status[i];
308
309 stat &= enabled;
310 if (!stat)
311 continue;
312
313 while (stat) {
314 int bit = __ffs(stat);
315 int line = bank * 8 + bit;
316 int child_irq = irq_find_mapping(stmpe_gpio->chip.irqdomain,
317 line);
318
319 handle_nested_irq(child_irq);
320 stat &= ~(1 << bit);
321 }
322
323 stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
324
325 /* Edge detect register is not present on 801 */
326 if (stmpe->partnum != STMPE801)
327 stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_GPEDR_MSB]
328 + i, status[i]);
329 }
330
331 return IRQ_HANDLED;
332}
333
334static int stmpe_gpio_probe(struct platform_device *pdev)
335{
336 struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent);
337 struct device_node *np = pdev->dev.of_node;
338 struct stmpe_gpio *stmpe_gpio;
339 int ret;
340 int irq = 0;
341
342 irq = platform_get_irq(pdev, 0);
343
344 stmpe_gpio = kzalloc(sizeof(struct stmpe_gpio), GFP_KERNEL);
345 if (!stmpe_gpio)
346 return -ENOMEM;
347
348 mutex_init(&stmpe_gpio->irq_lock);
349
350 stmpe_gpio->dev = &pdev->dev;
351 stmpe_gpio->stmpe = stmpe;
352 stmpe_gpio->chip = template_chip;
353 stmpe_gpio->chip.ngpio = stmpe->num_gpios;
354 stmpe_gpio->chip.parent = &pdev->dev;
355 stmpe_gpio->chip.of_node = np;
356 stmpe_gpio->chip.base = -1;
357
358 if (IS_ENABLED(CONFIG_DEBUG_FS))
359 stmpe_gpio->chip.dbg_show = stmpe_dbg_show;
360
361 of_property_read_u32(np, "st,norequest-mask",
362 &stmpe_gpio->norequest_mask);
363
364 if (irq < 0)
365 dev_info(&pdev->dev,
366 "device configured in no-irq mode: "
367 "irqs are not available\n");
368
369 ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
370 if (ret)
371 goto out_free;
372
373 ret = gpiochip_add_data(&stmpe_gpio->chip, stmpe_gpio);
374 if (ret) {
375 dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
376 goto out_disable;
377 }
378
379 if (irq > 0) {
380 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
381 stmpe_gpio_irq, IRQF_ONESHOT,
382 "stmpe-gpio", stmpe_gpio);
383 if (ret) {
384 dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
385 goto out_disable;
386 }
387 ret = gpiochip_irqchip_add(&stmpe_gpio->chip,
388 &stmpe_gpio_irq_chip,
389 0,
390 handle_simple_irq,
391 IRQ_TYPE_NONE);
392 if (ret) {
393 dev_err(&pdev->dev,
394 "could not connect irqchip to gpiochip\n");
395 goto out_disable;
396 }
397
398 gpiochip_set_chained_irqchip(&stmpe_gpio->chip,
399 &stmpe_gpio_irq_chip,
400 irq,
401 NULL);
402 }
403
404 platform_set_drvdata(pdev, stmpe_gpio);
405
406 return 0;
407
408out_disable:
409 stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
410 gpiochip_remove(&stmpe_gpio->chip);
411out_free:
412 kfree(stmpe_gpio);
413 return ret;
414}
415
416static int stmpe_gpio_remove(struct platform_device *pdev)
417{
418 struct stmpe_gpio *stmpe_gpio = platform_get_drvdata(pdev);
419 struct stmpe *stmpe = stmpe_gpio->stmpe;
420
421 gpiochip_remove(&stmpe_gpio->chip);
422 stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
423 kfree(stmpe_gpio);
424
425 return 0;
426}
427
428static struct platform_driver stmpe_gpio_driver = {
429 .driver.name = "stmpe-gpio",
430 .driver.owner = THIS_MODULE,
431 .probe = stmpe_gpio_probe,
432 .remove = stmpe_gpio_remove,
433};
434
435static int __init stmpe_gpio_init(void)
436{
437 return platform_driver_register(&stmpe_gpio_driver);
438}
439subsys_initcall(stmpe_gpio_init);
440
441static void __exit stmpe_gpio_exit(void)
442{
443 platform_driver_unregister(&stmpe_gpio_driver);
444}
445module_exit(stmpe_gpio_exit);
446
447MODULE_LICENSE("GPL v2");
448MODULE_DESCRIPTION("STMPExxxx GPIO driver");
449MODULE_AUTHOR("Rabin Vincent <rabin.vincent@stericsson.com>");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) ST-Ericsson SA 2010
4 *
5 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
6 */
7
8#include <linux/init.h>
9#include <linux/platform_device.h>
10#include <linux/slab.h>
11#include <linux/gpio/driver.h>
12#include <linux/interrupt.h>
13#include <linux/of.h>
14#include <linux/mfd/stmpe.h>
15#include <linux/seq_file.h>
16#include <linux/bitops.h>
17
18/*
19 * These registers are modified under the irq bus lock and cached to avoid
20 * unnecessary writes in bus_sync_unlock.
21 */
22enum { REG_RE, REG_FE, REG_IE };
23
24enum { LSB, CSB, MSB };
25
26#define CACHE_NR_REGS 3
27/* No variant has more than 24 GPIOs */
28#define CACHE_NR_BANKS (24 / 8)
29
30struct stmpe_gpio {
31 struct gpio_chip chip;
32 struct stmpe *stmpe;
33 struct device *dev;
34 struct mutex irq_lock;
35 u32 norequest_mask;
36 /* Caches of interrupt control registers for bus_lock */
37 u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
38 u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
39};
40
41static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
42{
43 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
44 struct stmpe *stmpe = stmpe_gpio->stmpe;
45 u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB + (offset / 8)];
46 u8 mask = BIT(offset % 8);
47 int ret;
48
49 ret = stmpe_reg_read(stmpe, reg);
50 if (ret < 0)
51 return ret;
52
53 return !!(ret & mask);
54}
55
56static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
57{
58 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
59 struct stmpe *stmpe = stmpe_gpio->stmpe;
60 int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;
61 u8 reg = stmpe->regs[which + (offset / 8)];
62 u8 mask = BIT(offset % 8);
63
64 /*
65 * Some variants have single register for gpio set/clear functionality.
66 * For them we need to write 0 to clear and 1 to set.
67 */
68 if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB])
69 stmpe_set_bits(stmpe, reg, mask, val ? mask : 0);
70 else
71 stmpe_reg_write(stmpe, reg, mask);
72}
73
74static int stmpe_gpio_get_direction(struct gpio_chip *chip,
75 unsigned offset)
76{
77 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
78 struct stmpe *stmpe = stmpe_gpio->stmpe;
79 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
80 u8 mask = BIT(offset % 8);
81 int ret;
82
83 ret = stmpe_reg_read(stmpe, reg);
84 if (ret < 0)
85 return ret;
86
87 if (ret & mask)
88 return GPIO_LINE_DIRECTION_OUT;
89
90 return GPIO_LINE_DIRECTION_IN;
91}
92
93static int stmpe_gpio_direction_output(struct gpio_chip *chip,
94 unsigned offset, int val)
95{
96 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
97 struct stmpe *stmpe = stmpe_gpio->stmpe;
98 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];
99 u8 mask = BIT(offset % 8);
100
101 stmpe_gpio_set(chip, offset, val);
102
103 return stmpe_set_bits(stmpe, reg, mask, mask);
104}
105
106static int stmpe_gpio_direction_input(struct gpio_chip *chip,
107 unsigned offset)
108{
109 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
110 struct stmpe *stmpe = stmpe_gpio->stmpe;
111 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];
112 u8 mask = BIT(offset % 8);
113
114 return stmpe_set_bits(stmpe, reg, mask, 0);
115}
116
117static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
118{
119 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
120 struct stmpe *stmpe = stmpe_gpio->stmpe;
121
122 if (stmpe_gpio->norequest_mask & BIT(offset))
123 return -EINVAL;
124
125 return stmpe_set_altfunc(stmpe, BIT(offset), STMPE_BLOCK_GPIO);
126}
127
128static const struct gpio_chip template_chip = {
129 .label = "stmpe",
130 .owner = THIS_MODULE,
131 .get_direction = stmpe_gpio_get_direction,
132 .direction_input = stmpe_gpio_direction_input,
133 .get = stmpe_gpio_get,
134 .direction_output = stmpe_gpio_direction_output,
135 .set = stmpe_gpio_set,
136 .request = stmpe_gpio_request,
137 .can_sleep = true,
138};
139
140static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
141{
142 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
143 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
144 int offset = d->hwirq;
145 int regoffset = offset / 8;
146 int mask = BIT(offset % 8);
147
148 if (type & IRQ_TYPE_LEVEL_LOW || type & IRQ_TYPE_LEVEL_HIGH)
149 return -EINVAL;
150
151 /* STMPE801 and STMPE 1600 don't have RE and FE registers */
152 if (stmpe_gpio->stmpe->partnum == STMPE801 ||
153 stmpe_gpio->stmpe->partnum == STMPE1600)
154 return 0;
155
156 if (type & IRQ_TYPE_EDGE_RISING)
157 stmpe_gpio->regs[REG_RE][regoffset] |= mask;
158 else
159 stmpe_gpio->regs[REG_RE][regoffset] &= ~mask;
160
161 if (type & IRQ_TYPE_EDGE_FALLING)
162 stmpe_gpio->regs[REG_FE][regoffset] |= mask;
163 else
164 stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;
165
166 return 0;
167}
168
169static void stmpe_gpio_irq_lock(struct irq_data *d)
170{
171 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
172 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
173
174 mutex_lock(&stmpe_gpio->irq_lock);
175}
176
177static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
178{
179 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
180 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
181 struct stmpe *stmpe = stmpe_gpio->stmpe;
182 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
183 static const u8 regmap[CACHE_NR_REGS][CACHE_NR_BANKS] = {
184 [REG_RE][LSB] = STMPE_IDX_GPRER_LSB,
185 [REG_RE][CSB] = STMPE_IDX_GPRER_CSB,
186 [REG_RE][MSB] = STMPE_IDX_GPRER_MSB,
187 [REG_FE][LSB] = STMPE_IDX_GPFER_LSB,
188 [REG_FE][CSB] = STMPE_IDX_GPFER_CSB,
189 [REG_FE][MSB] = STMPE_IDX_GPFER_MSB,
190 [REG_IE][LSB] = STMPE_IDX_IEGPIOR_LSB,
191 [REG_IE][CSB] = STMPE_IDX_IEGPIOR_CSB,
192 [REG_IE][MSB] = STMPE_IDX_IEGPIOR_MSB,
193 };
194 int i, j;
195
196 /*
197 * STMPE1600: to be able to get IRQ from pins,
198 * a read must be done on GPMR register, or a write in
199 * GPSR or GPCR registers
200 */
201 if (stmpe->partnum == STMPE1600) {
202 stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_LSB]);
203 stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_CSB]);
204 }
205
206 for (i = 0; i < CACHE_NR_REGS; i++) {
207 /* STMPE801 and STMPE1600 don't have RE and FE registers */
208 if ((stmpe->partnum == STMPE801 ||
209 stmpe->partnum == STMPE1600) &&
210 (i != REG_IE))
211 continue;
212
213 for (j = 0; j < num_banks; j++) {
214 u8 old = stmpe_gpio->oldregs[i][j];
215 u8 new = stmpe_gpio->regs[i][j];
216
217 if (new == old)
218 continue;
219
220 stmpe_gpio->oldregs[i][j] = new;
221 stmpe_reg_write(stmpe, stmpe->regs[regmap[i][j]], new);
222 }
223 }
224
225 mutex_unlock(&stmpe_gpio->irq_lock);
226}
227
228static void stmpe_gpio_irq_mask(struct irq_data *d)
229{
230 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
231 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
232 int offset = d->hwirq;
233 int regoffset = offset / 8;
234 int mask = BIT(offset % 8);
235
236 stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
237}
238
239static void stmpe_gpio_irq_unmask(struct irq_data *d)
240{
241 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
242 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
243 int offset = d->hwirq;
244 int regoffset = offset / 8;
245 int mask = BIT(offset % 8);
246
247 stmpe_gpio->regs[REG_IE][regoffset] |= mask;
248}
249
250static void stmpe_dbg_show_one(struct seq_file *s,
251 struct gpio_chip *gc,
252 unsigned offset, unsigned gpio)
253{
254 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
255 struct stmpe *stmpe = stmpe_gpio->stmpe;
256 const char *label = gpiochip_is_requested(gc, offset);
257 bool val = !!stmpe_gpio_get(gc, offset);
258 u8 bank = offset / 8;
259 u8 dir_reg = stmpe->regs[STMPE_IDX_GPDR_LSB + bank];
260 u8 mask = BIT(offset % 8);
261 int ret;
262 u8 dir;
263
264 ret = stmpe_reg_read(stmpe, dir_reg);
265 if (ret < 0)
266 return;
267 dir = !!(ret & mask);
268
269 if (dir) {
270 seq_printf(s, " gpio-%-3d (%-20.20s) out %s",
271 gpio, label ?: "(none)",
272 val ? "hi" : "lo");
273 } else {
274 u8 edge_det_reg;
275 u8 rise_reg;
276 u8 fall_reg;
277 u8 irqen_reg;
278
279 static const char * const edge_det_values[] = {
280 "edge-inactive",
281 "edge-asserted",
282 "not-supported"
283 };
284 static const char * const rise_values[] = {
285 "no-rising-edge-detection",
286 "rising-edge-detection",
287 "not-supported"
288 };
289 static const char * const fall_values[] = {
290 "no-falling-edge-detection",
291 "falling-edge-detection",
292 "not-supported"
293 };
294 #define NOT_SUPPORTED_IDX 2
295 u8 edge_det = NOT_SUPPORTED_IDX;
296 u8 rise = NOT_SUPPORTED_IDX;
297 u8 fall = NOT_SUPPORTED_IDX;
298 bool irqen;
299
300 switch (stmpe->partnum) {
301 case STMPE610:
302 case STMPE811:
303 case STMPE1601:
304 case STMPE2401:
305 case STMPE2403:
306 edge_det_reg = stmpe->regs[STMPE_IDX_GPEDR_LSB + bank];
307 ret = stmpe_reg_read(stmpe, edge_det_reg);
308 if (ret < 0)
309 return;
310 edge_det = !!(ret & mask);
311 fallthrough;
312 case STMPE1801:
313 rise_reg = stmpe->regs[STMPE_IDX_GPRER_LSB + bank];
314 fall_reg = stmpe->regs[STMPE_IDX_GPFER_LSB + bank];
315
316 ret = stmpe_reg_read(stmpe, rise_reg);
317 if (ret < 0)
318 return;
319 rise = !!(ret & mask);
320 ret = stmpe_reg_read(stmpe, fall_reg);
321 if (ret < 0)
322 return;
323 fall = !!(ret & mask);
324 fallthrough;
325 case STMPE801:
326 case STMPE1600:
327 irqen_reg = stmpe->regs[STMPE_IDX_IEGPIOR_LSB + bank];
328 break;
329
330 default:
331 return;
332 }
333
334 ret = stmpe_reg_read(stmpe, irqen_reg);
335 if (ret < 0)
336 return;
337 irqen = !!(ret & mask);
338
339 seq_printf(s, " gpio-%-3d (%-20.20s) in %s %13s %13s %25s %25s",
340 gpio, label ?: "(none)",
341 val ? "hi" : "lo",
342 edge_det_values[edge_det],
343 irqen ? "IRQ-enabled" : "IRQ-disabled",
344 rise_values[rise],
345 fall_values[fall]);
346 }
347}
348
349static void stmpe_dbg_show(struct seq_file *s, struct gpio_chip *gc)
350{
351 unsigned i;
352 unsigned gpio = gc->base;
353
354 for (i = 0; i < gc->ngpio; i++, gpio++) {
355 stmpe_dbg_show_one(s, gc, i, gpio);
356 seq_putc(s, '\n');
357 }
358}
359
360static struct irq_chip stmpe_gpio_irq_chip = {
361 .name = "stmpe-gpio",
362 .irq_bus_lock = stmpe_gpio_irq_lock,
363 .irq_bus_sync_unlock = stmpe_gpio_irq_sync_unlock,
364 .irq_mask = stmpe_gpio_irq_mask,
365 .irq_unmask = stmpe_gpio_irq_unmask,
366 .irq_set_type = stmpe_gpio_irq_set_type,
367};
368
369#define MAX_GPIOS 24
370
371static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
372{
373 struct stmpe_gpio *stmpe_gpio = dev;
374 struct stmpe *stmpe = stmpe_gpio->stmpe;
375 u8 statmsbreg;
376 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
377 u8 status[DIV_ROUND_UP(MAX_GPIOS, 8)];
378 int ret;
379 int i;
380
381 /*
382 * the stmpe_block_read() call below, imposes to set statmsbreg
383 * with the register located at the lowest address. As STMPE1600
384 * variant is the only one which respect registers address's order
385 * (LSB regs located at lowest address than MSB ones) whereas all
386 * the others have a registers layout with MSB located before the
387 * LSB regs.
388 */
389 if (stmpe->partnum == STMPE1600)
390 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_LSB];
391 else
392 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB];
393
394 ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status);
395 if (ret < 0)
396 return IRQ_NONE;
397
398 for (i = 0; i < num_banks; i++) {
399 int bank = (stmpe_gpio->stmpe->partnum == STMPE1600) ? i :
400 num_banks - i - 1;
401 unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];
402 unsigned int stat = status[i];
403
404 stat &= enabled;
405 if (!stat)
406 continue;
407
408 while (stat) {
409 int bit = __ffs(stat);
410 int line = bank * 8 + bit;
411 int child_irq = irq_find_mapping(stmpe_gpio->chip.irq.domain,
412 line);
413
414 handle_nested_irq(child_irq);
415 stat &= ~BIT(bit);
416 }
417
418 /*
419 * interrupt status register write has no effect on
420 * 801/1801/1600, bits are cleared when read.
421 * Edge detect register is not present on 801/1600/1801
422 */
423 if (stmpe->partnum != STMPE801 && stmpe->partnum != STMPE1600 &&
424 stmpe->partnum != STMPE1801) {
425 stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
426 stmpe_reg_write(stmpe,
427 stmpe->regs[STMPE_IDX_GPEDR_MSB] + i,
428 status[i]);
429 }
430 }
431
432 return IRQ_HANDLED;
433}
434
435static void stmpe_init_irq_valid_mask(struct gpio_chip *gc,
436 unsigned long *valid_mask,
437 unsigned int ngpios)
438{
439 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
440 int i;
441
442 if (!stmpe_gpio->norequest_mask)
443 return;
444
445 /* Forbid unused lines to be mapped as IRQs */
446 for (i = 0; i < sizeof(u32); i++) {
447 if (stmpe_gpio->norequest_mask & BIT(i))
448 clear_bit(i, valid_mask);
449 }
450}
451
452static void stmpe_gpio_disable(void *stmpe)
453{
454 stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
455}
456
457static int stmpe_gpio_probe(struct platform_device *pdev)
458{
459 struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent);
460 struct device_node *np = pdev->dev.of_node;
461 struct stmpe_gpio *stmpe_gpio;
462 int ret, irq;
463
464 if (stmpe->num_gpios > MAX_GPIOS) {
465 dev_err(&pdev->dev, "Need to increase maximum GPIO number\n");
466 return -EINVAL;
467 }
468
469 stmpe_gpio = devm_kzalloc(&pdev->dev, sizeof(*stmpe_gpio), GFP_KERNEL);
470 if (!stmpe_gpio)
471 return -ENOMEM;
472
473 mutex_init(&stmpe_gpio->irq_lock);
474
475 stmpe_gpio->dev = &pdev->dev;
476 stmpe_gpio->stmpe = stmpe;
477 stmpe_gpio->chip = template_chip;
478 stmpe_gpio->chip.ngpio = stmpe->num_gpios;
479 stmpe_gpio->chip.parent = &pdev->dev;
480 stmpe_gpio->chip.base = -1;
481
482 if (IS_ENABLED(CONFIG_DEBUG_FS))
483 stmpe_gpio->chip.dbg_show = stmpe_dbg_show;
484
485 of_property_read_u32(np, "st,norequest-mask",
486 &stmpe_gpio->norequest_mask);
487
488 irq = platform_get_irq(pdev, 0);
489 if (irq < 0)
490 dev_info(&pdev->dev,
491 "device configured in no-irq mode: "
492 "irqs are not available\n");
493
494 ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
495 if (ret)
496 return ret;
497
498 ret = devm_add_action_or_reset(&pdev->dev, stmpe_gpio_disable, stmpe);
499 if (ret)
500 return ret;
501
502 if (irq > 0) {
503 struct gpio_irq_chip *girq;
504
505 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
506 stmpe_gpio_irq, IRQF_ONESHOT,
507 "stmpe-gpio", stmpe_gpio);
508 if (ret) {
509 dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
510 return ret;
511 }
512
513 girq = &stmpe_gpio->chip.irq;
514 girq->chip = &stmpe_gpio_irq_chip;
515 /* This will let us handle the parent IRQ in the driver */
516 girq->parent_handler = NULL;
517 girq->num_parents = 0;
518 girq->parents = NULL;
519 girq->default_type = IRQ_TYPE_NONE;
520 girq->handler = handle_simple_irq;
521 girq->threaded = true;
522 girq->init_valid_mask = stmpe_init_irq_valid_mask;
523 }
524
525 return devm_gpiochip_add_data(&pdev->dev, &stmpe_gpio->chip, stmpe_gpio);
526}
527
528static struct platform_driver stmpe_gpio_driver = {
529 .driver = {
530 .suppress_bind_attrs = true,
531 .name = "stmpe-gpio",
532 },
533 .probe = stmpe_gpio_probe,
534};
535
536static int __init stmpe_gpio_init(void)
537{
538 return platform_driver_register(&stmpe_gpio_driver);
539}
540subsys_initcall(stmpe_gpio_init);