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1/*
2 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
6 * Jaswinder Singh <jassi.brar@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#include <linux/kernel.h>
15#include <linux/io.h>
16#include <linux/init.h>
17#include <linux/slab.h>
18#include <linux/module.h>
19#include <linux/string.h>
20#include <linux/delay.h>
21#include <linux/interrupt.h>
22#include <linux/dma-mapping.h>
23#include <linux/dmaengine.h>
24#include <linux/amba/bus.h>
25#include <linux/amba/pl330.h>
26#include <linux/scatterlist.h>
27#include <linux/of.h>
28#include <linux/of_dma.h>
29#include <linux/err.h>
30#include <linux/pm_runtime.h>
31
32#include "dmaengine.h"
33#define PL330_MAX_CHAN 8
34#define PL330_MAX_IRQS 32
35#define PL330_MAX_PERI 32
36#define PL330_MAX_BURST 16
37
38#define PL330_QUIRK_BROKEN_NO_FLUSHP BIT(0)
39
40enum pl330_cachectrl {
41 CCTRL0, /* Noncacheable and nonbufferable */
42 CCTRL1, /* Bufferable only */
43 CCTRL2, /* Cacheable, but do not allocate */
44 CCTRL3, /* Cacheable and bufferable, but do not allocate */
45 INVALID1, /* AWCACHE = 0x1000 */
46 INVALID2,
47 CCTRL6, /* Cacheable write-through, allocate on writes only */
48 CCTRL7, /* Cacheable write-back, allocate on writes only */
49};
50
51enum pl330_byteswap {
52 SWAP_NO,
53 SWAP_2,
54 SWAP_4,
55 SWAP_8,
56 SWAP_16,
57};
58
59/* Register and Bit field Definitions */
60#define DS 0x0
61#define DS_ST_STOP 0x0
62#define DS_ST_EXEC 0x1
63#define DS_ST_CMISS 0x2
64#define DS_ST_UPDTPC 0x3
65#define DS_ST_WFE 0x4
66#define DS_ST_ATBRR 0x5
67#define DS_ST_QBUSY 0x6
68#define DS_ST_WFP 0x7
69#define DS_ST_KILL 0x8
70#define DS_ST_CMPLT 0x9
71#define DS_ST_FLTCMP 0xe
72#define DS_ST_FAULT 0xf
73
74#define DPC 0x4
75#define INTEN 0x20
76#define ES 0x24
77#define INTSTATUS 0x28
78#define INTCLR 0x2c
79#define FSM 0x30
80#define FSC 0x34
81#define FTM 0x38
82
83#define _FTC 0x40
84#define FTC(n) (_FTC + (n)*0x4)
85
86#define _CS 0x100
87#define CS(n) (_CS + (n)*0x8)
88#define CS_CNS (1 << 21)
89
90#define _CPC 0x104
91#define CPC(n) (_CPC + (n)*0x8)
92
93#define _SA 0x400
94#define SA(n) (_SA + (n)*0x20)
95
96#define _DA 0x404
97#define DA(n) (_DA + (n)*0x20)
98
99#define _CC 0x408
100#define CC(n) (_CC + (n)*0x20)
101
102#define CC_SRCINC (1 << 0)
103#define CC_DSTINC (1 << 14)
104#define CC_SRCPRI (1 << 8)
105#define CC_DSTPRI (1 << 22)
106#define CC_SRCNS (1 << 9)
107#define CC_DSTNS (1 << 23)
108#define CC_SRCIA (1 << 10)
109#define CC_DSTIA (1 << 24)
110#define CC_SRCBRSTLEN_SHFT 4
111#define CC_DSTBRSTLEN_SHFT 18
112#define CC_SRCBRSTSIZE_SHFT 1
113#define CC_DSTBRSTSIZE_SHFT 15
114#define CC_SRCCCTRL_SHFT 11
115#define CC_SRCCCTRL_MASK 0x7
116#define CC_DSTCCTRL_SHFT 25
117#define CC_DRCCCTRL_MASK 0x7
118#define CC_SWAP_SHFT 28
119
120#define _LC0 0x40c
121#define LC0(n) (_LC0 + (n)*0x20)
122
123#define _LC1 0x410
124#define LC1(n) (_LC1 + (n)*0x20)
125
126#define DBGSTATUS 0xd00
127#define DBG_BUSY (1 << 0)
128
129#define DBGCMD 0xd04
130#define DBGINST0 0xd08
131#define DBGINST1 0xd0c
132
133#define CR0 0xe00
134#define CR1 0xe04
135#define CR2 0xe08
136#define CR3 0xe0c
137#define CR4 0xe10
138#define CRD 0xe14
139
140#define PERIPH_ID 0xfe0
141#define PERIPH_REV_SHIFT 20
142#define PERIPH_REV_MASK 0xf
143#define PERIPH_REV_R0P0 0
144#define PERIPH_REV_R1P0 1
145#define PERIPH_REV_R1P1 2
146
147#define CR0_PERIPH_REQ_SET (1 << 0)
148#define CR0_BOOT_EN_SET (1 << 1)
149#define CR0_BOOT_MAN_NS (1 << 2)
150#define CR0_NUM_CHANS_SHIFT 4
151#define CR0_NUM_CHANS_MASK 0x7
152#define CR0_NUM_PERIPH_SHIFT 12
153#define CR0_NUM_PERIPH_MASK 0x1f
154#define CR0_NUM_EVENTS_SHIFT 17
155#define CR0_NUM_EVENTS_MASK 0x1f
156
157#define CR1_ICACHE_LEN_SHIFT 0
158#define CR1_ICACHE_LEN_MASK 0x7
159#define CR1_NUM_ICACHELINES_SHIFT 4
160#define CR1_NUM_ICACHELINES_MASK 0xf
161
162#define CRD_DATA_WIDTH_SHIFT 0
163#define CRD_DATA_WIDTH_MASK 0x7
164#define CRD_WR_CAP_SHIFT 4
165#define CRD_WR_CAP_MASK 0x7
166#define CRD_WR_Q_DEP_SHIFT 8
167#define CRD_WR_Q_DEP_MASK 0xf
168#define CRD_RD_CAP_SHIFT 12
169#define CRD_RD_CAP_MASK 0x7
170#define CRD_RD_Q_DEP_SHIFT 16
171#define CRD_RD_Q_DEP_MASK 0xf
172#define CRD_DATA_BUFF_SHIFT 20
173#define CRD_DATA_BUFF_MASK 0x3ff
174
175#define PART 0x330
176#define DESIGNER 0x41
177#define REVISION 0x0
178#define INTEG_CFG 0x0
179#define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12))
180
181#define PL330_STATE_STOPPED (1 << 0)
182#define PL330_STATE_EXECUTING (1 << 1)
183#define PL330_STATE_WFE (1 << 2)
184#define PL330_STATE_FAULTING (1 << 3)
185#define PL330_STATE_COMPLETING (1 << 4)
186#define PL330_STATE_WFP (1 << 5)
187#define PL330_STATE_KILLING (1 << 6)
188#define PL330_STATE_FAULT_COMPLETING (1 << 7)
189#define PL330_STATE_CACHEMISS (1 << 8)
190#define PL330_STATE_UPDTPC (1 << 9)
191#define PL330_STATE_ATBARRIER (1 << 10)
192#define PL330_STATE_QUEUEBUSY (1 << 11)
193#define PL330_STATE_INVALID (1 << 15)
194
195#define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \
196 | PL330_STATE_WFE | PL330_STATE_FAULTING)
197
198#define CMD_DMAADDH 0x54
199#define CMD_DMAEND 0x00
200#define CMD_DMAFLUSHP 0x35
201#define CMD_DMAGO 0xa0
202#define CMD_DMALD 0x04
203#define CMD_DMALDP 0x25
204#define CMD_DMALP 0x20
205#define CMD_DMALPEND 0x28
206#define CMD_DMAKILL 0x01
207#define CMD_DMAMOV 0xbc
208#define CMD_DMANOP 0x18
209#define CMD_DMARMB 0x12
210#define CMD_DMASEV 0x34
211#define CMD_DMAST 0x08
212#define CMD_DMASTP 0x29
213#define CMD_DMASTZ 0x0c
214#define CMD_DMAWFE 0x36
215#define CMD_DMAWFP 0x30
216#define CMD_DMAWMB 0x13
217
218#define SZ_DMAADDH 3
219#define SZ_DMAEND 1
220#define SZ_DMAFLUSHP 2
221#define SZ_DMALD 1
222#define SZ_DMALDP 2
223#define SZ_DMALP 2
224#define SZ_DMALPEND 2
225#define SZ_DMAKILL 1
226#define SZ_DMAMOV 6
227#define SZ_DMANOP 1
228#define SZ_DMARMB 1
229#define SZ_DMASEV 2
230#define SZ_DMAST 1
231#define SZ_DMASTP 2
232#define SZ_DMASTZ 1
233#define SZ_DMAWFE 2
234#define SZ_DMAWFP 2
235#define SZ_DMAWMB 1
236#define SZ_DMAGO 6
237
238#define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1)
239#define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7))
240
241#define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr))
242#define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr))
243
244/*
245 * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req
246 * at 1byte/burst for P<->M and M<->M respectively.
247 * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req
248 * should be enough for P<->M and M<->M respectively.
249 */
250#define MCODE_BUFF_PER_REQ 256
251
252/* Use this _only_ to wait on transient states */
253#define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax();
254
255#ifdef PL330_DEBUG_MCGEN
256static unsigned cmd_line;
257#define PL330_DBGCMD_DUMP(off, x...) do { \
258 printk("%x:", cmd_line); \
259 printk(x); \
260 cmd_line += off; \
261 } while (0)
262#define PL330_DBGMC_START(addr) (cmd_line = addr)
263#else
264#define PL330_DBGCMD_DUMP(off, x...) do {} while (0)
265#define PL330_DBGMC_START(addr) do {} while (0)
266#endif
267
268/* The number of default descriptors */
269
270#define NR_DEFAULT_DESC 16
271
272/* Delay for runtime PM autosuspend, ms */
273#define PL330_AUTOSUSPEND_DELAY 20
274
275/* Populated by the PL330 core driver for DMA API driver's info */
276struct pl330_config {
277 u32 periph_id;
278#define DMAC_MODE_NS (1 << 0)
279 unsigned int mode;
280 unsigned int data_bus_width:10; /* In number of bits */
281 unsigned int data_buf_dep:11;
282 unsigned int num_chan:4;
283 unsigned int num_peri:6;
284 u32 peri_ns;
285 unsigned int num_events:6;
286 u32 irq_ns;
287};
288
289/**
290 * Request Configuration.
291 * The PL330 core does not modify this and uses the last
292 * working configuration if the request doesn't provide any.
293 *
294 * The Client may want to provide this info only for the
295 * first request and a request with new settings.
296 */
297struct pl330_reqcfg {
298 /* Address Incrementing */
299 unsigned dst_inc:1;
300 unsigned src_inc:1;
301
302 /*
303 * For now, the SRC & DST protection levels
304 * and burst size/length are assumed same.
305 */
306 bool nonsecure;
307 bool privileged;
308 bool insnaccess;
309 unsigned brst_len:5;
310 unsigned brst_size:3; /* in power of 2 */
311
312 enum pl330_cachectrl dcctl;
313 enum pl330_cachectrl scctl;
314 enum pl330_byteswap swap;
315 struct pl330_config *pcfg;
316};
317
318/*
319 * One cycle of DMAC operation.
320 * There may be more than one xfer in a request.
321 */
322struct pl330_xfer {
323 u32 src_addr;
324 u32 dst_addr;
325 /* Size to xfer */
326 u32 bytes;
327};
328
329/* The xfer callbacks are made with one of these arguments. */
330enum pl330_op_err {
331 /* The all xfers in the request were success. */
332 PL330_ERR_NONE,
333 /* If req aborted due to global error. */
334 PL330_ERR_ABORT,
335 /* If req failed due to problem with Channel. */
336 PL330_ERR_FAIL,
337};
338
339enum dmamov_dst {
340 SAR = 0,
341 CCR,
342 DAR,
343};
344
345enum pl330_dst {
346 SRC = 0,
347 DST,
348};
349
350enum pl330_cond {
351 SINGLE,
352 BURST,
353 ALWAYS,
354};
355
356struct dma_pl330_desc;
357
358struct _pl330_req {
359 u32 mc_bus;
360 void *mc_cpu;
361 struct dma_pl330_desc *desc;
362};
363
364/* ToBeDone for tasklet */
365struct _pl330_tbd {
366 bool reset_dmac;
367 bool reset_mngr;
368 u8 reset_chan;
369};
370
371/* A DMAC Thread */
372struct pl330_thread {
373 u8 id;
374 int ev;
375 /* If the channel is not yet acquired by any client */
376 bool free;
377 /* Parent DMAC */
378 struct pl330_dmac *dmac;
379 /* Only two at a time */
380 struct _pl330_req req[2];
381 /* Index of the last enqueued request */
382 unsigned lstenq;
383 /* Index of the last submitted request or -1 if the DMA is stopped */
384 int req_running;
385};
386
387enum pl330_dmac_state {
388 UNINIT,
389 INIT,
390 DYING,
391};
392
393enum desc_status {
394 /* In the DMAC pool */
395 FREE,
396 /*
397 * Allocated to some channel during prep_xxx
398 * Also may be sitting on the work_list.
399 */
400 PREP,
401 /*
402 * Sitting on the work_list and already submitted
403 * to the PL330 core. Not more than two descriptors
404 * of a channel can be BUSY at any time.
405 */
406 BUSY,
407 /*
408 * Sitting on the channel work_list but xfer done
409 * by PL330 core
410 */
411 DONE,
412};
413
414struct dma_pl330_chan {
415 /* Schedule desc completion */
416 struct tasklet_struct task;
417
418 /* DMA-Engine Channel */
419 struct dma_chan chan;
420
421 /* List of submitted descriptors */
422 struct list_head submitted_list;
423 /* List of issued descriptors */
424 struct list_head work_list;
425 /* List of completed descriptors */
426 struct list_head completed_list;
427
428 /* Pointer to the DMAC that manages this channel,
429 * NULL if the channel is available to be acquired.
430 * As the parent, this DMAC also provides descriptors
431 * to the channel.
432 */
433 struct pl330_dmac *dmac;
434
435 /* To protect channel manipulation */
436 spinlock_t lock;
437
438 /*
439 * Hardware channel thread of PL330 DMAC. NULL if the channel is
440 * available.
441 */
442 struct pl330_thread *thread;
443
444 /* For D-to-M and M-to-D channels */
445 int burst_sz; /* the peripheral fifo width */
446 int burst_len; /* the number of burst */
447 dma_addr_t fifo_addr;
448
449 /* for cyclic capability */
450 bool cyclic;
451};
452
453struct pl330_dmac {
454 /* DMA-Engine Device */
455 struct dma_device ddma;
456
457 /* Holds info about sg limitations */
458 struct device_dma_parameters dma_parms;
459
460 /* Pool of descriptors available for the DMAC's channels */
461 struct list_head desc_pool;
462 /* To protect desc_pool manipulation */
463 spinlock_t pool_lock;
464
465 /* Size of MicroCode buffers for each channel. */
466 unsigned mcbufsz;
467 /* ioremap'ed address of PL330 registers. */
468 void __iomem *base;
469 /* Populated by the PL330 core driver during pl330_add */
470 struct pl330_config pcfg;
471
472 spinlock_t lock;
473 /* Maximum possible events/irqs */
474 int events[32];
475 /* BUS address of MicroCode buffer */
476 dma_addr_t mcode_bus;
477 /* CPU address of MicroCode buffer */
478 void *mcode_cpu;
479 /* List of all Channel threads */
480 struct pl330_thread *channels;
481 /* Pointer to the MANAGER thread */
482 struct pl330_thread *manager;
483 /* To handle bad news in interrupt */
484 struct tasklet_struct tasks;
485 struct _pl330_tbd dmac_tbd;
486 /* State of DMAC operation */
487 enum pl330_dmac_state state;
488 /* Holds list of reqs with due callbacks */
489 struct list_head req_done;
490
491 /* Peripheral channels connected to this DMAC */
492 unsigned int num_peripherals;
493 struct dma_pl330_chan *peripherals; /* keep at end */
494 int quirks;
495};
496
497static struct pl330_of_quirks {
498 char *quirk;
499 int id;
500} of_quirks[] = {
501 {
502 .quirk = "arm,pl330-broken-no-flushp",
503 .id = PL330_QUIRK_BROKEN_NO_FLUSHP,
504 }
505};
506
507struct dma_pl330_desc {
508 /* To attach to a queue as child */
509 struct list_head node;
510
511 /* Descriptor for the DMA Engine API */
512 struct dma_async_tx_descriptor txd;
513
514 /* Xfer for PL330 core */
515 struct pl330_xfer px;
516
517 struct pl330_reqcfg rqcfg;
518
519 enum desc_status status;
520
521 int bytes_requested;
522 bool last;
523
524 /* The channel which currently holds this desc */
525 struct dma_pl330_chan *pchan;
526
527 enum dma_transfer_direction rqtype;
528 /* Index of peripheral for the xfer. */
529 unsigned peri:5;
530 /* Hook to attach to DMAC's list of reqs with due callback */
531 struct list_head rqd;
532};
533
534struct _xfer_spec {
535 u32 ccr;
536 struct dma_pl330_desc *desc;
537};
538
539static inline bool _queue_empty(struct pl330_thread *thrd)
540{
541 return thrd->req[0].desc == NULL && thrd->req[1].desc == NULL;
542}
543
544static inline bool _queue_full(struct pl330_thread *thrd)
545{
546 return thrd->req[0].desc != NULL && thrd->req[1].desc != NULL;
547}
548
549static inline bool is_manager(struct pl330_thread *thrd)
550{
551 return thrd->dmac->manager == thrd;
552}
553
554/* If manager of the thread is in Non-Secure mode */
555static inline bool _manager_ns(struct pl330_thread *thrd)
556{
557 return (thrd->dmac->pcfg.mode & DMAC_MODE_NS) ? true : false;
558}
559
560static inline u32 get_revision(u32 periph_id)
561{
562 return (periph_id >> PERIPH_REV_SHIFT) & PERIPH_REV_MASK;
563}
564
565static inline u32 _emit_ADDH(unsigned dry_run, u8 buf[],
566 enum pl330_dst da, u16 val)
567{
568 if (dry_run)
569 return SZ_DMAADDH;
570
571 buf[0] = CMD_DMAADDH;
572 buf[0] |= (da << 1);
573 *((__le16 *)&buf[1]) = cpu_to_le16(val);
574
575 PL330_DBGCMD_DUMP(SZ_DMAADDH, "\tDMAADDH %s %u\n",
576 da == 1 ? "DA" : "SA", val);
577
578 return SZ_DMAADDH;
579}
580
581static inline u32 _emit_END(unsigned dry_run, u8 buf[])
582{
583 if (dry_run)
584 return SZ_DMAEND;
585
586 buf[0] = CMD_DMAEND;
587
588 PL330_DBGCMD_DUMP(SZ_DMAEND, "\tDMAEND\n");
589
590 return SZ_DMAEND;
591}
592
593static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri)
594{
595 if (dry_run)
596 return SZ_DMAFLUSHP;
597
598 buf[0] = CMD_DMAFLUSHP;
599
600 peri &= 0x1f;
601 peri <<= 3;
602 buf[1] = peri;
603
604 PL330_DBGCMD_DUMP(SZ_DMAFLUSHP, "\tDMAFLUSHP %u\n", peri >> 3);
605
606 return SZ_DMAFLUSHP;
607}
608
609static inline u32 _emit_LD(unsigned dry_run, u8 buf[], enum pl330_cond cond)
610{
611 if (dry_run)
612 return SZ_DMALD;
613
614 buf[0] = CMD_DMALD;
615
616 if (cond == SINGLE)
617 buf[0] |= (0 << 1) | (1 << 0);
618 else if (cond == BURST)
619 buf[0] |= (1 << 1) | (1 << 0);
620
621 PL330_DBGCMD_DUMP(SZ_DMALD, "\tDMALD%c\n",
622 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
623
624 return SZ_DMALD;
625}
626
627static inline u32 _emit_LDP(unsigned dry_run, u8 buf[],
628 enum pl330_cond cond, u8 peri)
629{
630 if (dry_run)
631 return SZ_DMALDP;
632
633 buf[0] = CMD_DMALDP;
634
635 if (cond == BURST)
636 buf[0] |= (1 << 1);
637
638 peri &= 0x1f;
639 peri <<= 3;
640 buf[1] = peri;
641
642 PL330_DBGCMD_DUMP(SZ_DMALDP, "\tDMALDP%c %u\n",
643 cond == SINGLE ? 'S' : 'B', peri >> 3);
644
645 return SZ_DMALDP;
646}
647
648static inline u32 _emit_LP(unsigned dry_run, u8 buf[],
649 unsigned loop, u8 cnt)
650{
651 if (dry_run)
652 return SZ_DMALP;
653
654 buf[0] = CMD_DMALP;
655
656 if (loop)
657 buf[0] |= (1 << 1);
658
659 cnt--; /* DMAC increments by 1 internally */
660 buf[1] = cnt;
661
662 PL330_DBGCMD_DUMP(SZ_DMALP, "\tDMALP_%c %u\n", loop ? '1' : '0', cnt);
663
664 return SZ_DMALP;
665}
666
667struct _arg_LPEND {
668 enum pl330_cond cond;
669 bool forever;
670 unsigned loop;
671 u8 bjump;
672};
673
674static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[],
675 const struct _arg_LPEND *arg)
676{
677 enum pl330_cond cond = arg->cond;
678 bool forever = arg->forever;
679 unsigned loop = arg->loop;
680 u8 bjump = arg->bjump;
681
682 if (dry_run)
683 return SZ_DMALPEND;
684
685 buf[0] = CMD_DMALPEND;
686
687 if (loop)
688 buf[0] |= (1 << 2);
689
690 if (!forever)
691 buf[0] |= (1 << 4);
692
693 if (cond == SINGLE)
694 buf[0] |= (0 << 1) | (1 << 0);
695 else if (cond == BURST)
696 buf[0] |= (1 << 1) | (1 << 0);
697
698 buf[1] = bjump;
699
700 PL330_DBGCMD_DUMP(SZ_DMALPEND, "\tDMALP%s%c_%c bjmpto_%x\n",
701 forever ? "FE" : "END",
702 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'),
703 loop ? '1' : '0',
704 bjump);
705
706 return SZ_DMALPEND;
707}
708
709static inline u32 _emit_KILL(unsigned dry_run, u8 buf[])
710{
711 if (dry_run)
712 return SZ_DMAKILL;
713
714 buf[0] = CMD_DMAKILL;
715
716 return SZ_DMAKILL;
717}
718
719static inline u32 _emit_MOV(unsigned dry_run, u8 buf[],
720 enum dmamov_dst dst, u32 val)
721{
722 if (dry_run)
723 return SZ_DMAMOV;
724
725 buf[0] = CMD_DMAMOV;
726 buf[1] = dst;
727 *((__le32 *)&buf[2]) = cpu_to_le32(val);
728
729 PL330_DBGCMD_DUMP(SZ_DMAMOV, "\tDMAMOV %s 0x%x\n",
730 dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val);
731
732 return SZ_DMAMOV;
733}
734
735static inline u32 _emit_NOP(unsigned dry_run, u8 buf[])
736{
737 if (dry_run)
738 return SZ_DMANOP;
739
740 buf[0] = CMD_DMANOP;
741
742 PL330_DBGCMD_DUMP(SZ_DMANOP, "\tDMANOP\n");
743
744 return SZ_DMANOP;
745}
746
747static inline u32 _emit_RMB(unsigned dry_run, u8 buf[])
748{
749 if (dry_run)
750 return SZ_DMARMB;
751
752 buf[0] = CMD_DMARMB;
753
754 PL330_DBGCMD_DUMP(SZ_DMARMB, "\tDMARMB\n");
755
756 return SZ_DMARMB;
757}
758
759static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev)
760{
761 if (dry_run)
762 return SZ_DMASEV;
763
764 buf[0] = CMD_DMASEV;
765
766 ev &= 0x1f;
767 ev <<= 3;
768 buf[1] = ev;
769
770 PL330_DBGCMD_DUMP(SZ_DMASEV, "\tDMASEV %u\n", ev >> 3);
771
772 return SZ_DMASEV;
773}
774
775static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond)
776{
777 if (dry_run)
778 return SZ_DMAST;
779
780 buf[0] = CMD_DMAST;
781
782 if (cond == SINGLE)
783 buf[0] |= (0 << 1) | (1 << 0);
784 else if (cond == BURST)
785 buf[0] |= (1 << 1) | (1 << 0);
786
787 PL330_DBGCMD_DUMP(SZ_DMAST, "\tDMAST%c\n",
788 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
789
790 return SZ_DMAST;
791}
792
793static inline u32 _emit_STP(unsigned dry_run, u8 buf[],
794 enum pl330_cond cond, u8 peri)
795{
796 if (dry_run)
797 return SZ_DMASTP;
798
799 buf[0] = CMD_DMASTP;
800
801 if (cond == BURST)
802 buf[0] |= (1 << 1);
803
804 peri &= 0x1f;
805 peri <<= 3;
806 buf[1] = peri;
807
808 PL330_DBGCMD_DUMP(SZ_DMASTP, "\tDMASTP%c %u\n",
809 cond == SINGLE ? 'S' : 'B', peri >> 3);
810
811 return SZ_DMASTP;
812}
813
814static inline u32 _emit_STZ(unsigned dry_run, u8 buf[])
815{
816 if (dry_run)
817 return SZ_DMASTZ;
818
819 buf[0] = CMD_DMASTZ;
820
821 PL330_DBGCMD_DUMP(SZ_DMASTZ, "\tDMASTZ\n");
822
823 return SZ_DMASTZ;
824}
825
826static inline u32 _emit_WFE(unsigned dry_run, u8 buf[], u8 ev,
827 unsigned invalidate)
828{
829 if (dry_run)
830 return SZ_DMAWFE;
831
832 buf[0] = CMD_DMAWFE;
833
834 ev &= 0x1f;
835 ev <<= 3;
836 buf[1] = ev;
837
838 if (invalidate)
839 buf[1] |= (1 << 1);
840
841 PL330_DBGCMD_DUMP(SZ_DMAWFE, "\tDMAWFE %u%s\n",
842 ev >> 3, invalidate ? ", I" : "");
843
844 return SZ_DMAWFE;
845}
846
847static inline u32 _emit_WFP(unsigned dry_run, u8 buf[],
848 enum pl330_cond cond, u8 peri)
849{
850 if (dry_run)
851 return SZ_DMAWFP;
852
853 buf[0] = CMD_DMAWFP;
854
855 if (cond == SINGLE)
856 buf[0] |= (0 << 1) | (0 << 0);
857 else if (cond == BURST)
858 buf[0] |= (1 << 1) | (0 << 0);
859 else
860 buf[0] |= (0 << 1) | (1 << 0);
861
862 peri &= 0x1f;
863 peri <<= 3;
864 buf[1] = peri;
865
866 PL330_DBGCMD_DUMP(SZ_DMAWFP, "\tDMAWFP%c %u\n",
867 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'P'), peri >> 3);
868
869 return SZ_DMAWFP;
870}
871
872static inline u32 _emit_WMB(unsigned dry_run, u8 buf[])
873{
874 if (dry_run)
875 return SZ_DMAWMB;
876
877 buf[0] = CMD_DMAWMB;
878
879 PL330_DBGCMD_DUMP(SZ_DMAWMB, "\tDMAWMB\n");
880
881 return SZ_DMAWMB;
882}
883
884struct _arg_GO {
885 u8 chan;
886 u32 addr;
887 unsigned ns;
888};
889
890static inline u32 _emit_GO(unsigned dry_run, u8 buf[],
891 const struct _arg_GO *arg)
892{
893 u8 chan = arg->chan;
894 u32 addr = arg->addr;
895 unsigned ns = arg->ns;
896
897 if (dry_run)
898 return SZ_DMAGO;
899
900 buf[0] = CMD_DMAGO;
901 buf[0] |= (ns << 1);
902
903 buf[1] = chan & 0x7;
904
905 *((__le32 *)&buf[2]) = cpu_to_le32(addr);
906
907 return SZ_DMAGO;
908}
909
910#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
911
912/* Returns Time-Out */
913static bool _until_dmac_idle(struct pl330_thread *thrd)
914{
915 void __iomem *regs = thrd->dmac->base;
916 unsigned long loops = msecs_to_loops(5);
917
918 do {
919 /* Until Manager is Idle */
920 if (!(readl(regs + DBGSTATUS) & DBG_BUSY))
921 break;
922
923 cpu_relax();
924 } while (--loops);
925
926 if (!loops)
927 return true;
928
929 return false;
930}
931
932static inline void _execute_DBGINSN(struct pl330_thread *thrd,
933 u8 insn[], bool as_manager)
934{
935 void __iomem *regs = thrd->dmac->base;
936 u32 val;
937
938 val = (insn[0] << 16) | (insn[1] << 24);
939 if (!as_manager) {
940 val |= (1 << 0);
941 val |= (thrd->id << 8); /* Channel Number */
942 }
943 writel(val, regs + DBGINST0);
944
945 val = le32_to_cpu(*((__le32 *)&insn[2]));
946 writel(val, regs + DBGINST1);
947
948 /* If timed out due to halted state-machine */
949 if (_until_dmac_idle(thrd)) {
950 dev_err(thrd->dmac->ddma.dev, "DMAC halted!\n");
951 return;
952 }
953
954 /* Get going */
955 writel(0, regs + DBGCMD);
956}
957
958static inline u32 _state(struct pl330_thread *thrd)
959{
960 void __iomem *regs = thrd->dmac->base;
961 u32 val;
962
963 if (is_manager(thrd))
964 val = readl(regs + DS) & 0xf;
965 else
966 val = readl(regs + CS(thrd->id)) & 0xf;
967
968 switch (val) {
969 case DS_ST_STOP:
970 return PL330_STATE_STOPPED;
971 case DS_ST_EXEC:
972 return PL330_STATE_EXECUTING;
973 case DS_ST_CMISS:
974 return PL330_STATE_CACHEMISS;
975 case DS_ST_UPDTPC:
976 return PL330_STATE_UPDTPC;
977 case DS_ST_WFE:
978 return PL330_STATE_WFE;
979 case DS_ST_FAULT:
980 return PL330_STATE_FAULTING;
981 case DS_ST_ATBRR:
982 if (is_manager(thrd))
983 return PL330_STATE_INVALID;
984 else
985 return PL330_STATE_ATBARRIER;
986 case DS_ST_QBUSY:
987 if (is_manager(thrd))
988 return PL330_STATE_INVALID;
989 else
990 return PL330_STATE_QUEUEBUSY;
991 case DS_ST_WFP:
992 if (is_manager(thrd))
993 return PL330_STATE_INVALID;
994 else
995 return PL330_STATE_WFP;
996 case DS_ST_KILL:
997 if (is_manager(thrd))
998 return PL330_STATE_INVALID;
999 else
1000 return PL330_STATE_KILLING;
1001 case DS_ST_CMPLT:
1002 if (is_manager(thrd))
1003 return PL330_STATE_INVALID;
1004 else
1005 return PL330_STATE_COMPLETING;
1006 case DS_ST_FLTCMP:
1007 if (is_manager(thrd))
1008 return PL330_STATE_INVALID;
1009 else
1010 return PL330_STATE_FAULT_COMPLETING;
1011 default:
1012 return PL330_STATE_INVALID;
1013 }
1014}
1015
1016static void _stop(struct pl330_thread *thrd)
1017{
1018 void __iomem *regs = thrd->dmac->base;
1019 u8 insn[6] = {0, 0, 0, 0, 0, 0};
1020
1021 if (_state(thrd) == PL330_STATE_FAULT_COMPLETING)
1022 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
1023
1024 /* Return if nothing needs to be done */
1025 if (_state(thrd) == PL330_STATE_COMPLETING
1026 || _state(thrd) == PL330_STATE_KILLING
1027 || _state(thrd) == PL330_STATE_STOPPED)
1028 return;
1029
1030 _emit_KILL(0, insn);
1031
1032 /* Stop generating interrupts for SEV */
1033 writel(readl(regs + INTEN) & ~(1 << thrd->ev), regs + INTEN);
1034
1035 _execute_DBGINSN(thrd, insn, is_manager(thrd));
1036}
1037
1038/* Start doing req 'idx' of thread 'thrd' */
1039static bool _trigger(struct pl330_thread *thrd)
1040{
1041 void __iomem *regs = thrd->dmac->base;
1042 struct _pl330_req *req;
1043 struct dma_pl330_desc *desc;
1044 struct _arg_GO go;
1045 unsigned ns;
1046 u8 insn[6] = {0, 0, 0, 0, 0, 0};
1047 int idx;
1048
1049 /* Return if already ACTIVE */
1050 if (_state(thrd) != PL330_STATE_STOPPED)
1051 return true;
1052
1053 idx = 1 - thrd->lstenq;
1054 if (thrd->req[idx].desc != NULL) {
1055 req = &thrd->req[idx];
1056 } else {
1057 idx = thrd->lstenq;
1058 if (thrd->req[idx].desc != NULL)
1059 req = &thrd->req[idx];
1060 else
1061 req = NULL;
1062 }
1063
1064 /* Return if no request */
1065 if (!req)
1066 return true;
1067
1068 /* Return if req is running */
1069 if (idx == thrd->req_running)
1070 return true;
1071
1072 desc = req->desc;
1073
1074 ns = desc->rqcfg.nonsecure ? 1 : 0;
1075
1076 /* See 'Abort Sources' point-4 at Page 2-25 */
1077 if (_manager_ns(thrd) && !ns)
1078 dev_info(thrd->dmac->ddma.dev, "%s:%d Recipe for ABORT!\n",
1079 __func__, __LINE__);
1080
1081 go.chan = thrd->id;
1082 go.addr = req->mc_bus;
1083 go.ns = ns;
1084 _emit_GO(0, insn, &go);
1085
1086 /* Set to generate interrupts for SEV */
1087 writel(readl(regs + INTEN) | (1 << thrd->ev), regs + INTEN);
1088
1089 /* Only manager can execute GO */
1090 _execute_DBGINSN(thrd, insn, true);
1091
1092 thrd->req_running = idx;
1093
1094 return true;
1095}
1096
1097static bool _start(struct pl330_thread *thrd)
1098{
1099 switch (_state(thrd)) {
1100 case PL330_STATE_FAULT_COMPLETING:
1101 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
1102
1103 if (_state(thrd) == PL330_STATE_KILLING)
1104 UNTIL(thrd, PL330_STATE_STOPPED)
1105
1106 case PL330_STATE_FAULTING:
1107 _stop(thrd);
1108
1109 case PL330_STATE_KILLING:
1110 case PL330_STATE_COMPLETING:
1111 UNTIL(thrd, PL330_STATE_STOPPED)
1112
1113 case PL330_STATE_STOPPED:
1114 return _trigger(thrd);
1115
1116 case PL330_STATE_WFP:
1117 case PL330_STATE_QUEUEBUSY:
1118 case PL330_STATE_ATBARRIER:
1119 case PL330_STATE_UPDTPC:
1120 case PL330_STATE_CACHEMISS:
1121 case PL330_STATE_EXECUTING:
1122 return true;
1123
1124 case PL330_STATE_WFE: /* For RESUME, nothing yet */
1125 default:
1126 return false;
1127 }
1128}
1129
1130static inline int _ldst_memtomem(unsigned dry_run, u8 buf[],
1131 const struct _xfer_spec *pxs, int cyc)
1132{
1133 int off = 0;
1134 struct pl330_config *pcfg = pxs->desc->rqcfg.pcfg;
1135
1136 /* check lock-up free version */
1137 if (get_revision(pcfg->periph_id) >= PERIPH_REV_R1P0) {
1138 while (cyc--) {
1139 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1140 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1141 }
1142 } else {
1143 while (cyc--) {
1144 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1145 off += _emit_RMB(dry_run, &buf[off]);
1146 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1147 off += _emit_WMB(dry_run, &buf[off]);
1148 }
1149 }
1150
1151 return off;
1152}
1153
1154static inline int _ldst_devtomem(struct pl330_dmac *pl330, unsigned dry_run,
1155 u8 buf[], const struct _xfer_spec *pxs,
1156 int cyc)
1157{
1158 int off = 0;
1159 enum pl330_cond cond;
1160
1161 if (pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP)
1162 cond = BURST;
1163 else
1164 cond = SINGLE;
1165
1166 while (cyc--) {
1167 off += _emit_WFP(dry_run, &buf[off], cond, pxs->desc->peri);
1168 off += _emit_LDP(dry_run, &buf[off], cond, pxs->desc->peri);
1169 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1170
1171 if (!(pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP))
1172 off += _emit_FLUSHP(dry_run, &buf[off],
1173 pxs->desc->peri);
1174 }
1175
1176 return off;
1177}
1178
1179static inline int _ldst_memtodev(struct pl330_dmac *pl330,
1180 unsigned dry_run, u8 buf[],
1181 const struct _xfer_spec *pxs, int cyc)
1182{
1183 int off = 0;
1184 enum pl330_cond cond;
1185
1186 if (pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP)
1187 cond = BURST;
1188 else
1189 cond = SINGLE;
1190
1191 while (cyc--) {
1192 off += _emit_WFP(dry_run, &buf[off], cond, pxs->desc->peri);
1193 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1194 off += _emit_STP(dry_run, &buf[off], cond, pxs->desc->peri);
1195
1196 if (!(pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP))
1197 off += _emit_FLUSHP(dry_run, &buf[off],
1198 pxs->desc->peri);
1199 }
1200
1201 return off;
1202}
1203
1204static int _bursts(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[],
1205 const struct _xfer_spec *pxs, int cyc)
1206{
1207 int off = 0;
1208
1209 switch (pxs->desc->rqtype) {
1210 case DMA_MEM_TO_DEV:
1211 off += _ldst_memtodev(pl330, dry_run, &buf[off], pxs, cyc);
1212 break;
1213 case DMA_DEV_TO_MEM:
1214 off += _ldst_devtomem(pl330, dry_run, &buf[off], pxs, cyc);
1215 break;
1216 case DMA_MEM_TO_MEM:
1217 off += _ldst_memtomem(dry_run, &buf[off], pxs, cyc);
1218 break;
1219 default:
1220 off += 0x40000000; /* Scare off the Client */
1221 break;
1222 }
1223
1224 return off;
1225}
1226
1227/* Returns bytes consumed and updates bursts */
1228static inline int _loop(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[],
1229 unsigned long *bursts, const struct _xfer_spec *pxs)
1230{
1231 int cyc, cycmax, szlp, szlpend, szbrst, off;
1232 unsigned lcnt0, lcnt1, ljmp0, ljmp1;
1233 struct _arg_LPEND lpend;
1234
1235 if (*bursts == 1)
1236 return _bursts(pl330, dry_run, buf, pxs, 1);
1237
1238 /* Max iterations possible in DMALP is 256 */
1239 if (*bursts >= 256*256) {
1240 lcnt1 = 256;
1241 lcnt0 = 256;
1242 cyc = *bursts / lcnt1 / lcnt0;
1243 } else if (*bursts > 256) {
1244 lcnt1 = 256;
1245 lcnt0 = *bursts / lcnt1;
1246 cyc = 1;
1247 } else {
1248 lcnt1 = *bursts;
1249 lcnt0 = 0;
1250 cyc = 1;
1251 }
1252
1253 szlp = _emit_LP(1, buf, 0, 0);
1254 szbrst = _bursts(pl330, 1, buf, pxs, 1);
1255
1256 lpend.cond = ALWAYS;
1257 lpend.forever = false;
1258 lpend.loop = 0;
1259 lpend.bjump = 0;
1260 szlpend = _emit_LPEND(1, buf, &lpend);
1261
1262 if (lcnt0) {
1263 szlp *= 2;
1264 szlpend *= 2;
1265 }
1266
1267 /*
1268 * Max bursts that we can unroll due to limit on the
1269 * size of backward jump that can be encoded in DMALPEND
1270 * which is 8-bits and hence 255
1271 */
1272 cycmax = (255 - (szlp + szlpend)) / szbrst;
1273
1274 cyc = (cycmax < cyc) ? cycmax : cyc;
1275
1276 off = 0;
1277
1278 if (lcnt0) {
1279 off += _emit_LP(dry_run, &buf[off], 0, lcnt0);
1280 ljmp0 = off;
1281 }
1282
1283 off += _emit_LP(dry_run, &buf[off], 1, lcnt1);
1284 ljmp1 = off;
1285
1286 off += _bursts(pl330, dry_run, &buf[off], pxs, cyc);
1287
1288 lpend.cond = ALWAYS;
1289 lpend.forever = false;
1290 lpend.loop = 1;
1291 lpend.bjump = off - ljmp1;
1292 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1293
1294 if (lcnt0) {
1295 lpend.cond = ALWAYS;
1296 lpend.forever = false;
1297 lpend.loop = 0;
1298 lpend.bjump = off - ljmp0;
1299 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1300 }
1301
1302 *bursts = lcnt1 * cyc;
1303 if (lcnt0)
1304 *bursts *= lcnt0;
1305
1306 return off;
1307}
1308
1309static inline int _setup_loops(struct pl330_dmac *pl330,
1310 unsigned dry_run, u8 buf[],
1311 const struct _xfer_spec *pxs)
1312{
1313 struct pl330_xfer *x = &pxs->desc->px;
1314 u32 ccr = pxs->ccr;
1315 unsigned long c, bursts = BYTE_TO_BURST(x->bytes, ccr);
1316 int off = 0;
1317
1318 while (bursts) {
1319 c = bursts;
1320 off += _loop(pl330, dry_run, &buf[off], &c, pxs);
1321 bursts -= c;
1322 }
1323
1324 return off;
1325}
1326
1327static inline int _setup_xfer(struct pl330_dmac *pl330,
1328 unsigned dry_run, u8 buf[],
1329 const struct _xfer_spec *pxs)
1330{
1331 struct pl330_xfer *x = &pxs->desc->px;
1332 int off = 0;
1333
1334 /* DMAMOV SAR, x->src_addr */
1335 off += _emit_MOV(dry_run, &buf[off], SAR, x->src_addr);
1336 /* DMAMOV DAR, x->dst_addr */
1337 off += _emit_MOV(dry_run, &buf[off], DAR, x->dst_addr);
1338
1339 /* Setup Loop(s) */
1340 off += _setup_loops(pl330, dry_run, &buf[off], pxs);
1341
1342 return off;
1343}
1344
1345/*
1346 * A req is a sequence of one or more xfer units.
1347 * Returns the number of bytes taken to setup the MC for the req.
1348 */
1349static int _setup_req(struct pl330_dmac *pl330, unsigned dry_run,
1350 struct pl330_thread *thrd, unsigned index,
1351 struct _xfer_spec *pxs)
1352{
1353 struct _pl330_req *req = &thrd->req[index];
1354 struct pl330_xfer *x;
1355 u8 *buf = req->mc_cpu;
1356 int off = 0;
1357
1358 PL330_DBGMC_START(req->mc_bus);
1359
1360 /* DMAMOV CCR, ccr */
1361 off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr);
1362
1363 x = &pxs->desc->px;
1364 /* Error if xfer length is not aligned at burst size */
1365 if (x->bytes % (BRST_SIZE(pxs->ccr) * BRST_LEN(pxs->ccr)))
1366 return -EINVAL;
1367
1368 off += _setup_xfer(pl330, dry_run, &buf[off], pxs);
1369
1370 /* DMASEV peripheral/event */
1371 off += _emit_SEV(dry_run, &buf[off], thrd->ev);
1372 /* DMAEND */
1373 off += _emit_END(dry_run, &buf[off]);
1374
1375 return off;
1376}
1377
1378static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc)
1379{
1380 u32 ccr = 0;
1381
1382 if (rqc->src_inc)
1383 ccr |= CC_SRCINC;
1384
1385 if (rqc->dst_inc)
1386 ccr |= CC_DSTINC;
1387
1388 /* We set same protection levels for Src and DST for now */
1389 if (rqc->privileged)
1390 ccr |= CC_SRCPRI | CC_DSTPRI;
1391 if (rqc->nonsecure)
1392 ccr |= CC_SRCNS | CC_DSTNS;
1393 if (rqc->insnaccess)
1394 ccr |= CC_SRCIA | CC_DSTIA;
1395
1396 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_SRCBRSTLEN_SHFT);
1397 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_DSTBRSTLEN_SHFT);
1398
1399 ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT);
1400 ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT);
1401
1402 ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT);
1403 ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT);
1404
1405 ccr |= (rqc->swap << CC_SWAP_SHFT);
1406
1407 return ccr;
1408}
1409
1410/*
1411 * Submit a list of xfers after which the client wants notification.
1412 * Client is not notified after each xfer unit, just once after all
1413 * xfer units are done or some error occurs.
1414 */
1415static int pl330_submit_req(struct pl330_thread *thrd,
1416 struct dma_pl330_desc *desc)
1417{
1418 struct pl330_dmac *pl330 = thrd->dmac;
1419 struct _xfer_spec xs;
1420 unsigned long flags;
1421 unsigned idx;
1422 u32 ccr;
1423 int ret = 0;
1424
1425 if (pl330->state == DYING
1426 || pl330->dmac_tbd.reset_chan & (1 << thrd->id)) {
1427 dev_info(thrd->dmac->ddma.dev, "%s:%d\n",
1428 __func__, __LINE__);
1429 return -EAGAIN;
1430 }
1431
1432 /* If request for non-existing peripheral */
1433 if (desc->rqtype != DMA_MEM_TO_MEM &&
1434 desc->peri >= pl330->pcfg.num_peri) {
1435 dev_info(thrd->dmac->ddma.dev,
1436 "%s:%d Invalid peripheral(%u)!\n",
1437 __func__, __LINE__, desc->peri);
1438 return -EINVAL;
1439 }
1440
1441 spin_lock_irqsave(&pl330->lock, flags);
1442
1443 if (_queue_full(thrd)) {
1444 ret = -EAGAIN;
1445 goto xfer_exit;
1446 }
1447
1448 /* Prefer Secure Channel */
1449 if (!_manager_ns(thrd))
1450 desc->rqcfg.nonsecure = 0;
1451 else
1452 desc->rqcfg.nonsecure = 1;
1453
1454 ccr = _prepare_ccr(&desc->rqcfg);
1455
1456 idx = thrd->req[0].desc == NULL ? 0 : 1;
1457
1458 xs.ccr = ccr;
1459 xs.desc = desc;
1460
1461 /* First dry run to check if req is acceptable */
1462 ret = _setup_req(pl330, 1, thrd, idx, &xs);
1463 if (ret < 0)
1464 goto xfer_exit;
1465
1466 if (ret > pl330->mcbufsz / 2) {
1467 dev_info(pl330->ddma.dev, "%s:%d Try increasing mcbufsz (%i/%i)\n",
1468 __func__, __LINE__, ret, pl330->mcbufsz / 2);
1469 ret = -ENOMEM;
1470 goto xfer_exit;
1471 }
1472
1473 /* Hook the request */
1474 thrd->lstenq = idx;
1475 thrd->req[idx].desc = desc;
1476 _setup_req(pl330, 0, thrd, idx, &xs);
1477
1478 ret = 0;
1479
1480xfer_exit:
1481 spin_unlock_irqrestore(&pl330->lock, flags);
1482
1483 return ret;
1484}
1485
1486static void dma_pl330_rqcb(struct dma_pl330_desc *desc, enum pl330_op_err err)
1487{
1488 struct dma_pl330_chan *pch;
1489 unsigned long flags;
1490
1491 if (!desc)
1492 return;
1493
1494 pch = desc->pchan;
1495
1496 /* If desc aborted */
1497 if (!pch)
1498 return;
1499
1500 spin_lock_irqsave(&pch->lock, flags);
1501
1502 desc->status = DONE;
1503
1504 spin_unlock_irqrestore(&pch->lock, flags);
1505
1506 tasklet_schedule(&pch->task);
1507}
1508
1509static void pl330_dotask(unsigned long data)
1510{
1511 struct pl330_dmac *pl330 = (struct pl330_dmac *) data;
1512 unsigned long flags;
1513 int i;
1514
1515 spin_lock_irqsave(&pl330->lock, flags);
1516
1517 /* The DMAC itself gone nuts */
1518 if (pl330->dmac_tbd.reset_dmac) {
1519 pl330->state = DYING;
1520 /* Reset the manager too */
1521 pl330->dmac_tbd.reset_mngr = true;
1522 /* Clear the reset flag */
1523 pl330->dmac_tbd.reset_dmac = false;
1524 }
1525
1526 if (pl330->dmac_tbd.reset_mngr) {
1527 _stop(pl330->manager);
1528 /* Reset all channels */
1529 pl330->dmac_tbd.reset_chan = (1 << pl330->pcfg.num_chan) - 1;
1530 /* Clear the reset flag */
1531 pl330->dmac_tbd.reset_mngr = false;
1532 }
1533
1534 for (i = 0; i < pl330->pcfg.num_chan; i++) {
1535
1536 if (pl330->dmac_tbd.reset_chan & (1 << i)) {
1537 struct pl330_thread *thrd = &pl330->channels[i];
1538 void __iomem *regs = pl330->base;
1539 enum pl330_op_err err;
1540
1541 _stop(thrd);
1542
1543 if (readl(regs + FSC) & (1 << thrd->id))
1544 err = PL330_ERR_FAIL;
1545 else
1546 err = PL330_ERR_ABORT;
1547
1548 spin_unlock_irqrestore(&pl330->lock, flags);
1549 dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, err);
1550 dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, err);
1551 spin_lock_irqsave(&pl330->lock, flags);
1552
1553 thrd->req[0].desc = NULL;
1554 thrd->req[1].desc = NULL;
1555 thrd->req_running = -1;
1556
1557 /* Clear the reset flag */
1558 pl330->dmac_tbd.reset_chan &= ~(1 << i);
1559 }
1560 }
1561
1562 spin_unlock_irqrestore(&pl330->lock, flags);
1563
1564 return;
1565}
1566
1567/* Returns 1 if state was updated, 0 otherwise */
1568static int pl330_update(struct pl330_dmac *pl330)
1569{
1570 struct dma_pl330_desc *descdone, *tmp;
1571 unsigned long flags;
1572 void __iomem *regs;
1573 u32 val;
1574 int id, ev, ret = 0;
1575
1576 regs = pl330->base;
1577
1578 spin_lock_irqsave(&pl330->lock, flags);
1579
1580 val = readl(regs + FSM) & 0x1;
1581 if (val)
1582 pl330->dmac_tbd.reset_mngr = true;
1583 else
1584 pl330->dmac_tbd.reset_mngr = false;
1585
1586 val = readl(regs + FSC) & ((1 << pl330->pcfg.num_chan) - 1);
1587 pl330->dmac_tbd.reset_chan |= val;
1588 if (val) {
1589 int i = 0;
1590 while (i < pl330->pcfg.num_chan) {
1591 if (val & (1 << i)) {
1592 dev_info(pl330->ddma.dev,
1593 "Reset Channel-%d\t CS-%x FTC-%x\n",
1594 i, readl(regs + CS(i)),
1595 readl(regs + FTC(i)));
1596 _stop(&pl330->channels[i]);
1597 }
1598 i++;
1599 }
1600 }
1601
1602 /* Check which event happened i.e, thread notified */
1603 val = readl(regs + ES);
1604 if (pl330->pcfg.num_events < 32
1605 && val & ~((1 << pl330->pcfg.num_events) - 1)) {
1606 pl330->dmac_tbd.reset_dmac = true;
1607 dev_err(pl330->ddma.dev, "%s:%d Unexpected!\n", __func__,
1608 __LINE__);
1609 ret = 1;
1610 goto updt_exit;
1611 }
1612
1613 for (ev = 0; ev < pl330->pcfg.num_events; ev++) {
1614 if (val & (1 << ev)) { /* Event occurred */
1615 struct pl330_thread *thrd;
1616 u32 inten = readl(regs + INTEN);
1617 int active;
1618
1619 /* Clear the event */
1620 if (inten & (1 << ev))
1621 writel(1 << ev, regs + INTCLR);
1622
1623 ret = 1;
1624
1625 id = pl330->events[ev];
1626
1627 thrd = &pl330->channels[id];
1628
1629 active = thrd->req_running;
1630 if (active == -1) /* Aborted */
1631 continue;
1632
1633 /* Detach the req */
1634 descdone = thrd->req[active].desc;
1635 thrd->req[active].desc = NULL;
1636
1637 thrd->req_running = -1;
1638
1639 /* Get going again ASAP */
1640 _start(thrd);
1641
1642 /* For now, just make a list of callbacks to be done */
1643 list_add_tail(&descdone->rqd, &pl330->req_done);
1644 }
1645 }
1646
1647 /* Now that we are in no hurry, do the callbacks */
1648 list_for_each_entry_safe(descdone, tmp, &pl330->req_done, rqd) {
1649 list_del(&descdone->rqd);
1650 spin_unlock_irqrestore(&pl330->lock, flags);
1651 dma_pl330_rqcb(descdone, PL330_ERR_NONE);
1652 spin_lock_irqsave(&pl330->lock, flags);
1653 }
1654
1655updt_exit:
1656 spin_unlock_irqrestore(&pl330->lock, flags);
1657
1658 if (pl330->dmac_tbd.reset_dmac
1659 || pl330->dmac_tbd.reset_mngr
1660 || pl330->dmac_tbd.reset_chan) {
1661 ret = 1;
1662 tasklet_schedule(&pl330->tasks);
1663 }
1664
1665 return ret;
1666}
1667
1668/* Reserve an event */
1669static inline int _alloc_event(struct pl330_thread *thrd)
1670{
1671 struct pl330_dmac *pl330 = thrd->dmac;
1672 int ev;
1673
1674 for (ev = 0; ev < pl330->pcfg.num_events; ev++)
1675 if (pl330->events[ev] == -1) {
1676 pl330->events[ev] = thrd->id;
1677 return ev;
1678 }
1679
1680 return -1;
1681}
1682
1683static bool _chan_ns(const struct pl330_dmac *pl330, int i)
1684{
1685 return pl330->pcfg.irq_ns & (1 << i);
1686}
1687
1688/* Upon success, returns IdentityToken for the
1689 * allocated channel, NULL otherwise.
1690 */
1691static struct pl330_thread *pl330_request_channel(struct pl330_dmac *pl330)
1692{
1693 struct pl330_thread *thrd = NULL;
1694 unsigned long flags;
1695 int chans, i;
1696
1697 if (pl330->state == DYING)
1698 return NULL;
1699
1700 chans = pl330->pcfg.num_chan;
1701
1702 spin_lock_irqsave(&pl330->lock, flags);
1703
1704 for (i = 0; i < chans; i++) {
1705 thrd = &pl330->channels[i];
1706 if ((thrd->free) && (!_manager_ns(thrd) ||
1707 _chan_ns(pl330, i))) {
1708 thrd->ev = _alloc_event(thrd);
1709 if (thrd->ev >= 0) {
1710 thrd->free = false;
1711 thrd->lstenq = 1;
1712 thrd->req[0].desc = NULL;
1713 thrd->req[1].desc = NULL;
1714 thrd->req_running = -1;
1715 break;
1716 }
1717 }
1718 thrd = NULL;
1719 }
1720
1721 spin_unlock_irqrestore(&pl330->lock, flags);
1722
1723 return thrd;
1724}
1725
1726/* Release an event */
1727static inline void _free_event(struct pl330_thread *thrd, int ev)
1728{
1729 struct pl330_dmac *pl330 = thrd->dmac;
1730
1731 /* If the event is valid and was held by the thread */
1732 if (ev >= 0 && ev < pl330->pcfg.num_events
1733 && pl330->events[ev] == thrd->id)
1734 pl330->events[ev] = -1;
1735}
1736
1737static void pl330_release_channel(struct pl330_thread *thrd)
1738{
1739 struct pl330_dmac *pl330;
1740 unsigned long flags;
1741
1742 if (!thrd || thrd->free)
1743 return;
1744
1745 _stop(thrd);
1746
1747 dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, PL330_ERR_ABORT);
1748 dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, PL330_ERR_ABORT);
1749
1750 pl330 = thrd->dmac;
1751
1752 spin_lock_irqsave(&pl330->lock, flags);
1753 _free_event(thrd, thrd->ev);
1754 thrd->free = true;
1755 spin_unlock_irqrestore(&pl330->lock, flags);
1756}
1757
1758/* Initialize the structure for PL330 configuration, that can be used
1759 * by the client driver the make best use of the DMAC
1760 */
1761static void read_dmac_config(struct pl330_dmac *pl330)
1762{
1763 void __iomem *regs = pl330->base;
1764 u32 val;
1765
1766 val = readl(regs + CRD) >> CRD_DATA_WIDTH_SHIFT;
1767 val &= CRD_DATA_WIDTH_MASK;
1768 pl330->pcfg.data_bus_width = 8 * (1 << val);
1769
1770 val = readl(regs + CRD) >> CRD_DATA_BUFF_SHIFT;
1771 val &= CRD_DATA_BUFF_MASK;
1772 pl330->pcfg.data_buf_dep = val + 1;
1773
1774 val = readl(regs + CR0) >> CR0_NUM_CHANS_SHIFT;
1775 val &= CR0_NUM_CHANS_MASK;
1776 val += 1;
1777 pl330->pcfg.num_chan = val;
1778
1779 val = readl(regs + CR0);
1780 if (val & CR0_PERIPH_REQ_SET) {
1781 val = (val >> CR0_NUM_PERIPH_SHIFT) & CR0_NUM_PERIPH_MASK;
1782 val += 1;
1783 pl330->pcfg.num_peri = val;
1784 pl330->pcfg.peri_ns = readl(regs + CR4);
1785 } else {
1786 pl330->pcfg.num_peri = 0;
1787 }
1788
1789 val = readl(regs + CR0);
1790 if (val & CR0_BOOT_MAN_NS)
1791 pl330->pcfg.mode |= DMAC_MODE_NS;
1792 else
1793 pl330->pcfg.mode &= ~DMAC_MODE_NS;
1794
1795 val = readl(regs + CR0) >> CR0_NUM_EVENTS_SHIFT;
1796 val &= CR0_NUM_EVENTS_MASK;
1797 val += 1;
1798 pl330->pcfg.num_events = val;
1799
1800 pl330->pcfg.irq_ns = readl(regs + CR3);
1801}
1802
1803static inline void _reset_thread(struct pl330_thread *thrd)
1804{
1805 struct pl330_dmac *pl330 = thrd->dmac;
1806
1807 thrd->req[0].mc_cpu = pl330->mcode_cpu
1808 + (thrd->id * pl330->mcbufsz);
1809 thrd->req[0].mc_bus = pl330->mcode_bus
1810 + (thrd->id * pl330->mcbufsz);
1811 thrd->req[0].desc = NULL;
1812
1813 thrd->req[1].mc_cpu = thrd->req[0].mc_cpu
1814 + pl330->mcbufsz / 2;
1815 thrd->req[1].mc_bus = thrd->req[0].mc_bus
1816 + pl330->mcbufsz / 2;
1817 thrd->req[1].desc = NULL;
1818
1819 thrd->req_running = -1;
1820}
1821
1822static int dmac_alloc_threads(struct pl330_dmac *pl330)
1823{
1824 int chans = pl330->pcfg.num_chan;
1825 struct pl330_thread *thrd;
1826 int i;
1827
1828 /* Allocate 1 Manager and 'chans' Channel threads */
1829 pl330->channels = kzalloc((1 + chans) * sizeof(*thrd),
1830 GFP_KERNEL);
1831 if (!pl330->channels)
1832 return -ENOMEM;
1833
1834 /* Init Channel threads */
1835 for (i = 0; i < chans; i++) {
1836 thrd = &pl330->channels[i];
1837 thrd->id = i;
1838 thrd->dmac = pl330;
1839 _reset_thread(thrd);
1840 thrd->free = true;
1841 }
1842
1843 /* MANAGER is indexed at the end */
1844 thrd = &pl330->channels[chans];
1845 thrd->id = chans;
1846 thrd->dmac = pl330;
1847 thrd->free = false;
1848 pl330->manager = thrd;
1849
1850 return 0;
1851}
1852
1853static int dmac_alloc_resources(struct pl330_dmac *pl330)
1854{
1855 int chans = pl330->pcfg.num_chan;
1856 int ret;
1857
1858 /*
1859 * Alloc MicroCode buffer for 'chans' Channel threads.
1860 * A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN)
1861 */
1862 pl330->mcode_cpu = dma_alloc_coherent(pl330->ddma.dev,
1863 chans * pl330->mcbufsz,
1864 &pl330->mcode_bus, GFP_KERNEL);
1865 if (!pl330->mcode_cpu) {
1866 dev_err(pl330->ddma.dev, "%s:%d Can't allocate memory!\n",
1867 __func__, __LINE__);
1868 return -ENOMEM;
1869 }
1870
1871 ret = dmac_alloc_threads(pl330);
1872 if (ret) {
1873 dev_err(pl330->ddma.dev, "%s:%d Can't to create channels for DMAC!\n",
1874 __func__, __LINE__);
1875 dma_free_coherent(pl330->ddma.dev,
1876 chans * pl330->mcbufsz,
1877 pl330->mcode_cpu, pl330->mcode_bus);
1878 return ret;
1879 }
1880
1881 return 0;
1882}
1883
1884static int pl330_add(struct pl330_dmac *pl330)
1885{
1886 void __iomem *regs;
1887 int i, ret;
1888
1889 regs = pl330->base;
1890
1891 /* Check if we can handle this DMAC */
1892 if ((pl330->pcfg.periph_id & 0xfffff) != PERIPH_ID_VAL) {
1893 dev_err(pl330->ddma.dev, "PERIPH_ID 0x%x !\n",
1894 pl330->pcfg.periph_id);
1895 return -EINVAL;
1896 }
1897
1898 /* Read the configuration of the DMAC */
1899 read_dmac_config(pl330);
1900
1901 if (pl330->pcfg.num_events == 0) {
1902 dev_err(pl330->ddma.dev, "%s:%d Can't work without events!\n",
1903 __func__, __LINE__);
1904 return -EINVAL;
1905 }
1906
1907 spin_lock_init(&pl330->lock);
1908
1909 INIT_LIST_HEAD(&pl330->req_done);
1910
1911 /* Use default MC buffer size if not provided */
1912 if (!pl330->mcbufsz)
1913 pl330->mcbufsz = MCODE_BUFF_PER_REQ * 2;
1914
1915 /* Mark all events as free */
1916 for (i = 0; i < pl330->pcfg.num_events; i++)
1917 pl330->events[i] = -1;
1918
1919 /* Allocate resources needed by the DMAC */
1920 ret = dmac_alloc_resources(pl330);
1921 if (ret) {
1922 dev_err(pl330->ddma.dev, "Unable to create channels for DMAC\n");
1923 return ret;
1924 }
1925
1926 tasklet_init(&pl330->tasks, pl330_dotask, (unsigned long) pl330);
1927
1928 pl330->state = INIT;
1929
1930 return 0;
1931}
1932
1933static int dmac_free_threads(struct pl330_dmac *pl330)
1934{
1935 struct pl330_thread *thrd;
1936 int i;
1937
1938 /* Release Channel threads */
1939 for (i = 0; i < pl330->pcfg.num_chan; i++) {
1940 thrd = &pl330->channels[i];
1941 pl330_release_channel(thrd);
1942 }
1943
1944 /* Free memory */
1945 kfree(pl330->channels);
1946
1947 return 0;
1948}
1949
1950static void pl330_del(struct pl330_dmac *pl330)
1951{
1952 pl330->state = UNINIT;
1953
1954 tasklet_kill(&pl330->tasks);
1955
1956 /* Free DMAC resources */
1957 dmac_free_threads(pl330);
1958
1959 dma_free_coherent(pl330->ddma.dev,
1960 pl330->pcfg.num_chan * pl330->mcbufsz, pl330->mcode_cpu,
1961 pl330->mcode_bus);
1962}
1963
1964/* forward declaration */
1965static struct amba_driver pl330_driver;
1966
1967static inline struct dma_pl330_chan *
1968to_pchan(struct dma_chan *ch)
1969{
1970 if (!ch)
1971 return NULL;
1972
1973 return container_of(ch, struct dma_pl330_chan, chan);
1974}
1975
1976static inline struct dma_pl330_desc *
1977to_desc(struct dma_async_tx_descriptor *tx)
1978{
1979 return container_of(tx, struct dma_pl330_desc, txd);
1980}
1981
1982static inline void fill_queue(struct dma_pl330_chan *pch)
1983{
1984 struct dma_pl330_desc *desc;
1985 int ret;
1986
1987 list_for_each_entry(desc, &pch->work_list, node) {
1988
1989 /* If already submitted */
1990 if (desc->status == BUSY)
1991 continue;
1992
1993 ret = pl330_submit_req(pch->thread, desc);
1994 if (!ret) {
1995 desc->status = BUSY;
1996 } else if (ret == -EAGAIN) {
1997 /* QFull or DMAC Dying */
1998 break;
1999 } else {
2000 /* Unacceptable request */
2001 desc->status = DONE;
2002 dev_err(pch->dmac->ddma.dev, "%s:%d Bad Desc(%d)\n",
2003 __func__, __LINE__, desc->txd.cookie);
2004 tasklet_schedule(&pch->task);
2005 }
2006 }
2007}
2008
2009static void pl330_tasklet(unsigned long data)
2010{
2011 struct dma_pl330_chan *pch = (struct dma_pl330_chan *)data;
2012 struct dma_pl330_desc *desc, *_dt;
2013 unsigned long flags;
2014 bool power_down = false;
2015
2016 spin_lock_irqsave(&pch->lock, flags);
2017
2018 /* Pick up ripe tomatoes */
2019 list_for_each_entry_safe(desc, _dt, &pch->work_list, node)
2020 if (desc->status == DONE) {
2021 if (!pch->cyclic)
2022 dma_cookie_complete(&desc->txd);
2023 list_move_tail(&desc->node, &pch->completed_list);
2024 }
2025
2026 /* Try to submit a req imm. next to the last completed cookie */
2027 fill_queue(pch);
2028
2029 if (list_empty(&pch->work_list)) {
2030 spin_lock(&pch->thread->dmac->lock);
2031 _stop(pch->thread);
2032 spin_unlock(&pch->thread->dmac->lock);
2033 power_down = true;
2034 } else {
2035 /* Make sure the PL330 Channel thread is active */
2036 spin_lock(&pch->thread->dmac->lock);
2037 _start(pch->thread);
2038 spin_unlock(&pch->thread->dmac->lock);
2039 }
2040
2041 while (!list_empty(&pch->completed_list)) {
2042 dma_async_tx_callback callback;
2043 void *callback_param;
2044
2045 desc = list_first_entry(&pch->completed_list,
2046 struct dma_pl330_desc, node);
2047
2048 callback = desc->txd.callback;
2049 callback_param = desc->txd.callback_param;
2050
2051 if (pch->cyclic) {
2052 desc->status = PREP;
2053 list_move_tail(&desc->node, &pch->work_list);
2054 if (power_down) {
2055 spin_lock(&pch->thread->dmac->lock);
2056 _start(pch->thread);
2057 spin_unlock(&pch->thread->dmac->lock);
2058 power_down = false;
2059 }
2060 } else {
2061 desc->status = FREE;
2062 list_move_tail(&desc->node, &pch->dmac->desc_pool);
2063 }
2064
2065 dma_descriptor_unmap(&desc->txd);
2066
2067 if (callback) {
2068 spin_unlock_irqrestore(&pch->lock, flags);
2069 callback(callback_param);
2070 spin_lock_irqsave(&pch->lock, flags);
2071 }
2072 }
2073 spin_unlock_irqrestore(&pch->lock, flags);
2074
2075 /* If work list empty, power down */
2076 if (power_down) {
2077 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2078 pm_runtime_put_autosuspend(pch->dmac->ddma.dev);
2079 }
2080}
2081
2082bool pl330_filter(struct dma_chan *chan, void *param)
2083{
2084 u8 *peri_id;
2085
2086 if (chan->device->dev->driver != &pl330_driver.drv)
2087 return false;
2088
2089 peri_id = chan->private;
2090 return *peri_id == (unsigned long)param;
2091}
2092EXPORT_SYMBOL(pl330_filter);
2093
2094static struct dma_chan *of_dma_pl330_xlate(struct of_phandle_args *dma_spec,
2095 struct of_dma *ofdma)
2096{
2097 int count = dma_spec->args_count;
2098 struct pl330_dmac *pl330 = ofdma->of_dma_data;
2099 unsigned int chan_id;
2100
2101 if (!pl330)
2102 return NULL;
2103
2104 if (count != 1)
2105 return NULL;
2106
2107 chan_id = dma_spec->args[0];
2108 if (chan_id >= pl330->num_peripherals)
2109 return NULL;
2110
2111 return dma_get_slave_channel(&pl330->peripherals[chan_id].chan);
2112}
2113
2114static int pl330_alloc_chan_resources(struct dma_chan *chan)
2115{
2116 struct dma_pl330_chan *pch = to_pchan(chan);
2117 struct pl330_dmac *pl330 = pch->dmac;
2118 unsigned long flags;
2119
2120 spin_lock_irqsave(&pch->lock, flags);
2121
2122 dma_cookie_init(chan);
2123 pch->cyclic = false;
2124
2125 pch->thread = pl330_request_channel(pl330);
2126 if (!pch->thread) {
2127 spin_unlock_irqrestore(&pch->lock, flags);
2128 return -ENOMEM;
2129 }
2130
2131 tasklet_init(&pch->task, pl330_tasklet, (unsigned long) pch);
2132
2133 spin_unlock_irqrestore(&pch->lock, flags);
2134
2135 return 1;
2136}
2137
2138static int pl330_config(struct dma_chan *chan,
2139 struct dma_slave_config *slave_config)
2140{
2141 struct dma_pl330_chan *pch = to_pchan(chan);
2142
2143 if (slave_config->direction == DMA_MEM_TO_DEV) {
2144 if (slave_config->dst_addr)
2145 pch->fifo_addr = slave_config->dst_addr;
2146 if (slave_config->dst_addr_width)
2147 pch->burst_sz = __ffs(slave_config->dst_addr_width);
2148 if (slave_config->dst_maxburst)
2149 pch->burst_len = slave_config->dst_maxburst;
2150 } else if (slave_config->direction == DMA_DEV_TO_MEM) {
2151 if (slave_config->src_addr)
2152 pch->fifo_addr = slave_config->src_addr;
2153 if (slave_config->src_addr_width)
2154 pch->burst_sz = __ffs(slave_config->src_addr_width);
2155 if (slave_config->src_maxburst)
2156 pch->burst_len = slave_config->src_maxburst;
2157 }
2158
2159 return 0;
2160}
2161
2162static int pl330_terminate_all(struct dma_chan *chan)
2163{
2164 struct dma_pl330_chan *pch = to_pchan(chan);
2165 struct dma_pl330_desc *desc;
2166 unsigned long flags;
2167 struct pl330_dmac *pl330 = pch->dmac;
2168 LIST_HEAD(list);
2169
2170 pm_runtime_get_sync(pl330->ddma.dev);
2171 spin_lock_irqsave(&pch->lock, flags);
2172 spin_lock(&pl330->lock);
2173 _stop(pch->thread);
2174 spin_unlock(&pl330->lock);
2175
2176 pch->thread->req[0].desc = NULL;
2177 pch->thread->req[1].desc = NULL;
2178 pch->thread->req_running = -1;
2179
2180 /* Mark all desc done */
2181 list_for_each_entry(desc, &pch->submitted_list, node) {
2182 desc->status = FREE;
2183 dma_cookie_complete(&desc->txd);
2184 }
2185
2186 list_for_each_entry(desc, &pch->work_list , node) {
2187 desc->status = FREE;
2188 dma_cookie_complete(&desc->txd);
2189 }
2190
2191 list_splice_tail_init(&pch->submitted_list, &pl330->desc_pool);
2192 list_splice_tail_init(&pch->work_list, &pl330->desc_pool);
2193 list_splice_tail_init(&pch->completed_list, &pl330->desc_pool);
2194 spin_unlock_irqrestore(&pch->lock, flags);
2195 pm_runtime_mark_last_busy(pl330->ddma.dev);
2196 pm_runtime_put_autosuspend(pl330->ddma.dev);
2197
2198 return 0;
2199}
2200
2201/*
2202 * We don't support DMA_RESUME command because of hardware
2203 * limitations, so after pausing the channel we cannot restore
2204 * it to active state. We have to terminate channel and setup
2205 * DMA transfer again. This pause feature was implemented to
2206 * allow safely read residue before channel termination.
2207 */
2208static int pl330_pause(struct dma_chan *chan)
2209{
2210 struct dma_pl330_chan *pch = to_pchan(chan);
2211 struct pl330_dmac *pl330 = pch->dmac;
2212 unsigned long flags;
2213
2214 pm_runtime_get_sync(pl330->ddma.dev);
2215 spin_lock_irqsave(&pch->lock, flags);
2216
2217 spin_lock(&pl330->lock);
2218 _stop(pch->thread);
2219 spin_unlock(&pl330->lock);
2220
2221 spin_unlock_irqrestore(&pch->lock, flags);
2222 pm_runtime_mark_last_busy(pl330->ddma.dev);
2223 pm_runtime_put_autosuspend(pl330->ddma.dev);
2224
2225 return 0;
2226}
2227
2228static void pl330_free_chan_resources(struct dma_chan *chan)
2229{
2230 struct dma_pl330_chan *pch = to_pchan(chan);
2231 unsigned long flags;
2232
2233 tasklet_kill(&pch->task);
2234
2235 pm_runtime_get_sync(pch->dmac->ddma.dev);
2236 spin_lock_irqsave(&pch->lock, flags);
2237
2238 pl330_release_channel(pch->thread);
2239 pch->thread = NULL;
2240
2241 if (pch->cyclic)
2242 list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool);
2243
2244 spin_unlock_irqrestore(&pch->lock, flags);
2245 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2246 pm_runtime_put_autosuspend(pch->dmac->ddma.dev);
2247}
2248
2249static int pl330_get_current_xferred_count(struct dma_pl330_chan *pch,
2250 struct dma_pl330_desc *desc)
2251{
2252 struct pl330_thread *thrd = pch->thread;
2253 struct pl330_dmac *pl330 = pch->dmac;
2254 void __iomem *regs = thrd->dmac->base;
2255 u32 val, addr;
2256
2257 pm_runtime_get_sync(pl330->ddma.dev);
2258 val = addr = 0;
2259 if (desc->rqcfg.src_inc) {
2260 val = readl(regs + SA(thrd->id));
2261 addr = desc->px.src_addr;
2262 } else {
2263 val = readl(regs + DA(thrd->id));
2264 addr = desc->px.dst_addr;
2265 }
2266 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2267 pm_runtime_put_autosuspend(pl330->ddma.dev);
2268 return val - addr;
2269}
2270
2271static enum dma_status
2272pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
2273 struct dma_tx_state *txstate)
2274{
2275 enum dma_status ret;
2276 unsigned long flags;
2277 struct dma_pl330_desc *desc, *running = NULL;
2278 struct dma_pl330_chan *pch = to_pchan(chan);
2279 unsigned int transferred, residual = 0;
2280
2281 ret = dma_cookie_status(chan, cookie, txstate);
2282
2283 if (!txstate)
2284 return ret;
2285
2286 if (ret == DMA_COMPLETE)
2287 goto out;
2288
2289 spin_lock_irqsave(&pch->lock, flags);
2290
2291 if (pch->thread->req_running != -1)
2292 running = pch->thread->req[pch->thread->req_running].desc;
2293
2294 /* Check in pending list */
2295 list_for_each_entry(desc, &pch->work_list, node) {
2296 if (desc->status == DONE)
2297 transferred = desc->bytes_requested;
2298 else if (running && desc == running)
2299 transferred =
2300 pl330_get_current_xferred_count(pch, desc);
2301 else
2302 transferred = 0;
2303 residual += desc->bytes_requested - transferred;
2304 if (desc->txd.cookie == cookie) {
2305 switch (desc->status) {
2306 case DONE:
2307 ret = DMA_COMPLETE;
2308 break;
2309 case PREP:
2310 case BUSY:
2311 ret = DMA_IN_PROGRESS;
2312 break;
2313 default:
2314 WARN_ON(1);
2315 }
2316 break;
2317 }
2318 if (desc->last)
2319 residual = 0;
2320 }
2321 spin_unlock_irqrestore(&pch->lock, flags);
2322
2323out:
2324 dma_set_residue(txstate, residual);
2325
2326 return ret;
2327}
2328
2329static void pl330_issue_pending(struct dma_chan *chan)
2330{
2331 struct dma_pl330_chan *pch = to_pchan(chan);
2332 unsigned long flags;
2333
2334 spin_lock_irqsave(&pch->lock, flags);
2335 if (list_empty(&pch->work_list)) {
2336 /*
2337 * Warn on nothing pending. Empty submitted_list may
2338 * break our pm_runtime usage counter as it is
2339 * updated on work_list emptiness status.
2340 */
2341 WARN_ON(list_empty(&pch->submitted_list));
2342 pm_runtime_get_sync(pch->dmac->ddma.dev);
2343 }
2344 list_splice_tail_init(&pch->submitted_list, &pch->work_list);
2345 spin_unlock_irqrestore(&pch->lock, flags);
2346
2347 pl330_tasklet((unsigned long)pch);
2348}
2349
2350/*
2351 * We returned the last one of the circular list of descriptor(s)
2352 * from prep_xxx, so the argument to submit corresponds to the last
2353 * descriptor of the list.
2354 */
2355static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx)
2356{
2357 struct dma_pl330_desc *desc, *last = to_desc(tx);
2358 struct dma_pl330_chan *pch = to_pchan(tx->chan);
2359 dma_cookie_t cookie;
2360 unsigned long flags;
2361
2362 spin_lock_irqsave(&pch->lock, flags);
2363
2364 /* Assign cookies to all nodes */
2365 while (!list_empty(&last->node)) {
2366 desc = list_entry(last->node.next, struct dma_pl330_desc, node);
2367 if (pch->cyclic) {
2368 desc->txd.callback = last->txd.callback;
2369 desc->txd.callback_param = last->txd.callback_param;
2370 }
2371 desc->last = false;
2372
2373 dma_cookie_assign(&desc->txd);
2374
2375 list_move_tail(&desc->node, &pch->submitted_list);
2376 }
2377
2378 last->last = true;
2379 cookie = dma_cookie_assign(&last->txd);
2380 list_add_tail(&last->node, &pch->submitted_list);
2381 spin_unlock_irqrestore(&pch->lock, flags);
2382
2383 return cookie;
2384}
2385
2386static inline void _init_desc(struct dma_pl330_desc *desc)
2387{
2388 desc->rqcfg.swap = SWAP_NO;
2389 desc->rqcfg.scctl = CCTRL0;
2390 desc->rqcfg.dcctl = CCTRL0;
2391 desc->txd.tx_submit = pl330_tx_submit;
2392
2393 INIT_LIST_HEAD(&desc->node);
2394}
2395
2396/* Returns the number of descriptors added to the DMAC pool */
2397static int add_desc(struct pl330_dmac *pl330, gfp_t flg, int count)
2398{
2399 struct dma_pl330_desc *desc;
2400 unsigned long flags;
2401 int i;
2402
2403 desc = kcalloc(count, sizeof(*desc), flg);
2404 if (!desc)
2405 return 0;
2406
2407 spin_lock_irqsave(&pl330->pool_lock, flags);
2408
2409 for (i = 0; i < count; i++) {
2410 _init_desc(&desc[i]);
2411 list_add_tail(&desc[i].node, &pl330->desc_pool);
2412 }
2413
2414 spin_unlock_irqrestore(&pl330->pool_lock, flags);
2415
2416 return count;
2417}
2418
2419static struct dma_pl330_desc *pluck_desc(struct pl330_dmac *pl330)
2420{
2421 struct dma_pl330_desc *desc = NULL;
2422 unsigned long flags;
2423
2424 spin_lock_irqsave(&pl330->pool_lock, flags);
2425
2426 if (!list_empty(&pl330->desc_pool)) {
2427 desc = list_entry(pl330->desc_pool.next,
2428 struct dma_pl330_desc, node);
2429
2430 list_del_init(&desc->node);
2431
2432 desc->status = PREP;
2433 desc->txd.callback = NULL;
2434 }
2435
2436 spin_unlock_irqrestore(&pl330->pool_lock, flags);
2437
2438 return desc;
2439}
2440
2441static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch)
2442{
2443 struct pl330_dmac *pl330 = pch->dmac;
2444 u8 *peri_id = pch->chan.private;
2445 struct dma_pl330_desc *desc;
2446
2447 /* Pluck one desc from the pool of DMAC */
2448 desc = pluck_desc(pl330);
2449
2450 /* If the DMAC pool is empty, alloc new */
2451 if (!desc) {
2452 if (!add_desc(pl330, GFP_ATOMIC, 1))
2453 return NULL;
2454
2455 /* Try again */
2456 desc = pluck_desc(pl330);
2457 if (!desc) {
2458 dev_err(pch->dmac->ddma.dev,
2459 "%s:%d ALERT!\n", __func__, __LINE__);
2460 return NULL;
2461 }
2462 }
2463
2464 /* Initialize the descriptor */
2465 desc->pchan = pch;
2466 desc->txd.cookie = 0;
2467 async_tx_ack(&desc->txd);
2468
2469 desc->peri = peri_id ? pch->chan.chan_id : 0;
2470 desc->rqcfg.pcfg = &pch->dmac->pcfg;
2471
2472 dma_async_tx_descriptor_init(&desc->txd, &pch->chan);
2473
2474 return desc;
2475}
2476
2477static inline void fill_px(struct pl330_xfer *px,
2478 dma_addr_t dst, dma_addr_t src, size_t len)
2479{
2480 px->bytes = len;
2481 px->dst_addr = dst;
2482 px->src_addr = src;
2483}
2484
2485static struct dma_pl330_desc *
2486__pl330_prep_dma_memcpy(struct dma_pl330_chan *pch, dma_addr_t dst,
2487 dma_addr_t src, size_t len)
2488{
2489 struct dma_pl330_desc *desc = pl330_get_desc(pch);
2490
2491 if (!desc) {
2492 dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
2493 __func__, __LINE__);
2494 return NULL;
2495 }
2496
2497 /*
2498 * Ideally we should lookout for reqs bigger than
2499 * those that can be programmed with 256 bytes of
2500 * MC buffer, but considering a req size is seldom
2501 * going to be word-unaligned and more than 200MB,
2502 * we take it easy.
2503 * Also, should the limit is reached we'd rather
2504 * have the platform increase MC buffer size than
2505 * complicating this API driver.
2506 */
2507 fill_px(&desc->px, dst, src, len);
2508
2509 return desc;
2510}
2511
2512/* Call after fixing burst size */
2513static inline int get_burst_len(struct dma_pl330_desc *desc, size_t len)
2514{
2515 struct dma_pl330_chan *pch = desc->pchan;
2516 struct pl330_dmac *pl330 = pch->dmac;
2517 int burst_len;
2518
2519 burst_len = pl330->pcfg.data_bus_width / 8;
2520 burst_len *= pl330->pcfg.data_buf_dep / pl330->pcfg.num_chan;
2521 burst_len >>= desc->rqcfg.brst_size;
2522
2523 /* src/dst_burst_len can't be more than 16 */
2524 if (burst_len > 16)
2525 burst_len = 16;
2526
2527 while (burst_len > 1) {
2528 if (!(len % (burst_len << desc->rqcfg.brst_size)))
2529 break;
2530 burst_len--;
2531 }
2532
2533 return burst_len;
2534}
2535
2536static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic(
2537 struct dma_chan *chan, dma_addr_t dma_addr, size_t len,
2538 size_t period_len, enum dma_transfer_direction direction,
2539 unsigned long flags)
2540{
2541 struct dma_pl330_desc *desc = NULL, *first = NULL;
2542 struct dma_pl330_chan *pch = to_pchan(chan);
2543 struct pl330_dmac *pl330 = pch->dmac;
2544 unsigned int i;
2545 dma_addr_t dst;
2546 dma_addr_t src;
2547
2548 if (len % period_len != 0)
2549 return NULL;
2550
2551 if (!is_slave_direction(direction)) {
2552 dev_err(pch->dmac->ddma.dev, "%s:%d Invalid dma direction\n",
2553 __func__, __LINE__);
2554 return NULL;
2555 }
2556
2557 for (i = 0; i < len / period_len; i++) {
2558 desc = pl330_get_desc(pch);
2559 if (!desc) {
2560 dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
2561 __func__, __LINE__);
2562
2563 if (!first)
2564 return NULL;
2565
2566 spin_lock_irqsave(&pl330->pool_lock, flags);
2567
2568 while (!list_empty(&first->node)) {
2569 desc = list_entry(first->node.next,
2570 struct dma_pl330_desc, node);
2571 list_move_tail(&desc->node, &pl330->desc_pool);
2572 }
2573
2574 list_move_tail(&first->node, &pl330->desc_pool);
2575
2576 spin_unlock_irqrestore(&pl330->pool_lock, flags);
2577
2578 return NULL;
2579 }
2580
2581 switch (direction) {
2582 case DMA_MEM_TO_DEV:
2583 desc->rqcfg.src_inc = 1;
2584 desc->rqcfg.dst_inc = 0;
2585 src = dma_addr;
2586 dst = pch->fifo_addr;
2587 break;
2588 case DMA_DEV_TO_MEM:
2589 desc->rqcfg.src_inc = 0;
2590 desc->rqcfg.dst_inc = 1;
2591 src = pch->fifo_addr;
2592 dst = dma_addr;
2593 break;
2594 default:
2595 break;
2596 }
2597
2598 desc->rqtype = direction;
2599 desc->rqcfg.brst_size = pch->burst_sz;
2600 desc->rqcfg.brst_len = 1;
2601 desc->bytes_requested = period_len;
2602 fill_px(&desc->px, dst, src, period_len);
2603
2604 if (!first)
2605 first = desc;
2606 else
2607 list_add_tail(&desc->node, &first->node);
2608
2609 dma_addr += period_len;
2610 }
2611
2612 if (!desc)
2613 return NULL;
2614
2615 pch->cyclic = true;
2616 desc->txd.flags = flags;
2617
2618 return &desc->txd;
2619}
2620
2621static struct dma_async_tx_descriptor *
2622pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst,
2623 dma_addr_t src, size_t len, unsigned long flags)
2624{
2625 struct dma_pl330_desc *desc;
2626 struct dma_pl330_chan *pch = to_pchan(chan);
2627 struct pl330_dmac *pl330;
2628 int burst;
2629
2630 if (unlikely(!pch || !len))
2631 return NULL;
2632
2633 pl330 = pch->dmac;
2634
2635 desc = __pl330_prep_dma_memcpy(pch, dst, src, len);
2636 if (!desc)
2637 return NULL;
2638
2639 desc->rqcfg.src_inc = 1;
2640 desc->rqcfg.dst_inc = 1;
2641 desc->rqtype = DMA_MEM_TO_MEM;
2642
2643 /* Select max possible burst size */
2644 burst = pl330->pcfg.data_bus_width / 8;
2645
2646 /*
2647 * Make sure we use a burst size that aligns with all the memcpy
2648 * parameters because our DMA programming algorithm doesn't cope with
2649 * transfers which straddle an entry in the DMA device's MFIFO.
2650 */
2651 while ((src | dst | len) & (burst - 1))
2652 burst /= 2;
2653
2654 desc->rqcfg.brst_size = 0;
2655 while (burst != (1 << desc->rqcfg.brst_size))
2656 desc->rqcfg.brst_size++;
2657
2658 /*
2659 * If burst size is smaller than bus width then make sure we only
2660 * transfer one at a time to avoid a burst stradling an MFIFO entry.
2661 */
2662 if (desc->rqcfg.brst_size * 8 < pl330->pcfg.data_bus_width)
2663 desc->rqcfg.brst_len = 1;
2664
2665 desc->rqcfg.brst_len = get_burst_len(desc, len);
2666 desc->bytes_requested = len;
2667
2668 desc->txd.flags = flags;
2669
2670 return &desc->txd;
2671}
2672
2673static void __pl330_giveback_desc(struct pl330_dmac *pl330,
2674 struct dma_pl330_desc *first)
2675{
2676 unsigned long flags;
2677 struct dma_pl330_desc *desc;
2678
2679 if (!first)
2680 return;
2681
2682 spin_lock_irqsave(&pl330->pool_lock, flags);
2683
2684 while (!list_empty(&first->node)) {
2685 desc = list_entry(first->node.next,
2686 struct dma_pl330_desc, node);
2687 list_move_tail(&desc->node, &pl330->desc_pool);
2688 }
2689
2690 list_move_tail(&first->node, &pl330->desc_pool);
2691
2692 spin_unlock_irqrestore(&pl330->pool_lock, flags);
2693}
2694
2695static struct dma_async_tx_descriptor *
2696pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
2697 unsigned int sg_len, enum dma_transfer_direction direction,
2698 unsigned long flg, void *context)
2699{
2700 struct dma_pl330_desc *first, *desc = NULL;
2701 struct dma_pl330_chan *pch = to_pchan(chan);
2702 struct scatterlist *sg;
2703 int i;
2704 dma_addr_t addr;
2705
2706 if (unlikely(!pch || !sgl || !sg_len))
2707 return NULL;
2708
2709 addr = pch->fifo_addr;
2710
2711 first = NULL;
2712
2713 for_each_sg(sgl, sg, sg_len, i) {
2714
2715 desc = pl330_get_desc(pch);
2716 if (!desc) {
2717 struct pl330_dmac *pl330 = pch->dmac;
2718
2719 dev_err(pch->dmac->ddma.dev,
2720 "%s:%d Unable to fetch desc\n",
2721 __func__, __LINE__);
2722 __pl330_giveback_desc(pl330, first);
2723
2724 return NULL;
2725 }
2726
2727 if (!first)
2728 first = desc;
2729 else
2730 list_add_tail(&desc->node, &first->node);
2731
2732 if (direction == DMA_MEM_TO_DEV) {
2733 desc->rqcfg.src_inc = 1;
2734 desc->rqcfg.dst_inc = 0;
2735 fill_px(&desc->px,
2736 addr, sg_dma_address(sg), sg_dma_len(sg));
2737 } else {
2738 desc->rqcfg.src_inc = 0;
2739 desc->rqcfg.dst_inc = 1;
2740 fill_px(&desc->px,
2741 sg_dma_address(sg), addr, sg_dma_len(sg));
2742 }
2743
2744 desc->rqcfg.brst_size = pch->burst_sz;
2745 desc->rqcfg.brst_len = 1;
2746 desc->rqtype = direction;
2747 desc->bytes_requested = sg_dma_len(sg);
2748 }
2749
2750 /* Return the last desc in the chain */
2751 desc->txd.flags = flg;
2752 return &desc->txd;
2753}
2754
2755static irqreturn_t pl330_irq_handler(int irq, void *data)
2756{
2757 if (pl330_update(data))
2758 return IRQ_HANDLED;
2759 else
2760 return IRQ_NONE;
2761}
2762
2763#define PL330_DMA_BUSWIDTHS \
2764 BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
2765 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
2766 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
2767 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
2768 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)
2769
2770/*
2771 * Runtime PM callbacks are provided by amba/bus.c driver.
2772 *
2773 * It is assumed here that IRQ safe runtime PM is chosen in probe and amba
2774 * bus driver will only disable/enable the clock in runtime PM callbacks.
2775 */
2776static int __maybe_unused pl330_suspend(struct device *dev)
2777{
2778 struct amba_device *pcdev = to_amba_device(dev);
2779
2780 pm_runtime_disable(dev);
2781
2782 if (!pm_runtime_status_suspended(dev)) {
2783 /* amba did not disable the clock */
2784 amba_pclk_disable(pcdev);
2785 }
2786 amba_pclk_unprepare(pcdev);
2787
2788 return 0;
2789}
2790
2791static int __maybe_unused pl330_resume(struct device *dev)
2792{
2793 struct amba_device *pcdev = to_amba_device(dev);
2794 int ret;
2795
2796 ret = amba_pclk_prepare(pcdev);
2797 if (ret)
2798 return ret;
2799
2800 if (!pm_runtime_status_suspended(dev))
2801 ret = amba_pclk_enable(pcdev);
2802
2803 pm_runtime_enable(dev);
2804
2805 return ret;
2806}
2807
2808static SIMPLE_DEV_PM_OPS(pl330_pm, pl330_suspend, pl330_resume);
2809
2810static int
2811pl330_probe(struct amba_device *adev, const struct amba_id *id)
2812{
2813 struct dma_pl330_platdata *pdat;
2814 struct pl330_config *pcfg;
2815 struct pl330_dmac *pl330;
2816 struct dma_pl330_chan *pch, *_p;
2817 struct dma_device *pd;
2818 struct resource *res;
2819 int i, ret, irq;
2820 int num_chan;
2821 struct device_node *np = adev->dev.of_node;
2822
2823 pdat = dev_get_platdata(&adev->dev);
2824
2825 ret = dma_set_mask_and_coherent(&adev->dev, DMA_BIT_MASK(32));
2826 if (ret)
2827 return ret;
2828
2829 /* Allocate a new DMAC and its Channels */
2830 pl330 = devm_kzalloc(&adev->dev, sizeof(*pl330), GFP_KERNEL);
2831 if (!pl330) {
2832 dev_err(&adev->dev, "unable to allocate mem\n");
2833 return -ENOMEM;
2834 }
2835
2836 pd = &pl330->ddma;
2837 pd->dev = &adev->dev;
2838
2839 pl330->mcbufsz = pdat ? pdat->mcbuf_sz : 0;
2840
2841 /* get quirk */
2842 for (i = 0; i < ARRAY_SIZE(of_quirks); i++)
2843 if (of_property_read_bool(np, of_quirks[i].quirk))
2844 pl330->quirks |= of_quirks[i].id;
2845
2846 res = &adev->res;
2847 pl330->base = devm_ioremap_resource(&adev->dev, res);
2848 if (IS_ERR(pl330->base))
2849 return PTR_ERR(pl330->base);
2850
2851 amba_set_drvdata(adev, pl330);
2852
2853 for (i = 0; i < AMBA_NR_IRQS; i++) {
2854 irq = adev->irq[i];
2855 if (irq) {
2856 ret = devm_request_irq(&adev->dev, irq,
2857 pl330_irq_handler, 0,
2858 dev_name(&adev->dev), pl330);
2859 if (ret)
2860 return ret;
2861 } else {
2862 break;
2863 }
2864 }
2865
2866 pcfg = &pl330->pcfg;
2867
2868 pcfg->periph_id = adev->periphid;
2869 ret = pl330_add(pl330);
2870 if (ret)
2871 return ret;
2872
2873 INIT_LIST_HEAD(&pl330->desc_pool);
2874 spin_lock_init(&pl330->pool_lock);
2875
2876 /* Create a descriptor pool of default size */
2877 if (!add_desc(pl330, GFP_KERNEL, NR_DEFAULT_DESC))
2878 dev_warn(&adev->dev, "unable to allocate desc\n");
2879
2880 INIT_LIST_HEAD(&pd->channels);
2881
2882 /* Initialize channel parameters */
2883 if (pdat)
2884 num_chan = max_t(int, pdat->nr_valid_peri, pcfg->num_chan);
2885 else
2886 num_chan = max_t(int, pcfg->num_peri, pcfg->num_chan);
2887
2888 pl330->num_peripherals = num_chan;
2889
2890 pl330->peripherals = kzalloc(num_chan * sizeof(*pch), GFP_KERNEL);
2891 if (!pl330->peripherals) {
2892 ret = -ENOMEM;
2893 dev_err(&adev->dev, "unable to allocate pl330->peripherals\n");
2894 goto probe_err2;
2895 }
2896
2897 for (i = 0; i < num_chan; i++) {
2898 pch = &pl330->peripherals[i];
2899 if (!adev->dev.of_node)
2900 pch->chan.private = pdat ? &pdat->peri_id[i] : NULL;
2901 else
2902 pch->chan.private = adev->dev.of_node;
2903
2904 INIT_LIST_HEAD(&pch->submitted_list);
2905 INIT_LIST_HEAD(&pch->work_list);
2906 INIT_LIST_HEAD(&pch->completed_list);
2907 spin_lock_init(&pch->lock);
2908 pch->thread = NULL;
2909 pch->chan.device = pd;
2910 pch->dmac = pl330;
2911
2912 /* Add the channel to the DMAC list */
2913 list_add_tail(&pch->chan.device_node, &pd->channels);
2914 }
2915
2916 if (pdat) {
2917 pd->cap_mask = pdat->cap_mask;
2918 } else {
2919 dma_cap_set(DMA_MEMCPY, pd->cap_mask);
2920 if (pcfg->num_peri) {
2921 dma_cap_set(DMA_SLAVE, pd->cap_mask);
2922 dma_cap_set(DMA_CYCLIC, pd->cap_mask);
2923 dma_cap_set(DMA_PRIVATE, pd->cap_mask);
2924 }
2925 }
2926
2927 pd->device_alloc_chan_resources = pl330_alloc_chan_resources;
2928 pd->device_free_chan_resources = pl330_free_chan_resources;
2929 pd->device_prep_dma_memcpy = pl330_prep_dma_memcpy;
2930 pd->device_prep_dma_cyclic = pl330_prep_dma_cyclic;
2931 pd->device_tx_status = pl330_tx_status;
2932 pd->device_prep_slave_sg = pl330_prep_slave_sg;
2933 pd->device_config = pl330_config;
2934 pd->device_pause = pl330_pause;
2935 pd->device_terminate_all = pl330_terminate_all;
2936 pd->device_issue_pending = pl330_issue_pending;
2937 pd->src_addr_widths = PL330_DMA_BUSWIDTHS;
2938 pd->dst_addr_widths = PL330_DMA_BUSWIDTHS;
2939 pd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
2940 pd->residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
2941 pd->max_burst = ((pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP) ?
2942 1 : PL330_MAX_BURST);
2943
2944 ret = dma_async_device_register(pd);
2945 if (ret) {
2946 dev_err(&adev->dev, "unable to register DMAC\n");
2947 goto probe_err3;
2948 }
2949
2950 if (adev->dev.of_node) {
2951 ret = of_dma_controller_register(adev->dev.of_node,
2952 of_dma_pl330_xlate, pl330);
2953 if (ret) {
2954 dev_err(&adev->dev,
2955 "unable to register DMA to the generic DT DMA helpers\n");
2956 }
2957 }
2958
2959 adev->dev.dma_parms = &pl330->dma_parms;
2960
2961 /*
2962 * This is the limit for transfers with a buswidth of 1, larger
2963 * buswidths will have larger limits.
2964 */
2965 ret = dma_set_max_seg_size(&adev->dev, 1900800);
2966 if (ret)
2967 dev_err(&adev->dev, "unable to set the seg size\n");
2968
2969
2970 dev_info(&adev->dev,
2971 "Loaded driver for PL330 DMAC-%x\n", adev->periphid);
2972 dev_info(&adev->dev,
2973 "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n",
2974 pcfg->data_buf_dep, pcfg->data_bus_width / 8, pcfg->num_chan,
2975 pcfg->num_peri, pcfg->num_events);
2976
2977 pm_runtime_irq_safe(&adev->dev);
2978 pm_runtime_use_autosuspend(&adev->dev);
2979 pm_runtime_set_autosuspend_delay(&adev->dev, PL330_AUTOSUSPEND_DELAY);
2980 pm_runtime_mark_last_busy(&adev->dev);
2981 pm_runtime_put_autosuspend(&adev->dev);
2982
2983 return 0;
2984probe_err3:
2985 /* Idle the DMAC */
2986 list_for_each_entry_safe(pch, _p, &pl330->ddma.channels,
2987 chan.device_node) {
2988
2989 /* Remove the channel */
2990 list_del(&pch->chan.device_node);
2991
2992 /* Flush the channel */
2993 if (pch->thread) {
2994 pl330_terminate_all(&pch->chan);
2995 pl330_free_chan_resources(&pch->chan);
2996 }
2997 }
2998probe_err2:
2999 pl330_del(pl330);
3000
3001 return ret;
3002}
3003
3004static int pl330_remove(struct amba_device *adev)
3005{
3006 struct pl330_dmac *pl330 = amba_get_drvdata(adev);
3007 struct dma_pl330_chan *pch, *_p;
3008
3009 pm_runtime_get_noresume(pl330->ddma.dev);
3010
3011 if (adev->dev.of_node)
3012 of_dma_controller_free(adev->dev.of_node);
3013
3014 dma_async_device_unregister(&pl330->ddma);
3015
3016 /* Idle the DMAC */
3017 list_for_each_entry_safe(pch, _p, &pl330->ddma.channels,
3018 chan.device_node) {
3019
3020 /* Remove the channel */
3021 list_del(&pch->chan.device_node);
3022
3023 /* Flush the channel */
3024 if (pch->thread) {
3025 pl330_terminate_all(&pch->chan);
3026 pl330_free_chan_resources(&pch->chan);
3027 }
3028 }
3029
3030 pl330_del(pl330);
3031
3032 return 0;
3033}
3034
3035static struct amba_id pl330_ids[] = {
3036 {
3037 .id = 0x00041330,
3038 .mask = 0x000fffff,
3039 },
3040 { 0, 0 },
3041};
3042
3043MODULE_DEVICE_TABLE(amba, pl330_ids);
3044
3045static struct amba_driver pl330_driver = {
3046 .drv = {
3047 .owner = THIS_MODULE,
3048 .name = "dma-pl330",
3049 .pm = &pl330_pm,
3050 },
3051 .id_table = pl330_ids,
3052 .probe = pl330_probe,
3053 .remove = pl330_remove,
3054};
3055
3056module_amba_driver(pl330_driver);
3057
3058MODULE_AUTHOR("Jaswinder Singh <jassisinghbrar@gmail.com>");
3059MODULE_DESCRIPTION("API Driver for PL330 DMAC");
3060MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
7 * Jaswinder Singh <jassi.brar@samsung.com>
8 */
9
10#include <linux/debugfs.h>
11#include <linux/kernel.h>
12#include <linux/io.h>
13#include <linux/init.h>
14#include <linux/slab.h>
15#include <linux/module.h>
16#include <linux/string.h>
17#include <linux/delay.h>
18#include <linux/interrupt.h>
19#include <linux/dma-mapping.h>
20#include <linux/dmaengine.h>
21#include <linux/amba/bus.h>
22#include <linux/scatterlist.h>
23#include <linux/of.h>
24#include <linux/of_dma.h>
25#include <linux/err.h>
26#include <linux/pm_runtime.h>
27#include <linux/bug.h>
28#include <linux/reset.h>
29
30#include "dmaengine.h"
31#define PL330_MAX_CHAN 8
32#define PL330_MAX_IRQS 32
33#define PL330_MAX_PERI 32
34#define PL330_MAX_BURST 16
35
36#define PL330_QUIRK_BROKEN_NO_FLUSHP BIT(0)
37#define PL330_QUIRK_PERIPH_BURST BIT(1)
38
39enum pl330_cachectrl {
40 CCTRL0, /* Noncacheable and nonbufferable */
41 CCTRL1, /* Bufferable only */
42 CCTRL2, /* Cacheable, but do not allocate */
43 CCTRL3, /* Cacheable and bufferable, but do not allocate */
44 INVALID1, /* AWCACHE = 0x1000 */
45 INVALID2,
46 CCTRL6, /* Cacheable write-through, allocate on writes only */
47 CCTRL7, /* Cacheable write-back, allocate on writes only */
48};
49
50enum pl330_byteswap {
51 SWAP_NO,
52 SWAP_2,
53 SWAP_4,
54 SWAP_8,
55 SWAP_16,
56};
57
58/* Register and Bit field Definitions */
59#define DS 0x0
60#define DS_ST_STOP 0x0
61#define DS_ST_EXEC 0x1
62#define DS_ST_CMISS 0x2
63#define DS_ST_UPDTPC 0x3
64#define DS_ST_WFE 0x4
65#define DS_ST_ATBRR 0x5
66#define DS_ST_QBUSY 0x6
67#define DS_ST_WFP 0x7
68#define DS_ST_KILL 0x8
69#define DS_ST_CMPLT 0x9
70#define DS_ST_FLTCMP 0xe
71#define DS_ST_FAULT 0xf
72
73#define DPC 0x4
74#define INTEN 0x20
75#define ES 0x24
76#define INTSTATUS 0x28
77#define INTCLR 0x2c
78#define FSM 0x30
79#define FSC 0x34
80#define FTM 0x38
81
82#define _FTC 0x40
83#define FTC(n) (_FTC + (n)*0x4)
84
85#define _CS 0x100
86#define CS(n) (_CS + (n)*0x8)
87#define CS_CNS (1 << 21)
88
89#define _CPC 0x104
90#define CPC(n) (_CPC + (n)*0x8)
91
92#define _SA 0x400
93#define SA(n) (_SA + (n)*0x20)
94
95#define _DA 0x404
96#define DA(n) (_DA + (n)*0x20)
97
98#define _CC 0x408
99#define CC(n) (_CC + (n)*0x20)
100
101#define CC_SRCINC (1 << 0)
102#define CC_DSTINC (1 << 14)
103#define CC_SRCPRI (1 << 8)
104#define CC_DSTPRI (1 << 22)
105#define CC_SRCNS (1 << 9)
106#define CC_DSTNS (1 << 23)
107#define CC_SRCIA (1 << 10)
108#define CC_DSTIA (1 << 24)
109#define CC_SRCBRSTLEN_SHFT 4
110#define CC_DSTBRSTLEN_SHFT 18
111#define CC_SRCBRSTSIZE_SHFT 1
112#define CC_DSTBRSTSIZE_SHFT 15
113#define CC_SRCCCTRL_SHFT 11
114#define CC_SRCCCTRL_MASK 0x7
115#define CC_DSTCCTRL_SHFT 25
116#define CC_DRCCCTRL_MASK 0x7
117#define CC_SWAP_SHFT 28
118
119#define _LC0 0x40c
120#define LC0(n) (_LC0 + (n)*0x20)
121
122#define _LC1 0x410
123#define LC1(n) (_LC1 + (n)*0x20)
124
125#define DBGSTATUS 0xd00
126#define DBG_BUSY (1 << 0)
127
128#define DBGCMD 0xd04
129#define DBGINST0 0xd08
130#define DBGINST1 0xd0c
131
132#define CR0 0xe00
133#define CR1 0xe04
134#define CR2 0xe08
135#define CR3 0xe0c
136#define CR4 0xe10
137#define CRD 0xe14
138
139#define PERIPH_ID 0xfe0
140#define PERIPH_REV_SHIFT 20
141#define PERIPH_REV_MASK 0xf
142#define PERIPH_REV_R0P0 0
143#define PERIPH_REV_R1P0 1
144#define PERIPH_REV_R1P1 2
145
146#define CR0_PERIPH_REQ_SET (1 << 0)
147#define CR0_BOOT_EN_SET (1 << 1)
148#define CR0_BOOT_MAN_NS (1 << 2)
149#define CR0_NUM_CHANS_SHIFT 4
150#define CR0_NUM_CHANS_MASK 0x7
151#define CR0_NUM_PERIPH_SHIFT 12
152#define CR0_NUM_PERIPH_MASK 0x1f
153#define CR0_NUM_EVENTS_SHIFT 17
154#define CR0_NUM_EVENTS_MASK 0x1f
155
156#define CR1_ICACHE_LEN_SHIFT 0
157#define CR1_ICACHE_LEN_MASK 0x7
158#define CR1_NUM_ICACHELINES_SHIFT 4
159#define CR1_NUM_ICACHELINES_MASK 0xf
160
161#define CRD_DATA_WIDTH_SHIFT 0
162#define CRD_DATA_WIDTH_MASK 0x7
163#define CRD_WR_CAP_SHIFT 4
164#define CRD_WR_CAP_MASK 0x7
165#define CRD_WR_Q_DEP_SHIFT 8
166#define CRD_WR_Q_DEP_MASK 0xf
167#define CRD_RD_CAP_SHIFT 12
168#define CRD_RD_CAP_MASK 0x7
169#define CRD_RD_Q_DEP_SHIFT 16
170#define CRD_RD_Q_DEP_MASK 0xf
171#define CRD_DATA_BUFF_SHIFT 20
172#define CRD_DATA_BUFF_MASK 0x3ff
173
174#define PART 0x330
175#define DESIGNER 0x41
176#define REVISION 0x0
177#define INTEG_CFG 0x0
178#define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12))
179
180#define PL330_STATE_STOPPED (1 << 0)
181#define PL330_STATE_EXECUTING (1 << 1)
182#define PL330_STATE_WFE (1 << 2)
183#define PL330_STATE_FAULTING (1 << 3)
184#define PL330_STATE_COMPLETING (1 << 4)
185#define PL330_STATE_WFP (1 << 5)
186#define PL330_STATE_KILLING (1 << 6)
187#define PL330_STATE_FAULT_COMPLETING (1 << 7)
188#define PL330_STATE_CACHEMISS (1 << 8)
189#define PL330_STATE_UPDTPC (1 << 9)
190#define PL330_STATE_ATBARRIER (1 << 10)
191#define PL330_STATE_QUEUEBUSY (1 << 11)
192#define PL330_STATE_INVALID (1 << 15)
193
194#define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \
195 | PL330_STATE_WFE | PL330_STATE_FAULTING)
196
197#define CMD_DMAADDH 0x54
198#define CMD_DMAEND 0x00
199#define CMD_DMAFLUSHP 0x35
200#define CMD_DMAGO 0xa0
201#define CMD_DMALD 0x04
202#define CMD_DMALDP 0x25
203#define CMD_DMALP 0x20
204#define CMD_DMALPEND 0x28
205#define CMD_DMAKILL 0x01
206#define CMD_DMAMOV 0xbc
207#define CMD_DMANOP 0x18
208#define CMD_DMARMB 0x12
209#define CMD_DMASEV 0x34
210#define CMD_DMAST 0x08
211#define CMD_DMASTP 0x29
212#define CMD_DMASTZ 0x0c
213#define CMD_DMAWFE 0x36
214#define CMD_DMAWFP 0x30
215#define CMD_DMAWMB 0x13
216
217#define SZ_DMAADDH 3
218#define SZ_DMAEND 1
219#define SZ_DMAFLUSHP 2
220#define SZ_DMALD 1
221#define SZ_DMALDP 2
222#define SZ_DMALP 2
223#define SZ_DMALPEND 2
224#define SZ_DMAKILL 1
225#define SZ_DMAMOV 6
226#define SZ_DMANOP 1
227#define SZ_DMARMB 1
228#define SZ_DMASEV 2
229#define SZ_DMAST 1
230#define SZ_DMASTP 2
231#define SZ_DMASTZ 1
232#define SZ_DMAWFE 2
233#define SZ_DMAWFP 2
234#define SZ_DMAWMB 1
235#define SZ_DMAGO 6
236
237#define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1)
238#define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7))
239
240#define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr))
241#define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr))
242
243/*
244 * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req
245 * at 1byte/burst for P<->M and M<->M respectively.
246 * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req
247 * should be enough for P<->M and M<->M respectively.
248 */
249#define MCODE_BUFF_PER_REQ 256
250
251/* Use this _only_ to wait on transient states */
252#define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax();
253
254#ifdef PL330_DEBUG_MCGEN
255static unsigned cmd_line;
256#define PL330_DBGCMD_DUMP(off, x...) do { \
257 printk("%x:", cmd_line); \
258 printk(KERN_CONT x); \
259 cmd_line += off; \
260 } while (0)
261#define PL330_DBGMC_START(addr) (cmd_line = addr)
262#else
263#define PL330_DBGCMD_DUMP(off, x...) do {} while (0)
264#define PL330_DBGMC_START(addr) do {} while (0)
265#endif
266
267/* The number of default descriptors */
268
269#define NR_DEFAULT_DESC 16
270
271/* Delay for runtime PM autosuspend, ms */
272#define PL330_AUTOSUSPEND_DELAY 20
273
274/* Populated by the PL330 core driver for DMA API driver's info */
275struct pl330_config {
276 u32 periph_id;
277#define DMAC_MODE_NS (1 << 0)
278 unsigned int mode;
279 unsigned int data_bus_width:10; /* In number of bits */
280 unsigned int data_buf_dep:11;
281 unsigned int num_chan:4;
282 unsigned int num_peri:6;
283 u32 peri_ns;
284 unsigned int num_events:6;
285 u32 irq_ns;
286};
287
288/*
289 * Request Configuration.
290 * The PL330 core does not modify this and uses the last
291 * working configuration if the request doesn't provide any.
292 *
293 * The Client may want to provide this info only for the
294 * first request and a request with new settings.
295 */
296struct pl330_reqcfg {
297 /* Address Incrementing */
298 unsigned dst_inc:1;
299 unsigned src_inc:1;
300
301 /*
302 * For now, the SRC & DST protection levels
303 * and burst size/length are assumed same.
304 */
305 bool nonsecure;
306 bool privileged;
307 bool insnaccess;
308 unsigned brst_len:5;
309 unsigned brst_size:3; /* in power of 2 */
310
311 enum pl330_cachectrl dcctl;
312 enum pl330_cachectrl scctl;
313 enum pl330_byteswap swap;
314 struct pl330_config *pcfg;
315};
316
317/*
318 * One cycle of DMAC operation.
319 * There may be more than one xfer in a request.
320 */
321struct pl330_xfer {
322 u32 src_addr;
323 u32 dst_addr;
324 /* Size to xfer */
325 u32 bytes;
326};
327
328/* The xfer callbacks are made with one of these arguments. */
329enum pl330_op_err {
330 /* The all xfers in the request were success. */
331 PL330_ERR_NONE,
332 /* If req aborted due to global error. */
333 PL330_ERR_ABORT,
334 /* If req failed due to problem with Channel. */
335 PL330_ERR_FAIL,
336};
337
338enum dmamov_dst {
339 SAR = 0,
340 CCR,
341 DAR,
342};
343
344enum pl330_dst {
345 SRC = 0,
346 DST,
347};
348
349enum pl330_cond {
350 SINGLE,
351 BURST,
352 ALWAYS,
353};
354
355struct dma_pl330_desc;
356
357struct _pl330_req {
358 u32 mc_bus;
359 void *mc_cpu;
360 struct dma_pl330_desc *desc;
361};
362
363/* ToBeDone for tasklet */
364struct _pl330_tbd {
365 bool reset_dmac;
366 bool reset_mngr;
367 u8 reset_chan;
368};
369
370/* A DMAC Thread */
371struct pl330_thread {
372 u8 id;
373 int ev;
374 /* If the channel is not yet acquired by any client */
375 bool free;
376 /* Parent DMAC */
377 struct pl330_dmac *dmac;
378 /* Only two at a time */
379 struct _pl330_req req[2];
380 /* Index of the last enqueued request */
381 unsigned lstenq;
382 /* Index of the last submitted request or -1 if the DMA is stopped */
383 int req_running;
384};
385
386enum pl330_dmac_state {
387 UNINIT,
388 INIT,
389 DYING,
390};
391
392enum desc_status {
393 /* In the DMAC pool */
394 FREE,
395 /*
396 * Allocated to some channel during prep_xxx
397 * Also may be sitting on the work_list.
398 */
399 PREP,
400 /*
401 * Sitting on the work_list and already submitted
402 * to the PL330 core. Not more than two descriptors
403 * of a channel can be BUSY at any time.
404 */
405 BUSY,
406 /*
407 * Sitting on the channel work_list but xfer done
408 * by PL330 core
409 */
410 DONE,
411};
412
413struct dma_pl330_chan {
414 /* Schedule desc completion */
415 struct tasklet_struct task;
416
417 /* DMA-Engine Channel */
418 struct dma_chan chan;
419
420 /* List of submitted descriptors */
421 struct list_head submitted_list;
422 /* List of issued descriptors */
423 struct list_head work_list;
424 /* List of completed descriptors */
425 struct list_head completed_list;
426
427 /* Pointer to the DMAC that manages this channel,
428 * NULL if the channel is available to be acquired.
429 * As the parent, this DMAC also provides descriptors
430 * to the channel.
431 */
432 struct pl330_dmac *dmac;
433
434 /* To protect channel manipulation */
435 spinlock_t lock;
436
437 /*
438 * Hardware channel thread of PL330 DMAC. NULL if the channel is
439 * available.
440 */
441 struct pl330_thread *thread;
442
443 /* For D-to-M and M-to-D channels */
444 int burst_sz; /* the peripheral fifo width */
445 int burst_len; /* the number of burst */
446 phys_addr_t fifo_addr;
447 /* DMA-mapped view of the FIFO; may differ if an IOMMU is present */
448 dma_addr_t fifo_dma;
449 enum dma_data_direction dir;
450 struct dma_slave_config slave_config;
451
452 /* for cyclic capability */
453 bool cyclic;
454
455 /* for runtime pm tracking */
456 bool active;
457};
458
459struct pl330_dmac {
460 /* DMA-Engine Device */
461 struct dma_device ddma;
462
463 /* Pool of descriptors available for the DMAC's channels */
464 struct list_head desc_pool;
465 /* To protect desc_pool manipulation */
466 spinlock_t pool_lock;
467
468 /* Size of MicroCode buffers for each channel. */
469 unsigned mcbufsz;
470 /* ioremap'ed address of PL330 registers. */
471 void __iomem *base;
472 /* Populated by the PL330 core driver during pl330_add */
473 struct pl330_config pcfg;
474
475 spinlock_t lock;
476 /* Maximum possible events/irqs */
477 int events[32];
478 /* BUS address of MicroCode buffer */
479 dma_addr_t mcode_bus;
480 /* CPU address of MicroCode buffer */
481 void *mcode_cpu;
482 /* List of all Channel threads */
483 struct pl330_thread *channels;
484 /* Pointer to the MANAGER thread */
485 struct pl330_thread *manager;
486 /* To handle bad news in interrupt */
487 struct tasklet_struct tasks;
488 struct _pl330_tbd dmac_tbd;
489 /* State of DMAC operation */
490 enum pl330_dmac_state state;
491 /* Holds list of reqs with due callbacks */
492 struct list_head req_done;
493
494 /* Peripheral channels connected to this DMAC */
495 unsigned int num_peripherals;
496 struct dma_pl330_chan *peripherals; /* keep at end */
497 int quirks;
498
499 struct reset_control *rstc;
500 struct reset_control *rstc_ocp;
501};
502
503static struct pl330_of_quirks {
504 char *quirk;
505 int id;
506} of_quirks[] = {
507 {
508 .quirk = "arm,pl330-broken-no-flushp",
509 .id = PL330_QUIRK_BROKEN_NO_FLUSHP,
510 },
511 {
512 .quirk = "arm,pl330-periph-burst",
513 .id = PL330_QUIRK_PERIPH_BURST,
514 }
515};
516
517struct dma_pl330_desc {
518 /* To attach to a queue as child */
519 struct list_head node;
520
521 /* Descriptor for the DMA Engine API */
522 struct dma_async_tx_descriptor txd;
523
524 /* Xfer for PL330 core */
525 struct pl330_xfer px;
526
527 struct pl330_reqcfg rqcfg;
528
529 enum desc_status status;
530
531 int bytes_requested;
532 bool last;
533
534 /* The channel which currently holds this desc */
535 struct dma_pl330_chan *pchan;
536
537 enum dma_transfer_direction rqtype;
538 /* Index of peripheral for the xfer. */
539 unsigned peri:5;
540 /* Hook to attach to DMAC's list of reqs with due callback */
541 struct list_head rqd;
542};
543
544struct _xfer_spec {
545 u32 ccr;
546 struct dma_pl330_desc *desc;
547};
548
549static int pl330_config_write(struct dma_chan *chan,
550 struct dma_slave_config *slave_config,
551 enum dma_transfer_direction direction);
552
553static inline bool _queue_full(struct pl330_thread *thrd)
554{
555 return thrd->req[0].desc != NULL && thrd->req[1].desc != NULL;
556}
557
558static inline bool is_manager(struct pl330_thread *thrd)
559{
560 return thrd->dmac->manager == thrd;
561}
562
563/* If manager of the thread is in Non-Secure mode */
564static inline bool _manager_ns(struct pl330_thread *thrd)
565{
566 return (thrd->dmac->pcfg.mode & DMAC_MODE_NS) ? true : false;
567}
568
569static inline u32 get_revision(u32 periph_id)
570{
571 return (periph_id >> PERIPH_REV_SHIFT) & PERIPH_REV_MASK;
572}
573
574static inline u32 _emit_END(unsigned dry_run, u8 buf[])
575{
576 if (dry_run)
577 return SZ_DMAEND;
578
579 buf[0] = CMD_DMAEND;
580
581 PL330_DBGCMD_DUMP(SZ_DMAEND, "\tDMAEND\n");
582
583 return SZ_DMAEND;
584}
585
586static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri)
587{
588 if (dry_run)
589 return SZ_DMAFLUSHP;
590
591 buf[0] = CMD_DMAFLUSHP;
592
593 peri &= 0x1f;
594 peri <<= 3;
595 buf[1] = peri;
596
597 PL330_DBGCMD_DUMP(SZ_DMAFLUSHP, "\tDMAFLUSHP %u\n", peri >> 3);
598
599 return SZ_DMAFLUSHP;
600}
601
602static inline u32 _emit_LD(unsigned dry_run, u8 buf[], enum pl330_cond cond)
603{
604 if (dry_run)
605 return SZ_DMALD;
606
607 buf[0] = CMD_DMALD;
608
609 if (cond == SINGLE)
610 buf[0] |= (0 << 1) | (1 << 0);
611 else if (cond == BURST)
612 buf[0] |= (1 << 1) | (1 << 0);
613
614 PL330_DBGCMD_DUMP(SZ_DMALD, "\tDMALD%c\n",
615 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
616
617 return SZ_DMALD;
618}
619
620static inline u32 _emit_LDP(unsigned dry_run, u8 buf[],
621 enum pl330_cond cond, u8 peri)
622{
623 if (dry_run)
624 return SZ_DMALDP;
625
626 buf[0] = CMD_DMALDP;
627
628 if (cond == BURST)
629 buf[0] |= (1 << 1);
630
631 peri &= 0x1f;
632 peri <<= 3;
633 buf[1] = peri;
634
635 PL330_DBGCMD_DUMP(SZ_DMALDP, "\tDMALDP%c %u\n",
636 cond == SINGLE ? 'S' : 'B', peri >> 3);
637
638 return SZ_DMALDP;
639}
640
641static inline u32 _emit_LP(unsigned dry_run, u8 buf[],
642 unsigned loop, u8 cnt)
643{
644 if (dry_run)
645 return SZ_DMALP;
646
647 buf[0] = CMD_DMALP;
648
649 if (loop)
650 buf[0] |= (1 << 1);
651
652 cnt--; /* DMAC increments by 1 internally */
653 buf[1] = cnt;
654
655 PL330_DBGCMD_DUMP(SZ_DMALP, "\tDMALP_%c %u\n", loop ? '1' : '0', cnt);
656
657 return SZ_DMALP;
658}
659
660struct _arg_LPEND {
661 enum pl330_cond cond;
662 bool forever;
663 unsigned loop;
664 u8 bjump;
665};
666
667static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[],
668 const struct _arg_LPEND *arg)
669{
670 enum pl330_cond cond = arg->cond;
671 bool forever = arg->forever;
672 unsigned loop = arg->loop;
673 u8 bjump = arg->bjump;
674
675 if (dry_run)
676 return SZ_DMALPEND;
677
678 buf[0] = CMD_DMALPEND;
679
680 if (loop)
681 buf[0] |= (1 << 2);
682
683 if (!forever)
684 buf[0] |= (1 << 4);
685
686 if (cond == SINGLE)
687 buf[0] |= (0 << 1) | (1 << 0);
688 else if (cond == BURST)
689 buf[0] |= (1 << 1) | (1 << 0);
690
691 buf[1] = bjump;
692
693 PL330_DBGCMD_DUMP(SZ_DMALPEND, "\tDMALP%s%c_%c bjmpto_%x\n",
694 forever ? "FE" : "END",
695 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'),
696 loop ? '1' : '0',
697 bjump);
698
699 return SZ_DMALPEND;
700}
701
702static inline u32 _emit_KILL(unsigned dry_run, u8 buf[])
703{
704 if (dry_run)
705 return SZ_DMAKILL;
706
707 buf[0] = CMD_DMAKILL;
708
709 return SZ_DMAKILL;
710}
711
712static inline u32 _emit_MOV(unsigned dry_run, u8 buf[],
713 enum dmamov_dst dst, u32 val)
714{
715 if (dry_run)
716 return SZ_DMAMOV;
717
718 buf[0] = CMD_DMAMOV;
719 buf[1] = dst;
720 buf[2] = val;
721 buf[3] = val >> 8;
722 buf[4] = val >> 16;
723 buf[5] = val >> 24;
724
725 PL330_DBGCMD_DUMP(SZ_DMAMOV, "\tDMAMOV %s 0x%x\n",
726 dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val);
727
728 return SZ_DMAMOV;
729}
730
731static inline u32 _emit_RMB(unsigned dry_run, u8 buf[])
732{
733 if (dry_run)
734 return SZ_DMARMB;
735
736 buf[0] = CMD_DMARMB;
737
738 PL330_DBGCMD_DUMP(SZ_DMARMB, "\tDMARMB\n");
739
740 return SZ_DMARMB;
741}
742
743static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev)
744{
745 if (dry_run)
746 return SZ_DMASEV;
747
748 buf[0] = CMD_DMASEV;
749
750 ev &= 0x1f;
751 ev <<= 3;
752 buf[1] = ev;
753
754 PL330_DBGCMD_DUMP(SZ_DMASEV, "\tDMASEV %u\n", ev >> 3);
755
756 return SZ_DMASEV;
757}
758
759static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond)
760{
761 if (dry_run)
762 return SZ_DMAST;
763
764 buf[0] = CMD_DMAST;
765
766 if (cond == SINGLE)
767 buf[0] |= (0 << 1) | (1 << 0);
768 else if (cond == BURST)
769 buf[0] |= (1 << 1) | (1 << 0);
770
771 PL330_DBGCMD_DUMP(SZ_DMAST, "\tDMAST%c\n",
772 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
773
774 return SZ_DMAST;
775}
776
777static inline u32 _emit_STP(unsigned dry_run, u8 buf[],
778 enum pl330_cond cond, u8 peri)
779{
780 if (dry_run)
781 return SZ_DMASTP;
782
783 buf[0] = CMD_DMASTP;
784
785 if (cond == BURST)
786 buf[0] |= (1 << 1);
787
788 peri &= 0x1f;
789 peri <<= 3;
790 buf[1] = peri;
791
792 PL330_DBGCMD_DUMP(SZ_DMASTP, "\tDMASTP%c %u\n",
793 cond == SINGLE ? 'S' : 'B', peri >> 3);
794
795 return SZ_DMASTP;
796}
797
798static inline u32 _emit_WFP(unsigned dry_run, u8 buf[],
799 enum pl330_cond cond, u8 peri)
800{
801 if (dry_run)
802 return SZ_DMAWFP;
803
804 buf[0] = CMD_DMAWFP;
805
806 if (cond == SINGLE)
807 buf[0] |= (0 << 1) | (0 << 0);
808 else if (cond == BURST)
809 buf[0] |= (1 << 1) | (0 << 0);
810 else
811 buf[0] |= (0 << 1) | (1 << 0);
812
813 peri &= 0x1f;
814 peri <<= 3;
815 buf[1] = peri;
816
817 PL330_DBGCMD_DUMP(SZ_DMAWFP, "\tDMAWFP%c %u\n",
818 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'P'), peri >> 3);
819
820 return SZ_DMAWFP;
821}
822
823static inline u32 _emit_WMB(unsigned dry_run, u8 buf[])
824{
825 if (dry_run)
826 return SZ_DMAWMB;
827
828 buf[0] = CMD_DMAWMB;
829
830 PL330_DBGCMD_DUMP(SZ_DMAWMB, "\tDMAWMB\n");
831
832 return SZ_DMAWMB;
833}
834
835struct _arg_GO {
836 u8 chan;
837 u32 addr;
838 unsigned ns;
839};
840
841static inline u32 _emit_GO(unsigned dry_run, u8 buf[],
842 const struct _arg_GO *arg)
843{
844 u8 chan = arg->chan;
845 u32 addr = arg->addr;
846 unsigned ns = arg->ns;
847
848 if (dry_run)
849 return SZ_DMAGO;
850
851 buf[0] = CMD_DMAGO;
852 buf[0] |= (ns << 1);
853 buf[1] = chan & 0x7;
854 buf[2] = addr;
855 buf[3] = addr >> 8;
856 buf[4] = addr >> 16;
857 buf[5] = addr >> 24;
858
859 return SZ_DMAGO;
860}
861
862#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
863
864/* Returns Time-Out */
865static bool _until_dmac_idle(struct pl330_thread *thrd)
866{
867 void __iomem *regs = thrd->dmac->base;
868 unsigned long loops = msecs_to_loops(5);
869
870 do {
871 /* Until Manager is Idle */
872 if (!(readl(regs + DBGSTATUS) & DBG_BUSY))
873 break;
874
875 cpu_relax();
876 } while (--loops);
877
878 if (!loops)
879 return true;
880
881 return false;
882}
883
884static inline void _execute_DBGINSN(struct pl330_thread *thrd,
885 u8 insn[], bool as_manager)
886{
887 void __iomem *regs = thrd->dmac->base;
888 u32 val;
889
890 /* If timed out due to halted state-machine */
891 if (_until_dmac_idle(thrd)) {
892 dev_err(thrd->dmac->ddma.dev, "DMAC halted!\n");
893 return;
894 }
895
896 val = (insn[0] << 16) | (insn[1] << 24);
897 if (!as_manager) {
898 val |= (1 << 0);
899 val |= (thrd->id << 8); /* Channel Number */
900 }
901 writel(val, regs + DBGINST0);
902
903 val = le32_to_cpu(*((__le32 *)&insn[2]));
904 writel(val, regs + DBGINST1);
905
906 /* Get going */
907 writel(0, regs + DBGCMD);
908}
909
910static inline u32 _state(struct pl330_thread *thrd)
911{
912 void __iomem *regs = thrd->dmac->base;
913 u32 val;
914
915 if (is_manager(thrd))
916 val = readl(regs + DS) & 0xf;
917 else
918 val = readl(regs + CS(thrd->id)) & 0xf;
919
920 switch (val) {
921 case DS_ST_STOP:
922 return PL330_STATE_STOPPED;
923 case DS_ST_EXEC:
924 return PL330_STATE_EXECUTING;
925 case DS_ST_CMISS:
926 return PL330_STATE_CACHEMISS;
927 case DS_ST_UPDTPC:
928 return PL330_STATE_UPDTPC;
929 case DS_ST_WFE:
930 return PL330_STATE_WFE;
931 case DS_ST_FAULT:
932 return PL330_STATE_FAULTING;
933 case DS_ST_ATBRR:
934 if (is_manager(thrd))
935 return PL330_STATE_INVALID;
936 else
937 return PL330_STATE_ATBARRIER;
938 case DS_ST_QBUSY:
939 if (is_manager(thrd))
940 return PL330_STATE_INVALID;
941 else
942 return PL330_STATE_QUEUEBUSY;
943 case DS_ST_WFP:
944 if (is_manager(thrd))
945 return PL330_STATE_INVALID;
946 else
947 return PL330_STATE_WFP;
948 case DS_ST_KILL:
949 if (is_manager(thrd))
950 return PL330_STATE_INVALID;
951 else
952 return PL330_STATE_KILLING;
953 case DS_ST_CMPLT:
954 if (is_manager(thrd))
955 return PL330_STATE_INVALID;
956 else
957 return PL330_STATE_COMPLETING;
958 case DS_ST_FLTCMP:
959 if (is_manager(thrd))
960 return PL330_STATE_INVALID;
961 else
962 return PL330_STATE_FAULT_COMPLETING;
963 default:
964 return PL330_STATE_INVALID;
965 }
966}
967
968static void _stop(struct pl330_thread *thrd)
969{
970 void __iomem *regs = thrd->dmac->base;
971 u8 insn[6] = {0, 0, 0, 0, 0, 0};
972 u32 inten = readl(regs + INTEN);
973
974 if (_state(thrd) == PL330_STATE_FAULT_COMPLETING)
975 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
976
977 /* Return if nothing needs to be done */
978 if (_state(thrd) == PL330_STATE_COMPLETING
979 || _state(thrd) == PL330_STATE_KILLING
980 || _state(thrd) == PL330_STATE_STOPPED)
981 return;
982
983 _emit_KILL(0, insn);
984
985 _execute_DBGINSN(thrd, insn, is_manager(thrd));
986
987 /* clear the event */
988 if (inten & (1 << thrd->ev))
989 writel(1 << thrd->ev, regs + INTCLR);
990 /* Stop generating interrupts for SEV */
991 writel(inten & ~(1 << thrd->ev), regs + INTEN);
992}
993
994/* Start doing req 'idx' of thread 'thrd' */
995static bool _trigger(struct pl330_thread *thrd)
996{
997 void __iomem *regs = thrd->dmac->base;
998 struct _pl330_req *req;
999 struct dma_pl330_desc *desc;
1000 struct _arg_GO go;
1001 unsigned ns;
1002 u8 insn[6] = {0, 0, 0, 0, 0, 0};
1003 int idx;
1004
1005 /* Return if already ACTIVE */
1006 if (_state(thrd) != PL330_STATE_STOPPED)
1007 return true;
1008
1009 idx = 1 - thrd->lstenq;
1010 if (thrd->req[idx].desc != NULL) {
1011 req = &thrd->req[idx];
1012 } else {
1013 idx = thrd->lstenq;
1014 if (thrd->req[idx].desc != NULL)
1015 req = &thrd->req[idx];
1016 else
1017 req = NULL;
1018 }
1019
1020 /* Return if no request */
1021 if (!req)
1022 return true;
1023
1024 /* Return if req is running */
1025 if (idx == thrd->req_running)
1026 return true;
1027
1028 desc = req->desc;
1029
1030 ns = desc->rqcfg.nonsecure ? 1 : 0;
1031
1032 /* See 'Abort Sources' point-4 at Page 2-25 */
1033 if (_manager_ns(thrd) && !ns)
1034 dev_info(thrd->dmac->ddma.dev, "%s:%d Recipe for ABORT!\n",
1035 __func__, __LINE__);
1036
1037 go.chan = thrd->id;
1038 go.addr = req->mc_bus;
1039 go.ns = ns;
1040 _emit_GO(0, insn, &go);
1041
1042 /* Set to generate interrupts for SEV */
1043 writel(readl(regs + INTEN) | (1 << thrd->ev), regs + INTEN);
1044
1045 /* Only manager can execute GO */
1046 _execute_DBGINSN(thrd, insn, true);
1047
1048 thrd->req_running = idx;
1049
1050 return true;
1051}
1052
1053static bool _start(struct pl330_thread *thrd)
1054{
1055 switch (_state(thrd)) {
1056 case PL330_STATE_FAULT_COMPLETING:
1057 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
1058
1059 if (_state(thrd) == PL330_STATE_KILLING)
1060 UNTIL(thrd, PL330_STATE_STOPPED)
1061 fallthrough;
1062
1063 case PL330_STATE_FAULTING:
1064 _stop(thrd);
1065 fallthrough;
1066
1067 case PL330_STATE_KILLING:
1068 case PL330_STATE_COMPLETING:
1069 UNTIL(thrd, PL330_STATE_STOPPED)
1070 fallthrough;
1071
1072 case PL330_STATE_STOPPED:
1073 return _trigger(thrd);
1074
1075 case PL330_STATE_WFP:
1076 case PL330_STATE_QUEUEBUSY:
1077 case PL330_STATE_ATBARRIER:
1078 case PL330_STATE_UPDTPC:
1079 case PL330_STATE_CACHEMISS:
1080 case PL330_STATE_EXECUTING:
1081 return true;
1082
1083 case PL330_STATE_WFE: /* For RESUME, nothing yet */
1084 default:
1085 return false;
1086 }
1087}
1088
1089static inline int _ldst_memtomem(unsigned dry_run, u8 buf[],
1090 const struct _xfer_spec *pxs, int cyc)
1091{
1092 int off = 0;
1093 struct pl330_config *pcfg = pxs->desc->rqcfg.pcfg;
1094
1095 /* check lock-up free version */
1096 if (get_revision(pcfg->periph_id) >= PERIPH_REV_R1P0) {
1097 while (cyc--) {
1098 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1099 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1100 }
1101 } else {
1102 while (cyc--) {
1103 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1104 off += _emit_RMB(dry_run, &buf[off]);
1105 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1106 off += _emit_WMB(dry_run, &buf[off]);
1107 }
1108 }
1109
1110 return off;
1111}
1112
1113static u32 _emit_load(unsigned int dry_run, u8 buf[],
1114 enum pl330_cond cond, enum dma_transfer_direction direction,
1115 u8 peri)
1116{
1117 int off = 0;
1118
1119 switch (direction) {
1120 case DMA_MEM_TO_MEM:
1121 case DMA_MEM_TO_DEV:
1122 off += _emit_LD(dry_run, &buf[off], cond);
1123 break;
1124
1125 case DMA_DEV_TO_MEM:
1126 if (cond == ALWAYS) {
1127 off += _emit_LDP(dry_run, &buf[off], SINGLE,
1128 peri);
1129 off += _emit_LDP(dry_run, &buf[off], BURST,
1130 peri);
1131 } else {
1132 off += _emit_LDP(dry_run, &buf[off], cond,
1133 peri);
1134 }
1135 break;
1136
1137 default:
1138 /* this code should be unreachable */
1139 WARN_ON(1);
1140 break;
1141 }
1142
1143 return off;
1144}
1145
1146static inline u32 _emit_store(unsigned int dry_run, u8 buf[],
1147 enum pl330_cond cond, enum dma_transfer_direction direction,
1148 u8 peri)
1149{
1150 int off = 0;
1151
1152 switch (direction) {
1153 case DMA_MEM_TO_MEM:
1154 case DMA_DEV_TO_MEM:
1155 off += _emit_ST(dry_run, &buf[off], cond);
1156 break;
1157
1158 case DMA_MEM_TO_DEV:
1159 if (cond == ALWAYS) {
1160 off += _emit_STP(dry_run, &buf[off], SINGLE,
1161 peri);
1162 off += _emit_STP(dry_run, &buf[off], BURST,
1163 peri);
1164 } else {
1165 off += _emit_STP(dry_run, &buf[off], cond,
1166 peri);
1167 }
1168 break;
1169
1170 default:
1171 /* this code should be unreachable */
1172 WARN_ON(1);
1173 break;
1174 }
1175
1176 return off;
1177}
1178
1179static inline int _ldst_peripheral(struct pl330_dmac *pl330,
1180 unsigned dry_run, u8 buf[],
1181 const struct _xfer_spec *pxs, int cyc,
1182 enum pl330_cond cond)
1183{
1184 int off = 0;
1185
1186 /*
1187 * do FLUSHP at beginning to clear any stale dma requests before the
1188 * first WFP.
1189 */
1190 if (!(pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP))
1191 off += _emit_FLUSHP(dry_run, &buf[off], pxs->desc->peri);
1192 while (cyc--) {
1193 off += _emit_WFP(dry_run, &buf[off], cond, pxs->desc->peri);
1194 off += _emit_load(dry_run, &buf[off], cond, pxs->desc->rqtype,
1195 pxs->desc->peri);
1196 off += _emit_store(dry_run, &buf[off], cond, pxs->desc->rqtype,
1197 pxs->desc->peri);
1198 }
1199
1200 return off;
1201}
1202
1203static int _bursts(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[],
1204 const struct _xfer_spec *pxs, int cyc)
1205{
1206 int off = 0;
1207 enum pl330_cond cond = BRST_LEN(pxs->ccr) > 1 ? BURST : SINGLE;
1208
1209 if (pl330->quirks & PL330_QUIRK_PERIPH_BURST)
1210 cond = BURST;
1211
1212 switch (pxs->desc->rqtype) {
1213 case DMA_MEM_TO_DEV:
1214 case DMA_DEV_TO_MEM:
1215 off += _ldst_peripheral(pl330, dry_run, &buf[off], pxs, cyc,
1216 cond);
1217 break;
1218
1219 case DMA_MEM_TO_MEM:
1220 off += _ldst_memtomem(dry_run, &buf[off], pxs, cyc);
1221 break;
1222
1223 default:
1224 /* this code should be unreachable */
1225 WARN_ON(1);
1226 break;
1227 }
1228
1229 return off;
1230}
1231
1232/*
1233 * only the unaligned burst transfers have the dregs.
1234 * so, still transfer dregs with a reduced size burst
1235 * for mem-to-mem, mem-to-dev or dev-to-mem.
1236 */
1237static int _dregs(struct pl330_dmac *pl330, unsigned int dry_run, u8 buf[],
1238 const struct _xfer_spec *pxs, int transfer_length)
1239{
1240 int off = 0;
1241 int dregs_ccr;
1242
1243 if (transfer_length == 0)
1244 return off;
1245
1246 /*
1247 * dregs_len = (total bytes - BURST_TO_BYTE(bursts, ccr)) /
1248 * BRST_SIZE(ccr)
1249 * the dregs len must be smaller than burst len,
1250 * so, for higher efficiency, we can modify CCR
1251 * to use a reduced size burst len for the dregs.
1252 */
1253 dregs_ccr = pxs->ccr;
1254 dregs_ccr &= ~((0xf << CC_SRCBRSTLEN_SHFT) |
1255 (0xf << CC_DSTBRSTLEN_SHFT));
1256 dregs_ccr |= (((transfer_length - 1) & 0xf) <<
1257 CC_SRCBRSTLEN_SHFT);
1258 dregs_ccr |= (((transfer_length - 1) & 0xf) <<
1259 CC_DSTBRSTLEN_SHFT);
1260
1261 switch (pxs->desc->rqtype) {
1262 case DMA_MEM_TO_DEV:
1263 case DMA_DEV_TO_MEM:
1264 off += _emit_MOV(dry_run, &buf[off], CCR, dregs_ccr);
1265 off += _ldst_peripheral(pl330, dry_run, &buf[off], pxs, 1,
1266 BURST);
1267 break;
1268
1269 case DMA_MEM_TO_MEM:
1270 off += _emit_MOV(dry_run, &buf[off], CCR, dregs_ccr);
1271 off += _ldst_memtomem(dry_run, &buf[off], pxs, 1);
1272 break;
1273
1274 default:
1275 /* this code should be unreachable */
1276 WARN_ON(1);
1277 break;
1278 }
1279
1280 return off;
1281}
1282
1283/* Returns bytes consumed and updates bursts */
1284static inline int _loop(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[],
1285 unsigned long *bursts, const struct _xfer_spec *pxs)
1286{
1287 int cyc, cycmax, szlp, szlpend, szbrst, off;
1288 unsigned lcnt0, lcnt1, ljmp0, ljmp1;
1289 struct _arg_LPEND lpend;
1290
1291 if (*bursts == 1)
1292 return _bursts(pl330, dry_run, buf, pxs, 1);
1293
1294 /* Max iterations possible in DMALP is 256 */
1295 if (*bursts >= 256*256) {
1296 lcnt1 = 256;
1297 lcnt0 = 256;
1298 cyc = *bursts / lcnt1 / lcnt0;
1299 } else if (*bursts > 256) {
1300 lcnt1 = 256;
1301 lcnt0 = *bursts / lcnt1;
1302 cyc = 1;
1303 } else {
1304 lcnt1 = *bursts;
1305 lcnt0 = 0;
1306 cyc = 1;
1307 }
1308
1309 szlp = _emit_LP(1, buf, 0, 0);
1310 szbrst = _bursts(pl330, 1, buf, pxs, 1);
1311
1312 lpend.cond = ALWAYS;
1313 lpend.forever = false;
1314 lpend.loop = 0;
1315 lpend.bjump = 0;
1316 szlpend = _emit_LPEND(1, buf, &lpend);
1317
1318 if (lcnt0) {
1319 szlp *= 2;
1320 szlpend *= 2;
1321 }
1322
1323 /*
1324 * Max bursts that we can unroll due to limit on the
1325 * size of backward jump that can be encoded in DMALPEND
1326 * which is 8-bits and hence 255
1327 */
1328 cycmax = (255 - (szlp + szlpend)) / szbrst;
1329
1330 cyc = (cycmax < cyc) ? cycmax : cyc;
1331
1332 off = 0;
1333
1334 if (lcnt0) {
1335 off += _emit_LP(dry_run, &buf[off], 0, lcnt0);
1336 ljmp0 = off;
1337 }
1338
1339 off += _emit_LP(dry_run, &buf[off], 1, lcnt1);
1340 ljmp1 = off;
1341
1342 off += _bursts(pl330, dry_run, &buf[off], pxs, cyc);
1343
1344 lpend.cond = ALWAYS;
1345 lpend.forever = false;
1346 lpend.loop = 1;
1347 lpend.bjump = off - ljmp1;
1348 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1349
1350 if (lcnt0) {
1351 lpend.cond = ALWAYS;
1352 lpend.forever = false;
1353 lpend.loop = 0;
1354 lpend.bjump = off - ljmp0;
1355 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1356 }
1357
1358 *bursts = lcnt1 * cyc;
1359 if (lcnt0)
1360 *bursts *= lcnt0;
1361
1362 return off;
1363}
1364
1365static inline int _setup_loops(struct pl330_dmac *pl330,
1366 unsigned dry_run, u8 buf[],
1367 const struct _xfer_spec *pxs)
1368{
1369 struct pl330_xfer *x = &pxs->desc->px;
1370 u32 ccr = pxs->ccr;
1371 unsigned long c, bursts = BYTE_TO_BURST(x->bytes, ccr);
1372 int num_dregs = (x->bytes - BURST_TO_BYTE(bursts, ccr)) /
1373 BRST_SIZE(ccr);
1374 int off = 0;
1375
1376 while (bursts) {
1377 c = bursts;
1378 off += _loop(pl330, dry_run, &buf[off], &c, pxs);
1379 bursts -= c;
1380 }
1381 off += _dregs(pl330, dry_run, &buf[off], pxs, num_dregs);
1382
1383 return off;
1384}
1385
1386static inline int _setup_xfer(struct pl330_dmac *pl330,
1387 unsigned dry_run, u8 buf[],
1388 const struct _xfer_spec *pxs)
1389{
1390 struct pl330_xfer *x = &pxs->desc->px;
1391 int off = 0;
1392
1393 /* DMAMOV SAR, x->src_addr */
1394 off += _emit_MOV(dry_run, &buf[off], SAR, x->src_addr);
1395 /* DMAMOV DAR, x->dst_addr */
1396 off += _emit_MOV(dry_run, &buf[off], DAR, x->dst_addr);
1397
1398 /* Setup Loop(s) */
1399 off += _setup_loops(pl330, dry_run, &buf[off], pxs);
1400
1401 return off;
1402}
1403
1404/*
1405 * A req is a sequence of one or more xfer units.
1406 * Returns the number of bytes taken to setup the MC for the req.
1407 */
1408static int _setup_req(struct pl330_dmac *pl330, unsigned dry_run,
1409 struct pl330_thread *thrd, unsigned index,
1410 struct _xfer_spec *pxs)
1411{
1412 struct _pl330_req *req = &thrd->req[index];
1413 u8 *buf = req->mc_cpu;
1414 int off = 0;
1415
1416 PL330_DBGMC_START(req->mc_bus);
1417
1418 /* DMAMOV CCR, ccr */
1419 off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr);
1420
1421 off += _setup_xfer(pl330, dry_run, &buf[off], pxs);
1422
1423 /* DMASEV peripheral/event */
1424 off += _emit_SEV(dry_run, &buf[off], thrd->ev);
1425 /* DMAEND */
1426 off += _emit_END(dry_run, &buf[off]);
1427
1428 return off;
1429}
1430
1431static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc)
1432{
1433 u32 ccr = 0;
1434
1435 if (rqc->src_inc)
1436 ccr |= CC_SRCINC;
1437
1438 if (rqc->dst_inc)
1439 ccr |= CC_DSTINC;
1440
1441 /* We set same protection levels for Src and DST for now */
1442 if (rqc->privileged)
1443 ccr |= CC_SRCPRI | CC_DSTPRI;
1444 if (rqc->nonsecure)
1445 ccr |= CC_SRCNS | CC_DSTNS;
1446 if (rqc->insnaccess)
1447 ccr |= CC_SRCIA | CC_DSTIA;
1448
1449 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_SRCBRSTLEN_SHFT);
1450 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_DSTBRSTLEN_SHFT);
1451
1452 ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT);
1453 ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT);
1454
1455 ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT);
1456 ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT);
1457
1458 ccr |= (rqc->swap << CC_SWAP_SHFT);
1459
1460 return ccr;
1461}
1462
1463/*
1464 * Submit a list of xfers after which the client wants notification.
1465 * Client is not notified after each xfer unit, just once after all
1466 * xfer units are done or some error occurs.
1467 */
1468static int pl330_submit_req(struct pl330_thread *thrd,
1469 struct dma_pl330_desc *desc)
1470{
1471 struct pl330_dmac *pl330 = thrd->dmac;
1472 struct _xfer_spec xs;
1473 unsigned long flags;
1474 unsigned idx;
1475 u32 ccr;
1476 int ret = 0;
1477
1478 switch (desc->rqtype) {
1479 case DMA_MEM_TO_DEV:
1480 break;
1481
1482 case DMA_DEV_TO_MEM:
1483 break;
1484
1485 case DMA_MEM_TO_MEM:
1486 break;
1487
1488 default:
1489 return -ENOTSUPP;
1490 }
1491
1492 if (pl330->state == DYING
1493 || pl330->dmac_tbd.reset_chan & (1 << thrd->id)) {
1494 dev_info(thrd->dmac->ddma.dev, "%s:%d\n",
1495 __func__, __LINE__);
1496 return -EAGAIN;
1497 }
1498
1499 /* If request for non-existing peripheral */
1500 if (desc->rqtype != DMA_MEM_TO_MEM &&
1501 desc->peri >= pl330->pcfg.num_peri) {
1502 dev_info(thrd->dmac->ddma.dev,
1503 "%s:%d Invalid peripheral(%u)!\n",
1504 __func__, __LINE__, desc->peri);
1505 return -EINVAL;
1506 }
1507
1508 spin_lock_irqsave(&pl330->lock, flags);
1509
1510 if (_queue_full(thrd)) {
1511 ret = -EAGAIN;
1512 goto xfer_exit;
1513 }
1514
1515 /* Prefer Secure Channel */
1516 if (!_manager_ns(thrd))
1517 desc->rqcfg.nonsecure = 0;
1518 else
1519 desc->rqcfg.nonsecure = 1;
1520
1521 ccr = _prepare_ccr(&desc->rqcfg);
1522
1523 idx = thrd->req[0].desc == NULL ? 0 : 1;
1524
1525 xs.ccr = ccr;
1526 xs.desc = desc;
1527
1528 /* First dry run to check if req is acceptable */
1529 ret = _setup_req(pl330, 1, thrd, idx, &xs);
1530
1531 if (ret > pl330->mcbufsz / 2) {
1532 dev_info(pl330->ddma.dev, "%s:%d Try increasing mcbufsz (%i/%i)\n",
1533 __func__, __LINE__, ret, pl330->mcbufsz / 2);
1534 ret = -ENOMEM;
1535 goto xfer_exit;
1536 }
1537
1538 /* Hook the request */
1539 thrd->lstenq = idx;
1540 thrd->req[idx].desc = desc;
1541 _setup_req(pl330, 0, thrd, idx, &xs);
1542
1543 ret = 0;
1544
1545xfer_exit:
1546 spin_unlock_irqrestore(&pl330->lock, flags);
1547
1548 return ret;
1549}
1550
1551static void dma_pl330_rqcb(struct dma_pl330_desc *desc, enum pl330_op_err err)
1552{
1553 struct dma_pl330_chan *pch;
1554 unsigned long flags;
1555
1556 if (!desc)
1557 return;
1558
1559 pch = desc->pchan;
1560
1561 /* If desc aborted */
1562 if (!pch)
1563 return;
1564
1565 spin_lock_irqsave(&pch->lock, flags);
1566
1567 desc->status = DONE;
1568
1569 spin_unlock_irqrestore(&pch->lock, flags);
1570
1571 tasklet_schedule(&pch->task);
1572}
1573
1574static void pl330_dotask(struct tasklet_struct *t)
1575{
1576 struct pl330_dmac *pl330 = from_tasklet(pl330, t, tasks);
1577 unsigned long flags;
1578 int i;
1579
1580 spin_lock_irqsave(&pl330->lock, flags);
1581
1582 /* The DMAC itself gone nuts */
1583 if (pl330->dmac_tbd.reset_dmac) {
1584 pl330->state = DYING;
1585 /* Reset the manager too */
1586 pl330->dmac_tbd.reset_mngr = true;
1587 /* Clear the reset flag */
1588 pl330->dmac_tbd.reset_dmac = false;
1589 }
1590
1591 if (pl330->dmac_tbd.reset_mngr) {
1592 _stop(pl330->manager);
1593 /* Reset all channels */
1594 pl330->dmac_tbd.reset_chan = (1 << pl330->pcfg.num_chan) - 1;
1595 /* Clear the reset flag */
1596 pl330->dmac_tbd.reset_mngr = false;
1597 }
1598
1599 for (i = 0; i < pl330->pcfg.num_chan; i++) {
1600
1601 if (pl330->dmac_tbd.reset_chan & (1 << i)) {
1602 struct pl330_thread *thrd = &pl330->channels[i];
1603 void __iomem *regs = pl330->base;
1604 enum pl330_op_err err;
1605
1606 _stop(thrd);
1607
1608 if (readl(regs + FSC) & (1 << thrd->id))
1609 err = PL330_ERR_FAIL;
1610 else
1611 err = PL330_ERR_ABORT;
1612
1613 spin_unlock_irqrestore(&pl330->lock, flags);
1614 dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, err);
1615 dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, err);
1616 spin_lock_irqsave(&pl330->lock, flags);
1617
1618 thrd->req[0].desc = NULL;
1619 thrd->req[1].desc = NULL;
1620 thrd->req_running = -1;
1621
1622 /* Clear the reset flag */
1623 pl330->dmac_tbd.reset_chan &= ~(1 << i);
1624 }
1625 }
1626
1627 spin_unlock_irqrestore(&pl330->lock, flags);
1628
1629 return;
1630}
1631
1632/* Returns 1 if state was updated, 0 otherwise */
1633static int pl330_update(struct pl330_dmac *pl330)
1634{
1635 struct dma_pl330_desc *descdone;
1636 unsigned long flags;
1637 void __iomem *regs;
1638 u32 val;
1639 int id, ev, ret = 0;
1640
1641 regs = pl330->base;
1642
1643 spin_lock_irqsave(&pl330->lock, flags);
1644
1645 val = readl(regs + FSM) & 0x1;
1646 if (val)
1647 pl330->dmac_tbd.reset_mngr = true;
1648 else
1649 pl330->dmac_tbd.reset_mngr = false;
1650
1651 val = readl(regs + FSC) & ((1 << pl330->pcfg.num_chan) - 1);
1652 pl330->dmac_tbd.reset_chan |= val;
1653 if (val) {
1654 int i = 0;
1655 while (i < pl330->pcfg.num_chan) {
1656 if (val & (1 << i)) {
1657 dev_info(pl330->ddma.dev,
1658 "Reset Channel-%d\t CS-%x FTC-%x\n",
1659 i, readl(regs + CS(i)),
1660 readl(regs + FTC(i)));
1661 _stop(&pl330->channels[i]);
1662 }
1663 i++;
1664 }
1665 }
1666
1667 /* Check which event happened i.e, thread notified */
1668 val = readl(regs + ES);
1669 if (pl330->pcfg.num_events < 32
1670 && val & ~((1 << pl330->pcfg.num_events) - 1)) {
1671 pl330->dmac_tbd.reset_dmac = true;
1672 dev_err(pl330->ddma.dev, "%s:%d Unexpected!\n", __func__,
1673 __LINE__);
1674 ret = 1;
1675 goto updt_exit;
1676 }
1677
1678 for (ev = 0; ev < pl330->pcfg.num_events; ev++) {
1679 if (val & (1 << ev)) { /* Event occurred */
1680 struct pl330_thread *thrd;
1681 u32 inten = readl(regs + INTEN);
1682 int active;
1683
1684 /* Clear the event */
1685 if (inten & (1 << ev))
1686 writel(1 << ev, regs + INTCLR);
1687
1688 ret = 1;
1689
1690 id = pl330->events[ev];
1691
1692 thrd = &pl330->channels[id];
1693
1694 active = thrd->req_running;
1695 if (active == -1) /* Aborted */
1696 continue;
1697
1698 /* Detach the req */
1699 descdone = thrd->req[active].desc;
1700 thrd->req[active].desc = NULL;
1701
1702 thrd->req_running = -1;
1703
1704 /* Get going again ASAP */
1705 _start(thrd);
1706
1707 /* For now, just make a list of callbacks to be done */
1708 list_add_tail(&descdone->rqd, &pl330->req_done);
1709 }
1710 }
1711
1712 /* Now that we are in no hurry, do the callbacks */
1713 while (!list_empty(&pl330->req_done)) {
1714 descdone = list_first_entry(&pl330->req_done,
1715 struct dma_pl330_desc, rqd);
1716 list_del(&descdone->rqd);
1717 spin_unlock_irqrestore(&pl330->lock, flags);
1718 dma_pl330_rqcb(descdone, PL330_ERR_NONE);
1719 spin_lock_irqsave(&pl330->lock, flags);
1720 }
1721
1722updt_exit:
1723 spin_unlock_irqrestore(&pl330->lock, flags);
1724
1725 if (pl330->dmac_tbd.reset_dmac
1726 || pl330->dmac_tbd.reset_mngr
1727 || pl330->dmac_tbd.reset_chan) {
1728 ret = 1;
1729 tasklet_schedule(&pl330->tasks);
1730 }
1731
1732 return ret;
1733}
1734
1735/* Reserve an event */
1736static inline int _alloc_event(struct pl330_thread *thrd)
1737{
1738 struct pl330_dmac *pl330 = thrd->dmac;
1739 int ev;
1740
1741 for (ev = 0; ev < pl330->pcfg.num_events; ev++)
1742 if (pl330->events[ev] == -1) {
1743 pl330->events[ev] = thrd->id;
1744 return ev;
1745 }
1746
1747 return -1;
1748}
1749
1750static bool _chan_ns(const struct pl330_dmac *pl330, int i)
1751{
1752 return pl330->pcfg.irq_ns & (1 << i);
1753}
1754
1755/* Upon success, returns IdentityToken for the
1756 * allocated channel, NULL otherwise.
1757 */
1758static struct pl330_thread *pl330_request_channel(struct pl330_dmac *pl330)
1759{
1760 struct pl330_thread *thrd = NULL;
1761 int chans, i;
1762
1763 if (pl330->state == DYING)
1764 return NULL;
1765
1766 chans = pl330->pcfg.num_chan;
1767
1768 for (i = 0; i < chans; i++) {
1769 thrd = &pl330->channels[i];
1770 if ((thrd->free) && (!_manager_ns(thrd) ||
1771 _chan_ns(pl330, i))) {
1772 thrd->ev = _alloc_event(thrd);
1773 if (thrd->ev >= 0) {
1774 thrd->free = false;
1775 thrd->lstenq = 1;
1776 thrd->req[0].desc = NULL;
1777 thrd->req[1].desc = NULL;
1778 thrd->req_running = -1;
1779 break;
1780 }
1781 }
1782 thrd = NULL;
1783 }
1784
1785 return thrd;
1786}
1787
1788/* Release an event */
1789static inline void _free_event(struct pl330_thread *thrd, int ev)
1790{
1791 struct pl330_dmac *pl330 = thrd->dmac;
1792
1793 /* If the event is valid and was held by the thread */
1794 if (ev >= 0 && ev < pl330->pcfg.num_events
1795 && pl330->events[ev] == thrd->id)
1796 pl330->events[ev] = -1;
1797}
1798
1799static void pl330_release_channel(struct pl330_thread *thrd)
1800{
1801 if (!thrd || thrd->free)
1802 return;
1803
1804 _stop(thrd);
1805
1806 dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, PL330_ERR_ABORT);
1807 dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, PL330_ERR_ABORT);
1808
1809 _free_event(thrd, thrd->ev);
1810 thrd->free = true;
1811}
1812
1813/* Initialize the structure for PL330 configuration, that can be used
1814 * by the client driver the make best use of the DMAC
1815 */
1816static void read_dmac_config(struct pl330_dmac *pl330)
1817{
1818 void __iomem *regs = pl330->base;
1819 u32 val;
1820
1821 val = readl(regs + CRD) >> CRD_DATA_WIDTH_SHIFT;
1822 val &= CRD_DATA_WIDTH_MASK;
1823 pl330->pcfg.data_bus_width = 8 * (1 << val);
1824
1825 val = readl(regs + CRD) >> CRD_DATA_BUFF_SHIFT;
1826 val &= CRD_DATA_BUFF_MASK;
1827 pl330->pcfg.data_buf_dep = val + 1;
1828
1829 val = readl(regs + CR0) >> CR0_NUM_CHANS_SHIFT;
1830 val &= CR0_NUM_CHANS_MASK;
1831 val += 1;
1832 pl330->pcfg.num_chan = val;
1833
1834 val = readl(regs + CR0);
1835 if (val & CR0_PERIPH_REQ_SET) {
1836 val = (val >> CR0_NUM_PERIPH_SHIFT) & CR0_NUM_PERIPH_MASK;
1837 val += 1;
1838 pl330->pcfg.num_peri = val;
1839 pl330->pcfg.peri_ns = readl(regs + CR4);
1840 } else {
1841 pl330->pcfg.num_peri = 0;
1842 }
1843
1844 val = readl(regs + CR0);
1845 if (val & CR0_BOOT_MAN_NS)
1846 pl330->pcfg.mode |= DMAC_MODE_NS;
1847 else
1848 pl330->pcfg.mode &= ~DMAC_MODE_NS;
1849
1850 val = readl(regs + CR0) >> CR0_NUM_EVENTS_SHIFT;
1851 val &= CR0_NUM_EVENTS_MASK;
1852 val += 1;
1853 pl330->pcfg.num_events = val;
1854
1855 pl330->pcfg.irq_ns = readl(regs + CR3);
1856}
1857
1858static inline void _reset_thread(struct pl330_thread *thrd)
1859{
1860 struct pl330_dmac *pl330 = thrd->dmac;
1861
1862 thrd->req[0].mc_cpu = pl330->mcode_cpu
1863 + (thrd->id * pl330->mcbufsz);
1864 thrd->req[0].mc_bus = pl330->mcode_bus
1865 + (thrd->id * pl330->mcbufsz);
1866 thrd->req[0].desc = NULL;
1867
1868 thrd->req[1].mc_cpu = thrd->req[0].mc_cpu
1869 + pl330->mcbufsz / 2;
1870 thrd->req[1].mc_bus = thrd->req[0].mc_bus
1871 + pl330->mcbufsz / 2;
1872 thrd->req[1].desc = NULL;
1873
1874 thrd->req_running = -1;
1875}
1876
1877static int dmac_alloc_threads(struct pl330_dmac *pl330)
1878{
1879 int chans = pl330->pcfg.num_chan;
1880 struct pl330_thread *thrd;
1881 int i;
1882
1883 /* Allocate 1 Manager and 'chans' Channel threads */
1884 pl330->channels = kcalloc(1 + chans, sizeof(*thrd),
1885 GFP_KERNEL);
1886 if (!pl330->channels)
1887 return -ENOMEM;
1888
1889 /* Init Channel threads */
1890 for (i = 0; i < chans; i++) {
1891 thrd = &pl330->channels[i];
1892 thrd->id = i;
1893 thrd->dmac = pl330;
1894 _reset_thread(thrd);
1895 thrd->free = true;
1896 }
1897
1898 /* MANAGER is indexed at the end */
1899 thrd = &pl330->channels[chans];
1900 thrd->id = chans;
1901 thrd->dmac = pl330;
1902 thrd->free = false;
1903 pl330->manager = thrd;
1904
1905 return 0;
1906}
1907
1908static int dmac_alloc_resources(struct pl330_dmac *pl330)
1909{
1910 int chans = pl330->pcfg.num_chan;
1911 int ret;
1912
1913 /*
1914 * Alloc MicroCode buffer for 'chans' Channel threads.
1915 * A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN)
1916 */
1917 pl330->mcode_cpu = dma_alloc_attrs(pl330->ddma.dev,
1918 chans * pl330->mcbufsz,
1919 &pl330->mcode_bus, GFP_KERNEL,
1920 DMA_ATTR_PRIVILEGED);
1921 if (!pl330->mcode_cpu) {
1922 dev_err(pl330->ddma.dev, "%s:%d Can't allocate memory!\n",
1923 __func__, __LINE__);
1924 return -ENOMEM;
1925 }
1926
1927 ret = dmac_alloc_threads(pl330);
1928 if (ret) {
1929 dev_err(pl330->ddma.dev, "%s:%d Can't to create channels for DMAC!\n",
1930 __func__, __LINE__);
1931 dma_free_attrs(pl330->ddma.dev,
1932 chans * pl330->mcbufsz,
1933 pl330->mcode_cpu, pl330->mcode_bus,
1934 DMA_ATTR_PRIVILEGED);
1935 return ret;
1936 }
1937
1938 return 0;
1939}
1940
1941static int pl330_add(struct pl330_dmac *pl330)
1942{
1943 int i, ret;
1944
1945 /* Check if we can handle this DMAC */
1946 if ((pl330->pcfg.periph_id & 0xfffff) != PERIPH_ID_VAL) {
1947 dev_err(pl330->ddma.dev, "PERIPH_ID 0x%x !\n",
1948 pl330->pcfg.periph_id);
1949 return -EINVAL;
1950 }
1951
1952 /* Read the configuration of the DMAC */
1953 read_dmac_config(pl330);
1954
1955 if (pl330->pcfg.num_events == 0) {
1956 dev_err(pl330->ddma.dev, "%s:%d Can't work without events!\n",
1957 __func__, __LINE__);
1958 return -EINVAL;
1959 }
1960
1961 spin_lock_init(&pl330->lock);
1962
1963 INIT_LIST_HEAD(&pl330->req_done);
1964
1965 /* Use default MC buffer size if not provided */
1966 if (!pl330->mcbufsz)
1967 pl330->mcbufsz = MCODE_BUFF_PER_REQ * 2;
1968
1969 /* Mark all events as free */
1970 for (i = 0; i < pl330->pcfg.num_events; i++)
1971 pl330->events[i] = -1;
1972
1973 /* Allocate resources needed by the DMAC */
1974 ret = dmac_alloc_resources(pl330);
1975 if (ret) {
1976 dev_err(pl330->ddma.dev, "Unable to create channels for DMAC\n");
1977 return ret;
1978 }
1979
1980 tasklet_setup(&pl330->tasks, pl330_dotask);
1981
1982 pl330->state = INIT;
1983
1984 return 0;
1985}
1986
1987static int dmac_free_threads(struct pl330_dmac *pl330)
1988{
1989 struct pl330_thread *thrd;
1990 int i;
1991
1992 /* Release Channel threads */
1993 for (i = 0; i < pl330->pcfg.num_chan; i++) {
1994 thrd = &pl330->channels[i];
1995 pl330_release_channel(thrd);
1996 }
1997
1998 /* Free memory */
1999 kfree(pl330->channels);
2000
2001 return 0;
2002}
2003
2004static void pl330_del(struct pl330_dmac *pl330)
2005{
2006 pl330->state = UNINIT;
2007
2008 tasklet_kill(&pl330->tasks);
2009
2010 /* Free DMAC resources */
2011 dmac_free_threads(pl330);
2012
2013 dma_free_attrs(pl330->ddma.dev,
2014 pl330->pcfg.num_chan * pl330->mcbufsz, pl330->mcode_cpu,
2015 pl330->mcode_bus, DMA_ATTR_PRIVILEGED);
2016}
2017
2018/* forward declaration */
2019static struct amba_driver pl330_driver;
2020
2021static inline struct dma_pl330_chan *
2022to_pchan(struct dma_chan *ch)
2023{
2024 if (!ch)
2025 return NULL;
2026
2027 return container_of(ch, struct dma_pl330_chan, chan);
2028}
2029
2030static inline struct dma_pl330_desc *
2031to_desc(struct dma_async_tx_descriptor *tx)
2032{
2033 return container_of(tx, struct dma_pl330_desc, txd);
2034}
2035
2036static inline void fill_queue(struct dma_pl330_chan *pch)
2037{
2038 struct dma_pl330_desc *desc;
2039 int ret;
2040
2041 list_for_each_entry(desc, &pch->work_list, node) {
2042
2043 /* If already submitted */
2044 if (desc->status == BUSY)
2045 continue;
2046
2047 ret = pl330_submit_req(pch->thread, desc);
2048 if (!ret) {
2049 desc->status = BUSY;
2050 } else if (ret == -EAGAIN) {
2051 /* QFull or DMAC Dying */
2052 break;
2053 } else {
2054 /* Unacceptable request */
2055 desc->status = DONE;
2056 dev_err(pch->dmac->ddma.dev, "%s:%d Bad Desc(%d)\n",
2057 __func__, __LINE__, desc->txd.cookie);
2058 tasklet_schedule(&pch->task);
2059 }
2060 }
2061}
2062
2063static void pl330_tasklet(struct tasklet_struct *t)
2064{
2065 struct dma_pl330_chan *pch = from_tasklet(pch, t, task);
2066 struct dma_pl330_desc *desc, *_dt;
2067 unsigned long flags;
2068 bool power_down = false;
2069
2070 spin_lock_irqsave(&pch->lock, flags);
2071
2072 /* Pick up ripe tomatoes */
2073 list_for_each_entry_safe(desc, _dt, &pch->work_list, node)
2074 if (desc->status == DONE) {
2075 if (!pch->cyclic)
2076 dma_cookie_complete(&desc->txd);
2077 list_move_tail(&desc->node, &pch->completed_list);
2078 }
2079
2080 /* Try to submit a req imm. next to the last completed cookie */
2081 fill_queue(pch);
2082
2083 if (list_empty(&pch->work_list)) {
2084 spin_lock(&pch->thread->dmac->lock);
2085 _stop(pch->thread);
2086 spin_unlock(&pch->thread->dmac->lock);
2087 power_down = true;
2088 pch->active = false;
2089 } else {
2090 /* Make sure the PL330 Channel thread is active */
2091 spin_lock(&pch->thread->dmac->lock);
2092 _start(pch->thread);
2093 spin_unlock(&pch->thread->dmac->lock);
2094 }
2095
2096 while (!list_empty(&pch->completed_list)) {
2097 struct dmaengine_desc_callback cb;
2098
2099 desc = list_first_entry(&pch->completed_list,
2100 struct dma_pl330_desc, node);
2101
2102 dmaengine_desc_get_callback(&desc->txd, &cb);
2103
2104 if (pch->cyclic) {
2105 desc->status = PREP;
2106 list_move_tail(&desc->node, &pch->work_list);
2107 if (power_down) {
2108 pch->active = true;
2109 spin_lock(&pch->thread->dmac->lock);
2110 _start(pch->thread);
2111 spin_unlock(&pch->thread->dmac->lock);
2112 power_down = false;
2113 }
2114 } else {
2115 desc->status = FREE;
2116 list_move_tail(&desc->node, &pch->dmac->desc_pool);
2117 }
2118
2119 dma_descriptor_unmap(&desc->txd);
2120
2121 if (dmaengine_desc_callback_valid(&cb)) {
2122 spin_unlock_irqrestore(&pch->lock, flags);
2123 dmaengine_desc_callback_invoke(&cb, NULL);
2124 spin_lock_irqsave(&pch->lock, flags);
2125 }
2126 }
2127 spin_unlock_irqrestore(&pch->lock, flags);
2128
2129 /* If work list empty, power down */
2130 if (power_down) {
2131 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2132 pm_runtime_put_autosuspend(pch->dmac->ddma.dev);
2133 }
2134}
2135
2136static struct dma_chan *of_dma_pl330_xlate(struct of_phandle_args *dma_spec,
2137 struct of_dma *ofdma)
2138{
2139 int count = dma_spec->args_count;
2140 struct pl330_dmac *pl330 = ofdma->of_dma_data;
2141 unsigned int chan_id;
2142
2143 if (!pl330)
2144 return NULL;
2145
2146 if (count != 1)
2147 return NULL;
2148
2149 chan_id = dma_spec->args[0];
2150 if (chan_id >= pl330->num_peripherals)
2151 return NULL;
2152
2153 return dma_get_slave_channel(&pl330->peripherals[chan_id].chan);
2154}
2155
2156static int pl330_alloc_chan_resources(struct dma_chan *chan)
2157{
2158 struct dma_pl330_chan *pch = to_pchan(chan);
2159 struct pl330_dmac *pl330 = pch->dmac;
2160 unsigned long flags;
2161
2162 spin_lock_irqsave(&pl330->lock, flags);
2163
2164 dma_cookie_init(chan);
2165 pch->cyclic = false;
2166
2167 pch->thread = pl330_request_channel(pl330);
2168 if (!pch->thread) {
2169 spin_unlock_irqrestore(&pl330->lock, flags);
2170 return -ENOMEM;
2171 }
2172
2173 tasklet_setup(&pch->task, pl330_tasklet);
2174
2175 spin_unlock_irqrestore(&pl330->lock, flags);
2176
2177 return 1;
2178}
2179
2180/*
2181 * We need the data direction between the DMAC (the dma-mapping "device") and
2182 * the FIFO (the dmaengine "dev"), from the FIFO's point of view. Confusing!
2183 */
2184static enum dma_data_direction
2185pl330_dma_slave_map_dir(enum dma_transfer_direction dir)
2186{
2187 switch (dir) {
2188 case DMA_MEM_TO_DEV:
2189 return DMA_FROM_DEVICE;
2190 case DMA_DEV_TO_MEM:
2191 return DMA_TO_DEVICE;
2192 case DMA_DEV_TO_DEV:
2193 return DMA_BIDIRECTIONAL;
2194 default:
2195 return DMA_NONE;
2196 }
2197}
2198
2199static void pl330_unprep_slave_fifo(struct dma_pl330_chan *pch)
2200{
2201 if (pch->dir != DMA_NONE)
2202 dma_unmap_resource(pch->chan.device->dev, pch->fifo_dma,
2203 1 << pch->burst_sz, pch->dir, 0);
2204 pch->dir = DMA_NONE;
2205}
2206
2207
2208static bool pl330_prep_slave_fifo(struct dma_pl330_chan *pch,
2209 enum dma_transfer_direction dir)
2210{
2211 struct device *dev = pch->chan.device->dev;
2212 enum dma_data_direction dma_dir = pl330_dma_slave_map_dir(dir);
2213
2214 /* Already mapped for this config? */
2215 if (pch->dir == dma_dir)
2216 return true;
2217
2218 pl330_unprep_slave_fifo(pch);
2219 pch->fifo_dma = dma_map_resource(dev, pch->fifo_addr,
2220 1 << pch->burst_sz, dma_dir, 0);
2221 if (dma_mapping_error(dev, pch->fifo_dma))
2222 return false;
2223
2224 pch->dir = dma_dir;
2225 return true;
2226}
2227
2228static int fixup_burst_len(int max_burst_len, int quirks)
2229{
2230 if (max_burst_len > PL330_MAX_BURST)
2231 return PL330_MAX_BURST;
2232 else if (max_burst_len < 1)
2233 return 1;
2234 else
2235 return max_burst_len;
2236}
2237
2238static int pl330_config_write(struct dma_chan *chan,
2239 struct dma_slave_config *slave_config,
2240 enum dma_transfer_direction direction)
2241{
2242 struct dma_pl330_chan *pch = to_pchan(chan);
2243
2244 pl330_unprep_slave_fifo(pch);
2245 if (direction == DMA_MEM_TO_DEV) {
2246 if (slave_config->dst_addr)
2247 pch->fifo_addr = slave_config->dst_addr;
2248 if (slave_config->dst_addr_width)
2249 pch->burst_sz = __ffs(slave_config->dst_addr_width);
2250 pch->burst_len = fixup_burst_len(slave_config->dst_maxburst,
2251 pch->dmac->quirks);
2252 } else if (direction == DMA_DEV_TO_MEM) {
2253 if (slave_config->src_addr)
2254 pch->fifo_addr = slave_config->src_addr;
2255 if (slave_config->src_addr_width)
2256 pch->burst_sz = __ffs(slave_config->src_addr_width);
2257 pch->burst_len = fixup_burst_len(slave_config->src_maxburst,
2258 pch->dmac->quirks);
2259 }
2260
2261 return 0;
2262}
2263
2264static int pl330_config(struct dma_chan *chan,
2265 struct dma_slave_config *slave_config)
2266{
2267 struct dma_pl330_chan *pch = to_pchan(chan);
2268
2269 memcpy(&pch->slave_config, slave_config, sizeof(*slave_config));
2270
2271 return 0;
2272}
2273
2274static int pl330_terminate_all(struct dma_chan *chan)
2275{
2276 struct dma_pl330_chan *pch = to_pchan(chan);
2277 struct dma_pl330_desc *desc;
2278 unsigned long flags;
2279 struct pl330_dmac *pl330 = pch->dmac;
2280 bool power_down = false;
2281
2282 pm_runtime_get_sync(pl330->ddma.dev);
2283 spin_lock_irqsave(&pch->lock, flags);
2284
2285 spin_lock(&pl330->lock);
2286 _stop(pch->thread);
2287 pch->thread->req[0].desc = NULL;
2288 pch->thread->req[1].desc = NULL;
2289 pch->thread->req_running = -1;
2290 spin_unlock(&pl330->lock);
2291
2292 power_down = pch->active;
2293 pch->active = false;
2294
2295 /* Mark all desc done */
2296 list_for_each_entry(desc, &pch->submitted_list, node) {
2297 desc->status = FREE;
2298 dma_cookie_complete(&desc->txd);
2299 }
2300
2301 list_for_each_entry(desc, &pch->work_list , node) {
2302 desc->status = FREE;
2303 dma_cookie_complete(&desc->txd);
2304 }
2305
2306 list_splice_tail_init(&pch->submitted_list, &pl330->desc_pool);
2307 list_splice_tail_init(&pch->work_list, &pl330->desc_pool);
2308 list_splice_tail_init(&pch->completed_list, &pl330->desc_pool);
2309 spin_unlock_irqrestore(&pch->lock, flags);
2310 pm_runtime_mark_last_busy(pl330->ddma.dev);
2311 if (power_down)
2312 pm_runtime_put_autosuspend(pl330->ddma.dev);
2313 pm_runtime_put_autosuspend(pl330->ddma.dev);
2314
2315 return 0;
2316}
2317
2318/*
2319 * We don't support DMA_RESUME command because of hardware
2320 * limitations, so after pausing the channel we cannot restore
2321 * it to active state. We have to terminate channel and setup
2322 * DMA transfer again. This pause feature was implemented to
2323 * allow safely read residue before channel termination.
2324 */
2325static int pl330_pause(struct dma_chan *chan)
2326{
2327 struct dma_pl330_chan *pch = to_pchan(chan);
2328 struct pl330_dmac *pl330 = pch->dmac;
2329 unsigned long flags;
2330
2331 pm_runtime_get_sync(pl330->ddma.dev);
2332 spin_lock_irqsave(&pch->lock, flags);
2333
2334 spin_lock(&pl330->lock);
2335 _stop(pch->thread);
2336 spin_unlock(&pl330->lock);
2337
2338 spin_unlock_irqrestore(&pch->lock, flags);
2339 pm_runtime_mark_last_busy(pl330->ddma.dev);
2340 pm_runtime_put_autosuspend(pl330->ddma.dev);
2341
2342 return 0;
2343}
2344
2345static void pl330_free_chan_resources(struct dma_chan *chan)
2346{
2347 struct dma_pl330_chan *pch = to_pchan(chan);
2348 struct pl330_dmac *pl330 = pch->dmac;
2349 unsigned long flags;
2350
2351 tasklet_kill(&pch->task);
2352
2353 pm_runtime_get_sync(pch->dmac->ddma.dev);
2354 spin_lock_irqsave(&pl330->lock, flags);
2355
2356 pl330_release_channel(pch->thread);
2357 pch->thread = NULL;
2358
2359 if (pch->cyclic)
2360 list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool);
2361
2362 spin_unlock_irqrestore(&pl330->lock, flags);
2363 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2364 pm_runtime_put_autosuspend(pch->dmac->ddma.dev);
2365 pl330_unprep_slave_fifo(pch);
2366}
2367
2368static int pl330_get_current_xferred_count(struct dma_pl330_chan *pch,
2369 struct dma_pl330_desc *desc)
2370{
2371 struct pl330_thread *thrd = pch->thread;
2372 struct pl330_dmac *pl330 = pch->dmac;
2373 void __iomem *regs = thrd->dmac->base;
2374 u32 val, addr;
2375
2376 pm_runtime_get_sync(pl330->ddma.dev);
2377 val = addr = 0;
2378 if (desc->rqcfg.src_inc) {
2379 val = readl(regs + SA(thrd->id));
2380 addr = desc->px.src_addr;
2381 } else {
2382 val = readl(regs + DA(thrd->id));
2383 addr = desc->px.dst_addr;
2384 }
2385 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2386 pm_runtime_put_autosuspend(pl330->ddma.dev);
2387
2388 /* If DMAMOV hasn't finished yet, SAR/DAR can be zero */
2389 if (!val)
2390 return 0;
2391
2392 return val - addr;
2393}
2394
2395static enum dma_status
2396pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
2397 struct dma_tx_state *txstate)
2398{
2399 enum dma_status ret;
2400 unsigned long flags;
2401 struct dma_pl330_desc *desc, *running = NULL, *last_enq = NULL;
2402 struct dma_pl330_chan *pch = to_pchan(chan);
2403 unsigned int transferred, residual = 0;
2404
2405 ret = dma_cookie_status(chan, cookie, txstate);
2406
2407 if (!txstate)
2408 return ret;
2409
2410 if (ret == DMA_COMPLETE)
2411 goto out;
2412
2413 spin_lock_irqsave(&pch->lock, flags);
2414 spin_lock(&pch->thread->dmac->lock);
2415
2416 if (pch->thread->req_running != -1)
2417 running = pch->thread->req[pch->thread->req_running].desc;
2418
2419 last_enq = pch->thread->req[pch->thread->lstenq].desc;
2420
2421 /* Check in pending list */
2422 list_for_each_entry(desc, &pch->work_list, node) {
2423 if (desc->status == DONE)
2424 transferred = desc->bytes_requested;
2425 else if (running && desc == running)
2426 transferred =
2427 pl330_get_current_xferred_count(pch, desc);
2428 else if (desc->status == BUSY)
2429 /*
2430 * Busy but not running means either just enqueued,
2431 * or finished and not yet marked done
2432 */
2433 if (desc == last_enq)
2434 transferred = 0;
2435 else
2436 transferred = desc->bytes_requested;
2437 else
2438 transferred = 0;
2439 residual += desc->bytes_requested - transferred;
2440 if (desc->txd.cookie == cookie) {
2441 switch (desc->status) {
2442 case DONE:
2443 ret = DMA_COMPLETE;
2444 break;
2445 case PREP:
2446 case BUSY:
2447 ret = DMA_IN_PROGRESS;
2448 break;
2449 default:
2450 WARN_ON(1);
2451 }
2452 break;
2453 }
2454 if (desc->last)
2455 residual = 0;
2456 }
2457 spin_unlock(&pch->thread->dmac->lock);
2458 spin_unlock_irqrestore(&pch->lock, flags);
2459
2460out:
2461 dma_set_residue(txstate, residual);
2462
2463 return ret;
2464}
2465
2466static void pl330_issue_pending(struct dma_chan *chan)
2467{
2468 struct dma_pl330_chan *pch = to_pchan(chan);
2469 unsigned long flags;
2470
2471 spin_lock_irqsave(&pch->lock, flags);
2472 if (list_empty(&pch->work_list)) {
2473 /*
2474 * Warn on nothing pending. Empty submitted_list may
2475 * break our pm_runtime usage counter as it is
2476 * updated on work_list emptiness status.
2477 */
2478 WARN_ON(list_empty(&pch->submitted_list));
2479 pch->active = true;
2480 pm_runtime_get_sync(pch->dmac->ddma.dev);
2481 }
2482 list_splice_tail_init(&pch->submitted_list, &pch->work_list);
2483 spin_unlock_irqrestore(&pch->lock, flags);
2484
2485 pl330_tasklet(&pch->task);
2486}
2487
2488/*
2489 * We returned the last one of the circular list of descriptor(s)
2490 * from prep_xxx, so the argument to submit corresponds to the last
2491 * descriptor of the list.
2492 */
2493static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx)
2494{
2495 struct dma_pl330_desc *desc, *last = to_desc(tx);
2496 struct dma_pl330_chan *pch = to_pchan(tx->chan);
2497 dma_cookie_t cookie;
2498 unsigned long flags;
2499
2500 spin_lock_irqsave(&pch->lock, flags);
2501
2502 /* Assign cookies to all nodes */
2503 while (!list_empty(&last->node)) {
2504 desc = list_entry(last->node.next, struct dma_pl330_desc, node);
2505 if (pch->cyclic) {
2506 desc->txd.callback = last->txd.callback;
2507 desc->txd.callback_param = last->txd.callback_param;
2508 }
2509 desc->last = false;
2510
2511 dma_cookie_assign(&desc->txd);
2512
2513 list_move_tail(&desc->node, &pch->submitted_list);
2514 }
2515
2516 last->last = true;
2517 cookie = dma_cookie_assign(&last->txd);
2518 list_add_tail(&last->node, &pch->submitted_list);
2519 spin_unlock_irqrestore(&pch->lock, flags);
2520
2521 return cookie;
2522}
2523
2524static inline void _init_desc(struct dma_pl330_desc *desc)
2525{
2526 desc->rqcfg.swap = SWAP_NO;
2527 desc->rqcfg.scctl = CCTRL0;
2528 desc->rqcfg.dcctl = CCTRL0;
2529 desc->txd.tx_submit = pl330_tx_submit;
2530
2531 INIT_LIST_HEAD(&desc->node);
2532}
2533
2534/* Returns the number of descriptors added to the DMAC pool */
2535static int add_desc(struct list_head *pool, spinlock_t *lock,
2536 gfp_t flg, int count)
2537{
2538 struct dma_pl330_desc *desc;
2539 unsigned long flags;
2540 int i;
2541
2542 desc = kcalloc(count, sizeof(*desc), flg);
2543 if (!desc)
2544 return 0;
2545
2546 spin_lock_irqsave(lock, flags);
2547
2548 for (i = 0; i < count; i++) {
2549 _init_desc(&desc[i]);
2550 list_add_tail(&desc[i].node, pool);
2551 }
2552
2553 spin_unlock_irqrestore(lock, flags);
2554
2555 return count;
2556}
2557
2558static struct dma_pl330_desc *pluck_desc(struct list_head *pool,
2559 spinlock_t *lock)
2560{
2561 struct dma_pl330_desc *desc = NULL;
2562 unsigned long flags;
2563
2564 spin_lock_irqsave(lock, flags);
2565
2566 if (!list_empty(pool)) {
2567 desc = list_entry(pool->next,
2568 struct dma_pl330_desc, node);
2569
2570 list_del_init(&desc->node);
2571
2572 desc->status = PREP;
2573 desc->txd.callback = NULL;
2574 }
2575
2576 spin_unlock_irqrestore(lock, flags);
2577
2578 return desc;
2579}
2580
2581static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch)
2582{
2583 struct pl330_dmac *pl330 = pch->dmac;
2584 u8 *peri_id = pch->chan.private;
2585 struct dma_pl330_desc *desc;
2586
2587 /* Pluck one desc from the pool of DMAC */
2588 desc = pluck_desc(&pl330->desc_pool, &pl330->pool_lock);
2589
2590 /* If the DMAC pool is empty, alloc new */
2591 if (!desc) {
2592 static DEFINE_SPINLOCK(lock);
2593 LIST_HEAD(pool);
2594
2595 if (!add_desc(&pool, &lock, GFP_ATOMIC, 1))
2596 return NULL;
2597
2598 desc = pluck_desc(&pool, &lock);
2599 WARN_ON(!desc || !list_empty(&pool));
2600 }
2601
2602 /* Initialize the descriptor */
2603 desc->pchan = pch;
2604 desc->txd.cookie = 0;
2605 async_tx_ack(&desc->txd);
2606
2607 desc->peri = peri_id ? pch->chan.chan_id : 0;
2608 desc->rqcfg.pcfg = &pch->dmac->pcfg;
2609
2610 dma_async_tx_descriptor_init(&desc->txd, &pch->chan);
2611
2612 return desc;
2613}
2614
2615static inline void fill_px(struct pl330_xfer *px,
2616 dma_addr_t dst, dma_addr_t src, size_t len)
2617{
2618 px->bytes = len;
2619 px->dst_addr = dst;
2620 px->src_addr = src;
2621}
2622
2623static struct dma_pl330_desc *
2624__pl330_prep_dma_memcpy(struct dma_pl330_chan *pch, dma_addr_t dst,
2625 dma_addr_t src, size_t len)
2626{
2627 struct dma_pl330_desc *desc = pl330_get_desc(pch);
2628
2629 if (!desc) {
2630 dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
2631 __func__, __LINE__);
2632 return NULL;
2633 }
2634
2635 /*
2636 * Ideally we should lookout for reqs bigger than
2637 * those that can be programmed with 256 bytes of
2638 * MC buffer, but considering a req size is seldom
2639 * going to be word-unaligned and more than 200MB,
2640 * we take it easy.
2641 * Also, should the limit is reached we'd rather
2642 * have the platform increase MC buffer size than
2643 * complicating this API driver.
2644 */
2645 fill_px(&desc->px, dst, src, len);
2646
2647 return desc;
2648}
2649
2650/* Call after fixing burst size */
2651static inline int get_burst_len(struct dma_pl330_desc *desc, size_t len)
2652{
2653 struct dma_pl330_chan *pch = desc->pchan;
2654 struct pl330_dmac *pl330 = pch->dmac;
2655 int burst_len;
2656
2657 burst_len = pl330->pcfg.data_bus_width / 8;
2658 burst_len *= pl330->pcfg.data_buf_dep / pl330->pcfg.num_chan;
2659 burst_len >>= desc->rqcfg.brst_size;
2660
2661 /* src/dst_burst_len can't be more than 16 */
2662 if (burst_len > PL330_MAX_BURST)
2663 burst_len = PL330_MAX_BURST;
2664
2665 return burst_len;
2666}
2667
2668static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic(
2669 struct dma_chan *chan, dma_addr_t dma_addr, size_t len,
2670 size_t period_len, enum dma_transfer_direction direction,
2671 unsigned long flags)
2672{
2673 struct dma_pl330_desc *desc = NULL, *first = NULL;
2674 struct dma_pl330_chan *pch = to_pchan(chan);
2675 struct pl330_dmac *pl330 = pch->dmac;
2676 unsigned int i;
2677 dma_addr_t dst;
2678 dma_addr_t src;
2679
2680 if (len % period_len != 0)
2681 return NULL;
2682
2683 if (!is_slave_direction(direction)) {
2684 dev_err(pch->dmac->ddma.dev, "%s:%d Invalid dma direction\n",
2685 __func__, __LINE__);
2686 return NULL;
2687 }
2688
2689 pl330_config_write(chan, &pch->slave_config, direction);
2690
2691 if (!pl330_prep_slave_fifo(pch, direction))
2692 return NULL;
2693
2694 for (i = 0; i < len / period_len; i++) {
2695 desc = pl330_get_desc(pch);
2696 if (!desc) {
2697 unsigned long iflags;
2698
2699 dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
2700 __func__, __LINE__);
2701
2702 if (!first)
2703 return NULL;
2704
2705 spin_lock_irqsave(&pl330->pool_lock, iflags);
2706
2707 while (!list_empty(&first->node)) {
2708 desc = list_entry(first->node.next,
2709 struct dma_pl330_desc, node);
2710 list_move_tail(&desc->node, &pl330->desc_pool);
2711 }
2712
2713 list_move_tail(&first->node, &pl330->desc_pool);
2714
2715 spin_unlock_irqrestore(&pl330->pool_lock, iflags);
2716
2717 return NULL;
2718 }
2719
2720 switch (direction) {
2721 case DMA_MEM_TO_DEV:
2722 desc->rqcfg.src_inc = 1;
2723 desc->rqcfg.dst_inc = 0;
2724 src = dma_addr;
2725 dst = pch->fifo_dma;
2726 break;
2727 case DMA_DEV_TO_MEM:
2728 desc->rqcfg.src_inc = 0;
2729 desc->rqcfg.dst_inc = 1;
2730 src = pch->fifo_dma;
2731 dst = dma_addr;
2732 break;
2733 default:
2734 break;
2735 }
2736
2737 desc->rqtype = direction;
2738 desc->rqcfg.brst_size = pch->burst_sz;
2739 desc->rqcfg.brst_len = pch->burst_len;
2740 desc->bytes_requested = period_len;
2741 fill_px(&desc->px, dst, src, period_len);
2742
2743 if (!first)
2744 first = desc;
2745 else
2746 list_add_tail(&desc->node, &first->node);
2747
2748 dma_addr += period_len;
2749 }
2750
2751 if (!desc)
2752 return NULL;
2753
2754 pch->cyclic = true;
2755
2756 return &desc->txd;
2757}
2758
2759static struct dma_async_tx_descriptor *
2760pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst,
2761 dma_addr_t src, size_t len, unsigned long flags)
2762{
2763 struct dma_pl330_desc *desc;
2764 struct dma_pl330_chan *pch = to_pchan(chan);
2765 struct pl330_dmac *pl330;
2766 int burst;
2767
2768 if (unlikely(!pch || !len))
2769 return NULL;
2770
2771 pl330 = pch->dmac;
2772
2773 desc = __pl330_prep_dma_memcpy(pch, dst, src, len);
2774 if (!desc)
2775 return NULL;
2776
2777 desc->rqcfg.src_inc = 1;
2778 desc->rqcfg.dst_inc = 1;
2779 desc->rqtype = DMA_MEM_TO_MEM;
2780
2781 /* Select max possible burst size */
2782 burst = pl330->pcfg.data_bus_width / 8;
2783
2784 /*
2785 * Make sure we use a burst size that aligns with all the memcpy
2786 * parameters because our DMA programming algorithm doesn't cope with
2787 * transfers which straddle an entry in the DMA device's MFIFO.
2788 */
2789 while ((src | dst | len) & (burst - 1))
2790 burst /= 2;
2791
2792 desc->rqcfg.brst_size = 0;
2793 while (burst != (1 << desc->rqcfg.brst_size))
2794 desc->rqcfg.brst_size++;
2795
2796 desc->rqcfg.brst_len = get_burst_len(desc, len);
2797 /*
2798 * If burst size is smaller than bus width then make sure we only
2799 * transfer one at a time to avoid a burst stradling an MFIFO entry.
2800 */
2801 if (burst * 8 < pl330->pcfg.data_bus_width)
2802 desc->rqcfg.brst_len = 1;
2803
2804 desc->bytes_requested = len;
2805
2806 return &desc->txd;
2807}
2808
2809static void __pl330_giveback_desc(struct pl330_dmac *pl330,
2810 struct dma_pl330_desc *first)
2811{
2812 unsigned long flags;
2813 struct dma_pl330_desc *desc;
2814
2815 if (!first)
2816 return;
2817
2818 spin_lock_irqsave(&pl330->pool_lock, flags);
2819
2820 while (!list_empty(&first->node)) {
2821 desc = list_entry(first->node.next,
2822 struct dma_pl330_desc, node);
2823 list_move_tail(&desc->node, &pl330->desc_pool);
2824 }
2825
2826 list_move_tail(&first->node, &pl330->desc_pool);
2827
2828 spin_unlock_irqrestore(&pl330->pool_lock, flags);
2829}
2830
2831static struct dma_async_tx_descriptor *
2832pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
2833 unsigned int sg_len, enum dma_transfer_direction direction,
2834 unsigned long flg, void *context)
2835{
2836 struct dma_pl330_desc *first, *desc = NULL;
2837 struct dma_pl330_chan *pch = to_pchan(chan);
2838 struct scatterlist *sg;
2839 int i;
2840
2841 if (unlikely(!pch || !sgl || !sg_len))
2842 return NULL;
2843
2844 pl330_config_write(chan, &pch->slave_config, direction);
2845
2846 if (!pl330_prep_slave_fifo(pch, direction))
2847 return NULL;
2848
2849 first = NULL;
2850
2851 for_each_sg(sgl, sg, sg_len, i) {
2852
2853 desc = pl330_get_desc(pch);
2854 if (!desc) {
2855 struct pl330_dmac *pl330 = pch->dmac;
2856
2857 dev_err(pch->dmac->ddma.dev,
2858 "%s:%d Unable to fetch desc\n",
2859 __func__, __LINE__);
2860 __pl330_giveback_desc(pl330, first);
2861
2862 return NULL;
2863 }
2864
2865 if (!first)
2866 first = desc;
2867 else
2868 list_add_tail(&desc->node, &first->node);
2869
2870 if (direction == DMA_MEM_TO_DEV) {
2871 desc->rqcfg.src_inc = 1;
2872 desc->rqcfg.dst_inc = 0;
2873 fill_px(&desc->px, pch->fifo_dma, sg_dma_address(sg),
2874 sg_dma_len(sg));
2875 } else {
2876 desc->rqcfg.src_inc = 0;
2877 desc->rqcfg.dst_inc = 1;
2878 fill_px(&desc->px, sg_dma_address(sg), pch->fifo_dma,
2879 sg_dma_len(sg));
2880 }
2881
2882 desc->rqcfg.brst_size = pch->burst_sz;
2883 desc->rqcfg.brst_len = pch->burst_len;
2884 desc->rqtype = direction;
2885 desc->bytes_requested = sg_dma_len(sg);
2886 }
2887
2888 /* Return the last desc in the chain */
2889 return &desc->txd;
2890}
2891
2892static irqreturn_t pl330_irq_handler(int irq, void *data)
2893{
2894 if (pl330_update(data))
2895 return IRQ_HANDLED;
2896 else
2897 return IRQ_NONE;
2898}
2899
2900#define PL330_DMA_BUSWIDTHS \
2901 BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
2902 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
2903 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
2904 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
2905 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)
2906
2907#ifdef CONFIG_DEBUG_FS
2908static int pl330_debugfs_show(struct seq_file *s, void *data)
2909{
2910 struct pl330_dmac *pl330 = s->private;
2911 int chans, pchs, ch, pr;
2912
2913 chans = pl330->pcfg.num_chan;
2914 pchs = pl330->num_peripherals;
2915
2916 seq_puts(s, "PL330 physical channels:\n");
2917 seq_puts(s, "THREAD:\t\tCHANNEL:\n");
2918 seq_puts(s, "--------\t-----\n");
2919 for (ch = 0; ch < chans; ch++) {
2920 struct pl330_thread *thrd = &pl330->channels[ch];
2921 int found = -1;
2922
2923 for (pr = 0; pr < pchs; pr++) {
2924 struct dma_pl330_chan *pch = &pl330->peripherals[pr];
2925
2926 if (!pch->thread || thrd->id != pch->thread->id)
2927 continue;
2928
2929 found = pr;
2930 }
2931
2932 seq_printf(s, "%d\t\t", thrd->id);
2933 if (found == -1)
2934 seq_puts(s, "--\n");
2935 else
2936 seq_printf(s, "%d\n", found);
2937 }
2938
2939 return 0;
2940}
2941
2942DEFINE_SHOW_ATTRIBUTE(pl330_debugfs);
2943
2944static inline void init_pl330_debugfs(struct pl330_dmac *pl330)
2945{
2946 debugfs_create_file(dev_name(pl330->ddma.dev),
2947 S_IFREG | 0444, NULL, pl330,
2948 &pl330_debugfs_fops);
2949}
2950#else
2951static inline void init_pl330_debugfs(struct pl330_dmac *pl330)
2952{
2953}
2954#endif
2955
2956/*
2957 * Runtime PM callbacks are provided by amba/bus.c driver.
2958 *
2959 * It is assumed here that IRQ safe runtime PM is chosen in probe and amba
2960 * bus driver will only disable/enable the clock in runtime PM callbacks.
2961 */
2962static int __maybe_unused pl330_suspend(struct device *dev)
2963{
2964 struct amba_device *pcdev = to_amba_device(dev);
2965
2966 pm_runtime_force_suspend(dev);
2967 clk_unprepare(pcdev->pclk);
2968
2969 return 0;
2970}
2971
2972static int __maybe_unused pl330_resume(struct device *dev)
2973{
2974 struct amba_device *pcdev = to_amba_device(dev);
2975 int ret;
2976
2977 ret = clk_prepare(pcdev->pclk);
2978 if (ret)
2979 return ret;
2980
2981 pm_runtime_force_resume(dev);
2982
2983 return ret;
2984}
2985
2986static const struct dev_pm_ops pl330_pm = {
2987 SET_LATE_SYSTEM_SLEEP_PM_OPS(pl330_suspend, pl330_resume)
2988};
2989
2990static int
2991pl330_probe(struct amba_device *adev, const struct amba_id *id)
2992{
2993 struct pl330_config *pcfg;
2994 struct pl330_dmac *pl330;
2995 struct dma_pl330_chan *pch, *_p;
2996 struct dma_device *pd;
2997 struct resource *res;
2998 int i, ret, irq;
2999 int num_chan;
3000 struct device_node *np = adev->dev.of_node;
3001
3002 ret = dma_set_mask_and_coherent(&adev->dev, DMA_BIT_MASK(32));
3003 if (ret)
3004 return ret;
3005
3006 /* Allocate a new DMAC and its Channels */
3007 pl330 = devm_kzalloc(&adev->dev, sizeof(*pl330), GFP_KERNEL);
3008 if (!pl330)
3009 return -ENOMEM;
3010
3011 pd = &pl330->ddma;
3012 pd->dev = &adev->dev;
3013
3014 pl330->mcbufsz = 0;
3015
3016 /* get quirk */
3017 for (i = 0; i < ARRAY_SIZE(of_quirks); i++)
3018 if (of_property_read_bool(np, of_quirks[i].quirk))
3019 pl330->quirks |= of_quirks[i].id;
3020
3021 res = &adev->res;
3022 pl330->base = devm_ioremap_resource(&adev->dev, res);
3023 if (IS_ERR(pl330->base))
3024 return PTR_ERR(pl330->base);
3025
3026 amba_set_drvdata(adev, pl330);
3027
3028 pl330->rstc = devm_reset_control_get_optional(&adev->dev, "dma");
3029 if (IS_ERR(pl330->rstc)) {
3030 return dev_err_probe(&adev->dev, PTR_ERR(pl330->rstc), "Failed to get reset!\n");
3031 } else {
3032 ret = reset_control_deassert(pl330->rstc);
3033 if (ret) {
3034 dev_err(&adev->dev, "Couldn't deassert the device from reset!\n");
3035 return ret;
3036 }
3037 }
3038
3039 pl330->rstc_ocp = devm_reset_control_get_optional(&adev->dev, "dma-ocp");
3040 if (IS_ERR(pl330->rstc_ocp)) {
3041 return dev_err_probe(&adev->dev, PTR_ERR(pl330->rstc_ocp),
3042 "Failed to get OCP reset!\n");
3043 } else {
3044 ret = reset_control_deassert(pl330->rstc_ocp);
3045 if (ret) {
3046 dev_err(&adev->dev, "Couldn't deassert the device from OCP reset!\n");
3047 return ret;
3048 }
3049 }
3050
3051 for (i = 0; i < AMBA_NR_IRQS; i++) {
3052 irq = adev->irq[i];
3053 if (irq) {
3054 ret = devm_request_irq(&adev->dev, irq,
3055 pl330_irq_handler, 0,
3056 dev_name(&adev->dev), pl330);
3057 if (ret)
3058 return ret;
3059 } else {
3060 break;
3061 }
3062 }
3063
3064 pcfg = &pl330->pcfg;
3065
3066 pcfg->periph_id = adev->periphid;
3067 ret = pl330_add(pl330);
3068 if (ret)
3069 return ret;
3070
3071 INIT_LIST_HEAD(&pl330->desc_pool);
3072 spin_lock_init(&pl330->pool_lock);
3073
3074 /* Create a descriptor pool of default size */
3075 if (!add_desc(&pl330->desc_pool, &pl330->pool_lock,
3076 GFP_KERNEL, NR_DEFAULT_DESC))
3077 dev_warn(&adev->dev, "unable to allocate desc\n");
3078
3079 INIT_LIST_HEAD(&pd->channels);
3080
3081 /* Initialize channel parameters */
3082 num_chan = max_t(int, pcfg->num_peri, pcfg->num_chan);
3083
3084 pl330->num_peripherals = num_chan;
3085
3086 pl330->peripherals = kcalloc(num_chan, sizeof(*pch), GFP_KERNEL);
3087 if (!pl330->peripherals) {
3088 ret = -ENOMEM;
3089 goto probe_err2;
3090 }
3091
3092 for (i = 0; i < num_chan; i++) {
3093 pch = &pl330->peripherals[i];
3094
3095 pch->chan.private = adev->dev.of_node;
3096 INIT_LIST_HEAD(&pch->submitted_list);
3097 INIT_LIST_HEAD(&pch->work_list);
3098 INIT_LIST_HEAD(&pch->completed_list);
3099 spin_lock_init(&pch->lock);
3100 pch->thread = NULL;
3101 pch->chan.device = pd;
3102 pch->dmac = pl330;
3103 pch->dir = DMA_NONE;
3104
3105 /* Add the channel to the DMAC list */
3106 list_add_tail(&pch->chan.device_node, &pd->channels);
3107 }
3108
3109 dma_cap_set(DMA_MEMCPY, pd->cap_mask);
3110 if (pcfg->num_peri) {
3111 dma_cap_set(DMA_SLAVE, pd->cap_mask);
3112 dma_cap_set(DMA_CYCLIC, pd->cap_mask);
3113 dma_cap_set(DMA_PRIVATE, pd->cap_mask);
3114 }
3115
3116 pd->device_alloc_chan_resources = pl330_alloc_chan_resources;
3117 pd->device_free_chan_resources = pl330_free_chan_resources;
3118 pd->device_prep_dma_memcpy = pl330_prep_dma_memcpy;
3119 pd->device_prep_dma_cyclic = pl330_prep_dma_cyclic;
3120 pd->device_tx_status = pl330_tx_status;
3121 pd->device_prep_slave_sg = pl330_prep_slave_sg;
3122 pd->device_config = pl330_config;
3123 pd->device_pause = pl330_pause;
3124 pd->device_terminate_all = pl330_terminate_all;
3125 pd->device_issue_pending = pl330_issue_pending;
3126 pd->src_addr_widths = PL330_DMA_BUSWIDTHS;
3127 pd->dst_addr_widths = PL330_DMA_BUSWIDTHS;
3128 pd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
3129 pd->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
3130 pd->max_burst = PL330_MAX_BURST;
3131
3132 ret = dma_async_device_register(pd);
3133 if (ret) {
3134 dev_err(&adev->dev, "unable to register DMAC\n");
3135 goto probe_err3;
3136 }
3137
3138 if (adev->dev.of_node) {
3139 ret = of_dma_controller_register(adev->dev.of_node,
3140 of_dma_pl330_xlate, pl330);
3141 if (ret) {
3142 dev_err(&adev->dev,
3143 "unable to register DMA to the generic DT DMA helpers\n");
3144 }
3145 }
3146
3147 /*
3148 * This is the limit for transfers with a buswidth of 1, larger
3149 * buswidths will have larger limits.
3150 */
3151 ret = dma_set_max_seg_size(&adev->dev, 1900800);
3152 if (ret)
3153 dev_err(&adev->dev, "unable to set the seg size\n");
3154
3155
3156 init_pl330_debugfs(pl330);
3157 dev_info(&adev->dev,
3158 "Loaded driver for PL330 DMAC-%x\n", adev->periphid);
3159 dev_info(&adev->dev,
3160 "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n",
3161 pcfg->data_buf_dep, pcfg->data_bus_width / 8, pcfg->num_chan,
3162 pcfg->num_peri, pcfg->num_events);
3163
3164 pm_runtime_irq_safe(&adev->dev);
3165 pm_runtime_use_autosuspend(&adev->dev);
3166 pm_runtime_set_autosuspend_delay(&adev->dev, PL330_AUTOSUSPEND_DELAY);
3167 pm_runtime_mark_last_busy(&adev->dev);
3168 pm_runtime_put_autosuspend(&adev->dev);
3169
3170 return 0;
3171probe_err3:
3172 /* Idle the DMAC */
3173 list_for_each_entry_safe(pch, _p, &pl330->ddma.channels,
3174 chan.device_node) {
3175
3176 /* Remove the channel */
3177 list_del(&pch->chan.device_node);
3178
3179 /* Flush the channel */
3180 if (pch->thread) {
3181 pl330_terminate_all(&pch->chan);
3182 pl330_free_chan_resources(&pch->chan);
3183 }
3184 }
3185probe_err2:
3186 pl330_del(pl330);
3187
3188 if (pl330->rstc_ocp)
3189 reset_control_assert(pl330->rstc_ocp);
3190
3191 if (pl330->rstc)
3192 reset_control_assert(pl330->rstc);
3193 return ret;
3194}
3195
3196static void pl330_remove(struct amba_device *adev)
3197{
3198 struct pl330_dmac *pl330 = amba_get_drvdata(adev);
3199 struct dma_pl330_chan *pch, *_p;
3200 int i, irq;
3201
3202 pm_runtime_get_noresume(pl330->ddma.dev);
3203
3204 if (adev->dev.of_node)
3205 of_dma_controller_free(adev->dev.of_node);
3206
3207 for (i = 0; i < AMBA_NR_IRQS; i++) {
3208 irq = adev->irq[i];
3209 if (irq)
3210 devm_free_irq(&adev->dev, irq, pl330);
3211 }
3212
3213 dma_async_device_unregister(&pl330->ddma);
3214
3215 /* Idle the DMAC */
3216 list_for_each_entry_safe(pch, _p, &pl330->ddma.channels,
3217 chan.device_node) {
3218
3219 /* Remove the channel */
3220 list_del(&pch->chan.device_node);
3221
3222 /* Flush the channel */
3223 if (pch->thread) {
3224 pl330_terminate_all(&pch->chan);
3225 pl330_free_chan_resources(&pch->chan);
3226 }
3227 }
3228
3229 pl330_del(pl330);
3230
3231 if (pl330->rstc_ocp)
3232 reset_control_assert(pl330->rstc_ocp);
3233
3234 if (pl330->rstc)
3235 reset_control_assert(pl330->rstc);
3236}
3237
3238static const struct amba_id pl330_ids[] = {
3239 {
3240 .id = 0x00041330,
3241 .mask = 0x000fffff,
3242 },
3243 { 0, 0 },
3244};
3245
3246MODULE_DEVICE_TABLE(amba, pl330_ids);
3247
3248static struct amba_driver pl330_driver = {
3249 .drv = {
3250 .owner = THIS_MODULE,
3251 .name = "dma-pl330",
3252 .pm = &pl330_pm,
3253 },
3254 .id_table = pl330_ids,
3255 .probe = pl330_probe,
3256 .remove = pl330_remove,
3257};
3258
3259module_amba_driver(pl330_driver);
3260
3261MODULE_AUTHOR("Jaswinder Singh <jassisinghbrar@gmail.com>");
3262MODULE_DESCRIPTION("API Driver for PL330 DMAC");
3263MODULE_LICENSE("GPL");