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1#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
2
3#include <linux/errno.h>
4#include <linux/kernel.h>
5#include <linux/mm.h>
6#include <linux/smp.h>
7#include <linux/prctl.h>
8#include <linux/slab.h>
9#include <linux/sched.h>
10#include <linux/module.h>
11#include <linux/pm.h>
12#include <linux/tick.h>
13#include <linux/random.h>
14#include <linux/user-return-notifier.h>
15#include <linux/dmi.h>
16#include <linux/utsname.h>
17#include <linux/stackprotector.h>
18#include <linux/tick.h>
19#include <linux/cpuidle.h>
20#include <trace/events/power.h>
21#include <linux/hw_breakpoint.h>
22#include <asm/cpu.h>
23#include <asm/apic.h>
24#include <asm/syscalls.h>
25#include <asm/idle.h>
26#include <asm/uaccess.h>
27#include <asm/mwait.h>
28#include <asm/fpu/internal.h>
29#include <asm/debugreg.h>
30#include <asm/nmi.h>
31#include <asm/tlbflush.h>
32#include <asm/mce.h>
33#include <asm/vm86.h>
34
35/*
36 * per-CPU TSS segments. Threads are completely 'soft' on Linux,
37 * no more per-task TSS's. The TSS size is kept cacheline-aligned
38 * so they are allowed to end up in the .data..cacheline_aligned
39 * section. Since TSS's are completely CPU-local, we want them
40 * on exact cacheline boundaries, to eliminate cacheline ping-pong.
41 */
42__visible DEFINE_PER_CPU_SHARED_ALIGNED(struct tss_struct, cpu_tss) = {
43 .x86_tss = {
44 .sp0 = TOP_OF_INIT_STACK,
45#ifdef CONFIG_X86_32
46 .ss0 = __KERNEL_DS,
47 .ss1 = __KERNEL_CS,
48 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET,
49#endif
50 },
51#ifdef CONFIG_X86_32
52 /*
53 * Note that the .io_bitmap member must be extra-big. This is because
54 * the CPU will access an additional byte beyond the end of the IO
55 * permission bitmap. The extra byte must be all 1 bits, and must
56 * be within the limit.
57 */
58 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 },
59#endif
60#ifdef CONFIG_X86_32
61 .SYSENTER_stack_canary = STACK_END_MAGIC,
62#endif
63};
64EXPORT_PER_CPU_SYMBOL(cpu_tss);
65
66#ifdef CONFIG_X86_64
67static DEFINE_PER_CPU(unsigned char, is_idle);
68static ATOMIC_NOTIFIER_HEAD(idle_notifier);
69
70void idle_notifier_register(struct notifier_block *n)
71{
72 atomic_notifier_chain_register(&idle_notifier, n);
73}
74EXPORT_SYMBOL_GPL(idle_notifier_register);
75
76void idle_notifier_unregister(struct notifier_block *n)
77{
78 atomic_notifier_chain_unregister(&idle_notifier, n);
79}
80EXPORT_SYMBOL_GPL(idle_notifier_unregister);
81#endif
82
83/*
84 * this gets called so that we can store lazy state into memory and copy the
85 * current task into the new thread.
86 */
87int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
88{
89 memcpy(dst, src, arch_task_struct_size);
90#ifdef CONFIG_VM86
91 dst->thread.vm86 = NULL;
92#endif
93
94 return fpu__copy(&dst->thread.fpu, &src->thread.fpu);
95}
96
97/*
98 * Free current thread data structures etc..
99 */
100void exit_thread(void)
101{
102 struct task_struct *me = current;
103 struct thread_struct *t = &me->thread;
104 unsigned long *bp = t->io_bitmap_ptr;
105 struct fpu *fpu = &t->fpu;
106
107 if (bp) {
108 struct tss_struct *tss = &per_cpu(cpu_tss, get_cpu());
109
110 t->io_bitmap_ptr = NULL;
111 clear_thread_flag(TIF_IO_BITMAP);
112 /*
113 * Careful, clear this in the TSS too:
114 */
115 memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
116 t->io_bitmap_max = 0;
117 put_cpu();
118 kfree(bp);
119 }
120
121 free_vm86(t);
122
123 fpu__drop(fpu);
124}
125
126void flush_thread(void)
127{
128 struct task_struct *tsk = current;
129
130 flush_ptrace_hw_breakpoint(tsk);
131 memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
132
133 fpu__clear(&tsk->thread.fpu);
134}
135
136static void hard_disable_TSC(void)
137{
138 cr4_set_bits(X86_CR4_TSD);
139}
140
141void disable_TSC(void)
142{
143 preempt_disable();
144 if (!test_and_set_thread_flag(TIF_NOTSC))
145 /*
146 * Must flip the CPU state synchronously with
147 * TIF_NOTSC in the current running context.
148 */
149 hard_disable_TSC();
150 preempt_enable();
151}
152
153static void hard_enable_TSC(void)
154{
155 cr4_clear_bits(X86_CR4_TSD);
156}
157
158static void enable_TSC(void)
159{
160 preempt_disable();
161 if (test_and_clear_thread_flag(TIF_NOTSC))
162 /*
163 * Must flip the CPU state synchronously with
164 * TIF_NOTSC in the current running context.
165 */
166 hard_enable_TSC();
167 preempt_enable();
168}
169
170int get_tsc_mode(unsigned long adr)
171{
172 unsigned int val;
173
174 if (test_thread_flag(TIF_NOTSC))
175 val = PR_TSC_SIGSEGV;
176 else
177 val = PR_TSC_ENABLE;
178
179 return put_user(val, (unsigned int __user *)adr);
180}
181
182int set_tsc_mode(unsigned int val)
183{
184 if (val == PR_TSC_SIGSEGV)
185 disable_TSC();
186 else if (val == PR_TSC_ENABLE)
187 enable_TSC();
188 else
189 return -EINVAL;
190
191 return 0;
192}
193
194void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
195 struct tss_struct *tss)
196{
197 struct thread_struct *prev, *next;
198
199 prev = &prev_p->thread;
200 next = &next_p->thread;
201
202 if (test_tsk_thread_flag(prev_p, TIF_BLOCKSTEP) ^
203 test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) {
204 unsigned long debugctl = get_debugctlmsr();
205
206 debugctl &= ~DEBUGCTLMSR_BTF;
207 if (test_tsk_thread_flag(next_p, TIF_BLOCKSTEP))
208 debugctl |= DEBUGCTLMSR_BTF;
209
210 update_debugctlmsr(debugctl);
211 }
212
213 if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
214 test_tsk_thread_flag(next_p, TIF_NOTSC)) {
215 /* prev and next are different */
216 if (test_tsk_thread_flag(next_p, TIF_NOTSC))
217 hard_disable_TSC();
218 else
219 hard_enable_TSC();
220 }
221
222 if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
223 /*
224 * Copy the relevant range of the IO bitmap.
225 * Normally this is 128 bytes or less:
226 */
227 memcpy(tss->io_bitmap, next->io_bitmap_ptr,
228 max(prev->io_bitmap_max, next->io_bitmap_max));
229 } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) {
230 /*
231 * Clear any possible leftover bits:
232 */
233 memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
234 }
235 propagate_user_return_notify(prev_p, next_p);
236}
237
238/*
239 * Idle related variables and functions
240 */
241unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
242EXPORT_SYMBOL(boot_option_idle_override);
243
244static void (*x86_idle)(void);
245
246#ifndef CONFIG_SMP
247static inline void play_dead(void)
248{
249 BUG();
250}
251#endif
252
253#ifdef CONFIG_X86_64
254void enter_idle(void)
255{
256 this_cpu_write(is_idle, 1);
257 atomic_notifier_call_chain(&idle_notifier, IDLE_START, NULL);
258}
259
260static void __exit_idle(void)
261{
262 if (x86_test_and_clear_bit_percpu(0, is_idle) == 0)
263 return;
264 atomic_notifier_call_chain(&idle_notifier, IDLE_END, NULL);
265}
266
267/* Called from interrupts to signify idle end */
268void exit_idle(void)
269{
270 /* idle loop has pid 0 */
271 if (current->pid)
272 return;
273 __exit_idle();
274}
275#endif
276
277void arch_cpu_idle_enter(void)
278{
279 local_touch_nmi();
280 enter_idle();
281}
282
283void arch_cpu_idle_exit(void)
284{
285 __exit_idle();
286}
287
288void arch_cpu_idle_dead(void)
289{
290 play_dead();
291}
292
293/*
294 * Called from the generic idle code.
295 */
296void arch_cpu_idle(void)
297{
298 x86_idle();
299}
300
301/*
302 * We use this if we don't have any better idle routine..
303 */
304void default_idle(void)
305{
306 trace_cpu_idle_rcuidle(1, smp_processor_id());
307 safe_halt();
308 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
309}
310#ifdef CONFIG_APM_MODULE
311EXPORT_SYMBOL(default_idle);
312#endif
313
314#ifdef CONFIG_XEN
315bool xen_set_default_idle(void)
316{
317 bool ret = !!x86_idle;
318
319 x86_idle = default_idle;
320
321 return ret;
322}
323#endif
324void stop_this_cpu(void *dummy)
325{
326 local_irq_disable();
327 /*
328 * Remove this CPU:
329 */
330 set_cpu_online(smp_processor_id(), false);
331 disable_local_APIC();
332 mcheck_cpu_clear(this_cpu_ptr(&cpu_info));
333
334 for (;;)
335 halt();
336}
337
338bool amd_e400_c1e_detected;
339EXPORT_SYMBOL(amd_e400_c1e_detected);
340
341static cpumask_var_t amd_e400_c1e_mask;
342
343void amd_e400_remove_cpu(int cpu)
344{
345 if (amd_e400_c1e_mask != NULL)
346 cpumask_clear_cpu(cpu, amd_e400_c1e_mask);
347}
348
349/*
350 * AMD Erratum 400 aware idle routine. We check for C1E active in the interrupt
351 * pending message MSR. If we detect C1E, then we handle it the same
352 * way as C3 power states (local apic timer and TSC stop)
353 */
354static void amd_e400_idle(void)
355{
356 if (!amd_e400_c1e_detected) {
357 u32 lo, hi;
358
359 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
360
361 if (lo & K8_INTP_C1E_ACTIVE_MASK) {
362 amd_e400_c1e_detected = true;
363 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
364 mark_tsc_unstable("TSC halt in AMD C1E");
365 pr_info("System has AMD C1E enabled\n");
366 }
367 }
368
369 if (amd_e400_c1e_detected) {
370 int cpu = smp_processor_id();
371
372 if (!cpumask_test_cpu(cpu, amd_e400_c1e_mask)) {
373 cpumask_set_cpu(cpu, amd_e400_c1e_mask);
374 /* Force broadcast so ACPI can not interfere. */
375 tick_broadcast_force();
376 pr_info("Switch to broadcast mode on CPU%d\n", cpu);
377 }
378 tick_broadcast_enter();
379
380 default_idle();
381
382 /*
383 * The switch back from broadcast mode needs to be
384 * called with interrupts disabled.
385 */
386 local_irq_disable();
387 tick_broadcast_exit();
388 local_irq_enable();
389 } else
390 default_idle();
391}
392
393/*
394 * Intel Core2 and older machines prefer MWAIT over HALT for C1.
395 * We can't rely on cpuidle installing MWAIT, because it will not load
396 * on systems that support only C1 -- so the boot default must be MWAIT.
397 *
398 * Some AMD machines are the opposite, they depend on using HALT.
399 *
400 * So for default C1, which is used during boot until cpuidle loads,
401 * use MWAIT-C1 on Intel HW that has it, else use HALT.
402 */
403static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c)
404{
405 if (c->x86_vendor != X86_VENDOR_INTEL)
406 return 0;
407
408 if (!cpu_has(c, X86_FEATURE_MWAIT))
409 return 0;
410
411 return 1;
412}
413
414/*
415 * MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT
416 * with interrupts enabled and no flags, which is backwards compatible with the
417 * original MWAIT implementation.
418 */
419static void mwait_idle(void)
420{
421 if (!current_set_polling_and_test()) {
422 trace_cpu_idle_rcuidle(1, smp_processor_id());
423 if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) {
424 mb(); /* quirk */
425 clflush((void *)¤t_thread_info()->flags);
426 mb(); /* quirk */
427 }
428
429 __monitor((void *)¤t_thread_info()->flags, 0, 0);
430 if (!need_resched())
431 __sti_mwait(0, 0);
432 else
433 local_irq_enable();
434 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
435 } else {
436 local_irq_enable();
437 }
438 __current_clr_polling();
439}
440
441void select_idle_routine(const struct cpuinfo_x86 *c)
442{
443#ifdef CONFIG_SMP
444 if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1)
445 pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n");
446#endif
447 if (x86_idle || boot_option_idle_override == IDLE_POLL)
448 return;
449
450 if (cpu_has_bug(c, X86_BUG_AMD_APIC_C1E)) {
451 /* E400: APIC timer interrupt does not wake up CPU from C1e */
452 pr_info("using AMD E400 aware idle routine\n");
453 x86_idle = amd_e400_idle;
454 } else if (prefer_mwait_c1_over_halt(c)) {
455 pr_info("using mwait in idle threads\n");
456 x86_idle = mwait_idle;
457 } else
458 x86_idle = default_idle;
459}
460
461void __init init_amd_e400_c1e_mask(void)
462{
463 /* If we're using amd_e400_idle, we need to allocate amd_e400_c1e_mask. */
464 if (x86_idle == amd_e400_idle)
465 zalloc_cpumask_var(&amd_e400_c1e_mask, GFP_KERNEL);
466}
467
468static int __init idle_setup(char *str)
469{
470 if (!str)
471 return -EINVAL;
472
473 if (!strcmp(str, "poll")) {
474 pr_info("using polling idle threads\n");
475 boot_option_idle_override = IDLE_POLL;
476 cpu_idle_poll_ctrl(true);
477 } else if (!strcmp(str, "halt")) {
478 /*
479 * When the boot option of idle=halt is added, halt is
480 * forced to be used for CPU idle. In such case CPU C2/C3
481 * won't be used again.
482 * To continue to load the CPU idle driver, don't touch
483 * the boot_option_idle_override.
484 */
485 x86_idle = default_idle;
486 boot_option_idle_override = IDLE_HALT;
487 } else if (!strcmp(str, "nomwait")) {
488 /*
489 * If the boot option of "idle=nomwait" is added,
490 * it means that mwait will be disabled for CPU C2/C3
491 * states. In such case it won't touch the variable
492 * of boot_option_idle_override.
493 */
494 boot_option_idle_override = IDLE_NOMWAIT;
495 } else
496 return -1;
497
498 return 0;
499}
500early_param("idle", idle_setup);
501
502unsigned long arch_align_stack(unsigned long sp)
503{
504 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
505 sp -= get_random_int() % 8192;
506 return sp & ~0xf;
507}
508
509unsigned long arch_randomize_brk(struct mm_struct *mm)
510{
511 unsigned long range_end = mm->brk + 0x02000000;
512 return randomize_range(mm->brk, range_end, 0) ? : mm->brk;
513}
514
515/*
516 * Called from fs/proc with a reference on @p to find the function
517 * which called into schedule(). This needs to be done carefully
518 * because the task might wake up and we might look at a stack
519 * changing under us.
520 */
521unsigned long get_wchan(struct task_struct *p)
522{
523 unsigned long start, bottom, top, sp, fp, ip;
524 int count = 0;
525
526 if (!p || p == current || p->state == TASK_RUNNING)
527 return 0;
528
529 start = (unsigned long)task_stack_page(p);
530 if (!start)
531 return 0;
532
533 /*
534 * Layout of the stack page:
535 *
536 * ----------- topmax = start + THREAD_SIZE - sizeof(unsigned long)
537 * PADDING
538 * ----------- top = topmax - TOP_OF_KERNEL_STACK_PADDING
539 * stack
540 * ----------- bottom = start + sizeof(thread_info)
541 * thread_info
542 * ----------- start
543 *
544 * The tasks stack pointer points at the location where the
545 * framepointer is stored. The data on the stack is:
546 * ... IP FP ... IP FP
547 *
548 * We need to read FP and IP, so we need to adjust the upper
549 * bound by another unsigned long.
550 */
551 top = start + THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING;
552 top -= 2 * sizeof(unsigned long);
553 bottom = start + sizeof(struct thread_info);
554
555 sp = READ_ONCE(p->thread.sp);
556 if (sp < bottom || sp > top)
557 return 0;
558
559 fp = READ_ONCE_NOCHECK(*(unsigned long *)sp);
560 do {
561 if (fp < bottom || fp > top)
562 return 0;
563 ip = READ_ONCE_NOCHECK(*(unsigned long *)(fp + sizeof(unsigned long)));
564 if (!in_sched_functions(ip))
565 return ip;
566 fp = READ_ONCE_NOCHECK(*(unsigned long *)fp);
567 } while (count++ < 16 && p->state != TASK_RUNNING);
568 return 0;
569}
1// SPDX-License-Identifier: GPL-2.0
2#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
3
4#include <linux/errno.h>
5#include <linux/kernel.h>
6#include <linux/mm.h>
7#include <linux/smp.h>
8#include <linux/prctl.h>
9#include <linux/slab.h>
10#include <linux/sched.h>
11#include <linux/sched/idle.h>
12#include <linux/sched/debug.h>
13#include <linux/sched/task.h>
14#include <linux/sched/task_stack.h>
15#include <linux/init.h>
16#include <linux/export.h>
17#include <linux/pm.h>
18#include <linux/tick.h>
19#include <linux/random.h>
20#include <linux/user-return-notifier.h>
21#include <linux/dmi.h>
22#include <linux/utsname.h>
23#include <linux/stackprotector.h>
24#include <linux/cpuidle.h>
25#include <linux/acpi.h>
26#include <linux/elf-randomize.h>
27#include <trace/events/power.h>
28#include <linux/hw_breakpoint.h>
29#include <asm/cpu.h>
30#include <asm/apic.h>
31#include <linux/uaccess.h>
32#include <asm/mwait.h>
33#include <asm/fpu/api.h>
34#include <asm/fpu/sched.h>
35#include <asm/fpu/xstate.h>
36#include <asm/debugreg.h>
37#include <asm/nmi.h>
38#include <asm/tlbflush.h>
39#include <asm/mce.h>
40#include <asm/vm86.h>
41#include <asm/switch_to.h>
42#include <asm/desc.h>
43#include <asm/prctl.h>
44#include <asm/spec-ctrl.h>
45#include <asm/io_bitmap.h>
46#include <asm/proto.h>
47#include <asm/frame.h>
48#include <asm/unwind.h>
49#include <asm/tdx.h>
50
51#include "process.h"
52
53/*
54 * per-CPU TSS segments. Threads are completely 'soft' on Linux,
55 * no more per-task TSS's. The TSS size is kept cacheline-aligned
56 * so they are allowed to end up in the .data..cacheline_aligned
57 * section. Since TSS's are completely CPU-local, we want them
58 * on exact cacheline boundaries, to eliminate cacheline ping-pong.
59 */
60__visible DEFINE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw) = {
61 .x86_tss = {
62 /*
63 * .sp0 is only used when entering ring 0 from a lower
64 * privilege level. Since the init task never runs anything
65 * but ring 0 code, there is no need for a valid value here.
66 * Poison it.
67 */
68 .sp0 = (1UL << (BITS_PER_LONG-1)) + 1,
69
70#ifdef CONFIG_X86_32
71 .sp1 = TOP_OF_INIT_STACK,
72
73 .ss0 = __KERNEL_DS,
74 .ss1 = __KERNEL_CS,
75#endif
76 .io_bitmap_base = IO_BITMAP_OFFSET_INVALID,
77 },
78};
79EXPORT_PER_CPU_SYMBOL(cpu_tss_rw);
80
81DEFINE_PER_CPU(bool, __tss_limit_invalid);
82EXPORT_PER_CPU_SYMBOL_GPL(__tss_limit_invalid);
83
84/*
85 * this gets called so that we can store lazy state into memory and copy the
86 * current task into the new thread.
87 */
88int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
89{
90 memcpy(dst, src, arch_task_struct_size);
91#ifdef CONFIG_VM86
92 dst->thread.vm86 = NULL;
93#endif
94 /* Drop the copied pointer to current's fpstate */
95 dst->thread.fpu.fpstate = NULL;
96
97 return 0;
98}
99
100#ifdef CONFIG_X86_64
101void arch_release_task_struct(struct task_struct *tsk)
102{
103 if (fpu_state_size_dynamic())
104 fpstate_free(&tsk->thread.fpu);
105}
106#endif
107
108/*
109 * Free thread data structures etc..
110 */
111void exit_thread(struct task_struct *tsk)
112{
113 struct thread_struct *t = &tsk->thread;
114 struct fpu *fpu = &t->fpu;
115
116 if (test_thread_flag(TIF_IO_BITMAP))
117 io_bitmap_exit(tsk);
118
119 free_vm86(t);
120
121 fpu__drop(fpu);
122}
123
124static int set_new_tls(struct task_struct *p, unsigned long tls)
125{
126 struct user_desc __user *utls = (struct user_desc __user *)tls;
127
128 if (in_ia32_syscall())
129 return do_set_thread_area(p, -1, utls, 0);
130 else
131 return do_set_thread_area_64(p, ARCH_SET_FS, tls);
132}
133
134int copy_thread(struct task_struct *p, const struct kernel_clone_args *args)
135{
136 unsigned long clone_flags = args->flags;
137 unsigned long sp = args->stack;
138 unsigned long tls = args->tls;
139 struct inactive_task_frame *frame;
140 struct fork_frame *fork_frame;
141 struct pt_regs *childregs;
142 int ret = 0;
143
144 childregs = task_pt_regs(p);
145 fork_frame = container_of(childregs, struct fork_frame, regs);
146 frame = &fork_frame->frame;
147
148 frame->bp = encode_frame_pointer(childregs);
149 frame->ret_addr = (unsigned long) ret_from_fork;
150 p->thread.sp = (unsigned long) fork_frame;
151 p->thread.io_bitmap = NULL;
152 p->thread.iopl_warn = 0;
153 memset(p->thread.ptrace_bps, 0, sizeof(p->thread.ptrace_bps));
154
155#ifdef CONFIG_X86_64
156 current_save_fsgs();
157 p->thread.fsindex = current->thread.fsindex;
158 p->thread.fsbase = current->thread.fsbase;
159 p->thread.gsindex = current->thread.gsindex;
160 p->thread.gsbase = current->thread.gsbase;
161
162 savesegment(es, p->thread.es);
163 savesegment(ds, p->thread.ds);
164#else
165 p->thread.sp0 = (unsigned long) (childregs + 1);
166 savesegment(gs, p->thread.gs);
167 /*
168 * Clear all status flags including IF and set fixed bit. 64bit
169 * does not have this initialization as the frame does not contain
170 * flags. The flags consistency (especially vs. AC) is there
171 * ensured via objtool, which lacks 32bit support.
172 */
173 frame->flags = X86_EFLAGS_FIXED;
174#endif
175
176 fpu_clone(p, clone_flags, args->fn);
177
178 /* Kernel thread ? */
179 if (unlikely(p->flags & PF_KTHREAD)) {
180 p->thread.pkru = pkru_get_init_value();
181 memset(childregs, 0, sizeof(struct pt_regs));
182 kthread_frame_init(frame, args->fn, args->fn_arg);
183 return 0;
184 }
185
186 /*
187 * Clone current's PKRU value from hardware. tsk->thread.pkru
188 * is only valid when scheduled out.
189 */
190 p->thread.pkru = read_pkru();
191
192 frame->bx = 0;
193 *childregs = *current_pt_regs();
194 childregs->ax = 0;
195 if (sp)
196 childregs->sp = sp;
197
198 if (unlikely(args->fn)) {
199 /*
200 * A user space thread, but it doesn't return to
201 * ret_after_fork().
202 *
203 * In order to indicate that to tools like gdb,
204 * we reset the stack and instruction pointers.
205 *
206 * It does the same kernel frame setup to return to a kernel
207 * function that a kernel thread does.
208 */
209 childregs->sp = 0;
210 childregs->ip = 0;
211 kthread_frame_init(frame, args->fn, args->fn_arg);
212 return 0;
213 }
214
215 /* Set a new TLS for the child thread? */
216 if (clone_flags & CLONE_SETTLS)
217 ret = set_new_tls(p, tls);
218
219 if (!ret && unlikely(test_tsk_thread_flag(current, TIF_IO_BITMAP)))
220 io_bitmap_share(p);
221
222 return ret;
223}
224
225static void pkru_flush_thread(void)
226{
227 /*
228 * If PKRU is enabled the default PKRU value has to be loaded into
229 * the hardware right here (similar to context switch).
230 */
231 pkru_write_default();
232}
233
234void flush_thread(void)
235{
236 struct task_struct *tsk = current;
237
238 flush_ptrace_hw_breakpoint(tsk);
239 memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
240
241 fpu_flush_thread();
242 pkru_flush_thread();
243}
244
245void disable_TSC(void)
246{
247 preempt_disable();
248 if (!test_and_set_thread_flag(TIF_NOTSC))
249 /*
250 * Must flip the CPU state synchronously with
251 * TIF_NOTSC in the current running context.
252 */
253 cr4_set_bits(X86_CR4_TSD);
254 preempt_enable();
255}
256
257static void enable_TSC(void)
258{
259 preempt_disable();
260 if (test_and_clear_thread_flag(TIF_NOTSC))
261 /*
262 * Must flip the CPU state synchronously with
263 * TIF_NOTSC in the current running context.
264 */
265 cr4_clear_bits(X86_CR4_TSD);
266 preempt_enable();
267}
268
269int get_tsc_mode(unsigned long adr)
270{
271 unsigned int val;
272
273 if (test_thread_flag(TIF_NOTSC))
274 val = PR_TSC_SIGSEGV;
275 else
276 val = PR_TSC_ENABLE;
277
278 return put_user(val, (unsigned int __user *)adr);
279}
280
281int set_tsc_mode(unsigned int val)
282{
283 if (val == PR_TSC_SIGSEGV)
284 disable_TSC();
285 else if (val == PR_TSC_ENABLE)
286 enable_TSC();
287 else
288 return -EINVAL;
289
290 return 0;
291}
292
293DEFINE_PER_CPU(u64, msr_misc_features_shadow);
294
295static void set_cpuid_faulting(bool on)
296{
297 u64 msrval;
298
299 msrval = this_cpu_read(msr_misc_features_shadow);
300 msrval &= ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT;
301 msrval |= (on << MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT);
302 this_cpu_write(msr_misc_features_shadow, msrval);
303 wrmsrl(MSR_MISC_FEATURES_ENABLES, msrval);
304}
305
306static void disable_cpuid(void)
307{
308 preempt_disable();
309 if (!test_and_set_thread_flag(TIF_NOCPUID)) {
310 /*
311 * Must flip the CPU state synchronously with
312 * TIF_NOCPUID in the current running context.
313 */
314 set_cpuid_faulting(true);
315 }
316 preempt_enable();
317}
318
319static void enable_cpuid(void)
320{
321 preempt_disable();
322 if (test_and_clear_thread_flag(TIF_NOCPUID)) {
323 /*
324 * Must flip the CPU state synchronously with
325 * TIF_NOCPUID in the current running context.
326 */
327 set_cpuid_faulting(false);
328 }
329 preempt_enable();
330}
331
332static int get_cpuid_mode(void)
333{
334 return !test_thread_flag(TIF_NOCPUID);
335}
336
337static int set_cpuid_mode(unsigned long cpuid_enabled)
338{
339 if (!boot_cpu_has(X86_FEATURE_CPUID_FAULT))
340 return -ENODEV;
341
342 if (cpuid_enabled)
343 enable_cpuid();
344 else
345 disable_cpuid();
346
347 return 0;
348}
349
350/*
351 * Called immediately after a successful exec.
352 */
353void arch_setup_new_exec(void)
354{
355 /* If cpuid was previously disabled for this task, re-enable it. */
356 if (test_thread_flag(TIF_NOCPUID))
357 enable_cpuid();
358
359 /*
360 * Don't inherit TIF_SSBD across exec boundary when
361 * PR_SPEC_DISABLE_NOEXEC is used.
362 */
363 if (test_thread_flag(TIF_SSBD) &&
364 task_spec_ssb_noexec(current)) {
365 clear_thread_flag(TIF_SSBD);
366 task_clear_spec_ssb_disable(current);
367 task_clear_spec_ssb_noexec(current);
368 speculation_ctrl_update(read_thread_flags());
369 }
370}
371
372#ifdef CONFIG_X86_IOPL_IOPERM
373static inline void switch_to_bitmap(unsigned long tifp)
374{
375 /*
376 * Invalidate I/O bitmap if the previous task used it. This prevents
377 * any possible leakage of an active I/O bitmap.
378 *
379 * If the next task has an I/O bitmap it will handle it on exit to
380 * user mode.
381 */
382 if (tifp & _TIF_IO_BITMAP)
383 tss_invalidate_io_bitmap();
384}
385
386static void tss_copy_io_bitmap(struct tss_struct *tss, struct io_bitmap *iobm)
387{
388 /*
389 * Copy at least the byte range of the incoming tasks bitmap which
390 * covers the permitted I/O ports.
391 *
392 * If the previous task which used an I/O bitmap had more bits
393 * permitted, then the copy needs to cover those as well so they
394 * get turned off.
395 */
396 memcpy(tss->io_bitmap.bitmap, iobm->bitmap,
397 max(tss->io_bitmap.prev_max, iobm->max));
398
399 /*
400 * Store the new max and the sequence number of this bitmap
401 * and a pointer to the bitmap itself.
402 */
403 tss->io_bitmap.prev_max = iobm->max;
404 tss->io_bitmap.prev_sequence = iobm->sequence;
405}
406
407/**
408 * native_tss_update_io_bitmap - Update I/O bitmap before exiting to user mode
409 */
410void native_tss_update_io_bitmap(void)
411{
412 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw);
413 struct thread_struct *t = ¤t->thread;
414 u16 *base = &tss->x86_tss.io_bitmap_base;
415
416 if (!test_thread_flag(TIF_IO_BITMAP)) {
417 native_tss_invalidate_io_bitmap();
418 return;
419 }
420
421 if (IS_ENABLED(CONFIG_X86_IOPL_IOPERM) && t->iopl_emul == 3) {
422 *base = IO_BITMAP_OFFSET_VALID_ALL;
423 } else {
424 struct io_bitmap *iobm = t->io_bitmap;
425
426 /*
427 * Only copy bitmap data when the sequence number differs. The
428 * update time is accounted to the incoming task.
429 */
430 if (tss->io_bitmap.prev_sequence != iobm->sequence)
431 tss_copy_io_bitmap(tss, iobm);
432
433 /* Enable the bitmap */
434 *base = IO_BITMAP_OFFSET_VALID_MAP;
435 }
436
437 /*
438 * Make sure that the TSS limit is covering the IO bitmap. It might have
439 * been cut down by a VMEXIT to 0x67 which would cause a subsequent I/O
440 * access from user space to trigger a #GP because tbe bitmap is outside
441 * the TSS limit.
442 */
443 refresh_tss_limit();
444}
445#else /* CONFIG_X86_IOPL_IOPERM */
446static inline void switch_to_bitmap(unsigned long tifp) { }
447#endif
448
449#ifdef CONFIG_SMP
450
451struct ssb_state {
452 struct ssb_state *shared_state;
453 raw_spinlock_t lock;
454 unsigned int disable_state;
455 unsigned long local_state;
456};
457
458#define LSTATE_SSB 0
459
460static DEFINE_PER_CPU(struct ssb_state, ssb_state);
461
462void speculative_store_bypass_ht_init(void)
463{
464 struct ssb_state *st = this_cpu_ptr(&ssb_state);
465 unsigned int this_cpu = smp_processor_id();
466 unsigned int cpu;
467
468 st->local_state = 0;
469
470 /*
471 * Shared state setup happens once on the first bringup
472 * of the CPU. It's not destroyed on CPU hotunplug.
473 */
474 if (st->shared_state)
475 return;
476
477 raw_spin_lock_init(&st->lock);
478
479 /*
480 * Go over HT siblings and check whether one of them has set up the
481 * shared state pointer already.
482 */
483 for_each_cpu(cpu, topology_sibling_cpumask(this_cpu)) {
484 if (cpu == this_cpu)
485 continue;
486
487 if (!per_cpu(ssb_state, cpu).shared_state)
488 continue;
489
490 /* Link it to the state of the sibling: */
491 st->shared_state = per_cpu(ssb_state, cpu).shared_state;
492 return;
493 }
494
495 /*
496 * First HT sibling to come up on the core. Link shared state of
497 * the first HT sibling to itself. The siblings on the same core
498 * which come up later will see the shared state pointer and link
499 * themselves to the state of this CPU.
500 */
501 st->shared_state = st;
502}
503
504/*
505 * Logic is: First HT sibling enables SSBD for both siblings in the core
506 * and last sibling to disable it, disables it for the whole core. This how
507 * MSR_SPEC_CTRL works in "hardware":
508 *
509 * CORE_SPEC_CTRL = THREAD0_SPEC_CTRL | THREAD1_SPEC_CTRL
510 */
511static __always_inline void amd_set_core_ssb_state(unsigned long tifn)
512{
513 struct ssb_state *st = this_cpu_ptr(&ssb_state);
514 u64 msr = x86_amd_ls_cfg_base;
515
516 if (!static_cpu_has(X86_FEATURE_ZEN)) {
517 msr |= ssbd_tif_to_amd_ls_cfg(tifn);
518 wrmsrl(MSR_AMD64_LS_CFG, msr);
519 return;
520 }
521
522 if (tifn & _TIF_SSBD) {
523 /*
524 * Since this can race with prctl(), block reentry on the
525 * same CPU.
526 */
527 if (__test_and_set_bit(LSTATE_SSB, &st->local_state))
528 return;
529
530 msr |= x86_amd_ls_cfg_ssbd_mask;
531
532 raw_spin_lock(&st->shared_state->lock);
533 /* First sibling enables SSBD: */
534 if (!st->shared_state->disable_state)
535 wrmsrl(MSR_AMD64_LS_CFG, msr);
536 st->shared_state->disable_state++;
537 raw_spin_unlock(&st->shared_state->lock);
538 } else {
539 if (!__test_and_clear_bit(LSTATE_SSB, &st->local_state))
540 return;
541
542 raw_spin_lock(&st->shared_state->lock);
543 st->shared_state->disable_state--;
544 if (!st->shared_state->disable_state)
545 wrmsrl(MSR_AMD64_LS_CFG, msr);
546 raw_spin_unlock(&st->shared_state->lock);
547 }
548}
549#else
550static __always_inline void amd_set_core_ssb_state(unsigned long tifn)
551{
552 u64 msr = x86_amd_ls_cfg_base | ssbd_tif_to_amd_ls_cfg(tifn);
553
554 wrmsrl(MSR_AMD64_LS_CFG, msr);
555}
556#endif
557
558static __always_inline void amd_set_ssb_virt_state(unsigned long tifn)
559{
560 /*
561 * SSBD has the same definition in SPEC_CTRL and VIRT_SPEC_CTRL,
562 * so ssbd_tif_to_spec_ctrl() just works.
563 */
564 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, ssbd_tif_to_spec_ctrl(tifn));
565}
566
567/*
568 * Update the MSRs managing speculation control, during context switch.
569 *
570 * tifp: Previous task's thread flags
571 * tifn: Next task's thread flags
572 */
573static __always_inline void __speculation_ctrl_update(unsigned long tifp,
574 unsigned long tifn)
575{
576 unsigned long tif_diff = tifp ^ tifn;
577 u64 msr = x86_spec_ctrl_base;
578 bool updmsr = false;
579
580 lockdep_assert_irqs_disabled();
581
582 /* Handle change of TIF_SSBD depending on the mitigation method. */
583 if (static_cpu_has(X86_FEATURE_VIRT_SSBD)) {
584 if (tif_diff & _TIF_SSBD)
585 amd_set_ssb_virt_state(tifn);
586 } else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD)) {
587 if (tif_diff & _TIF_SSBD)
588 amd_set_core_ssb_state(tifn);
589 } else if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
590 static_cpu_has(X86_FEATURE_AMD_SSBD)) {
591 updmsr |= !!(tif_diff & _TIF_SSBD);
592 msr |= ssbd_tif_to_spec_ctrl(tifn);
593 }
594
595 /* Only evaluate TIF_SPEC_IB if conditional STIBP is enabled. */
596 if (IS_ENABLED(CONFIG_SMP) &&
597 static_branch_unlikely(&switch_to_cond_stibp)) {
598 updmsr |= !!(tif_diff & _TIF_SPEC_IB);
599 msr |= stibp_tif_to_spec_ctrl(tifn);
600 }
601
602 if (updmsr)
603 update_spec_ctrl_cond(msr);
604}
605
606static unsigned long speculation_ctrl_update_tif(struct task_struct *tsk)
607{
608 if (test_and_clear_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE)) {
609 if (task_spec_ssb_disable(tsk))
610 set_tsk_thread_flag(tsk, TIF_SSBD);
611 else
612 clear_tsk_thread_flag(tsk, TIF_SSBD);
613
614 if (task_spec_ib_disable(tsk))
615 set_tsk_thread_flag(tsk, TIF_SPEC_IB);
616 else
617 clear_tsk_thread_flag(tsk, TIF_SPEC_IB);
618 }
619 /* Return the updated threadinfo flags*/
620 return read_task_thread_flags(tsk);
621}
622
623void speculation_ctrl_update(unsigned long tif)
624{
625 unsigned long flags;
626
627 /* Forced update. Make sure all relevant TIF flags are different */
628 local_irq_save(flags);
629 __speculation_ctrl_update(~tif, tif);
630 local_irq_restore(flags);
631}
632
633/* Called from seccomp/prctl update */
634void speculation_ctrl_update_current(void)
635{
636 preempt_disable();
637 speculation_ctrl_update(speculation_ctrl_update_tif(current));
638 preempt_enable();
639}
640
641static inline void cr4_toggle_bits_irqsoff(unsigned long mask)
642{
643 unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4);
644
645 newval = cr4 ^ mask;
646 if (newval != cr4) {
647 this_cpu_write(cpu_tlbstate.cr4, newval);
648 __write_cr4(newval);
649 }
650}
651
652void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p)
653{
654 unsigned long tifp, tifn;
655
656 tifn = read_task_thread_flags(next_p);
657 tifp = read_task_thread_flags(prev_p);
658
659 switch_to_bitmap(tifp);
660
661 propagate_user_return_notify(prev_p, next_p);
662
663 if ((tifp & _TIF_BLOCKSTEP || tifn & _TIF_BLOCKSTEP) &&
664 arch_has_block_step()) {
665 unsigned long debugctl, msk;
666
667 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
668 debugctl &= ~DEBUGCTLMSR_BTF;
669 msk = tifn & _TIF_BLOCKSTEP;
670 debugctl |= (msk >> TIF_BLOCKSTEP) << DEBUGCTLMSR_BTF_SHIFT;
671 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
672 }
673
674 if ((tifp ^ tifn) & _TIF_NOTSC)
675 cr4_toggle_bits_irqsoff(X86_CR4_TSD);
676
677 if ((tifp ^ tifn) & _TIF_NOCPUID)
678 set_cpuid_faulting(!!(tifn & _TIF_NOCPUID));
679
680 if (likely(!((tifp | tifn) & _TIF_SPEC_FORCE_UPDATE))) {
681 __speculation_ctrl_update(tifp, tifn);
682 } else {
683 speculation_ctrl_update_tif(prev_p);
684 tifn = speculation_ctrl_update_tif(next_p);
685
686 /* Enforce MSR update to ensure consistent state */
687 __speculation_ctrl_update(~tifn, tifn);
688 }
689}
690
691/*
692 * Idle related variables and functions
693 */
694unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
695EXPORT_SYMBOL(boot_option_idle_override);
696
697static void (*x86_idle)(void);
698
699#ifndef CONFIG_SMP
700static inline void play_dead(void)
701{
702 BUG();
703}
704#endif
705
706void arch_cpu_idle_enter(void)
707{
708 tsc_verify_tsc_adjust(false);
709 local_touch_nmi();
710}
711
712void arch_cpu_idle_dead(void)
713{
714 play_dead();
715}
716
717/*
718 * Called from the generic idle code.
719 */
720void arch_cpu_idle(void)
721{
722 x86_idle();
723}
724
725/*
726 * We use this if we don't have any better idle routine..
727 */
728void __cpuidle default_idle(void)
729{
730 raw_safe_halt();
731}
732#if defined(CONFIG_APM_MODULE) || defined(CONFIG_HALTPOLL_CPUIDLE_MODULE)
733EXPORT_SYMBOL(default_idle);
734#endif
735
736#ifdef CONFIG_XEN
737bool xen_set_default_idle(void)
738{
739 bool ret = !!x86_idle;
740
741 x86_idle = default_idle;
742
743 return ret;
744}
745#endif
746
747void __noreturn stop_this_cpu(void *dummy)
748{
749 local_irq_disable();
750 /*
751 * Remove this CPU:
752 */
753 set_cpu_online(smp_processor_id(), false);
754 disable_local_APIC();
755 mcheck_cpu_clear(this_cpu_ptr(&cpu_info));
756
757 /*
758 * Use wbinvd on processors that support SME. This provides support
759 * for performing a successful kexec when going from SME inactive
760 * to SME active (or vice-versa). The cache must be cleared so that
761 * if there are entries with the same physical address, both with and
762 * without the encryption bit, they don't race each other when flushed
763 * and potentially end up with the wrong entry being committed to
764 * memory.
765 *
766 * Test the CPUID bit directly because the machine might've cleared
767 * X86_FEATURE_SME due to cmdline options.
768 */
769 if (cpuid_eax(0x8000001f) & BIT(0))
770 native_wbinvd();
771 for (;;) {
772 /*
773 * Use native_halt() so that memory contents don't change
774 * (stack usage and variables) after possibly issuing the
775 * native_wbinvd() above.
776 */
777 native_halt();
778 }
779}
780
781/*
782 * AMD Erratum 400 aware idle routine. We handle it the same way as C3 power
783 * states (local apic timer and TSC stop).
784 *
785 * XXX this function is completely buggered vs RCU and tracing.
786 */
787static void amd_e400_idle(void)
788{
789 /*
790 * We cannot use static_cpu_has_bug() here because X86_BUG_AMD_APIC_C1E
791 * gets set after static_cpu_has() places have been converted via
792 * alternatives.
793 */
794 if (!boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
795 default_idle();
796 return;
797 }
798
799 tick_broadcast_enter();
800
801 default_idle();
802
803 /*
804 * The switch back from broadcast mode needs to be called with
805 * interrupts disabled.
806 */
807 raw_local_irq_disable();
808 tick_broadcast_exit();
809 raw_local_irq_enable();
810}
811
812/*
813 * Prefer MWAIT over HALT if MWAIT is supported, MWAIT_CPUID leaf
814 * exists and whenever MONITOR/MWAIT extensions are present there is at
815 * least one C1 substate.
816 *
817 * Do not prefer MWAIT if MONITOR instruction has a bug or idle=nomwait
818 * is passed to kernel commandline parameter.
819 */
820static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c)
821{
822 u32 eax, ebx, ecx, edx;
823
824 /* User has disallowed the use of MWAIT. Fallback to HALT */
825 if (boot_option_idle_override == IDLE_NOMWAIT)
826 return 0;
827
828 /* MWAIT is not supported on this platform. Fallback to HALT */
829 if (!cpu_has(c, X86_FEATURE_MWAIT))
830 return 0;
831
832 /* Monitor has a bug. Fallback to HALT */
833 if (boot_cpu_has_bug(X86_BUG_MONITOR))
834 return 0;
835
836 cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &edx);
837
838 /*
839 * If MWAIT extensions are not available, it is safe to use MWAIT
840 * with EAX=0, ECX=0.
841 */
842 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED))
843 return 1;
844
845 /*
846 * If MWAIT extensions are available, there should be at least one
847 * MWAIT C1 substate present.
848 */
849 return (edx & MWAIT_C1_SUBSTATE_MASK);
850}
851
852/*
853 * MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT
854 * with interrupts enabled and no flags, which is backwards compatible with the
855 * original MWAIT implementation.
856 */
857static __cpuidle void mwait_idle(void)
858{
859 if (!current_set_polling_and_test()) {
860 if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) {
861 mb(); /* quirk */
862 clflush((void *)¤t_thread_info()->flags);
863 mb(); /* quirk */
864 }
865
866 __monitor((void *)¤t_thread_info()->flags, 0, 0);
867 if (!need_resched())
868 __sti_mwait(0, 0);
869 else
870 raw_local_irq_enable();
871 } else {
872 raw_local_irq_enable();
873 }
874 __current_clr_polling();
875}
876
877void select_idle_routine(const struct cpuinfo_x86 *c)
878{
879#ifdef CONFIG_SMP
880 if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1)
881 pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n");
882#endif
883 if (x86_idle || boot_option_idle_override == IDLE_POLL)
884 return;
885
886 if (boot_cpu_has_bug(X86_BUG_AMD_E400)) {
887 pr_info("using AMD E400 aware idle routine\n");
888 x86_idle = amd_e400_idle;
889 } else if (prefer_mwait_c1_over_halt(c)) {
890 pr_info("using mwait in idle threads\n");
891 x86_idle = mwait_idle;
892 } else if (cpu_feature_enabled(X86_FEATURE_TDX_GUEST)) {
893 pr_info("using TDX aware idle routine\n");
894 x86_idle = tdx_safe_halt;
895 } else
896 x86_idle = default_idle;
897}
898
899void amd_e400_c1e_apic_setup(void)
900{
901 if (boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
902 pr_info("Switch to broadcast mode on CPU%d\n", smp_processor_id());
903 local_irq_disable();
904 tick_broadcast_force();
905 local_irq_enable();
906 }
907}
908
909void __init arch_post_acpi_subsys_init(void)
910{
911 u32 lo, hi;
912
913 if (!boot_cpu_has_bug(X86_BUG_AMD_E400))
914 return;
915
916 /*
917 * AMD E400 detection needs to happen after ACPI has been enabled. If
918 * the machine is affected K8_INTP_C1E_ACTIVE_MASK bits are set in
919 * MSR_K8_INT_PENDING_MSG.
920 */
921 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
922 if (!(lo & K8_INTP_C1E_ACTIVE_MASK))
923 return;
924
925 boot_cpu_set_bug(X86_BUG_AMD_APIC_C1E);
926
927 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
928 mark_tsc_unstable("TSC halt in AMD C1E");
929 pr_info("System has AMD C1E enabled\n");
930}
931
932static int __init idle_setup(char *str)
933{
934 if (!str)
935 return -EINVAL;
936
937 if (!strcmp(str, "poll")) {
938 pr_info("using polling idle threads\n");
939 boot_option_idle_override = IDLE_POLL;
940 cpu_idle_poll_ctrl(true);
941 } else if (!strcmp(str, "halt")) {
942 /*
943 * When the boot option of idle=halt is added, halt is
944 * forced to be used for CPU idle. In such case CPU C2/C3
945 * won't be used again.
946 * To continue to load the CPU idle driver, don't touch
947 * the boot_option_idle_override.
948 */
949 x86_idle = default_idle;
950 boot_option_idle_override = IDLE_HALT;
951 } else if (!strcmp(str, "nomwait")) {
952 /*
953 * If the boot option of "idle=nomwait" is added,
954 * it means that mwait will be disabled for CPU C1/C2/C3
955 * states.
956 */
957 boot_option_idle_override = IDLE_NOMWAIT;
958 } else
959 return -1;
960
961 return 0;
962}
963early_param("idle", idle_setup);
964
965unsigned long arch_align_stack(unsigned long sp)
966{
967 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
968 sp -= get_random_u32_below(8192);
969 return sp & ~0xf;
970}
971
972unsigned long arch_randomize_brk(struct mm_struct *mm)
973{
974 return randomize_page(mm->brk, 0x02000000);
975}
976
977/*
978 * Called from fs/proc with a reference on @p to find the function
979 * which called into schedule(). This needs to be done carefully
980 * because the task might wake up and we might look at a stack
981 * changing under us.
982 */
983unsigned long __get_wchan(struct task_struct *p)
984{
985 struct unwind_state state;
986 unsigned long addr = 0;
987
988 if (!try_get_task_stack(p))
989 return 0;
990
991 for (unwind_start(&state, p, NULL, NULL); !unwind_done(&state);
992 unwind_next_frame(&state)) {
993 addr = unwind_get_return_address(&state);
994 if (!addr)
995 break;
996 if (in_sched_functions(addr))
997 continue;
998 break;
999 }
1000
1001 put_task_stack(p);
1002
1003 return addr;
1004}
1005
1006long do_arch_prctl_common(int option, unsigned long arg2)
1007{
1008 switch (option) {
1009 case ARCH_GET_CPUID:
1010 return get_cpuid_mode();
1011 case ARCH_SET_CPUID:
1012 return set_cpuid_mode(arg2);
1013 case ARCH_GET_XCOMP_SUPP:
1014 case ARCH_GET_XCOMP_PERM:
1015 case ARCH_REQ_XCOMP_PERM:
1016 case ARCH_GET_XCOMP_GUEST_PERM:
1017 case ARCH_REQ_XCOMP_GUEST_PERM:
1018 return fpu_xstate_prctl(option, arg2);
1019 }
1020
1021 return -EINVAL;
1022}