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1/*
2 * Copyright (C) 2013 Imagination Technologies
3 * Author: Paul Burton <paul.burton@imgtec.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10
11#ifndef __MIPS_ASM_MIPS_CPC_H__
12#define __MIPS_ASM_MIPS_CPC_H__
13
14#include <linux/io.h>
15#include <linux/types.h>
16
17/* The base address of the CPC registers */
18extern void __iomem *mips_cpc_base;
19
20/**
21 * mips_cpc_default_phys_base - retrieve the default physical base address of
22 * the CPC
23 *
24 * Returns the default physical base address of the Cluster Power Controller
25 * memory mapped registers. This is platform dependant & must therefore be
26 * implemented per-platform.
27 */
28extern phys_addr_t mips_cpc_default_phys_base(void);
29
30/**
31 * mips_cpc_probe - probe for a Cluster Power Controller
32 *
33 * Attempt to detect the presence of a Cluster Power Controller. Returns 0 if
34 * a CPC is successfully detected, else -errno.
35 */
36#ifdef CONFIG_MIPS_CPC
37extern int mips_cpc_probe(void);
38#else
39static inline int mips_cpc_probe(void)
40{
41 return -ENODEV;
42}
43#endif
44
45/**
46 * mips_cpc_present - determine whether a Cluster Power Controller is present
47 *
48 * Returns true if a CPC is present in the system, else false.
49 */
50static inline bool mips_cpc_present(void)
51{
52#ifdef CONFIG_MIPS_CPC
53 return mips_cpc_base != NULL;
54#else
55 return false;
56#endif
57}
58
59/* Offsets from the CPC base address to various control blocks */
60#define MIPS_CPC_GCB_OFS 0x0000
61#define MIPS_CPC_CLCB_OFS 0x2000
62#define MIPS_CPC_COCB_OFS 0x4000
63
64/* Macros to ease the creation of register access functions */
65#define BUILD_CPC_R_(name, off) \
66static inline u32 *addr_cpc_##name(void) \
67{ \
68 return (u32 *)(mips_cpc_base + (off)); \
69} \
70 \
71static inline u32 read_cpc_##name(void) \
72{ \
73 return __raw_readl(mips_cpc_base + (off)); \
74}
75
76#define BUILD_CPC__W(name, off) \
77static inline void write_cpc_##name(u32 value) \
78{ \
79 __raw_writel(value, mips_cpc_base + (off)); \
80}
81
82#define BUILD_CPC_RW(name, off) \
83 BUILD_CPC_R_(name, off) \
84 BUILD_CPC__W(name, off)
85
86#define BUILD_CPC_Cx_R_(name, off) \
87 BUILD_CPC_R_(cl_##name, MIPS_CPC_CLCB_OFS + (off)) \
88 BUILD_CPC_R_(co_##name, MIPS_CPC_COCB_OFS + (off))
89
90#define BUILD_CPC_Cx__W(name, off) \
91 BUILD_CPC__W(cl_##name, MIPS_CPC_CLCB_OFS + (off)) \
92 BUILD_CPC__W(co_##name, MIPS_CPC_COCB_OFS + (off))
93
94#define BUILD_CPC_Cx_RW(name, off) \
95 BUILD_CPC_Cx_R_(name, off) \
96 BUILD_CPC_Cx__W(name, off)
97
98/* GCB register accessor functions */
99BUILD_CPC_RW(access, MIPS_CPC_GCB_OFS + 0x00)
100BUILD_CPC_RW(seqdel, MIPS_CPC_GCB_OFS + 0x08)
101BUILD_CPC_RW(rail, MIPS_CPC_GCB_OFS + 0x10)
102BUILD_CPC_RW(resetlen, MIPS_CPC_GCB_OFS + 0x18)
103BUILD_CPC_R_(revision, MIPS_CPC_GCB_OFS + 0x20)
104
105/* Core Local & Core Other accessor functions */
106BUILD_CPC_Cx_RW(cmd, 0x00)
107BUILD_CPC_Cx_RW(stat_conf, 0x08)
108BUILD_CPC_Cx_RW(other, 0x10)
109
110/* CPC_Cx_CMD register fields */
111#define CPC_Cx_CMD_SHF 0
112#define CPC_Cx_CMD_MSK (_ULCAST_(0xf) << 0)
113#define CPC_Cx_CMD_CLOCKOFF (_ULCAST_(0x1) << 0)
114#define CPC_Cx_CMD_PWRDOWN (_ULCAST_(0x2) << 0)
115#define CPC_Cx_CMD_PWRUP (_ULCAST_(0x3) << 0)
116#define CPC_Cx_CMD_RESET (_ULCAST_(0x4) << 0)
117
118/* CPC_Cx_STAT_CONF register fields */
119#define CPC_Cx_STAT_CONF_PWRUPE_SHF 23
120#define CPC_Cx_STAT_CONF_PWRUPE_MSK (_ULCAST_(0x1) << 23)
121#define CPC_Cx_STAT_CONF_SEQSTATE_SHF 19
122#define CPC_Cx_STAT_CONF_SEQSTATE_MSK (_ULCAST_(0xf) << 19)
123#define CPC_Cx_STAT_CONF_SEQSTATE_D0 (_ULCAST_(0x0) << 19)
124#define CPC_Cx_STAT_CONF_SEQSTATE_U0 (_ULCAST_(0x1) << 19)
125#define CPC_Cx_STAT_CONF_SEQSTATE_U1 (_ULCAST_(0x2) << 19)
126#define CPC_Cx_STAT_CONF_SEQSTATE_U2 (_ULCAST_(0x3) << 19)
127#define CPC_Cx_STAT_CONF_SEQSTATE_U3 (_ULCAST_(0x4) << 19)
128#define CPC_Cx_STAT_CONF_SEQSTATE_U4 (_ULCAST_(0x5) << 19)
129#define CPC_Cx_STAT_CONF_SEQSTATE_U5 (_ULCAST_(0x6) << 19)
130#define CPC_Cx_STAT_CONF_SEQSTATE_U6 (_ULCAST_(0x7) << 19)
131#define CPC_Cx_STAT_CONF_SEQSTATE_D1 (_ULCAST_(0x8) << 19)
132#define CPC_Cx_STAT_CONF_SEQSTATE_D3 (_ULCAST_(0x9) << 19)
133#define CPC_Cx_STAT_CONF_SEQSTATE_D2 (_ULCAST_(0xa) << 19)
134#define CPC_Cx_STAT_CONF_CLKGAT_IMPL_SHF 17
135#define CPC_Cx_STAT_CONF_CLKGAT_IMPL_MSK (_ULCAST_(0x1) << 17)
136#define CPC_Cx_STAT_CONF_PWRDN_IMPL_SHF 16
137#define CPC_Cx_STAT_CONF_PWRDN_IMPL_MSK (_ULCAST_(0x1) << 16)
138#define CPC_Cx_STAT_CONF_EJTAG_PROBE_SHF 15
139#define CPC_Cx_STAT_CONF_EJTAG_PROBE_MSK (_ULCAST_(0x1) << 15)
140
141/* CPC_Cx_OTHER register fields */
142#define CPC_Cx_OTHER_CORENUM_SHF 16
143#define CPC_Cx_OTHER_CORENUM_MSK (_ULCAST_(0xff) << 16)
144
145#ifdef CONFIG_MIPS_CPC
146
147/**
148 * mips_cpc_lock_other - lock access to another core
149 * core: the other core to be accessed
150 *
151 * Call before operating upon a core via the 'other' register region in
152 * order to prevent the region being moved during access. Must be called
153 * within the bounds of a mips_cm_{lock,unlock}_other pair, and followed
154 * by a call to mips_cpc_unlock_other.
155 */
156extern void mips_cpc_lock_other(unsigned int core);
157
158/**
159 * mips_cpc_unlock_other - unlock access to another core
160 *
161 * Call after operating upon another core via the 'other' register region.
162 * Must be called after mips_cpc_lock_other.
163 */
164extern void mips_cpc_unlock_other(void);
165
166#else /* !CONFIG_MIPS_CPC */
167
168static inline void mips_cpc_lock_other(unsigned int core) { }
169static inline void mips_cpc_unlock_other(void) { }
170
171#endif /* !CONFIG_MIPS_CPC */
172
173#endif /* __MIPS_ASM_MIPS_CPC_H__ */
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Copyright (C) 2013 Imagination Technologies
4 * Author: Paul Burton <paul.burton@mips.com>
5 */
6
7#ifndef __MIPS_ASM_MIPS_CPS_H__
8# error Please include asm/mips-cps.h rather than asm/mips-cpc.h
9#endif
10
11#ifndef __MIPS_ASM_MIPS_CPC_H__
12#define __MIPS_ASM_MIPS_CPC_H__
13
14#include <linux/bitops.h>
15#include <linux/errno.h>
16
17/* The base address of the CPC registers */
18extern void __iomem *mips_cpc_base;
19
20/**
21 * mips_cpc_default_phys_base - retrieve the default physical base address of
22 * the CPC
23 *
24 * Returns the default physical base address of the Cluster Power Controller
25 * memory mapped registers. This is platform dependant & must therefore be
26 * implemented per-platform.
27 */
28extern phys_addr_t mips_cpc_default_phys_base(void);
29
30/**
31 * mips_cpc_probe - probe for a Cluster Power Controller
32 *
33 * Attempt to detect the presence of a Cluster Power Controller. Returns 0 if
34 * a CPC is successfully detected, else -errno.
35 */
36#ifdef CONFIG_MIPS_CPC
37extern int mips_cpc_probe(void);
38#else
39static inline int mips_cpc_probe(void)
40{
41 return -ENODEV;
42}
43#endif
44
45/**
46 * mips_cpc_present - determine whether a Cluster Power Controller is present
47 *
48 * Returns true if a CPC is present in the system, else false.
49 */
50static inline bool mips_cpc_present(void)
51{
52#ifdef CONFIG_MIPS_CPC
53 return mips_cpc_base != NULL;
54#else
55 return false;
56#endif
57}
58
59/* Offsets from the CPC base address to various control blocks */
60#define MIPS_CPC_GCB_OFS 0x0000
61#define MIPS_CPC_CLCB_OFS 0x2000
62#define MIPS_CPC_COCB_OFS 0x4000
63
64#define CPC_ACCESSOR_RO(sz, off, name) \
65 CPS_ACCESSOR_RO(cpc, sz, MIPS_CPC_GCB_OFS + off, name) \
66 CPS_ACCESSOR_RO(cpc, sz, MIPS_CPC_COCB_OFS + off, redir_##name)
67
68#define CPC_ACCESSOR_RW(sz, off, name) \
69 CPS_ACCESSOR_RW(cpc, sz, MIPS_CPC_GCB_OFS + off, name) \
70 CPS_ACCESSOR_RW(cpc, sz, MIPS_CPC_COCB_OFS + off, redir_##name)
71
72#define CPC_CX_ACCESSOR_RO(sz, off, name) \
73 CPS_ACCESSOR_RO(cpc, sz, MIPS_CPC_CLCB_OFS + off, cl_##name) \
74 CPS_ACCESSOR_RO(cpc, sz, MIPS_CPC_COCB_OFS + off, co_##name)
75
76#define CPC_CX_ACCESSOR_RW(sz, off, name) \
77 CPS_ACCESSOR_RW(cpc, sz, MIPS_CPC_CLCB_OFS + off, cl_##name) \
78 CPS_ACCESSOR_RW(cpc, sz, MIPS_CPC_COCB_OFS + off, co_##name)
79
80/* CPC_ACCESS - Control core/IOCU access to CPC registers prior to CM 3 */
81CPC_ACCESSOR_RW(32, 0x000, access)
82
83/* CPC_SEQDEL - Configure delays between command sequencer steps */
84CPC_ACCESSOR_RW(32, 0x008, seqdel)
85
86/* CPC_RAIL - Configure the delay from rail power-up to stability */
87CPC_ACCESSOR_RW(32, 0x010, rail)
88
89/* CPC_RESETLEN - Configure the length of reset sequences */
90CPC_ACCESSOR_RW(32, 0x018, resetlen)
91
92/* CPC_REVISION - Indicates the revisison of the CPC */
93CPC_ACCESSOR_RO(32, 0x020, revision)
94
95/* CPC_PWRUP_CTL - Control power to the Coherence Manager (CM) */
96CPC_ACCESSOR_RW(32, 0x030, pwrup_ctl)
97#define CPC_PWRUP_CTL_CM_PWRUP BIT(0)
98
99/* CPC_CONFIG - Mirrors GCR_CONFIG */
100CPC_ACCESSOR_RW(64, 0x138, config)
101
102/* CPC_SYS_CONFIG - Control cluster endianness */
103CPC_ACCESSOR_RW(32, 0x140, sys_config)
104#define CPC_SYS_CONFIG_BE_IMMEDIATE BIT(2)
105#define CPC_SYS_CONFIG_BE_STATUS BIT(1)
106#define CPC_SYS_CONFIG_BE BIT(0)
107
108/* CPC_Cx_CMD - Instruct the CPC to take action on a core */
109CPC_CX_ACCESSOR_RW(32, 0x000, cmd)
110#define CPC_Cx_CMD GENMASK(3, 0)
111#define CPC_Cx_CMD_CLOCKOFF 0x1
112#define CPC_Cx_CMD_PWRDOWN 0x2
113#define CPC_Cx_CMD_PWRUP 0x3
114#define CPC_Cx_CMD_RESET 0x4
115
116/* CPC_Cx_STAT_CONF - Indicates core configuration & state */
117CPC_CX_ACCESSOR_RW(32, 0x008, stat_conf)
118#define CPC_Cx_STAT_CONF_PWRUPE BIT(23)
119#define CPC_Cx_STAT_CONF_SEQSTATE GENMASK(22, 19)
120#define CPC_Cx_STAT_CONF_SEQSTATE_D0 0x0
121#define CPC_Cx_STAT_CONF_SEQSTATE_U0 0x1
122#define CPC_Cx_STAT_CONF_SEQSTATE_U1 0x2
123#define CPC_Cx_STAT_CONF_SEQSTATE_U2 0x3
124#define CPC_Cx_STAT_CONF_SEQSTATE_U3 0x4
125#define CPC_Cx_STAT_CONF_SEQSTATE_U4 0x5
126#define CPC_Cx_STAT_CONF_SEQSTATE_U5 0x6
127#define CPC_Cx_STAT_CONF_SEQSTATE_U6 0x7
128#define CPC_Cx_STAT_CONF_SEQSTATE_D1 0x8
129#define CPC_Cx_STAT_CONF_SEQSTATE_D3 0x9
130#define CPC_Cx_STAT_CONF_SEQSTATE_D2 0xa
131#define CPC_Cx_STAT_CONF_CLKGAT_IMPL BIT(17)
132#define CPC_Cx_STAT_CONF_PWRDN_IMPL BIT(16)
133#define CPC_Cx_STAT_CONF_EJTAG_PROBE BIT(15)
134
135/* CPC_Cx_OTHER - Configure the core-other register block prior to CM 3 */
136CPC_CX_ACCESSOR_RW(32, 0x010, other)
137#define CPC_Cx_OTHER_CORENUM GENMASK(23, 16)
138
139/* CPC_Cx_VP_STOP - Stop Virtual Processors (VPs) within a core from running */
140CPC_CX_ACCESSOR_RW(32, 0x020, vp_stop)
141
142/* CPC_Cx_VP_START - Start Virtual Processors (VPs) within a core running */
143CPC_CX_ACCESSOR_RW(32, 0x028, vp_run)
144
145/* CPC_Cx_VP_RUNNING - Indicate which Virtual Processors (VPs) are running */
146CPC_CX_ACCESSOR_RW(32, 0x030, vp_running)
147
148/* CPC_Cx_CONFIG - Mirrors GCR_Cx_CONFIG */
149CPC_CX_ACCESSOR_RW(32, 0x090, config)
150
151#ifdef CONFIG_MIPS_CPC
152
153/**
154 * mips_cpc_lock_other - lock access to another core
155 * core: the other core to be accessed
156 *
157 * Call before operating upon a core via the 'other' register region in
158 * order to prevent the region being moved during access. Must be called
159 * within the bounds of a mips_cm_{lock,unlock}_other pair, and followed
160 * by a call to mips_cpc_unlock_other.
161 */
162extern void mips_cpc_lock_other(unsigned int core);
163
164/**
165 * mips_cpc_unlock_other - unlock access to another core
166 *
167 * Call after operating upon another core via the 'other' register region.
168 * Must be called after mips_cpc_lock_other.
169 */
170extern void mips_cpc_unlock_other(void);
171
172#else /* !CONFIG_MIPS_CPC */
173
174static inline void mips_cpc_lock_other(unsigned int core) { }
175static inline void mips_cpc_unlock_other(void) { }
176
177#endif /* !CONFIG_MIPS_CPC */
178
179#endif /* __MIPS_ASM_MIPS_CPC_H__ */