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1/*
2 * arch/arm/mach-orion5x/rd88f5182-setup.c
3 *
4 * Marvell Orion-NAS Reference Design Setup
5 *
6 * Maintainer: Ronen Shitrit <rshitrit@marvell.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12#include <linux/gpio.h>
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/platform_device.h>
16#include <linux/pci.h>
17#include <linux/irq.h>
18#include <linux/mtd/physmap.h>
19#include <linux/mv643xx_eth.h>
20#include <linux/ata_platform.h>
21#include <linux/i2c.h>
22#include <linux/leds.h>
23#include <asm/mach-types.h>
24#include <asm/mach/arch.h>
25#include <asm/mach/pci.h>
26#include "common.h"
27#include "mpp.h"
28#include "orion5x.h"
29
30/*****************************************************************************
31 * RD-88F5182 Info
32 ****************************************************************************/
33
34/*
35 * 512K NOR flash Device bus boot chip select
36 */
37
38#define RD88F5182_NOR_BOOT_BASE 0xf4000000
39#define RD88F5182_NOR_BOOT_SIZE SZ_512K
40
41/*
42 * 16M NOR flash on Device bus chip select 1
43 */
44
45#define RD88F5182_NOR_BASE 0xfc000000
46#define RD88F5182_NOR_SIZE SZ_16M
47
48/*
49 * PCI
50 */
51
52#define RD88F5182_PCI_SLOT0_OFFS 7
53#define RD88F5182_PCI_SLOT0_IRQ_A_PIN 7
54#define RD88F5182_PCI_SLOT0_IRQ_B_PIN 6
55
56/*****************************************************************************
57 * 16M NOR Flash on Device bus CS1
58 ****************************************************************************/
59
60static struct physmap_flash_data rd88f5182_nor_flash_data = {
61 .width = 1,
62};
63
64static struct resource rd88f5182_nor_flash_resource = {
65 .flags = IORESOURCE_MEM,
66 .start = RD88F5182_NOR_BASE,
67 .end = RD88F5182_NOR_BASE + RD88F5182_NOR_SIZE - 1,
68};
69
70static struct platform_device rd88f5182_nor_flash = {
71 .name = "physmap-flash",
72 .id = 0,
73 .dev = {
74 .platform_data = &rd88f5182_nor_flash_data,
75 },
76 .num_resources = 1,
77 .resource = &rd88f5182_nor_flash_resource,
78};
79
80/*****************************************************************************
81 * Use GPIO LED as CPU active indication
82 ****************************************************************************/
83
84#define RD88F5182_GPIO_LED 0
85
86static struct gpio_led rd88f5182_gpio_led_pins[] = {
87 {
88 .name = "rd88f5182:cpu",
89 .default_trigger = "cpu0",
90 .gpio = RD88F5182_GPIO_LED,
91 },
92};
93
94static struct gpio_led_platform_data rd88f5182_gpio_led_data = {
95 .leds = rd88f5182_gpio_led_pins,
96 .num_leds = ARRAY_SIZE(rd88f5182_gpio_led_pins),
97};
98
99static struct platform_device rd88f5182_gpio_leds = {
100 .name = "leds-gpio",
101 .id = -1,
102 .dev = {
103 .platform_data = &rd88f5182_gpio_led_data,
104 },
105};
106
107/*****************************************************************************
108 * PCI
109 ****************************************************************************/
110
111static void __init rd88f5182_pci_preinit(void)
112{
113 int pin;
114
115 /*
116 * Configure PCI GPIO IRQ pins
117 */
118 pin = RD88F5182_PCI_SLOT0_IRQ_A_PIN;
119 if (gpio_request(pin, "PCI IntA") == 0) {
120 if (gpio_direction_input(pin) == 0) {
121 irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
122 } else {
123 printk(KERN_ERR "rd88f5182_pci_preinit failed to "
124 "set_irq_type pin %d\n", pin);
125 gpio_free(pin);
126 }
127 } else {
128 printk(KERN_ERR "rd88f5182_pci_preinit failed to request gpio %d\n", pin);
129 }
130
131 pin = RD88F5182_PCI_SLOT0_IRQ_B_PIN;
132 if (gpio_request(pin, "PCI IntB") == 0) {
133 if (gpio_direction_input(pin) == 0) {
134 irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
135 } else {
136 printk(KERN_ERR "rd88f5182_pci_preinit failed to "
137 "set_irq_type pin %d\n", pin);
138 gpio_free(pin);
139 }
140 } else {
141 printk(KERN_ERR "rd88f5182_pci_preinit failed to gpio_request %d\n", pin);
142 }
143}
144
145static int __init rd88f5182_pci_map_irq(const struct pci_dev *dev, u8 slot,
146 u8 pin)
147{
148 int irq;
149
150 /*
151 * Check for devices with hard-wired IRQs.
152 */
153 irq = orion5x_pci_map_irq(dev, slot, pin);
154 if (irq != -1)
155 return irq;
156
157 /*
158 * PCI IRQs are connected via GPIOs
159 */
160 switch (slot - RD88F5182_PCI_SLOT0_OFFS) {
161 case 0:
162 if (pin == 1)
163 return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_A_PIN);
164 else
165 return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_B_PIN);
166 default:
167 return -1;
168 }
169}
170
171static struct hw_pci rd88f5182_pci __initdata = {
172 .nr_controllers = 2,
173 .preinit = rd88f5182_pci_preinit,
174 .setup = orion5x_pci_sys_setup,
175 .scan = orion5x_pci_sys_scan_bus,
176 .map_irq = rd88f5182_pci_map_irq,
177};
178
179static int __init rd88f5182_pci_init(void)
180{
181 if (machine_is_rd88f5182())
182 pci_common_init(&rd88f5182_pci);
183
184 return 0;
185}
186
187subsys_initcall(rd88f5182_pci_init);
188
189/*****************************************************************************
190 * Ethernet
191 ****************************************************************************/
192
193static struct mv643xx_eth_platform_data rd88f5182_eth_data = {
194 .phy_addr = MV643XX_ETH_PHY_ADDR(8),
195};
196
197/*****************************************************************************
198 * RTC DS1338 on I2C bus
199 ****************************************************************************/
200static struct i2c_board_info __initdata rd88f5182_i2c_rtc = {
201 I2C_BOARD_INFO("ds1338", 0x68),
202};
203
204/*****************************************************************************
205 * Sata
206 ****************************************************************************/
207static struct mv_sata_platform_data rd88f5182_sata_data = {
208 .n_ports = 2,
209};
210
211/*****************************************************************************
212 * General Setup
213 ****************************************************************************/
214static unsigned int rd88f5182_mpp_modes[] __initdata = {
215 MPP0_GPIO, /* Debug Led */
216 MPP1_GPIO, /* Reset Switch */
217 MPP2_UNUSED,
218 MPP3_GPIO, /* RTC Int */
219 MPP4_GPIO,
220 MPP5_GPIO,
221 MPP6_GPIO, /* PCI_intA */
222 MPP7_GPIO, /* PCI_intB */
223 MPP8_UNUSED,
224 MPP9_UNUSED,
225 MPP10_UNUSED,
226 MPP11_UNUSED,
227 MPP12_SATA_LED, /* SATA 0 presence */
228 MPP13_SATA_LED, /* SATA 1 presence */
229 MPP14_SATA_LED, /* SATA 0 active */
230 MPP15_SATA_LED, /* SATA 1 active */
231 MPP16_UNUSED,
232 MPP17_UNUSED,
233 MPP18_UNUSED,
234 MPP19_UNUSED,
235 0,
236};
237
238static void __init rd88f5182_init(void)
239{
240 /*
241 * Setup basic Orion functions. Need to be called early.
242 */
243 orion5x_init();
244
245 orion5x_mpp_conf(rd88f5182_mpp_modes);
246
247 /*
248 * MPP[20] PCI Clock to MV88F5182
249 * MPP[21] PCI Clock to mini PCI CON11
250 * MPP[22] USB 0 over current indication
251 * MPP[23] USB 1 over current indication
252 * MPP[24] USB 1 over current enable
253 * MPP[25] USB 0 over current enable
254 */
255
256 /*
257 * Configure peripherals.
258 */
259 orion5x_ehci0_init();
260 orion5x_ehci1_init();
261 orion5x_eth_init(&rd88f5182_eth_data);
262 orion5x_i2c_init();
263 orion5x_sata_init(&rd88f5182_sata_data);
264 orion5x_uart0_init();
265 orion5x_xor_init();
266
267 mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
268 ORION_MBUS_DEVBUS_BOOT_ATTR,
269 RD88F5182_NOR_BOOT_BASE,
270 RD88F5182_NOR_BOOT_SIZE);
271 mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(1),
272 ORION_MBUS_DEVBUS_ATTR(1),
273 RD88F5182_NOR_BASE,
274 RD88F5182_NOR_SIZE);
275 platform_device_register(&rd88f5182_nor_flash);
276 platform_device_register(&rd88f5182_gpio_leds);
277
278 i2c_register_board_info(0, &rd88f5182_i2c_rtc, 1);
279}
280
281MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design")
282 /* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */
283 .atag_offset = 0x100,
284 .nr_irqs = ORION5X_NR_IRQS,
285 .init_machine = rd88f5182_init,
286 .map_io = orion5x_map_io,
287 .init_early = orion5x_init_early,
288 .init_irq = orion5x_init_irq,
289 .init_time = orion5x_timer_init,
290 .restart = orion5x_restart,
291MACHINE_END
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * arch/arm/mach-orion5x/rd88f5182-setup.c
4 *
5 * Marvell Orion-NAS Reference Design Setup
6 *
7 * Maintainer: Ronen Shitrit <rshitrit@marvell.com>
8 */
9#include <linux/gpio.h>
10#include <linux/kernel.h>
11#include <linux/init.h>
12#include <linux/platform_device.h>
13#include <linux/pci.h>
14#include <linux/irq.h>
15#include <linux/mtd/physmap.h>
16#include <linux/mv643xx_eth.h>
17#include <linux/ata_platform.h>
18#include <linux/i2c.h>
19#include <linux/leds.h>
20#include <asm/mach-types.h>
21#include <asm/mach/arch.h>
22#include <asm/mach/pci.h>
23#include "common.h"
24#include "mpp.h"
25#include "orion5x.h"
26
27/*****************************************************************************
28 * RD-88F5182 Info
29 ****************************************************************************/
30
31/*
32 * 512K NOR flash Device bus boot chip select
33 */
34
35#define RD88F5182_NOR_BOOT_BASE 0xf4000000
36#define RD88F5182_NOR_BOOT_SIZE SZ_512K
37
38/*
39 * 16M NOR flash on Device bus chip select 1
40 */
41
42#define RD88F5182_NOR_BASE 0xfc000000
43#define RD88F5182_NOR_SIZE SZ_16M
44
45/*
46 * PCI
47 */
48
49#define RD88F5182_PCI_SLOT0_OFFS 7
50#define RD88F5182_PCI_SLOT0_IRQ_A_PIN 7
51#define RD88F5182_PCI_SLOT0_IRQ_B_PIN 6
52
53/*****************************************************************************
54 * 16M NOR Flash on Device bus CS1
55 ****************************************************************************/
56
57static struct physmap_flash_data rd88f5182_nor_flash_data = {
58 .width = 1,
59};
60
61static struct resource rd88f5182_nor_flash_resource = {
62 .flags = IORESOURCE_MEM,
63 .start = RD88F5182_NOR_BASE,
64 .end = RD88F5182_NOR_BASE + RD88F5182_NOR_SIZE - 1,
65};
66
67static struct platform_device rd88f5182_nor_flash = {
68 .name = "physmap-flash",
69 .id = 0,
70 .dev = {
71 .platform_data = &rd88f5182_nor_flash_data,
72 },
73 .num_resources = 1,
74 .resource = &rd88f5182_nor_flash_resource,
75};
76
77/*****************************************************************************
78 * Use GPIO LED as CPU active indication
79 ****************************************************************************/
80
81#define RD88F5182_GPIO_LED 0
82
83static struct gpio_led rd88f5182_gpio_led_pins[] = {
84 {
85 .name = "rd88f5182:cpu",
86 .default_trigger = "cpu0",
87 .gpio = RD88F5182_GPIO_LED,
88 },
89};
90
91static struct gpio_led_platform_data rd88f5182_gpio_led_data = {
92 .leds = rd88f5182_gpio_led_pins,
93 .num_leds = ARRAY_SIZE(rd88f5182_gpio_led_pins),
94};
95
96static struct platform_device rd88f5182_gpio_leds = {
97 .name = "leds-gpio",
98 .id = -1,
99 .dev = {
100 .platform_data = &rd88f5182_gpio_led_data,
101 },
102};
103
104/*****************************************************************************
105 * PCI
106 ****************************************************************************/
107
108static void __init rd88f5182_pci_preinit(void)
109{
110 int pin;
111
112 /*
113 * Configure PCI GPIO IRQ pins
114 */
115 pin = RD88F5182_PCI_SLOT0_IRQ_A_PIN;
116 if (gpio_request(pin, "PCI IntA") == 0) {
117 if (gpio_direction_input(pin) == 0) {
118 irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
119 } else {
120 printk(KERN_ERR "rd88f5182_pci_preinit failed to "
121 "set_irq_type pin %d\n", pin);
122 gpio_free(pin);
123 }
124 } else {
125 printk(KERN_ERR "rd88f5182_pci_preinit failed to request gpio %d\n", pin);
126 }
127
128 pin = RD88F5182_PCI_SLOT0_IRQ_B_PIN;
129 if (gpio_request(pin, "PCI IntB") == 0) {
130 if (gpio_direction_input(pin) == 0) {
131 irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
132 } else {
133 printk(KERN_ERR "rd88f5182_pci_preinit failed to "
134 "set_irq_type pin %d\n", pin);
135 gpio_free(pin);
136 }
137 } else {
138 printk(KERN_ERR "rd88f5182_pci_preinit failed to gpio_request %d\n", pin);
139 }
140}
141
142static int __init rd88f5182_pci_map_irq(const struct pci_dev *dev, u8 slot,
143 u8 pin)
144{
145 int irq;
146
147 /*
148 * Check for devices with hard-wired IRQs.
149 */
150 irq = orion5x_pci_map_irq(dev, slot, pin);
151 if (irq != -1)
152 return irq;
153
154 /*
155 * PCI IRQs are connected via GPIOs
156 */
157 switch (slot - RD88F5182_PCI_SLOT0_OFFS) {
158 case 0:
159 if (pin == 1)
160 return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_A_PIN);
161 else
162 return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_B_PIN);
163 default:
164 return -1;
165 }
166}
167
168static struct hw_pci rd88f5182_pci __initdata = {
169 .nr_controllers = 2,
170 .preinit = rd88f5182_pci_preinit,
171 .setup = orion5x_pci_sys_setup,
172 .scan = orion5x_pci_sys_scan_bus,
173 .map_irq = rd88f5182_pci_map_irq,
174};
175
176static int __init rd88f5182_pci_init(void)
177{
178 if (machine_is_rd88f5182())
179 pci_common_init(&rd88f5182_pci);
180
181 return 0;
182}
183
184subsys_initcall(rd88f5182_pci_init);
185
186/*****************************************************************************
187 * Ethernet
188 ****************************************************************************/
189
190static struct mv643xx_eth_platform_data rd88f5182_eth_data = {
191 .phy_addr = MV643XX_ETH_PHY_ADDR(8),
192};
193
194/*****************************************************************************
195 * RTC DS1338 on I2C bus
196 ****************************************************************************/
197static struct i2c_board_info __initdata rd88f5182_i2c_rtc = {
198 I2C_BOARD_INFO("ds1338", 0x68),
199};
200
201/*****************************************************************************
202 * Sata
203 ****************************************************************************/
204static struct mv_sata_platform_data rd88f5182_sata_data = {
205 .n_ports = 2,
206};
207
208/*****************************************************************************
209 * General Setup
210 ****************************************************************************/
211static unsigned int rd88f5182_mpp_modes[] __initdata = {
212 MPP0_GPIO, /* Debug Led */
213 MPP1_GPIO, /* Reset Switch */
214 MPP2_UNUSED,
215 MPP3_GPIO, /* RTC Int */
216 MPP4_GPIO,
217 MPP5_GPIO,
218 MPP6_GPIO, /* PCI_intA */
219 MPP7_GPIO, /* PCI_intB */
220 MPP8_UNUSED,
221 MPP9_UNUSED,
222 MPP10_UNUSED,
223 MPP11_UNUSED,
224 MPP12_SATA_LED, /* SATA 0 presence */
225 MPP13_SATA_LED, /* SATA 1 presence */
226 MPP14_SATA_LED, /* SATA 0 active */
227 MPP15_SATA_LED, /* SATA 1 active */
228 MPP16_UNUSED,
229 MPP17_UNUSED,
230 MPP18_UNUSED,
231 MPP19_UNUSED,
232 0,
233};
234
235static void __init rd88f5182_init(void)
236{
237 /*
238 * Setup basic Orion functions. Need to be called early.
239 */
240 orion5x_init();
241
242 orion5x_mpp_conf(rd88f5182_mpp_modes);
243
244 /*
245 * MPP[20] PCI Clock to MV88F5182
246 * MPP[21] PCI Clock to mini PCI CON11
247 * MPP[22] USB 0 over current indication
248 * MPP[23] USB 1 over current indication
249 * MPP[24] USB 1 over current enable
250 * MPP[25] USB 0 over current enable
251 */
252
253 /*
254 * Configure peripherals.
255 */
256 orion5x_ehci0_init();
257 orion5x_ehci1_init();
258 orion5x_eth_init(&rd88f5182_eth_data);
259 orion5x_i2c_init();
260 orion5x_sata_init(&rd88f5182_sata_data);
261 orion5x_uart0_init();
262 orion5x_xor_init();
263
264 mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
265 ORION_MBUS_DEVBUS_BOOT_ATTR,
266 RD88F5182_NOR_BOOT_BASE,
267 RD88F5182_NOR_BOOT_SIZE);
268 mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(1),
269 ORION_MBUS_DEVBUS_ATTR(1),
270 RD88F5182_NOR_BASE,
271 RD88F5182_NOR_SIZE);
272 platform_device_register(&rd88f5182_nor_flash);
273 platform_device_register(&rd88f5182_gpio_leds);
274
275 i2c_register_board_info(0, &rd88f5182_i2c_rtc, 1);
276}
277
278MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design")
279 /* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */
280 .atag_offset = 0x100,
281 .nr_irqs = ORION5X_NR_IRQS,
282 .init_machine = rd88f5182_init,
283 .map_io = orion5x_map_io,
284 .init_early = orion5x_init_early,
285 .init_irq = orion5x_init_irq,
286 .init_time = orion5x_timer_init,
287 .restart = orion5x_restart,
288MACHINE_END