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1/*
2* Copyright (c) 2014-2015 MediaTek Inc.
3* Author: Tianping.Fang <tianping.fang@mediatek.com>
4*
5* This program is free software; you can redistribute it and/or modify
6* it under the terms of the GNU General Public License version 2 as
7* published by the Free Software Foundation.
8*
9* This program is distributed in the hope that it will be useful,
10* but WITHOUT ANY WARRANTY; without even the implied warranty of
11* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12* GNU General Public License for more details.
13*/
14
15#include <linux/delay.h>
16#include <linux/init.h>
17#include <linux/module.h>
18#include <linux/regmap.h>
19#include <linux/rtc.h>
20#include <linux/irqdomain.h>
21#include <linux/platform_device.h>
22#include <linux/of_address.h>
23#include <linux/of_irq.h>
24#include <linux/io.h>
25#include <linux/mfd/mt6397/core.h>
26
27#define RTC_BBPU 0x0000
28#define RTC_BBPU_CBUSY BIT(6)
29
30#define RTC_WRTGR 0x003c
31
32#define RTC_IRQ_STA 0x0002
33#define RTC_IRQ_STA_AL BIT(0)
34#define RTC_IRQ_STA_LP BIT(3)
35
36#define RTC_IRQ_EN 0x0004
37#define RTC_IRQ_EN_AL BIT(0)
38#define RTC_IRQ_EN_ONESHOT BIT(2)
39#define RTC_IRQ_EN_LP BIT(3)
40#define RTC_IRQ_EN_ONESHOT_AL (RTC_IRQ_EN_ONESHOT | RTC_IRQ_EN_AL)
41
42#define RTC_AL_MASK 0x0008
43#define RTC_AL_MASK_DOW BIT(4)
44
45#define RTC_TC_SEC 0x000a
46/* Min, Hour, Dom... register offset to RTC_TC_SEC */
47#define RTC_OFFSET_SEC 0
48#define RTC_OFFSET_MIN 1
49#define RTC_OFFSET_HOUR 2
50#define RTC_OFFSET_DOM 3
51#define RTC_OFFSET_DOW 4
52#define RTC_OFFSET_MTH 5
53#define RTC_OFFSET_YEAR 6
54#define RTC_OFFSET_COUNT 7
55
56#define RTC_AL_SEC 0x0018
57
58#define RTC_PDN2 0x002e
59#define RTC_PDN2_PWRON_ALARM BIT(4)
60
61#define RTC_MIN_YEAR 1968
62#define RTC_BASE_YEAR 1900
63#define RTC_NUM_YEARS 128
64#define RTC_MIN_YEAR_OFFSET (RTC_MIN_YEAR - RTC_BASE_YEAR)
65
66struct mt6397_rtc {
67 struct device *dev;
68 struct rtc_device *rtc_dev;
69 struct mutex lock;
70 struct regmap *regmap;
71 int irq;
72 u32 addr_base;
73};
74
75static int mtk_rtc_write_trigger(struct mt6397_rtc *rtc)
76{
77 unsigned long timeout = jiffies + HZ;
78 int ret;
79 u32 data;
80
81 ret = regmap_write(rtc->regmap, rtc->addr_base + RTC_WRTGR, 1);
82 if (ret < 0)
83 return ret;
84
85 while (1) {
86 ret = regmap_read(rtc->regmap, rtc->addr_base + RTC_BBPU,
87 &data);
88 if (ret < 0)
89 break;
90 if (!(data & RTC_BBPU_CBUSY))
91 break;
92 if (time_after(jiffies, timeout)) {
93 ret = -ETIMEDOUT;
94 break;
95 }
96 cpu_relax();
97 }
98
99 return ret;
100}
101
102static irqreturn_t mtk_rtc_irq_handler_thread(int irq, void *data)
103{
104 struct mt6397_rtc *rtc = data;
105 u32 irqsta, irqen;
106 int ret;
107
108 ret = regmap_read(rtc->regmap, rtc->addr_base + RTC_IRQ_STA, &irqsta);
109 if ((ret >= 0) && (irqsta & RTC_IRQ_STA_AL)) {
110 rtc_update_irq(rtc->rtc_dev, 1, RTC_IRQF | RTC_AF);
111 irqen = irqsta & ~RTC_IRQ_EN_AL;
112 mutex_lock(&rtc->lock);
113 if (regmap_write(rtc->regmap, rtc->addr_base + RTC_IRQ_EN,
114 irqen) < 0)
115 mtk_rtc_write_trigger(rtc);
116 mutex_unlock(&rtc->lock);
117
118 return IRQ_HANDLED;
119 }
120
121 return IRQ_NONE;
122}
123
124static int __mtk_rtc_read_time(struct mt6397_rtc *rtc,
125 struct rtc_time *tm, int *sec)
126{
127 int ret;
128 u16 data[RTC_OFFSET_COUNT];
129
130 mutex_lock(&rtc->lock);
131 ret = regmap_bulk_read(rtc->regmap, rtc->addr_base + RTC_TC_SEC,
132 data, RTC_OFFSET_COUNT);
133 if (ret < 0)
134 goto exit;
135
136 tm->tm_sec = data[RTC_OFFSET_SEC];
137 tm->tm_min = data[RTC_OFFSET_MIN];
138 tm->tm_hour = data[RTC_OFFSET_HOUR];
139 tm->tm_mday = data[RTC_OFFSET_DOM];
140 tm->tm_mon = data[RTC_OFFSET_MTH];
141 tm->tm_year = data[RTC_OFFSET_YEAR];
142
143 ret = regmap_read(rtc->regmap, rtc->addr_base + RTC_TC_SEC, sec);
144exit:
145 mutex_unlock(&rtc->lock);
146 return ret;
147}
148
149static int mtk_rtc_read_time(struct device *dev, struct rtc_time *tm)
150{
151 time64_t time;
152 struct mt6397_rtc *rtc = dev_get_drvdata(dev);
153 int days, sec, ret;
154
155 do {
156 ret = __mtk_rtc_read_time(rtc, tm, &sec);
157 if (ret < 0)
158 goto exit;
159 } while (sec < tm->tm_sec);
160
161 /* HW register use 7 bits to store year data, minus
162 * RTC_MIN_YEAR_OFFSET before write year data to register, and plus
163 * RTC_MIN_YEAR_OFFSET back after read year from register
164 */
165 tm->tm_year += RTC_MIN_YEAR_OFFSET;
166
167 /* HW register start mon from one, but tm_mon start from zero. */
168 tm->tm_mon--;
169 time = rtc_tm_to_time64(tm);
170
171 /* rtc_tm_to_time64 covert Gregorian date to seconds since
172 * 01-01-1970 00:00:00, and this date is Thursday.
173 */
174 days = div_s64(time, 86400);
175 tm->tm_wday = (days + 4) % 7;
176
177exit:
178 return ret;
179}
180
181static int mtk_rtc_set_time(struct device *dev, struct rtc_time *tm)
182{
183 struct mt6397_rtc *rtc = dev_get_drvdata(dev);
184 int ret;
185 u16 data[RTC_OFFSET_COUNT];
186
187 tm->tm_year -= RTC_MIN_YEAR_OFFSET;
188 tm->tm_mon++;
189
190 data[RTC_OFFSET_SEC] = tm->tm_sec;
191 data[RTC_OFFSET_MIN] = tm->tm_min;
192 data[RTC_OFFSET_HOUR] = tm->tm_hour;
193 data[RTC_OFFSET_DOM] = tm->tm_mday;
194 data[RTC_OFFSET_MTH] = tm->tm_mon;
195 data[RTC_OFFSET_YEAR] = tm->tm_year;
196
197 mutex_lock(&rtc->lock);
198 ret = regmap_bulk_write(rtc->regmap, rtc->addr_base + RTC_TC_SEC,
199 data, RTC_OFFSET_COUNT);
200 if (ret < 0)
201 goto exit;
202
203 /* Time register write to hardware after call trigger function */
204 ret = mtk_rtc_write_trigger(rtc);
205
206exit:
207 mutex_unlock(&rtc->lock);
208 return ret;
209}
210
211static int mtk_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
212{
213 struct rtc_time *tm = &alm->time;
214 struct mt6397_rtc *rtc = dev_get_drvdata(dev);
215 u32 irqen, pdn2;
216 int ret;
217 u16 data[RTC_OFFSET_COUNT];
218
219 mutex_lock(&rtc->lock);
220 ret = regmap_read(rtc->regmap, rtc->addr_base + RTC_IRQ_EN, &irqen);
221 if (ret < 0)
222 goto err_exit;
223 ret = regmap_read(rtc->regmap, rtc->addr_base + RTC_PDN2, &pdn2);
224 if (ret < 0)
225 goto err_exit;
226
227 ret = regmap_bulk_read(rtc->regmap, rtc->addr_base + RTC_AL_SEC,
228 data, RTC_OFFSET_COUNT);
229 if (ret < 0)
230 goto err_exit;
231
232 alm->enabled = !!(irqen & RTC_IRQ_EN_AL);
233 alm->pending = !!(pdn2 & RTC_PDN2_PWRON_ALARM);
234 mutex_unlock(&rtc->lock);
235
236 tm->tm_sec = data[RTC_OFFSET_SEC];
237 tm->tm_min = data[RTC_OFFSET_MIN];
238 tm->tm_hour = data[RTC_OFFSET_HOUR];
239 tm->tm_mday = data[RTC_OFFSET_DOM];
240 tm->tm_mon = data[RTC_OFFSET_MTH];
241 tm->tm_year = data[RTC_OFFSET_YEAR];
242
243 tm->tm_year += RTC_MIN_YEAR_OFFSET;
244 tm->tm_mon--;
245
246 return 0;
247err_exit:
248 mutex_unlock(&rtc->lock);
249 return ret;
250}
251
252static int mtk_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
253{
254 struct rtc_time *tm = &alm->time;
255 struct mt6397_rtc *rtc = dev_get_drvdata(dev);
256 int ret;
257 u16 data[RTC_OFFSET_COUNT];
258
259 tm->tm_year -= RTC_MIN_YEAR_OFFSET;
260 tm->tm_mon++;
261
262 data[RTC_OFFSET_SEC] = tm->tm_sec;
263 data[RTC_OFFSET_MIN] = tm->tm_min;
264 data[RTC_OFFSET_HOUR] = tm->tm_hour;
265 data[RTC_OFFSET_DOM] = tm->tm_mday;
266 data[RTC_OFFSET_MTH] = tm->tm_mon;
267 data[RTC_OFFSET_YEAR] = tm->tm_year;
268
269 mutex_lock(&rtc->lock);
270 if (alm->enabled) {
271 ret = regmap_bulk_write(rtc->regmap,
272 rtc->addr_base + RTC_AL_SEC,
273 data, RTC_OFFSET_COUNT);
274 if (ret < 0)
275 goto exit;
276 ret = regmap_write(rtc->regmap, rtc->addr_base + RTC_AL_MASK,
277 RTC_AL_MASK_DOW);
278 if (ret < 0)
279 goto exit;
280 ret = regmap_update_bits(rtc->regmap,
281 rtc->addr_base + RTC_IRQ_EN,
282 RTC_IRQ_EN_ONESHOT_AL,
283 RTC_IRQ_EN_ONESHOT_AL);
284 if (ret < 0)
285 goto exit;
286 } else {
287 ret = regmap_update_bits(rtc->regmap,
288 rtc->addr_base + RTC_IRQ_EN,
289 RTC_IRQ_EN_ONESHOT_AL, 0);
290 if (ret < 0)
291 goto exit;
292 }
293
294 /* All alarm time register write to hardware after calling
295 * mtk_rtc_write_trigger. This can avoid race condition if alarm
296 * occur happen during writing alarm time register.
297 */
298 ret = mtk_rtc_write_trigger(rtc);
299exit:
300 mutex_unlock(&rtc->lock);
301 return ret;
302}
303
304static struct rtc_class_ops mtk_rtc_ops = {
305 .read_time = mtk_rtc_read_time,
306 .set_time = mtk_rtc_set_time,
307 .read_alarm = mtk_rtc_read_alarm,
308 .set_alarm = mtk_rtc_set_alarm,
309};
310
311static int mtk_rtc_probe(struct platform_device *pdev)
312{
313 struct resource *res;
314 struct mt6397_chip *mt6397_chip = dev_get_drvdata(pdev->dev.parent);
315 struct mt6397_rtc *rtc;
316 int ret;
317
318 rtc = devm_kzalloc(&pdev->dev, sizeof(struct mt6397_rtc), GFP_KERNEL);
319 if (!rtc)
320 return -ENOMEM;
321
322 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
323 rtc->addr_base = res->start;
324
325 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
326 rtc->irq = irq_create_mapping(mt6397_chip->irq_domain, res->start);
327 if (rtc->irq <= 0)
328 return -EINVAL;
329
330 rtc->regmap = mt6397_chip->regmap;
331 rtc->dev = &pdev->dev;
332 mutex_init(&rtc->lock);
333
334 platform_set_drvdata(pdev, rtc);
335
336 ret = request_threaded_irq(rtc->irq, NULL,
337 mtk_rtc_irq_handler_thread,
338 IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
339 "mt6397-rtc", rtc);
340 if (ret) {
341 dev_err(&pdev->dev, "Failed to request alarm IRQ: %d: %d\n",
342 rtc->irq, ret);
343 goto out_dispose_irq;
344 }
345
346 device_init_wakeup(&pdev->dev, 1);
347
348 rtc->rtc_dev = rtc_device_register("mt6397-rtc", &pdev->dev,
349 &mtk_rtc_ops, THIS_MODULE);
350 if (IS_ERR(rtc->rtc_dev)) {
351 dev_err(&pdev->dev, "register rtc device failed\n");
352 ret = PTR_ERR(rtc->rtc_dev);
353 goto out_free_irq;
354 }
355
356 return 0;
357
358out_free_irq:
359 free_irq(rtc->irq, rtc->rtc_dev);
360out_dispose_irq:
361 irq_dispose_mapping(rtc->irq);
362 return ret;
363}
364
365static int mtk_rtc_remove(struct platform_device *pdev)
366{
367 struct mt6397_rtc *rtc = platform_get_drvdata(pdev);
368
369 rtc_device_unregister(rtc->rtc_dev);
370 free_irq(rtc->irq, rtc->rtc_dev);
371 irq_dispose_mapping(rtc->irq);
372
373 return 0;
374}
375
376#ifdef CONFIG_PM_SLEEP
377static int mt6397_rtc_suspend(struct device *dev)
378{
379 struct mt6397_rtc *rtc = dev_get_drvdata(dev);
380
381 if (device_may_wakeup(dev))
382 enable_irq_wake(rtc->irq);
383
384 return 0;
385}
386
387static int mt6397_rtc_resume(struct device *dev)
388{
389 struct mt6397_rtc *rtc = dev_get_drvdata(dev);
390
391 if (device_may_wakeup(dev))
392 disable_irq_wake(rtc->irq);
393
394 return 0;
395}
396#endif
397
398static SIMPLE_DEV_PM_OPS(mt6397_pm_ops, mt6397_rtc_suspend,
399 mt6397_rtc_resume);
400
401static const struct of_device_id mt6397_rtc_of_match[] = {
402 { .compatible = "mediatek,mt6397-rtc", },
403 { }
404};
405MODULE_DEVICE_TABLE(of, mt6397_rtc_of_match);
406
407static struct platform_driver mtk_rtc_driver = {
408 .driver = {
409 .name = "mt6397-rtc",
410 .of_match_table = mt6397_rtc_of_match,
411 .pm = &mt6397_pm_ops,
412 },
413 .probe = mtk_rtc_probe,
414 .remove = mtk_rtc_remove,
415};
416
417module_platform_driver(mtk_rtc_driver);
418
419MODULE_LICENSE("GPL v2");
420MODULE_AUTHOR("Tianping Fang <tianping.fang@mediatek.com>");
421MODULE_DESCRIPTION("RTC Driver for MediaTek MT6397 PMIC");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3* Copyright (c) 2014-2015 MediaTek Inc.
4* Author: Tianping.Fang <tianping.fang@mediatek.com>
5*/
6
7#include <linux/err.h>
8#include <linux/interrupt.h>
9#include <linux/mfd/mt6397/core.h>
10#include <linux/module.h>
11#include <linux/mutex.h>
12#include <linux/of_device.h>
13#include <linux/platform_device.h>
14#include <linux/regmap.h>
15#include <linux/rtc.h>
16#include <linux/mfd/mt6397/rtc.h>
17#include <linux/mod_devicetable.h>
18
19static int mtk_rtc_write_trigger(struct mt6397_rtc *rtc)
20{
21 int ret;
22 u32 data;
23
24 ret = regmap_write(rtc->regmap, rtc->addr_base + rtc->data->wrtgr, 1);
25 if (ret < 0)
26 return ret;
27
28 ret = regmap_read_poll_timeout(rtc->regmap,
29 rtc->addr_base + RTC_BBPU, data,
30 !(data & RTC_BBPU_CBUSY),
31 MTK_RTC_POLL_DELAY_US,
32 MTK_RTC_POLL_TIMEOUT);
33 if (ret < 0)
34 dev_err(rtc->rtc_dev->dev.parent,
35 "failed to write WRTGR: %d\n", ret);
36
37 return ret;
38}
39
40static irqreturn_t mtk_rtc_irq_handler_thread(int irq, void *data)
41{
42 struct mt6397_rtc *rtc = data;
43 u32 irqsta, irqen;
44 int ret;
45
46 ret = regmap_read(rtc->regmap, rtc->addr_base + RTC_IRQ_STA, &irqsta);
47 if ((ret >= 0) && (irqsta & RTC_IRQ_STA_AL)) {
48 rtc_update_irq(rtc->rtc_dev, 1, RTC_IRQF | RTC_AF);
49 irqen = irqsta & ~RTC_IRQ_EN_AL;
50 mutex_lock(&rtc->lock);
51 if (regmap_write(rtc->regmap, rtc->addr_base + RTC_IRQ_EN,
52 irqen) == 0)
53 mtk_rtc_write_trigger(rtc);
54 mutex_unlock(&rtc->lock);
55
56 return IRQ_HANDLED;
57 }
58
59 return IRQ_NONE;
60}
61
62static int __mtk_rtc_read_time(struct mt6397_rtc *rtc,
63 struct rtc_time *tm, int *sec)
64{
65 int ret;
66 u16 data[RTC_OFFSET_COUNT];
67
68 mutex_lock(&rtc->lock);
69 ret = regmap_bulk_read(rtc->regmap, rtc->addr_base + RTC_TC_SEC,
70 data, RTC_OFFSET_COUNT);
71 if (ret < 0)
72 goto exit;
73
74 tm->tm_sec = data[RTC_OFFSET_SEC];
75 tm->tm_min = data[RTC_OFFSET_MIN];
76 tm->tm_hour = data[RTC_OFFSET_HOUR];
77 tm->tm_mday = data[RTC_OFFSET_DOM];
78 tm->tm_mon = data[RTC_OFFSET_MTH] & RTC_TC_MTH_MASK;
79 tm->tm_year = data[RTC_OFFSET_YEAR];
80
81 ret = regmap_read(rtc->regmap, rtc->addr_base + RTC_TC_SEC, sec);
82exit:
83 mutex_unlock(&rtc->lock);
84 return ret;
85}
86
87static int mtk_rtc_read_time(struct device *dev, struct rtc_time *tm)
88{
89 time64_t time;
90 struct mt6397_rtc *rtc = dev_get_drvdata(dev);
91 int days, sec, ret;
92
93 do {
94 ret = __mtk_rtc_read_time(rtc, tm, &sec);
95 if (ret < 0)
96 goto exit;
97 } while (sec < tm->tm_sec);
98
99 /* HW register use 7 bits to store year data, minus
100 * RTC_MIN_YEAR_OFFSET before write year data to register, and plus
101 * RTC_MIN_YEAR_OFFSET back after read year from register
102 */
103 tm->tm_year += RTC_MIN_YEAR_OFFSET;
104
105 /* HW register start mon from one, but tm_mon start from zero. */
106 tm->tm_mon--;
107 time = rtc_tm_to_time64(tm);
108
109 /* rtc_tm_to_time64 covert Gregorian date to seconds since
110 * 01-01-1970 00:00:00, and this date is Thursday.
111 */
112 days = div_s64(time, 86400);
113 tm->tm_wday = (days + 4) % 7;
114
115exit:
116 return ret;
117}
118
119static int mtk_rtc_set_time(struct device *dev, struct rtc_time *tm)
120{
121 struct mt6397_rtc *rtc = dev_get_drvdata(dev);
122 int ret;
123 u16 data[RTC_OFFSET_COUNT];
124
125 tm->tm_year -= RTC_MIN_YEAR_OFFSET;
126 tm->tm_mon++;
127
128 data[RTC_OFFSET_SEC] = tm->tm_sec;
129 data[RTC_OFFSET_MIN] = tm->tm_min;
130 data[RTC_OFFSET_HOUR] = tm->tm_hour;
131 data[RTC_OFFSET_DOM] = tm->tm_mday;
132 data[RTC_OFFSET_MTH] = tm->tm_mon;
133 data[RTC_OFFSET_YEAR] = tm->tm_year;
134
135 mutex_lock(&rtc->lock);
136 ret = regmap_bulk_write(rtc->regmap, rtc->addr_base + RTC_TC_SEC,
137 data, RTC_OFFSET_COUNT);
138 if (ret < 0)
139 goto exit;
140
141 /* Time register write to hardware after call trigger function */
142 ret = mtk_rtc_write_trigger(rtc);
143
144exit:
145 mutex_unlock(&rtc->lock);
146 return ret;
147}
148
149static int mtk_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
150{
151 struct rtc_time *tm = &alm->time;
152 struct mt6397_rtc *rtc = dev_get_drvdata(dev);
153 u32 irqen, pdn2;
154 int ret;
155 u16 data[RTC_OFFSET_COUNT];
156
157 mutex_lock(&rtc->lock);
158 ret = regmap_read(rtc->regmap, rtc->addr_base + RTC_IRQ_EN, &irqen);
159 if (ret < 0)
160 goto err_exit;
161 ret = regmap_read(rtc->regmap, rtc->addr_base + RTC_PDN2, &pdn2);
162 if (ret < 0)
163 goto err_exit;
164
165 ret = regmap_bulk_read(rtc->regmap, rtc->addr_base + RTC_AL_SEC,
166 data, RTC_OFFSET_COUNT);
167 if (ret < 0)
168 goto err_exit;
169
170 alm->enabled = !!(irqen & RTC_IRQ_EN_AL);
171 alm->pending = !!(pdn2 & RTC_PDN2_PWRON_ALARM);
172 mutex_unlock(&rtc->lock);
173
174 tm->tm_sec = data[RTC_OFFSET_SEC] & RTC_AL_SEC_MASK;
175 tm->tm_min = data[RTC_OFFSET_MIN] & RTC_AL_MIN_MASK;
176 tm->tm_hour = data[RTC_OFFSET_HOUR] & RTC_AL_HOU_MASK;
177 tm->tm_mday = data[RTC_OFFSET_DOM] & RTC_AL_DOM_MASK;
178 tm->tm_mon = data[RTC_OFFSET_MTH] & RTC_AL_MTH_MASK;
179 tm->tm_year = data[RTC_OFFSET_YEAR] & RTC_AL_YEA_MASK;
180
181 tm->tm_year += RTC_MIN_YEAR_OFFSET;
182 tm->tm_mon--;
183
184 return 0;
185err_exit:
186 mutex_unlock(&rtc->lock);
187 return ret;
188}
189
190static int mtk_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
191{
192 struct rtc_time *tm = &alm->time;
193 struct mt6397_rtc *rtc = dev_get_drvdata(dev);
194 int ret;
195 u16 data[RTC_OFFSET_COUNT];
196
197 tm->tm_year -= RTC_MIN_YEAR_OFFSET;
198 tm->tm_mon++;
199
200 mutex_lock(&rtc->lock);
201 ret = regmap_bulk_read(rtc->regmap, rtc->addr_base + RTC_AL_SEC,
202 data, RTC_OFFSET_COUNT);
203 if (ret < 0)
204 goto exit;
205
206 data[RTC_OFFSET_SEC] = ((data[RTC_OFFSET_SEC] & ~(RTC_AL_SEC_MASK)) |
207 (tm->tm_sec & RTC_AL_SEC_MASK));
208 data[RTC_OFFSET_MIN] = ((data[RTC_OFFSET_MIN] & ~(RTC_AL_MIN_MASK)) |
209 (tm->tm_min & RTC_AL_MIN_MASK));
210 data[RTC_OFFSET_HOUR] = ((data[RTC_OFFSET_HOUR] & ~(RTC_AL_HOU_MASK)) |
211 (tm->tm_hour & RTC_AL_HOU_MASK));
212 data[RTC_OFFSET_DOM] = ((data[RTC_OFFSET_DOM] & ~(RTC_AL_DOM_MASK)) |
213 (tm->tm_mday & RTC_AL_DOM_MASK));
214 data[RTC_OFFSET_MTH] = ((data[RTC_OFFSET_MTH] & ~(RTC_AL_MTH_MASK)) |
215 (tm->tm_mon & RTC_AL_MTH_MASK));
216 data[RTC_OFFSET_YEAR] = ((data[RTC_OFFSET_YEAR] & ~(RTC_AL_YEA_MASK)) |
217 (tm->tm_year & RTC_AL_YEA_MASK));
218
219 if (alm->enabled) {
220 ret = regmap_bulk_write(rtc->regmap,
221 rtc->addr_base + RTC_AL_SEC,
222 data, RTC_OFFSET_COUNT);
223 if (ret < 0)
224 goto exit;
225 ret = regmap_write(rtc->regmap, rtc->addr_base + RTC_AL_MASK,
226 RTC_AL_MASK_DOW);
227 if (ret < 0)
228 goto exit;
229 ret = regmap_update_bits(rtc->regmap,
230 rtc->addr_base + RTC_IRQ_EN,
231 RTC_IRQ_EN_ONESHOT_AL,
232 RTC_IRQ_EN_ONESHOT_AL);
233 if (ret < 0)
234 goto exit;
235 } else {
236 ret = regmap_update_bits(rtc->regmap,
237 rtc->addr_base + RTC_IRQ_EN,
238 RTC_IRQ_EN_ONESHOT_AL, 0);
239 if (ret < 0)
240 goto exit;
241 }
242
243 /* All alarm time register write to hardware after calling
244 * mtk_rtc_write_trigger. This can avoid race condition if alarm
245 * occur happen during writing alarm time register.
246 */
247 ret = mtk_rtc_write_trigger(rtc);
248exit:
249 mutex_unlock(&rtc->lock);
250 return ret;
251}
252
253static const struct rtc_class_ops mtk_rtc_ops = {
254 .read_time = mtk_rtc_read_time,
255 .set_time = mtk_rtc_set_time,
256 .read_alarm = mtk_rtc_read_alarm,
257 .set_alarm = mtk_rtc_set_alarm,
258};
259
260static int mtk_rtc_probe(struct platform_device *pdev)
261{
262 struct resource *res;
263 struct mt6397_chip *mt6397_chip = dev_get_drvdata(pdev->dev.parent);
264 struct mt6397_rtc *rtc;
265 int ret;
266
267 rtc = devm_kzalloc(&pdev->dev, sizeof(struct mt6397_rtc), GFP_KERNEL);
268 if (!rtc)
269 return -ENOMEM;
270
271 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
272 if (!res)
273 return -EINVAL;
274 rtc->addr_base = res->start;
275
276 rtc->data = of_device_get_match_data(&pdev->dev);
277
278 rtc->irq = platform_get_irq(pdev, 0);
279 if (rtc->irq < 0)
280 return rtc->irq;
281
282 rtc->regmap = mt6397_chip->regmap;
283 mutex_init(&rtc->lock);
284
285 platform_set_drvdata(pdev, rtc);
286
287 rtc->rtc_dev = devm_rtc_allocate_device(&pdev->dev);
288 if (IS_ERR(rtc->rtc_dev))
289 return PTR_ERR(rtc->rtc_dev);
290
291 ret = devm_request_threaded_irq(&pdev->dev, rtc->irq, NULL,
292 mtk_rtc_irq_handler_thread,
293 IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
294 "mt6397-rtc", rtc);
295
296 if (ret) {
297 dev_err(&pdev->dev, "Failed to request alarm IRQ: %d: %d\n",
298 rtc->irq, ret);
299 return ret;
300 }
301
302 device_init_wakeup(&pdev->dev, 1);
303
304 rtc->rtc_dev->ops = &mtk_rtc_ops;
305
306 return devm_rtc_register_device(rtc->rtc_dev);
307}
308
309#ifdef CONFIG_PM_SLEEP
310static int mt6397_rtc_suspend(struct device *dev)
311{
312 struct mt6397_rtc *rtc = dev_get_drvdata(dev);
313
314 if (device_may_wakeup(dev))
315 enable_irq_wake(rtc->irq);
316
317 return 0;
318}
319
320static int mt6397_rtc_resume(struct device *dev)
321{
322 struct mt6397_rtc *rtc = dev_get_drvdata(dev);
323
324 if (device_may_wakeup(dev))
325 disable_irq_wake(rtc->irq);
326
327 return 0;
328}
329#endif
330
331static SIMPLE_DEV_PM_OPS(mt6397_pm_ops, mt6397_rtc_suspend,
332 mt6397_rtc_resume);
333
334static const struct mtk_rtc_data mt6358_rtc_data = {
335 .wrtgr = RTC_WRTGR_MT6358,
336};
337
338static const struct mtk_rtc_data mt6397_rtc_data = {
339 .wrtgr = RTC_WRTGR_MT6397,
340};
341
342static const struct of_device_id mt6397_rtc_of_match[] = {
343 { .compatible = "mediatek,mt6323-rtc", .data = &mt6397_rtc_data },
344 { .compatible = "mediatek,mt6358-rtc", .data = &mt6358_rtc_data },
345 { .compatible = "mediatek,mt6397-rtc", .data = &mt6397_rtc_data },
346 { }
347};
348MODULE_DEVICE_TABLE(of, mt6397_rtc_of_match);
349
350static struct platform_driver mtk_rtc_driver = {
351 .driver = {
352 .name = "mt6397-rtc",
353 .of_match_table = mt6397_rtc_of_match,
354 .pm = &mt6397_pm_ops,
355 },
356 .probe = mtk_rtc_probe,
357};
358
359module_platform_driver(mtk_rtc_driver);
360
361MODULE_LICENSE("GPL v2");
362MODULE_AUTHOR("Tianping Fang <tianping.fang@mediatek.com>");
363MODULE_DESCRIPTION("RTC Driver for MediaTek MT6397 PMIC");