1/*
   2 * Copyright 2008 Advanced Micro Devices, Inc.
   3 * Copyright 2008 Red Hat Inc.
   4 * Copyright 2009 Jerome Glisse.
   5 *
   6 * Permission is hereby granted, free of charge, to any person obtaining a
   7 * copy of this software and associated documentation files (the "Software"),
   8 * to deal in the Software without restriction, including without limitation
   9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10 * and/or sell copies of the Software, and to permit persons to whom the
  11 * Software is furnished to do so, subject to the following conditions:
  12 *
  13 * The above copyright notice and this permission notice shall be included in
  14 * all copies or substantial portions of the Software.
  15 *
  16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22 * OTHER DEALINGS IN THE SOFTWARE.
  23 *
  24 * Authors: Dave Airlie
  25 *          Alex Deucher
  26 *          Jerome Glisse
  27 */
 
  28#include <linux/console.h>
 
 
 
  29#include <linux/slab.h>
  30#include <drm/drmP.h>
 
 
 
  31#include <drm/drm_crtc_helper.h>
 
 
 
 
  32#include <drm/radeon_drm.h>
  33#include <linux/vgaarb.h>
  34#include <linux/vga_switcheroo.h>
  35#include <linux/efi.h>
  36#include "radeon_reg.h"
  37#include "radeon.h"
  38#include "atom.h"
  39
  40static const char radeon_family_name[][16] = {
  41	"R100",
  42	"RV100",
  43	"RS100",
  44	"RV200",
  45	"RS200",
  46	"R200",
  47	"RV250",
  48	"RS300",
  49	"RV280",
  50	"R300",
  51	"R350",
  52	"RV350",
  53	"RV380",
  54	"R420",
  55	"R423",
  56	"RV410",
  57	"RS400",
  58	"RS480",
  59	"RS600",
  60	"RS690",
  61	"RS740",
  62	"RV515",
  63	"R520",
  64	"RV530",
  65	"RV560",
  66	"RV570",
  67	"R580",
  68	"R600",
  69	"RV610",
  70	"RV630",
  71	"RV670",
  72	"RV620",
  73	"RV635",
  74	"RS780",
  75	"RS880",
  76	"RV770",
  77	"RV730",
  78	"RV710",
  79	"RV740",
  80	"CEDAR",
  81	"REDWOOD",
  82	"JUNIPER",
  83	"CYPRESS",
  84	"HEMLOCK",
  85	"PALM",
  86	"SUMO",
  87	"SUMO2",
  88	"BARTS",
  89	"TURKS",
  90	"CAICOS",
  91	"CAYMAN",
  92	"ARUBA",
  93	"TAHITI",
  94	"PITCAIRN",
  95	"VERDE",
  96	"OLAND",
  97	"HAINAN",
  98	"BONAIRE",
  99	"KAVERI",
 100	"KABINI",
 101	"HAWAII",
 102	"MULLINS",
 103	"LAST",
 104};
 105
 
 
 
 
 
 
 
 
 106#define RADEON_PX_QUIRK_DISABLE_PX  (1 << 0)
 107#define RADEON_PX_QUIRK_LONG_WAKEUP (1 << 1)
 108
 109struct radeon_px_quirk {
 110	u32 chip_vendor;
 111	u32 chip_device;
 112	u32 subsys_vendor;
 113	u32 subsys_device;
 114	u32 px_quirk_flags;
 115};
 116
 117static struct radeon_px_quirk radeon_px_quirk_list[] = {
 118	/* Acer aspire 5560g (CPU: AMD A4-3305M; GPU: AMD Radeon HD 6480g + 7470m)
 119	 * https://bugzilla.kernel.org/show_bug.cgi?id=74551
 120	 */
 121	{ PCI_VENDOR_ID_ATI, 0x6760, 0x1025, 0x0672, RADEON_PX_QUIRK_DISABLE_PX },
 122	/* Asus K73TA laptop with AMD A6-3400M APU and Radeon 6550 GPU
 123	 * https://bugzilla.kernel.org/show_bug.cgi?id=51381
 124	 */
 125	{ PCI_VENDOR_ID_ATI, 0x6741, 0x1043, 0x108c, RADEON_PX_QUIRK_DISABLE_PX },
 126	/* Asus K53TK laptop with AMD A6-3420M APU and Radeon 7670m GPU
 127	 * https://bugzilla.kernel.org/show_bug.cgi?id=51381
 128	 */
 129	{ PCI_VENDOR_ID_ATI, 0x6840, 0x1043, 0x2122, RADEON_PX_QUIRK_DISABLE_PX },
 130	/* macbook pro 8.2 */
 131	{ PCI_VENDOR_ID_ATI, 0x6741, PCI_VENDOR_ID_APPLE, 0x00e2, RADEON_PX_QUIRK_LONG_WAKEUP },
 
 
 
 
 
 
 132	{ 0, 0, 0, 0, 0 },
 133};
 134
 135bool radeon_is_px(struct drm_device *dev)
 136{
 137	struct radeon_device *rdev = dev->dev_private;
 138
 139	if (rdev->flags & RADEON_IS_PX)
 140		return true;
 141	return false;
 142}
 143
 144static void radeon_device_handle_px_quirks(struct radeon_device *rdev)
 145{
 146	struct radeon_px_quirk *p = radeon_px_quirk_list;
 147
 148	/* Apply PX quirks */
 149	while (p && p->chip_device != 0) {
 150		if (rdev->pdev->vendor == p->chip_vendor &&
 151		    rdev->pdev->device == p->chip_device &&
 152		    rdev->pdev->subsystem_vendor == p->subsys_vendor &&
 153		    rdev->pdev->subsystem_device == p->subsys_device) {
 154			rdev->px_quirk_flags = p->px_quirk_flags;
 155			break;
 156		}
 157		++p;
 158	}
 159
 160	if (rdev->px_quirk_flags & RADEON_PX_QUIRK_DISABLE_PX)
 161		rdev->flags &= ~RADEON_IS_PX;
 
 
 
 
 
 162}
 163
 164/**
 165 * radeon_program_register_sequence - program an array of registers.
 166 *
 167 * @rdev: radeon_device pointer
 168 * @registers: pointer to the register array
 169 * @array_size: size of the register array
 170 *
 171 * Programs an array or registers with and and or masks.
 172 * This is a helper for setting golden registers.
 173 */
 174void radeon_program_register_sequence(struct radeon_device *rdev,
 175				      const u32 *registers,
 176				      const u32 array_size)
 177{
 178	u32 tmp, reg, and_mask, or_mask;
 179	int i;
 180
 181	if (array_size % 3)
 182		return;
 183
 184	for (i = 0; i < array_size; i +=3) {
 185		reg = registers[i + 0];
 186		and_mask = registers[i + 1];
 187		or_mask = registers[i + 2];
 188
 189		if (and_mask == 0xffffffff) {
 190			tmp = or_mask;
 191		} else {
 192			tmp = RREG32(reg);
 193			tmp &= ~and_mask;
 194			tmp |= or_mask;
 195		}
 196		WREG32(reg, tmp);
 197	}
 198}
 199
 200void radeon_pci_config_reset(struct radeon_device *rdev)
 201{
 202	pci_write_config_dword(rdev->pdev, 0x7c, RADEON_ASIC_RESET_DATA);
 203}
 204
 205/**
 206 * radeon_surface_init - Clear GPU surface registers.
 207 *
 208 * @rdev: radeon_device pointer
 209 *
 210 * Clear GPU surface registers (r1xx-r5xx).
 211 */
 212void radeon_surface_init(struct radeon_device *rdev)
 213{
 214	/* FIXME: check this out */
 215	if (rdev->family < CHIP_R600) {
 216		int i;
 217
 218		for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
 219			if (rdev->surface_regs[i].bo)
 220				radeon_bo_get_surface_reg(rdev->surface_regs[i].bo);
 221			else
 222				radeon_clear_surface_reg(rdev, i);
 223		}
 224		/* enable surfaces */
 225		WREG32(RADEON_SURFACE_CNTL, 0);
 226	}
 227}
 228
 229/*
 230 * GPU scratch registers helpers function.
 231 */
 232/**
 233 * radeon_scratch_init - Init scratch register driver information.
 234 *
 235 * @rdev: radeon_device pointer
 236 *
 237 * Init CP scratch register driver information (r1xx-r5xx)
 238 */
 239void radeon_scratch_init(struct radeon_device *rdev)
 240{
 241	int i;
 242
 243	/* FIXME: check this out */
 244	if (rdev->family < CHIP_R300) {
 245		rdev->scratch.num_reg = 5;
 246	} else {
 247		rdev->scratch.num_reg = 7;
 248	}
 249	rdev->scratch.reg_base = RADEON_SCRATCH_REG0;
 250	for (i = 0; i < rdev->scratch.num_reg; i++) {
 251		rdev->scratch.free[i] = true;
 252		rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
 253	}
 254}
 255
 256/**
 257 * radeon_scratch_get - Allocate a scratch register
 258 *
 259 * @rdev: radeon_device pointer
 260 * @reg: scratch register mmio offset
 261 *
 262 * Allocate a CP scratch register for use by the driver (all asics).
 263 * Returns 0 on success or -EINVAL on failure.
 264 */
 265int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
 266{
 267	int i;
 268
 269	for (i = 0; i < rdev->scratch.num_reg; i++) {
 270		if (rdev->scratch.free[i]) {
 271			rdev->scratch.free[i] = false;
 272			*reg = rdev->scratch.reg[i];
 273			return 0;
 274		}
 275	}
 276	return -EINVAL;
 277}
 278
 279/**
 280 * radeon_scratch_free - Free a scratch register
 281 *
 282 * @rdev: radeon_device pointer
 283 * @reg: scratch register mmio offset
 284 *
 285 * Free a CP scratch register allocated for use by the driver (all asics)
 286 */
 287void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
 288{
 289	int i;
 290
 291	for (i = 0; i < rdev->scratch.num_reg; i++) {
 292		if (rdev->scratch.reg[i] == reg) {
 293			rdev->scratch.free[i] = true;
 294			return;
 295		}
 296	}
 297}
 298
 299/*
 300 * GPU doorbell aperture helpers function.
 301 */
 302/**
 303 * radeon_doorbell_init - Init doorbell driver information.
 304 *
 305 * @rdev: radeon_device pointer
 306 *
 307 * Init doorbell driver information (CIK)
 308 * Returns 0 on success, error on failure.
 309 */
 310static int radeon_doorbell_init(struct radeon_device *rdev)
 311{
 312	/* doorbell bar mapping */
 313	rdev->doorbell.base = pci_resource_start(rdev->pdev, 2);
 314	rdev->doorbell.size = pci_resource_len(rdev->pdev, 2);
 315
 316	rdev->doorbell.num_doorbells = min_t(u32, rdev->doorbell.size / sizeof(u32), RADEON_MAX_DOORBELLS);
 317	if (rdev->doorbell.num_doorbells == 0)
 318		return -EINVAL;
 319
 320	rdev->doorbell.ptr = ioremap(rdev->doorbell.base, rdev->doorbell.num_doorbells * sizeof(u32));
 321	if (rdev->doorbell.ptr == NULL) {
 322		return -ENOMEM;
 323	}
 324	DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)rdev->doorbell.base);
 325	DRM_INFO("doorbell mmio size: %u\n", (unsigned)rdev->doorbell.size);
 326
 327	memset(&rdev->doorbell.used, 0, sizeof(rdev->doorbell.used));
 328
 329	return 0;
 330}
 331
 332/**
 333 * radeon_doorbell_fini - Tear down doorbell driver information.
 334 *
 335 * @rdev: radeon_device pointer
 336 *
 337 * Tear down doorbell driver information (CIK)
 338 */
 339static void radeon_doorbell_fini(struct radeon_device *rdev)
 340{
 341	iounmap(rdev->doorbell.ptr);
 342	rdev->doorbell.ptr = NULL;
 343}
 344
 345/**
 346 * radeon_doorbell_get - Allocate a doorbell entry
 347 *
 348 * @rdev: radeon_device pointer
 349 * @doorbell: doorbell index
 350 *
 351 * Allocate a doorbell for use by the driver (all asics).
 352 * Returns 0 on success or -EINVAL on failure.
 353 */
 354int radeon_doorbell_get(struct radeon_device *rdev, u32 *doorbell)
 355{
 356	unsigned long offset = find_first_zero_bit(rdev->doorbell.used, rdev->doorbell.num_doorbells);
 357	if (offset < rdev->doorbell.num_doorbells) {
 358		__set_bit(offset, rdev->doorbell.used);
 359		*doorbell = offset;
 360		return 0;
 361	} else {
 362		return -EINVAL;
 363	}
 364}
 365
 366/**
 367 * radeon_doorbell_free - Free a doorbell entry
 368 *
 369 * @rdev: radeon_device pointer
 370 * @doorbell: doorbell index
 371 *
 372 * Free a doorbell allocated for use by the driver (all asics)
 373 */
 374void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell)
 375{
 376	if (doorbell < rdev->doorbell.num_doorbells)
 377		__clear_bit(doorbell, rdev->doorbell.used);
 378}
 379
 380/**
 381 * radeon_doorbell_get_kfd_info - Report doorbell configuration required to
 382 *                                setup KFD
 383 *
 384 * @rdev: radeon_device pointer
 385 * @aperture_base: output returning doorbell aperture base physical address
 386 * @aperture_size: output returning doorbell aperture size in bytes
 387 * @start_offset: output returning # of doorbell bytes reserved for radeon.
 388 *
 389 * Radeon and the KFD share the doorbell aperture. Radeon sets it up,
 390 * takes doorbells required for its own rings and reports the setup to KFD.
 391 * Radeon reserved doorbells are at the start of the doorbell aperture.
 392 */
 393void radeon_doorbell_get_kfd_info(struct radeon_device *rdev,
 394				  phys_addr_t *aperture_base,
 395				  size_t *aperture_size,
 396				  size_t *start_offset)
 397{
 398	/* The first num_doorbells are used by radeon.
 399	 * KFD takes whatever's left in the aperture. */
 400	if (rdev->doorbell.size > rdev->doorbell.num_doorbells * sizeof(u32)) {
 401		*aperture_base = rdev->doorbell.base;
 402		*aperture_size = rdev->doorbell.size;
 403		*start_offset = rdev->doorbell.num_doorbells * sizeof(u32);
 404	} else {
 405		*aperture_base = 0;
 406		*aperture_size = 0;
 407		*start_offset = 0;
 408	}
 409}
 410
 411/*
 412 * radeon_wb_*()
 413 * Writeback is the the method by which the the GPU updates special pages
 414 * in memory with the status of certain GPU events (fences, ring pointers,
 415 * etc.).
 416 */
 417
 418/**
 419 * radeon_wb_disable - Disable Writeback
 420 *
 421 * @rdev: radeon_device pointer
 422 *
 423 * Disables Writeback (all asics).  Used for suspend.
 424 */
 425void radeon_wb_disable(struct radeon_device *rdev)
 426{
 427	rdev->wb.enabled = false;
 428}
 429
 430/**
 431 * radeon_wb_fini - Disable Writeback and free memory
 432 *
 433 * @rdev: radeon_device pointer
 434 *
 435 * Disables Writeback and frees the Writeback memory (all asics).
 436 * Used at driver shutdown.
 437 */
 438void radeon_wb_fini(struct radeon_device *rdev)
 439{
 440	radeon_wb_disable(rdev);
 441	if (rdev->wb.wb_obj) {
 442		if (!radeon_bo_reserve(rdev->wb.wb_obj, false)) {
 443			radeon_bo_kunmap(rdev->wb.wb_obj);
 444			radeon_bo_unpin(rdev->wb.wb_obj);
 445			radeon_bo_unreserve(rdev->wb.wb_obj);
 446		}
 447		radeon_bo_unref(&rdev->wb.wb_obj);
 448		rdev->wb.wb = NULL;
 449		rdev->wb.wb_obj = NULL;
 450	}
 451}
 452
 453/**
 454 * radeon_wb_init- Init Writeback driver info and allocate memory
 455 *
 456 * @rdev: radeon_device pointer
 457 *
 458 * Disables Writeback and frees the Writeback memory (all asics).
 459 * Used at driver startup.
 460 * Returns 0 on success or an -error on failure.
 461 */
 462int radeon_wb_init(struct radeon_device *rdev)
 463{
 464	int r;
 465
 466	if (rdev->wb.wb_obj == NULL) {
 467		r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
 468				     RADEON_GEM_DOMAIN_GTT, 0, NULL, NULL,
 469				     &rdev->wb.wb_obj);
 470		if (r) {
 471			dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
 472			return r;
 473		}
 474		r = radeon_bo_reserve(rdev->wb.wb_obj, false);
 475		if (unlikely(r != 0)) {
 476			radeon_wb_fini(rdev);
 477			return r;
 478		}
 479		r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
 480				&rdev->wb.gpu_addr);
 481		if (r) {
 482			radeon_bo_unreserve(rdev->wb.wb_obj);
 483			dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
 484			radeon_wb_fini(rdev);
 485			return r;
 486		}
 487		r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
 488		radeon_bo_unreserve(rdev->wb.wb_obj);
 489		if (r) {
 490			dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
 491			radeon_wb_fini(rdev);
 492			return r;
 493		}
 494	}
 495
 496	/* clear wb memory */
 497	memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE);
 498	/* disable event_write fences */
 499	rdev->wb.use_event = false;
 500	/* disabled via module param */
 501	if (radeon_no_wb == 1) {
 502		rdev->wb.enabled = false;
 503	} else {
 504		if (rdev->flags & RADEON_IS_AGP) {
 505			/* often unreliable on AGP */
 506			rdev->wb.enabled = false;
 507		} else if (rdev->family < CHIP_R300) {
 508			/* often unreliable on pre-r300 */
 509			rdev->wb.enabled = false;
 510		} else {
 511			rdev->wb.enabled = true;
 512			/* event_write fences are only available on r600+ */
 513			if (rdev->family >= CHIP_R600) {
 514				rdev->wb.use_event = true;
 515			}
 516		}
 517	}
 518	/* always use writeback/events on NI, APUs */
 519	if (rdev->family >= CHIP_PALM) {
 520		rdev->wb.enabled = true;
 521		rdev->wb.use_event = true;
 522	}
 523
 524	dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis");
 525
 526	return 0;
 527}
 528
 529/**
 530 * radeon_vram_location - try to find VRAM location
 531 * @rdev: radeon device structure holding all necessary informations
 532 * @mc: memory controller structure holding memory informations
 533 * @base: base address at which to put VRAM
 534 *
 535 * Function will place try to place VRAM at base address provided
 536 * as parameter (which is so far either PCI aperture address or
 537 * for IGP TOM base address).
 538 *
 539 * If there is not enough space to fit the unvisible VRAM in the 32bits
 540 * address space then we limit the VRAM size to the aperture.
 541 *
 542 * If we are using AGP and if the AGP aperture doesn't allow us to have
 543 * room for all the VRAM than we restrict the VRAM to the PCI aperture
 544 * size and print a warning.
 545 *
 546 * This function will never fails, worst case are limiting VRAM.
 547 *
 548 * Note: GTT start, end, size should be initialized before calling this
 549 * function on AGP platform.
 550 *
 551 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
 552 * this shouldn't be a problem as we are using the PCI aperture as a reference.
 553 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
 554 * not IGP.
 555 *
 556 * Note: we use mc_vram_size as on some board we need to program the mc to
 557 * cover the whole aperture even if VRAM size is inferior to aperture size
 558 * Novell bug 204882 + along with lots of ubuntu ones
 559 *
 560 * Note: when limiting vram it's safe to overwritte real_vram_size because
 561 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
 562 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
 563 * ones)
 564 *
 565 * Note: IGP TOM addr should be the same as the aperture addr, we don't
 566 * explicitly check for that thought.
 567 *
 568 * FIXME: when reducing VRAM size align new size on power of 2.
 569 */
 570void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)
 571{
 572	uint64_t limit = (uint64_t)radeon_vram_limit << 20;
 573
 574	mc->vram_start = base;
 575	if (mc->mc_vram_size > (rdev->mc.mc_mask - base + 1)) {
 576		dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
 577		mc->real_vram_size = mc->aper_size;
 578		mc->mc_vram_size = mc->aper_size;
 579	}
 580	mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
 581	if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) {
 582		dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
 583		mc->real_vram_size = mc->aper_size;
 584		mc->mc_vram_size = mc->aper_size;
 585	}
 586	mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
 587	if (limit && limit < mc->real_vram_size)
 588		mc->real_vram_size = limit;
 589	dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
 590			mc->mc_vram_size >> 20, mc->vram_start,
 591			mc->vram_end, mc->real_vram_size >> 20);
 592}
 593
 594/**
 595 * radeon_gtt_location - try to find GTT location
 596 * @rdev: radeon device structure holding all necessary informations
 597 * @mc: memory controller structure holding memory informations
 598 *
 599 * Function will place try to place GTT before or after VRAM.
 600 *
 601 * If GTT size is bigger than space left then we ajust GTT size.
 602 * Thus function will never fails.
 603 *
 604 * FIXME: when reducing GTT size align new size on power of 2.
 605 */
 606void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
 607{
 608	u64 size_af, size_bf;
 609
 610	size_af = ((rdev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
 611	size_bf = mc->vram_start & ~mc->gtt_base_align;
 612	if (size_bf > size_af) {
 613		if (mc->gtt_size > size_bf) {
 614			dev_warn(rdev->dev, "limiting GTT\n");
 615			mc->gtt_size = size_bf;
 616		}
 617		mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
 618	} else {
 619		if (mc->gtt_size > size_af) {
 620			dev_warn(rdev->dev, "limiting GTT\n");
 621			mc->gtt_size = size_af;
 622		}
 623		mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
 624	}
 625	mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
 626	dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
 627			mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
 628}
 629
 630/*
 631 * GPU helpers function.
 632 */
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 633/**
 634 * radeon_card_posted - check if the hw has already been initialized
 635 *
 636 * @rdev: radeon_device pointer
 637 *
 638 * Check if the asic has been initialized (all asics).
 639 * Used at driver startup.
 640 * Returns true if initialized or false if not.
 641 */
 642bool radeon_card_posted(struct radeon_device *rdev)
 643{
 644	uint32_t reg;
 645
 
 
 
 
 
 646	/* required for EFI mode on macbook2,1 which uses an r5xx asic */
 647	if (efi_enabled(EFI_BOOT) &&
 648	    (rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
 649	    (rdev->family < CHIP_R600))
 650		return false;
 651
 652	if (ASIC_IS_NODCE(rdev))
 653		goto check_memsize;
 654
 655	/* first check CRTCs */
 656	if (ASIC_IS_DCE4(rdev)) {
 657		reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
 658			RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
 659			if (rdev->num_crtc >= 4) {
 660				reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
 661					RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
 662			}
 663			if (rdev->num_crtc >= 6) {
 664				reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
 665					RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
 666			}
 667		if (reg & EVERGREEN_CRTC_MASTER_EN)
 668			return true;
 669	} else if (ASIC_IS_AVIVO(rdev)) {
 670		reg = RREG32(AVIVO_D1CRTC_CONTROL) |
 671		      RREG32(AVIVO_D2CRTC_CONTROL);
 672		if (reg & AVIVO_CRTC_EN) {
 673			return true;
 674		}
 675	} else {
 676		reg = RREG32(RADEON_CRTC_GEN_CNTL) |
 677		      RREG32(RADEON_CRTC2_GEN_CNTL);
 678		if (reg & RADEON_CRTC_EN) {
 679			return true;
 680		}
 681	}
 682
 683check_memsize:
 684	/* then check MEM_SIZE, in case the crtcs are off */
 685	if (rdev->family >= CHIP_R600)
 686		reg = RREG32(R600_CONFIG_MEMSIZE);
 687	else
 688		reg = RREG32(RADEON_CONFIG_MEMSIZE);
 689
 690	if (reg)
 691		return true;
 692
 693	return false;
 694
 695}
 696
 697/**
 698 * radeon_update_bandwidth_info - update display bandwidth params
 699 *
 700 * @rdev: radeon_device pointer
 701 *
 702 * Used when sclk/mclk are switched or display modes are set.
 703 * params are used to calculate display watermarks (all asics)
 704 */
 705void radeon_update_bandwidth_info(struct radeon_device *rdev)
 706{
 707	fixed20_12 a;
 708	u32 sclk = rdev->pm.current_sclk;
 709	u32 mclk = rdev->pm.current_mclk;
 710
 711	/* sclk/mclk in Mhz */
 712	a.full = dfixed_const(100);
 713	rdev->pm.sclk.full = dfixed_const(sclk);
 714	rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
 715	rdev->pm.mclk.full = dfixed_const(mclk);
 716	rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
 717
 718	if (rdev->flags & RADEON_IS_IGP) {
 719		a.full = dfixed_const(16);
 720		/* core_bandwidth = sclk(Mhz) * 16 */
 721		rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
 722	}
 723}
 724
 725/**
 726 * radeon_boot_test_post_card - check and possibly initialize the hw
 727 *
 728 * @rdev: radeon_device pointer
 729 *
 730 * Check if the asic is initialized and if not, attempt to initialize
 731 * it (all asics).
 732 * Returns true if initialized or false if not.
 733 */
 734bool radeon_boot_test_post_card(struct radeon_device *rdev)
 735{
 736	if (radeon_card_posted(rdev))
 737		return true;
 738
 739	if (rdev->bios) {
 740		DRM_INFO("GPU not posted. posting now...\n");
 741		if (rdev->is_atom_bios)
 742			atom_asic_init(rdev->mode_info.atom_context);
 743		else
 744			radeon_combios_asic_init(rdev->ddev);
 745		return true;
 746	} else {
 747		dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
 748		return false;
 749	}
 750}
 751
 752/**
 753 * radeon_dummy_page_init - init dummy page used by the driver
 754 *
 755 * @rdev: radeon_device pointer
 756 *
 757 * Allocate the dummy page used by the driver (all asics).
 758 * This dummy page is used by the driver as a filler for gart entries
 759 * when pages are taken out of the GART
 760 * Returns 0 on sucess, -ENOMEM on failure.
 761 */
 762int radeon_dummy_page_init(struct radeon_device *rdev)
 763{
 764	if (rdev->dummy_page.page)
 765		return 0;
 766	rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
 767	if (rdev->dummy_page.page == NULL)
 768		return -ENOMEM;
 769	rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
 770					0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 771	if (pci_dma_mapping_error(rdev->pdev, rdev->dummy_page.addr)) {
 772		dev_err(&rdev->pdev->dev, "Failed to DMA MAP the dummy page\n");
 773		__free_page(rdev->dummy_page.page);
 774		rdev->dummy_page.page = NULL;
 775		return -ENOMEM;
 776	}
 777	rdev->dummy_page.entry = radeon_gart_get_page_entry(rdev->dummy_page.addr,
 778							    RADEON_GART_PAGE_DUMMY);
 779	return 0;
 780}
 781
 782/**
 783 * radeon_dummy_page_fini - free dummy page used by the driver
 784 *
 785 * @rdev: radeon_device pointer
 786 *
 787 * Frees the dummy page used by the driver (all asics).
 788 */
 789void radeon_dummy_page_fini(struct radeon_device *rdev)
 790{
 791	if (rdev->dummy_page.page == NULL)
 792		return;
 793	pci_unmap_page(rdev->pdev, rdev->dummy_page.addr,
 794			PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 795	__free_page(rdev->dummy_page.page);
 796	rdev->dummy_page.page = NULL;
 797}
 798
 799
 800/* ATOM accessor methods */
 801/*
 802 * ATOM is an interpreted byte code stored in tables in the vbios.  The
 803 * driver registers callbacks to access registers and the interpreter
 804 * in the driver parses the tables and executes then to program specific
 805 * actions (set display modes, asic init, etc.).  See radeon_atombios.c,
 806 * atombios.h, and atom.c
 807 */
 808
 809/**
 810 * cail_pll_read - read PLL register
 811 *
 812 * @info: atom card_info pointer
 813 * @reg: PLL register offset
 814 *
 815 * Provides a PLL register accessor for the atom interpreter (r4xx+).
 816 * Returns the value of the PLL register.
 817 */
 818static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
 819{
 820	struct radeon_device *rdev = info->dev->dev_private;
 821	uint32_t r;
 822
 823	r = rdev->pll_rreg(rdev, reg);
 824	return r;
 825}
 826
 827/**
 828 * cail_pll_write - write PLL register
 829 *
 830 * @info: atom card_info pointer
 831 * @reg: PLL register offset
 832 * @val: value to write to the pll register
 833 *
 834 * Provides a PLL register accessor for the atom interpreter (r4xx+).
 835 */
 836static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
 837{
 838	struct radeon_device *rdev = info->dev->dev_private;
 839
 840	rdev->pll_wreg(rdev, reg, val);
 841}
 842
 843/**
 844 * cail_mc_read - read MC (Memory Controller) register
 845 *
 846 * @info: atom card_info pointer
 847 * @reg: MC register offset
 848 *
 849 * Provides an MC register accessor for the atom interpreter (r4xx+).
 850 * Returns the value of the MC register.
 851 */
 852static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
 853{
 854	struct radeon_device *rdev = info->dev->dev_private;
 855	uint32_t r;
 856
 857	r = rdev->mc_rreg(rdev, reg);
 858	return r;
 859}
 860
 861/**
 862 * cail_mc_write - write MC (Memory Controller) register
 863 *
 864 * @info: atom card_info pointer
 865 * @reg: MC register offset
 866 * @val: value to write to the pll register
 867 *
 868 * Provides a MC register accessor for the atom interpreter (r4xx+).
 869 */
 870static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
 871{
 872	struct radeon_device *rdev = info->dev->dev_private;
 873
 874	rdev->mc_wreg(rdev, reg, val);
 875}
 876
 877/**
 878 * cail_reg_write - write MMIO register
 879 *
 880 * @info: atom card_info pointer
 881 * @reg: MMIO register offset
 882 * @val: value to write to the pll register
 883 *
 884 * Provides a MMIO register accessor for the atom interpreter (r4xx+).
 885 */
 886static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
 887{
 888	struct radeon_device *rdev = info->dev->dev_private;
 889
 890	WREG32(reg*4, val);
 891}
 892
 893/**
 894 * cail_reg_read - read MMIO register
 895 *
 896 * @info: atom card_info pointer
 897 * @reg: MMIO register offset
 898 *
 899 * Provides an MMIO register accessor for the atom interpreter (r4xx+).
 900 * Returns the value of the MMIO register.
 901 */
 902static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
 903{
 904	struct radeon_device *rdev = info->dev->dev_private;
 905	uint32_t r;
 906
 907	r = RREG32(reg*4);
 908	return r;
 909}
 910
 911/**
 912 * cail_ioreg_write - write IO register
 913 *
 914 * @info: atom card_info pointer
 915 * @reg: IO register offset
 916 * @val: value to write to the pll register
 917 *
 918 * Provides a IO register accessor for the atom interpreter (r4xx+).
 919 */
 920static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
 921{
 922	struct radeon_device *rdev = info->dev->dev_private;
 923
 924	WREG32_IO(reg*4, val);
 925}
 926
 927/**
 928 * cail_ioreg_read - read IO register
 929 *
 930 * @info: atom card_info pointer
 931 * @reg: IO register offset
 932 *
 933 * Provides an IO register accessor for the atom interpreter (r4xx+).
 934 * Returns the value of the IO register.
 935 */
 936static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
 937{
 938	struct radeon_device *rdev = info->dev->dev_private;
 939	uint32_t r;
 940
 941	r = RREG32_IO(reg*4);
 942	return r;
 943}
 944
 945/**
 946 * radeon_atombios_init - init the driver info and callbacks for atombios
 947 *
 948 * @rdev: radeon_device pointer
 949 *
 950 * Initializes the driver info and register access callbacks for the
 951 * ATOM interpreter (r4xx+).
 952 * Returns 0 on sucess, -ENOMEM on failure.
 953 * Called at driver startup.
 954 */
 955int radeon_atombios_init(struct radeon_device *rdev)
 956{
 957	struct card_info *atom_card_info =
 958	    kzalloc(sizeof(struct card_info), GFP_KERNEL);
 959
 960	if (!atom_card_info)
 961		return -ENOMEM;
 962
 963	rdev->mode_info.atom_card_info = atom_card_info;
 964	atom_card_info->dev = rdev->ddev;
 965	atom_card_info->reg_read = cail_reg_read;
 966	atom_card_info->reg_write = cail_reg_write;
 967	/* needed for iio ops */
 968	if (rdev->rio_mem) {
 969		atom_card_info->ioreg_read = cail_ioreg_read;
 970		atom_card_info->ioreg_write = cail_ioreg_write;
 971	} else {
 972		DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
 973		atom_card_info->ioreg_read = cail_reg_read;
 974		atom_card_info->ioreg_write = cail_reg_write;
 975	}
 976	atom_card_info->mc_read = cail_mc_read;
 977	atom_card_info->mc_write = cail_mc_write;
 978	atom_card_info->pll_read = cail_pll_read;
 979	atom_card_info->pll_write = cail_pll_write;
 980
 981	rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
 982	if (!rdev->mode_info.atom_context) {
 983		radeon_atombios_fini(rdev);
 984		return -ENOMEM;
 985	}
 986
 987	mutex_init(&rdev->mode_info.atom_context->mutex);
 988	mutex_init(&rdev->mode_info.atom_context->scratch_mutex);
 989	radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
 990	atom_allocate_fb_scratch(rdev->mode_info.atom_context);
 991	return 0;
 992}
 993
 994/**
 995 * radeon_atombios_fini - free the driver info and callbacks for atombios
 996 *
 997 * @rdev: radeon_device pointer
 998 *
 999 * Frees the driver info and register access callbacks for the ATOM
1000 * interpreter (r4xx+).
1001 * Called at driver shutdown.
1002 */
1003void radeon_atombios_fini(struct radeon_device *rdev)
1004{
1005	if (rdev->mode_info.atom_context) {
1006		kfree(rdev->mode_info.atom_context->scratch);
1007	}
1008	kfree(rdev->mode_info.atom_context);
1009	rdev->mode_info.atom_context = NULL;
1010	kfree(rdev->mode_info.atom_card_info);
1011	rdev->mode_info.atom_card_info = NULL;
1012}
1013
1014/* COMBIOS */
1015/*
1016 * COMBIOS is the bios format prior to ATOM. It provides
1017 * command tables similar to ATOM, but doesn't have a unified
1018 * parser.  See radeon_combios.c
1019 */
1020
1021/**
1022 * radeon_combios_init - init the driver info for combios
1023 *
1024 * @rdev: radeon_device pointer
1025 *
1026 * Initializes the driver info for combios (r1xx-r3xx).
1027 * Returns 0 on sucess.
1028 * Called at driver startup.
1029 */
1030int radeon_combios_init(struct radeon_device *rdev)
1031{
1032	radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
1033	return 0;
1034}
1035
1036/**
1037 * radeon_combios_fini - free the driver info for combios
1038 *
1039 * @rdev: radeon_device pointer
1040 *
1041 * Frees the driver info for combios (r1xx-r3xx).
1042 * Called at driver shutdown.
1043 */
1044void radeon_combios_fini(struct radeon_device *rdev)
1045{
1046}
1047
1048/* if we get transitioned to only one device, take VGA back */
1049/**
1050 * radeon_vga_set_decode - enable/disable vga decode
1051 *
1052 * @cookie: radeon_device pointer
1053 * @state: enable/disable vga decode
1054 *
1055 * Enable/disable vga decode (all asics).
1056 * Returns VGA resource flags.
1057 */
1058static unsigned int radeon_vga_set_decode(void *cookie, bool state)
1059{
1060	struct radeon_device *rdev = cookie;
 
1061	radeon_vga_set_state(rdev, state);
1062	if (state)
1063		return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1064		       VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1065	else
1066		return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1067}
1068
1069/**
1070 * radeon_check_pot_argument - check that argument is a power of two
1071 *
1072 * @arg: value to check
1073 *
1074 * Validates that a certain argument is a power of two (all asics).
1075 * Returns true if argument is valid.
1076 */
1077static bool radeon_check_pot_argument(int arg)
1078{
1079	return (arg & (arg - 1)) == 0;
1080}
1081
1082/**
1083 * Determine a sensible default GART size according to ASIC family.
1084 *
1085 * @family ASIC family name
1086 */
1087static int radeon_gart_size_auto(enum radeon_family family)
1088{
1089	/* default to a larger gart size on newer asics */
1090	if (family >= CHIP_TAHITI)
1091		return 2048;
1092	else if (family >= CHIP_RV770)
1093		return 1024;
1094	else
1095		return 512;
1096}
1097
1098/**
1099 * radeon_check_arguments - validate module params
1100 *
1101 * @rdev: radeon_device pointer
1102 *
1103 * Validates certain module parameters and updates
1104 * the associated values used by the driver (all asics).
1105 */
1106static void radeon_check_arguments(struct radeon_device *rdev)
1107{
1108	/* vramlimit must be a power of two */
1109	if (!radeon_check_pot_argument(radeon_vram_limit)) {
1110		dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
1111				radeon_vram_limit);
1112		radeon_vram_limit = 0;
1113	}
1114
1115	if (radeon_gart_size == -1) {
1116		radeon_gart_size = radeon_gart_size_auto(rdev->family);
1117	}
1118	/* gtt size must be power of two and greater or equal to 32M */
1119	if (radeon_gart_size < 32) {
1120		dev_warn(rdev->dev, "gart size (%d) too small\n",
1121				radeon_gart_size);
1122		radeon_gart_size = radeon_gart_size_auto(rdev->family);
1123	} else if (!radeon_check_pot_argument(radeon_gart_size)) {
1124		dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
1125				radeon_gart_size);
1126		radeon_gart_size = radeon_gart_size_auto(rdev->family);
1127	}
1128	rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20;
1129
1130	/* AGP mode can only be -1, 1, 2, 4, 8 */
1131	switch (radeon_agpmode) {
1132	case -1:
1133	case 0:
1134	case 1:
1135	case 2:
1136	case 4:
1137	case 8:
1138		break;
1139	default:
1140		dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
1141				"-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
1142		radeon_agpmode = 0;
1143		break;
1144	}
1145
1146	if (!radeon_check_pot_argument(radeon_vm_size)) {
1147		dev_warn(rdev->dev, "VM size (%d) must be a power of 2\n",
1148			 radeon_vm_size);
1149		radeon_vm_size = 4;
1150	}
1151
1152	if (radeon_vm_size < 1) {
1153		dev_warn(rdev->dev, "VM size (%d) too small, min is 1GB\n",
1154			 radeon_vm_size);
1155		radeon_vm_size = 4;
1156	}
1157
1158	/*
1159	 * Max GPUVM size for Cayman, SI and CI are 40 bits.
1160	 */
1161	if (radeon_vm_size > 1024) {
1162		dev_warn(rdev->dev, "VM size (%d) too large, max is 1TB\n",
1163			 radeon_vm_size);
1164		radeon_vm_size = 4;
1165	}
1166
1167	/* defines number of bits in page table versus page directory,
1168	 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1169	 * page table and the remaining bits are in the page directory */
1170	if (radeon_vm_block_size == -1) {
1171
1172		/* Total bits covered by PD + PTs */
1173		unsigned bits = ilog2(radeon_vm_size) + 18;
1174
1175		/* Make sure the PD is 4K in size up to 8GB address space.
1176		   Above that split equal between PD and PTs */
1177		if (radeon_vm_size <= 8)
1178			radeon_vm_block_size = bits - 9;
1179		else
1180			radeon_vm_block_size = (bits + 3) / 2;
1181
1182	} else if (radeon_vm_block_size < 9) {
1183		dev_warn(rdev->dev, "VM page table size (%d) too small\n",
1184			 radeon_vm_block_size);
1185		radeon_vm_block_size = 9;
1186	}
1187
1188	if (radeon_vm_block_size > 24 ||
1189	    (radeon_vm_size * 1024) < (1ull << radeon_vm_block_size)) {
1190		dev_warn(rdev->dev, "VM page table size (%d) too large\n",
1191			 radeon_vm_block_size);
1192		radeon_vm_block_size = 9;
1193	}
1194}
1195
1196/**
1197 * radeon_switcheroo_set_state - set switcheroo state
1198 *
1199 * @pdev: pci dev pointer
1200 * @state: vga_switcheroo state
1201 *
1202 * Callback for the switcheroo driver.  Suspends or resumes the
1203 * the asics before or after it is powered up using ACPI methods.
1204 */
1205static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1206{
1207	struct drm_device *dev = pci_get_drvdata(pdev);
1208	struct radeon_device *rdev = dev->dev_private;
1209
1210	if (radeon_is_px(dev) && state == VGA_SWITCHEROO_OFF)
1211		return;
1212
1213	if (state == VGA_SWITCHEROO_ON) {
1214		unsigned d3_delay = dev->pdev->d3_delay;
1215
1216		printk(KERN_INFO "radeon: switched on\n");
1217		/* don't suspend or resume card normally */
1218		dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1219
1220		if (d3_delay < 20 && (rdev->px_quirk_flags & RADEON_PX_QUIRK_LONG_WAKEUP))
1221			dev->pdev->d3_delay = 20;
1222
1223		radeon_resume_kms(dev, true, true);
1224
1225		dev->pdev->d3_delay = d3_delay;
1226
1227		dev->switch_power_state = DRM_SWITCH_POWER_ON;
1228		drm_kms_helper_poll_enable(dev);
1229	} else {
1230		printk(KERN_INFO "radeon: switched off\n");
1231		drm_kms_helper_poll_disable(dev);
1232		dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1233		radeon_suspend_kms(dev, true, true);
1234		dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1235	}
1236}
1237
1238/**
1239 * radeon_switcheroo_can_switch - see if switcheroo state can change
1240 *
1241 * @pdev: pci dev pointer
1242 *
1243 * Callback for the switcheroo driver.  Check of the switcheroo
1244 * state can be changed.
1245 * Returns true if the state can be changed, false if not.
1246 */
1247static bool radeon_switcheroo_can_switch(struct pci_dev *pdev)
1248{
1249	struct drm_device *dev = pci_get_drvdata(pdev);
1250
1251	/*
1252	 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1253	 * locking inversion with the driver load path. And the access here is
1254	 * completely racy anyway. So don't bother with locking for now.
1255	 */
1256	return dev->open_count == 0;
1257}
1258
1259static const struct vga_switcheroo_client_ops radeon_switcheroo_ops = {
1260	.set_gpu_state = radeon_switcheroo_set_state,
1261	.reprobe = NULL,
1262	.can_switch = radeon_switcheroo_can_switch,
1263};
1264
1265/**
1266 * radeon_device_init - initialize the driver
1267 *
1268 * @rdev: radeon_device pointer
1269 * @pdev: drm dev pointer
1270 * @pdev: pci dev pointer
1271 * @flags: driver flags
1272 *
1273 * Initializes the driver info and hw (all asics).
1274 * Returns 0 for success or an error on failure.
1275 * Called at driver startup.
1276 */
1277int radeon_device_init(struct radeon_device *rdev,
1278		       struct drm_device *ddev,
1279		       struct pci_dev *pdev,
1280		       uint32_t flags)
1281{
1282	int r, i;
1283	int dma_bits;
1284	bool runtime = false;
1285
1286	rdev->shutdown = false;
1287	rdev->dev = &pdev->dev;
1288	rdev->ddev = ddev;
1289	rdev->pdev = pdev;
1290	rdev->flags = flags;
1291	rdev->family = flags & RADEON_FAMILY_MASK;
1292	rdev->is_atom_bios = false;
1293	rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
1294	rdev->mc.gtt_size = 512 * 1024 * 1024;
1295	rdev->accel_working = false;
1296	/* set up ring ids */
1297	for (i = 0; i < RADEON_NUM_RINGS; i++) {
1298		rdev->ring[i].idx = i;
1299	}
1300	rdev->fence_context = fence_context_alloc(RADEON_NUM_RINGS);
1301
1302	DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
1303		 radeon_family_name[rdev->family], pdev->vendor, pdev->device,
1304		 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
1305
1306	/* mutex initialization are all done here so we
1307	 * can recall function without having locking issues */
1308	mutex_init(&rdev->ring_lock);
1309	mutex_init(&rdev->dc_hw_i2c_mutex);
1310	atomic_set(&rdev->ih.lock, 0);
1311	mutex_init(&rdev->gem.mutex);
1312	mutex_init(&rdev->pm.mutex);
1313	mutex_init(&rdev->gpu_clock_mutex);
1314	mutex_init(&rdev->srbm_mutex);
1315	mutex_init(&rdev->grbm_idx_mutex);
1316	init_rwsem(&rdev->pm.mclk_lock);
1317	init_rwsem(&rdev->exclusive_lock);
1318	init_waitqueue_head(&rdev->irq.vblank_queue);
1319	mutex_init(&rdev->mn_lock);
1320	hash_init(rdev->mn_hash);
1321	r = radeon_gem_init(rdev);
1322	if (r)
1323		return r;
1324
1325	radeon_check_arguments(rdev);
1326	/* Adjust VM size here.
1327	 * Max GPUVM size for cayman+ is 40 bits.
1328	 */
1329	rdev->vm_manager.max_pfn = radeon_vm_size << 18;
1330
1331	/* Set asic functions */
1332	r = radeon_asic_init(rdev);
1333	if (r)
1334		return r;
1335
1336	/* all of the newer IGP chips have an internal gart
1337	 * However some rs4xx report as AGP, so remove that here.
1338	 */
1339	if ((rdev->family >= CHIP_RS400) &&
1340	    (rdev->flags & RADEON_IS_IGP)) {
1341		rdev->flags &= ~RADEON_IS_AGP;
1342	}
1343
1344	if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
1345		radeon_agp_disable(rdev);
1346	}
1347
1348	/* Set the internal MC address mask
1349	 * This is the max address of the GPU's
1350	 * internal address space.
1351	 */
1352	if (rdev->family >= CHIP_CAYMAN)
1353		rdev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
1354	else if (rdev->family >= CHIP_CEDAR)
1355		rdev->mc.mc_mask = 0xfffffffffULL; /* 36 bit MC */
1356	else
1357		rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */
1358
1359	/* set DMA mask + need_dma32 flags.
1360	 * PCIE - can handle 40-bits.
1361	 * IGP - can handle 40-bits
1362	 * AGP - generally dma32 is safest
1363	 * PCI - dma32 for legacy pci gart, 40 bits on newer asics
1364	 */
1365	rdev->need_dma32 = false;
1366	if (rdev->flags & RADEON_IS_AGP)
1367		rdev->need_dma32 = true;
1368	if ((rdev->flags & RADEON_IS_PCI) &&
1369	    (rdev->family <= CHIP_RS740))
1370		rdev->need_dma32 = true;
1371
1372	dma_bits = rdev->need_dma32 ? 32 : 40;
1373	r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
1374	if (r) {
1375		rdev->need_dma32 = true;
1376		dma_bits = 32;
1377		printk(KERN_WARNING "radeon: No suitable DMA available.\n");
1378	}
1379	r = pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
 
 
 
1380	if (r) {
1381		pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(32));
1382		printk(KERN_WARNING "radeon: No coherent DMA available.\n");
1383	}
 
1384
1385	/* Registers mapping */
1386	/* TODO: block userspace mapping of io register */
1387	spin_lock_init(&rdev->mmio_idx_lock);
1388	spin_lock_init(&rdev->smc_idx_lock);
1389	spin_lock_init(&rdev->pll_idx_lock);
1390	spin_lock_init(&rdev->mc_idx_lock);
1391	spin_lock_init(&rdev->pcie_idx_lock);
1392	spin_lock_init(&rdev->pciep_idx_lock);
1393	spin_lock_init(&rdev->pif_idx_lock);
1394	spin_lock_init(&rdev->cg_idx_lock);
1395	spin_lock_init(&rdev->uvd_idx_lock);
1396	spin_lock_init(&rdev->rcu_idx_lock);
1397	spin_lock_init(&rdev->didt_idx_lock);
1398	spin_lock_init(&rdev->end_idx_lock);
1399	if (rdev->family >= CHIP_BONAIRE) {
1400		rdev->rmmio_base = pci_resource_start(rdev->pdev, 5);
1401		rdev->rmmio_size = pci_resource_len(rdev->pdev, 5);
1402	} else {
1403		rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
1404		rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
1405	}
1406	rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
1407	if (rdev->rmmio == NULL) {
1408		return -ENOMEM;
1409	}
1410	DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
1411	DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
1412
1413	/* doorbell bar mapping */
1414	if (rdev->family >= CHIP_BONAIRE)
1415		radeon_doorbell_init(rdev);
1416
1417	/* io port mapping */
1418	for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1419		if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) {
1420			rdev->rio_mem_size = pci_resource_len(rdev->pdev, i);
1421			rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size);
1422			break;
1423		}
1424	}
1425	if (rdev->rio_mem == NULL)
1426		DRM_ERROR("Unable to find PCI I/O BAR\n");
1427
1428	if (rdev->flags & RADEON_IS_PX)
1429		radeon_device_handle_px_quirks(rdev);
1430
1431	/* if we have > 1 VGA cards, then disable the radeon VGA resources */
1432	/* this will fail for cards that aren't VGA class devices, just
1433	 * ignore it */
1434	vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
1435
1436	if (rdev->flags & RADEON_IS_PX)
1437		runtime = true;
1438	vga_switcheroo_register_client(rdev->pdev, &radeon_switcheroo_ops, runtime);
 
 
1439	if (runtime)
1440		vga_switcheroo_init_domain_pm_ops(rdev->dev, &rdev->vga_pm_domain);
1441
1442	r = radeon_init(rdev);
1443	if (r)
1444		goto failed;
1445
1446	r = radeon_gem_debugfs_init(rdev);
1447	if (r) {
1448		DRM_ERROR("registering gem debugfs failed (%d).\n", r);
1449	}
1450
1451	r = radeon_mst_debugfs_init(rdev);
1452	if (r) {
1453		DRM_ERROR("registering mst debugfs failed (%d).\n", r);
1454	}
1455
1456	if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
1457		/* Acceleration not working on AGP card try again
1458		 * with fallback to PCI or PCIE GART
1459		 */
1460		radeon_asic_reset(rdev);
1461		radeon_fini(rdev);
1462		radeon_agp_disable(rdev);
1463		r = radeon_init(rdev);
1464		if (r)
1465			goto failed;
1466	}
1467
 
 
1468	r = radeon_ib_ring_tests(rdev);
1469	if (r)
1470		DRM_ERROR("ib ring test failed (%d).\n", r);
1471
1472	/*
1473	 * Turks/Thames GPU will freeze whole laptop if DPM is not restarted
1474	 * after the CP ring have chew one packet at least. Hence here we stop
1475	 * and restart DPM after the radeon_ib_ring_tests().
1476	 */
1477	if (rdev->pm.dpm_enabled &&
1478	    (rdev->pm.pm_method == PM_METHOD_DPM) &&
1479	    (rdev->family == CHIP_TURKS) &&
1480	    (rdev->flags & RADEON_IS_MOBILITY)) {
1481		mutex_lock(&rdev->pm.mutex);
1482		radeon_dpm_disable(rdev);
1483		radeon_dpm_enable(rdev);
1484		mutex_unlock(&rdev->pm.mutex);
1485	}
1486
1487	if ((radeon_testing & 1)) {
1488		if (rdev->accel_working)
1489			radeon_test_moves(rdev);
1490		else
1491			DRM_INFO("radeon: acceleration disabled, skipping move tests\n");
1492	}
1493	if ((radeon_testing & 2)) {
1494		if (rdev->accel_working)
1495			radeon_test_syncing(rdev);
1496		else
1497			DRM_INFO("radeon: acceleration disabled, skipping sync tests\n");
1498	}
1499	if (radeon_benchmarking) {
1500		if (rdev->accel_working)
1501			radeon_benchmark(rdev, radeon_benchmarking);
1502		else
1503			DRM_INFO("radeon: acceleration disabled, skipping benchmarks\n");
1504	}
1505	return 0;
1506
1507failed:
 
 
 
1508	if (runtime)
1509		vga_switcheroo_fini_domain_pm_ops(rdev->dev);
1510	return r;
1511}
1512
1513static void radeon_debugfs_remove_files(struct radeon_device *rdev);
1514
1515/**
1516 * radeon_device_fini - tear down the driver
1517 *
1518 * @rdev: radeon_device pointer
1519 *
1520 * Tear down the driver info (all asics).
1521 * Called at driver shutdown.
1522 */
1523void radeon_device_fini(struct radeon_device *rdev)
1524{
1525	DRM_INFO("radeon: finishing device.\n");
1526	rdev->shutdown = true;
1527	/* evict vram memory */
1528	radeon_bo_evict_vram(rdev);
 
1529	radeon_fini(rdev);
1530	vga_switcheroo_unregister_client(rdev->pdev);
 
1531	if (rdev->flags & RADEON_IS_PX)
1532		vga_switcheroo_fini_domain_pm_ops(rdev->dev);
1533	vga_client_register(rdev->pdev, NULL, NULL, NULL);
1534	if (rdev->rio_mem)
1535		pci_iounmap(rdev->pdev, rdev->rio_mem);
1536	rdev->rio_mem = NULL;
1537	iounmap(rdev->rmmio);
1538	rdev->rmmio = NULL;
1539	if (rdev->family >= CHIP_BONAIRE)
1540		radeon_doorbell_fini(rdev);
1541	radeon_debugfs_remove_files(rdev);
1542}
1543
1544
1545/*
1546 * Suspend & resume.
1547 */
1548/**
1549 * radeon_suspend_kms - initiate device suspend
1550 *
1551 * @pdev: drm dev pointer
1552 * @state: suspend state
1553 *
1554 * Puts the hw in the suspend state (all asics).
1555 * Returns 0 for success or an error on failure.
1556 * Called at driver suspend.
1557 */
1558int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon)
 
1559{
1560	struct radeon_device *rdev;
 
1561	struct drm_crtc *crtc;
1562	struct drm_connector *connector;
1563	int i, r;
1564
1565	if (dev == NULL || dev->dev_private == NULL) {
1566		return -ENODEV;
1567	}
1568
1569	rdev = dev->dev_private;
 
1570
1571	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1572		return 0;
1573
1574	drm_kms_helper_poll_disable(dev);
1575
1576	drm_modeset_lock_all(dev);
1577	/* turn off display hw */
1578	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1579		drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
1580	}
1581	drm_modeset_unlock_all(dev);
1582
1583	/* unpin the front buffers and cursors */
1584	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1585		struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1586		struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->primary->fb);
1587		struct radeon_bo *robj;
1588
1589		if (radeon_crtc->cursor_bo) {
1590			struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo);
1591			r = radeon_bo_reserve(robj, false);
1592			if (r == 0) {
1593				radeon_bo_unpin(robj);
1594				radeon_bo_unreserve(robj);
1595			}
1596		}
1597
1598		if (rfb == NULL || rfb->obj == NULL) {
1599			continue;
1600		}
1601		robj = gem_to_radeon_bo(rfb->obj);
1602		/* don't unpin kernel fb objects */
1603		if (!radeon_fbdev_robj_is_fb(rdev, robj)) {
1604			r = radeon_bo_reserve(robj, false);
1605			if (r == 0) {
1606				radeon_bo_unpin(robj);
1607				radeon_bo_unreserve(robj);
1608			}
1609		}
1610	}
1611	/* evict vram memory */
1612	radeon_bo_evict_vram(rdev);
1613
1614	/* wait for gpu to finish processing current batch */
1615	for (i = 0; i < RADEON_NUM_RINGS; i++) {
1616		r = radeon_fence_wait_empty(rdev, i);
1617		if (r) {
1618			/* delay GPU reset to resume */
1619			radeon_fence_driver_force_completion(rdev, i);
 
 
 
1620		}
1621	}
1622
1623	radeon_save_bios_scratch_regs(rdev);
1624
1625	radeon_suspend(rdev);
1626	radeon_hpd_fini(rdev);
1627	/* evict remaining vram memory */
 
 
 
1628	radeon_bo_evict_vram(rdev);
1629
1630	radeon_agp_suspend(rdev);
1631
1632	pci_save_state(dev->pdev);
1633	if (suspend) {
 
 
 
1634		/* Shut down the device */
1635		pci_disable_device(dev->pdev);
1636		pci_set_power_state(dev->pdev, PCI_D3hot);
1637	}
1638
1639	if (fbcon) {
1640		console_lock();
1641		radeon_fbdev_set_suspend(rdev, 1);
1642		console_unlock();
1643	}
1644	return 0;
1645}
1646
1647/**
1648 * radeon_resume_kms - initiate device resume
1649 *
1650 * @pdev: drm dev pointer
1651 *
1652 * Bring the hw back to operating state (all asics).
1653 * Returns 0 for success or an error on failure.
1654 * Called at driver resume.
1655 */
1656int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon)
1657{
1658	struct drm_connector *connector;
1659	struct radeon_device *rdev = dev->dev_private;
 
1660	struct drm_crtc *crtc;
1661	int r;
1662
1663	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1664		return 0;
1665
1666	if (fbcon) {
1667		console_lock();
1668	}
1669	if (resume) {
1670		pci_set_power_state(dev->pdev, PCI_D0);
1671		pci_restore_state(dev->pdev);
1672		if (pci_enable_device(dev->pdev)) {
1673			if (fbcon)
1674				console_unlock();
1675			return -1;
1676		}
1677	}
1678	/* resume AGP if in use */
1679	radeon_agp_resume(rdev);
1680	radeon_resume(rdev);
1681
1682	r = radeon_ib_ring_tests(rdev);
1683	if (r)
1684		DRM_ERROR("ib ring test failed (%d).\n", r);
1685
1686	if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
1687		/* do dpm late init */
1688		r = radeon_pm_late_init(rdev);
1689		if (r) {
1690			rdev->pm.dpm_enabled = false;
1691			DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1692		}
1693	} else {
1694		/* resume old pm late */
1695		radeon_pm_resume(rdev);
1696	}
1697
1698	radeon_restore_bios_scratch_regs(rdev);
1699
1700	/* pin cursors */
1701	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1702		struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1703
1704		if (radeon_crtc->cursor_bo) {
1705			struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo);
1706			r = radeon_bo_reserve(robj, false);
1707			if (r == 0) {
1708				/* Only 27 bit offset for legacy cursor */
1709				r = radeon_bo_pin_restricted(robj,
1710							     RADEON_GEM_DOMAIN_VRAM,
1711							     ASIC_IS_AVIVO(rdev) ?
1712							     0 : 1 << 27,
1713							     &radeon_crtc->cursor_addr);
1714				if (r != 0)
1715					DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
1716				radeon_bo_unreserve(robj);
1717			}
1718		}
1719	}
1720
1721	/* init dig PHYs, disp eng pll */
1722	if (rdev->is_atom_bios) {
1723		radeon_atom_encoder_init(rdev);
1724		radeon_atom_disp_eng_pll_init(rdev);
1725		/* turn on the BL */
1726		if (rdev->mode_info.bl_encoder) {
1727			u8 bl_level = radeon_get_backlight_level(rdev,
1728								 rdev->mode_info.bl_encoder);
1729			radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder,
1730						   bl_level);
1731		}
1732	}
1733	/* reset hpd state */
1734	radeon_hpd_init(rdev);
1735	/* blat the mode back in */
1736	if (fbcon) {
1737		drm_helper_resume_force_mode(dev);
1738		/* turn on display hw */
1739		drm_modeset_lock_all(dev);
1740		list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1741			drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
1742		}
1743		drm_modeset_unlock_all(dev);
1744	}
1745
1746	drm_kms_helper_poll_enable(dev);
1747
1748	/* set the power state here in case we are a PX system or headless */
1749	if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
1750		radeon_pm_compute_clocks(rdev);
1751
1752	if (fbcon) {
1753		radeon_fbdev_set_suspend(rdev, 0);
1754		console_unlock();
1755	}
1756
1757	return 0;
1758}
1759
1760/**
1761 * radeon_gpu_reset - reset the asic
1762 *
1763 * @rdev: radeon device pointer
1764 *
1765 * Attempt the reset the GPU if it has hung (all asics).
1766 * Returns 0 for success or an error on failure.
1767 */
1768int radeon_gpu_reset(struct radeon_device *rdev)
1769{
1770	unsigned ring_sizes[RADEON_NUM_RINGS];
1771	uint32_t *ring_data[RADEON_NUM_RINGS];
1772
1773	bool saved = false;
1774
1775	int i, r;
1776	int resched;
1777
1778	down_write(&rdev->exclusive_lock);
1779
1780	if (!rdev->needs_reset) {
1781		up_write(&rdev->exclusive_lock);
1782		return 0;
1783	}
1784
1785	atomic_inc(&rdev->gpu_reset_counter);
1786
1787	radeon_save_bios_scratch_regs(rdev);
1788	/* block TTM */
1789	resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
1790	radeon_suspend(rdev);
1791	radeon_hpd_fini(rdev);
1792
1793	for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1794		ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i],
1795						   &ring_data[i]);
1796		if (ring_sizes[i]) {
1797			saved = true;
1798			dev_info(rdev->dev, "Saved %d dwords of commands "
1799				 "on ring %d.\n", ring_sizes[i], i);
1800		}
1801	}
1802
1803	r = radeon_asic_reset(rdev);
1804	if (!r) {
1805		dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n");
1806		radeon_resume(rdev);
1807	}
1808
1809	radeon_restore_bios_scratch_regs(rdev);
1810
1811	for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1812		if (!r && ring_data[i]) {
1813			radeon_ring_restore(rdev, &rdev->ring[i],
1814					    ring_sizes[i], ring_data[i]);
1815		} else {
1816			radeon_fence_driver_force_completion(rdev, i);
1817			kfree(ring_data[i]);
1818		}
1819	}
1820
1821	if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
1822		/* do dpm late init */
1823		r = radeon_pm_late_init(rdev);
1824		if (r) {
1825			rdev->pm.dpm_enabled = false;
1826			DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1827		}
1828	} else {
1829		/* resume old pm late */
1830		radeon_pm_resume(rdev);
1831	}
1832
1833	/* init dig PHYs, disp eng pll */
1834	if (rdev->is_atom_bios) {
1835		radeon_atom_encoder_init(rdev);
1836		radeon_atom_disp_eng_pll_init(rdev);
1837		/* turn on the BL */
1838		if (rdev->mode_info.bl_encoder) {
1839			u8 bl_level = radeon_get_backlight_level(rdev,
1840								 rdev->mode_info.bl_encoder);
1841			radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder,
1842						   bl_level);
1843		}
1844	}
1845	/* reset hpd state */
1846	radeon_hpd_init(rdev);
1847
1848	ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
1849
1850	rdev->in_reset = true;
1851	rdev->needs_reset = false;
1852
1853	downgrade_write(&rdev->exclusive_lock);
1854
1855	drm_helper_resume_force_mode(rdev->ddev);
1856
1857	/* set the power state here in case we are a PX system or headless */
1858	if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
1859		radeon_pm_compute_clocks(rdev);
1860
1861	if (!r) {
1862		r = radeon_ib_ring_tests(rdev);
1863		if (r && saved)
1864			r = -EAGAIN;
1865	} else {
1866		/* bad news, how to tell it to userspace ? */
1867		dev_info(rdev->dev, "GPU reset failed\n");
1868	}
1869
1870	rdev->needs_reset = r == -EAGAIN;
1871	rdev->in_reset = false;
1872
1873	up_read(&rdev->exclusive_lock);
1874	return r;
1875}
1876
1877
1878/*
1879 * Debugfs
1880 */
1881int radeon_debugfs_add_files(struct radeon_device *rdev,
1882			     struct drm_info_list *files,
1883			     unsigned nfiles)
1884{
1885	unsigned i;
1886
1887	for (i = 0; i < rdev->debugfs_count; i++) {
1888		if (rdev->debugfs[i].files == files) {
1889			/* Already registered */
1890			return 0;
1891		}
1892	}
1893
1894	i = rdev->debugfs_count + 1;
1895	if (i > RADEON_DEBUGFS_MAX_COMPONENTS) {
1896		DRM_ERROR("Reached maximum number of debugfs components.\n");
1897		DRM_ERROR("Report so we increase "
1898			  "RADEON_DEBUGFS_MAX_COMPONENTS.\n");
1899		return -EINVAL;
1900	}
1901	rdev->debugfs[rdev->debugfs_count].files = files;
1902	rdev->debugfs[rdev->debugfs_count].num_files = nfiles;
1903	rdev->debugfs_count = i;
1904#if defined(CONFIG_DEBUG_FS)
1905	drm_debugfs_create_files(files, nfiles,
1906				 rdev->ddev->control->debugfs_root,
1907				 rdev->ddev->control);
1908	drm_debugfs_create_files(files, nfiles,
1909				 rdev->ddev->primary->debugfs_root,
1910				 rdev->ddev->primary);
1911#endif
1912	return 0;
1913}
1914
1915static void radeon_debugfs_remove_files(struct radeon_device *rdev)
1916{
1917#if defined(CONFIG_DEBUG_FS)
1918	unsigned i;
1919
1920	for (i = 0; i < rdev->debugfs_count; i++) {
1921		drm_debugfs_remove_files(rdev->debugfs[i].files,
1922					 rdev->debugfs[i].num_files,
1923					 rdev->ddev->control);
1924		drm_debugfs_remove_files(rdev->debugfs[i].files,
1925					 rdev->debugfs[i].num_files,
1926					 rdev->ddev->primary);
1927	}
1928#endif
1929}
1930
1931#if defined(CONFIG_DEBUG_FS)
1932int radeon_debugfs_init(struct drm_minor *minor)
1933{
1934	return 0;
1935}
1936
1937void radeon_debugfs_cleanup(struct drm_minor *minor)
1938{
1939}
1940#endif