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1/*
2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#include "msm_drv.h"
19#include "msm_mmu.h"
20
21struct msm_iommu {
22 struct msm_mmu base;
23 struct iommu_domain *domain;
24};
25#define to_msm_iommu(x) container_of(x, struct msm_iommu, base)
26
27static int msm_fault_handler(struct iommu_domain *iommu, struct device *dev,
28 unsigned long iova, int flags, void *arg)
29{
30 pr_warn_ratelimited("*** fault: iova=%08lx, flags=%d\n", iova, flags);
31 return 0;
32}
33
34static int msm_iommu_attach(struct msm_mmu *mmu, const char * const *names,
35 int cnt)
36{
37 struct msm_iommu *iommu = to_msm_iommu(mmu);
38 return iommu_attach_device(iommu->domain, mmu->dev);
39}
40
41static void msm_iommu_detach(struct msm_mmu *mmu, const char * const *names,
42 int cnt)
43{
44 struct msm_iommu *iommu = to_msm_iommu(mmu);
45 iommu_detach_device(iommu->domain, mmu->dev);
46}
47
48static int msm_iommu_map(struct msm_mmu *mmu, uint32_t iova,
49 struct sg_table *sgt, unsigned len, int prot)
50{
51 struct msm_iommu *iommu = to_msm_iommu(mmu);
52 struct iommu_domain *domain = iommu->domain;
53 struct scatterlist *sg;
54 unsigned int da = iova;
55 unsigned int i, j;
56 int ret;
57
58 if (!domain || !sgt)
59 return -EINVAL;
60
61 for_each_sg(sgt->sgl, sg, sgt->nents, i) {
62 u32 pa = sg_phys(sg) - sg->offset;
63 size_t bytes = sg->length + sg->offset;
64
65 VERB("map[%d]: %08x %08x(%zx)", i, iova, pa, bytes);
66
67 ret = iommu_map(domain, da, pa, bytes, prot);
68 if (ret)
69 goto fail;
70
71 da += bytes;
72 }
73
74 return 0;
75
76fail:
77 da = iova;
78
79 for_each_sg(sgt->sgl, sg, i, j) {
80 size_t bytes = sg->length + sg->offset;
81 iommu_unmap(domain, da, bytes);
82 da += bytes;
83 }
84 return ret;
85}
86
87static int msm_iommu_unmap(struct msm_mmu *mmu, uint32_t iova,
88 struct sg_table *sgt, unsigned len)
89{
90 struct msm_iommu *iommu = to_msm_iommu(mmu);
91 struct iommu_domain *domain = iommu->domain;
92 struct scatterlist *sg;
93 unsigned int da = iova;
94 int i;
95
96 for_each_sg(sgt->sgl, sg, sgt->nents, i) {
97 size_t bytes = sg->length + sg->offset;
98 size_t unmapped;
99
100 unmapped = iommu_unmap(domain, da, bytes);
101 if (unmapped < bytes)
102 return unmapped;
103
104 VERB("unmap[%d]: %08x(%zx)", i, iova, bytes);
105
106 BUG_ON(!PAGE_ALIGNED(bytes));
107
108 da += bytes;
109 }
110
111 return 0;
112}
113
114static void msm_iommu_destroy(struct msm_mmu *mmu)
115{
116 struct msm_iommu *iommu = to_msm_iommu(mmu);
117 iommu_domain_free(iommu->domain);
118 kfree(iommu);
119}
120
121static const struct msm_mmu_funcs funcs = {
122 .attach = msm_iommu_attach,
123 .detach = msm_iommu_detach,
124 .map = msm_iommu_map,
125 .unmap = msm_iommu_unmap,
126 .destroy = msm_iommu_destroy,
127};
128
129struct msm_mmu *msm_iommu_new(struct device *dev, struct iommu_domain *domain)
130{
131 struct msm_iommu *iommu;
132
133 iommu = kzalloc(sizeof(*iommu), GFP_KERNEL);
134 if (!iommu)
135 return ERR_PTR(-ENOMEM);
136
137 iommu->domain = domain;
138 msm_mmu_init(&iommu->base, dev, &funcs);
139 iommu_set_fault_handler(domain, msm_fault_handler, dev);
140
141 return &iommu->base;
142}
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
5 */
6
7#include <linux/adreno-smmu-priv.h>
8#include <linux/io-pgtable.h>
9#include "msm_drv.h"
10#include "msm_mmu.h"
11
12struct msm_iommu {
13 struct msm_mmu base;
14 struct iommu_domain *domain;
15 atomic_t pagetables;
16};
17
18#define to_msm_iommu(x) container_of(x, struct msm_iommu, base)
19
20struct msm_iommu_pagetable {
21 struct msm_mmu base;
22 struct msm_mmu *parent;
23 struct io_pgtable_ops *pgtbl_ops;
24 unsigned long pgsize_bitmap; /* Bitmap of page sizes in use */
25 phys_addr_t ttbr;
26 u32 asid;
27};
28static struct msm_iommu_pagetable *to_pagetable(struct msm_mmu *mmu)
29{
30 return container_of(mmu, struct msm_iommu_pagetable, base);
31}
32
33/* based on iommu_pgsize() in iommu.c: */
34static size_t calc_pgsize(struct msm_iommu_pagetable *pagetable,
35 unsigned long iova, phys_addr_t paddr,
36 size_t size, size_t *count)
37{
38 unsigned int pgsize_idx, pgsize_idx_next;
39 unsigned long pgsizes;
40 size_t offset, pgsize, pgsize_next;
41 unsigned long addr_merge = paddr | iova;
42
43 /* Page sizes supported by the hardware and small enough for @size */
44 pgsizes = pagetable->pgsize_bitmap & GENMASK(__fls(size), 0);
45
46 /* Constrain the page sizes further based on the maximum alignment */
47 if (likely(addr_merge))
48 pgsizes &= GENMASK(__ffs(addr_merge), 0);
49
50 /* Make sure we have at least one suitable page size */
51 BUG_ON(!pgsizes);
52
53 /* Pick the biggest page size remaining */
54 pgsize_idx = __fls(pgsizes);
55 pgsize = BIT(pgsize_idx);
56 if (!count)
57 return pgsize;
58
59 /* Find the next biggest support page size, if it exists */
60 pgsizes = pagetable->pgsize_bitmap & ~GENMASK(pgsize_idx, 0);
61 if (!pgsizes)
62 goto out_set_count;
63
64 pgsize_idx_next = __ffs(pgsizes);
65 pgsize_next = BIT(pgsize_idx_next);
66
67 /*
68 * There's no point trying a bigger page size unless the virtual
69 * and physical addresses are similarly offset within the larger page.
70 */
71 if ((iova ^ paddr) & (pgsize_next - 1))
72 goto out_set_count;
73
74 /* Calculate the offset to the next page size alignment boundary */
75 offset = pgsize_next - (addr_merge & (pgsize_next - 1));
76
77 /*
78 * If size is big enough to accommodate the larger page, reduce
79 * the number of smaller pages.
80 */
81 if (offset + pgsize_next <= size)
82 size = offset;
83
84out_set_count:
85 *count = size >> pgsize_idx;
86 return pgsize;
87}
88
89static int msm_iommu_pagetable_unmap(struct msm_mmu *mmu, u64 iova,
90 size_t size)
91{
92 struct msm_iommu_pagetable *pagetable = to_pagetable(mmu);
93 struct io_pgtable_ops *ops = pagetable->pgtbl_ops;
94
95 while (size) {
96 size_t unmapped, pgsize, count;
97
98 pgsize = calc_pgsize(pagetable, iova, iova, size, &count);
99
100 unmapped = ops->unmap_pages(ops, iova, pgsize, count, NULL);
101 if (!unmapped)
102 break;
103
104 iova += unmapped;
105 size -= unmapped;
106 }
107
108 iommu_flush_iotlb_all(to_msm_iommu(pagetable->parent)->domain);
109
110 return (size == 0) ? 0 : -EINVAL;
111}
112
113static int msm_iommu_pagetable_map(struct msm_mmu *mmu, u64 iova,
114 struct sg_table *sgt, size_t len, int prot)
115{
116 struct msm_iommu_pagetable *pagetable = to_pagetable(mmu);
117 struct io_pgtable_ops *ops = pagetable->pgtbl_ops;
118 struct scatterlist *sg;
119 u64 addr = iova;
120 unsigned int i;
121
122 for_each_sgtable_sg(sgt, sg, i) {
123 size_t size = sg->length;
124 phys_addr_t phys = sg_phys(sg);
125
126 while (size) {
127 size_t pgsize, count, mapped = 0;
128 int ret;
129
130 pgsize = calc_pgsize(pagetable, addr, phys, size, &count);
131
132 ret = ops->map_pages(ops, addr, phys, pgsize, count,
133 prot, GFP_KERNEL, &mapped);
134
135 /* map_pages could fail after mapping some of the pages,
136 * so update the counters before error handling.
137 */
138 phys += mapped;
139 addr += mapped;
140 size -= mapped;
141
142 if (ret) {
143 msm_iommu_pagetable_unmap(mmu, iova, addr - iova);
144 return -EINVAL;
145 }
146 }
147 }
148
149 return 0;
150}
151
152static void msm_iommu_pagetable_destroy(struct msm_mmu *mmu)
153{
154 struct msm_iommu_pagetable *pagetable = to_pagetable(mmu);
155 struct msm_iommu *iommu = to_msm_iommu(pagetable->parent);
156 struct adreno_smmu_priv *adreno_smmu =
157 dev_get_drvdata(pagetable->parent->dev);
158
159 /*
160 * If this is the last attached pagetable for the parent,
161 * disable TTBR0 in the arm-smmu driver
162 */
163 if (atomic_dec_return(&iommu->pagetables) == 0)
164 adreno_smmu->set_ttbr0_cfg(adreno_smmu->cookie, NULL);
165
166 free_io_pgtable_ops(pagetable->pgtbl_ops);
167 kfree(pagetable);
168}
169
170int msm_iommu_pagetable_params(struct msm_mmu *mmu,
171 phys_addr_t *ttbr, int *asid)
172{
173 struct msm_iommu_pagetable *pagetable;
174
175 if (mmu->type != MSM_MMU_IOMMU_PAGETABLE)
176 return -EINVAL;
177
178 pagetable = to_pagetable(mmu);
179
180 if (ttbr)
181 *ttbr = pagetable->ttbr;
182
183 if (asid)
184 *asid = pagetable->asid;
185
186 return 0;
187}
188
189struct iommu_domain_geometry *msm_iommu_get_geometry(struct msm_mmu *mmu)
190{
191 struct msm_iommu *iommu = to_msm_iommu(mmu);
192
193 return &iommu->domain->geometry;
194}
195
196static const struct msm_mmu_funcs pagetable_funcs = {
197 .map = msm_iommu_pagetable_map,
198 .unmap = msm_iommu_pagetable_unmap,
199 .destroy = msm_iommu_pagetable_destroy,
200};
201
202static void msm_iommu_tlb_flush_all(void *cookie)
203{
204}
205
206static void msm_iommu_tlb_flush_walk(unsigned long iova, size_t size,
207 size_t granule, void *cookie)
208{
209}
210
211static void msm_iommu_tlb_add_page(struct iommu_iotlb_gather *gather,
212 unsigned long iova, size_t granule, void *cookie)
213{
214}
215
216static const struct iommu_flush_ops null_tlb_ops = {
217 .tlb_flush_all = msm_iommu_tlb_flush_all,
218 .tlb_flush_walk = msm_iommu_tlb_flush_walk,
219 .tlb_add_page = msm_iommu_tlb_add_page,
220};
221
222static int msm_fault_handler(struct iommu_domain *domain, struct device *dev,
223 unsigned long iova, int flags, void *arg);
224
225struct msm_mmu *msm_iommu_pagetable_create(struct msm_mmu *parent)
226{
227 struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(parent->dev);
228 struct msm_iommu *iommu = to_msm_iommu(parent);
229 struct msm_iommu_pagetable *pagetable;
230 const struct io_pgtable_cfg *ttbr1_cfg = NULL;
231 struct io_pgtable_cfg ttbr0_cfg;
232 int ret;
233
234 /* Get the pagetable configuration from the domain */
235 if (adreno_smmu->cookie)
236 ttbr1_cfg = adreno_smmu->get_ttbr1_cfg(adreno_smmu->cookie);
237 if (!ttbr1_cfg)
238 return ERR_PTR(-ENODEV);
239
240 /*
241 * Defer setting the fault handler until we have a valid adreno_smmu
242 * to avoid accidentially installing a GPU specific fault handler for
243 * the display's iommu
244 */
245 iommu_set_fault_handler(iommu->domain, msm_fault_handler, iommu);
246
247 pagetable = kzalloc(sizeof(*pagetable), GFP_KERNEL);
248 if (!pagetable)
249 return ERR_PTR(-ENOMEM);
250
251 msm_mmu_init(&pagetable->base, parent->dev, &pagetable_funcs,
252 MSM_MMU_IOMMU_PAGETABLE);
253
254 /* Clone the TTBR1 cfg as starting point for TTBR0 cfg: */
255 ttbr0_cfg = *ttbr1_cfg;
256
257 /* The incoming cfg will have the TTBR1 quirk enabled */
258 ttbr0_cfg.quirks &= ~IO_PGTABLE_QUIRK_ARM_TTBR1;
259 ttbr0_cfg.tlb = &null_tlb_ops;
260
261 pagetable->pgtbl_ops = alloc_io_pgtable_ops(ARM_64_LPAE_S1,
262 &ttbr0_cfg, iommu->domain);
263
264 if (!pagetable->pgtbl_ops) {
265 kfree(pagetable);
266 return ERR_PTR(-ENOMEM);
267 }
268
269 /*
270 * If this is the first pagetable that we've allocated, send it back to
271 * the arm-smmu driver as a trigger to set up TTBR0
272 */
273 if (atomic_inc_return(&iommu->pagetables) == 1) {
274 /* Enable stall on iommu fault: */
275 adreno_smmu->set_stall(adreno_smmu->cookie, true);
276
277 ret = adreno_smmu->set_ttbr0_cfg(adreno_smmu->cookie, &ttbr0_cfg);
278 if (ret) {
279 free_io_pgtable_ops(pagetable->pgtbl_ops);
280 kfree(pagetable);
281 return ERR_PTR(ret);
282 }
283 }
284
285 /* Needed later for TLB flush */
286 pagetable->parent = parent;
287 pagetable->pgsize_bitmap = ttbr0_cfg.pgsize_bitmap;
288 pagetable->ttbr = ttbr0_cfg.arm_lpae_s1_cfg.ttbr;
289
290 /*
291 * TODO we would like each set of page tables to have a unique ASID
292 * to optimize TLB invalidation. But iommu_flush_iotlb_all() will
293 * end up flushing the ASID used for TTBR1 pagetables, which is not
294 * what we want. So for now just use the same ASID as TTBR1.
295 */
296 pagetable->asid = 0;
297
298 return &pagetable->base;
299}
300
301static int msm_fault_handler(struct iommu_domain *domain, struct device *dev,
302 unsigned long iova, int flags, void *arg)
303{
304 struct msm_iommu *iommu = arg;
305 struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(iommu->base.dev);
306 struct adreno_smmu_fault_info info, *ptr = NULL;
307
308 if (adreno_smmu->get_fault_info) {
309 adreno_smmu->get_fault_info(adreno_smmu->cookie, &info);
310 ptr = &info;
311 }
312
313 if (iommu->base.handler)
314 return iommu->base.handler(iommu->base.arg, iova, flags, ptr);
315
316 pr_warn_ratelimited("*** fault: iova=%16lx, flags=%d\n", iova, flags);
317 return 0;
318}
319
320static void msm_iommu_resume_translation(struct msm_mmu *mmu)
321{
322 struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(mmu->dev);
323
324 adreno_smmu->resume_translation(adreno_smmu->cookie, true);
325}
326
327static void msm_iommu_detach(struct msm_mmu *mmu)
328{
329 struct msm_iommu *iommu = to_msm_iommu(mmu);
330
331 iommu_detach_device(iommu->domain, mmu->dev);
332}
333
334static int msm_iommu_map(struct msm_mmu *mmu, uint64_t iova,
335 struct sg_table *sgt, size_t len, int prot)
336{
337 struct msm_iommu *iommu = to_msm_iommu(mmu);
338 size_t ret;
339
340 /* The arm-smmu driver expects the addresses to be sign extended */
341 if (iova & BIT_ULL(48))
342 iova |= GENMASK_ULL(63, 49);
343
344 ret = iommu_map_sgtable(iommu->domain, iova, sgt, prot);
345 WARN_ON(!ret);
346
347 return (ret == len) ? 0 : -EINVAL;
348}
349
350static int msm_iommu_unmap(struct msm_mmu *mmu, uint64_t iova, size_t len)
351{
352 struct msm_iommu *iommu = to_msm_iommu(mmu);
353
354 if (iova & BIT_ULL(48))
355 iova |= GENMASK_ULL(63, 49);
356
357 iommu_unmap(iommu->domain, iova, len);
358
359 return 0;
360}
361
362static void msm_iommu_destroy(struct msm_mmu *mmu)
363{
364 struct msm_iommu *iommu = to_msm_iommu(mmu);
365 iommu_domain_free(iommu->domain);
366 kfree(iommu);
367}
368
369static const struct msm_mmu_funcs funcs = {
370 .detach = msm_iommu_detach,
371 .map = msm_iommu_map,
372 .unmap = msm_iommu_unmap,
373 .destroy = msm_iommu_destroy,
374 .resume_translation = msm_iommu_resume_translation,
375};
376
377struct msm_mmu *msm_iommu_new(struct device *dev, unsigned long quirks)
378{
379 struct iommu_domain *domain;
380 struct msm_iommu *iommu;
381 int ret;
382
383 domain = iommu_domain_alloc(dev->bus);
384 if (!domain)
385 return NULL;
386
387 iommu_set_pgtable_quirks(domain, quirks);
388
389 iommu = kzalloc(sizeof(*iommu), GFP_KERNEL);
390 if (!iommu) {
391 iommu_domain_free(domain);
392 return ERR_PTR(-ENOMEM);
393 }
394
395 iommu->domain = domain;
396 msm_mmu_init(&iommu->base, dev, &funcs, MSM_MMU_IOMMU);
397
398 atomic_set(&iommu->pagetables, 0);
399
400 ret = iommu_attach_device(iommu->domain, dev);
401 if (ret) {
402 iommu_domain_free(domain);
403 kfree(iommu);
404 return ERR_PTR(ret);
405 }
406
407 return &iommu->base;
408}