1// SPDX-License-Identifier: MIT
  2/*
  3 * Copyright © 2019 Intel Corporation
  4 */
  5
  6#include "gt/intel_engine_pm.h"
  7#include "gt/intel_gpu_commands.h"
  8#include "i915_selftest.h"
  9
 10#include "gem/selftests/igt_gem_utils.h"
 11#include "gem/selftests/mock_context.h"
 12#include "selftests/igt_reset.h"
 13#include "selftests/igt_spinner.h"
 14#include "selftests/intel_scheduler_helpers.h"
 15
 16struct live_mocs {
 17	struct drm_i915_mocs_table table;
 18	struct drm_i915_mocs_table *mocs;
 19	struct drm_i915_mocs_table *l3cc;
 20	struct i915_vma *scratch;
 21	void *vaddr;
 22};
 23
 24static struct intel_context *mocs_context_create(struct intel_engine_cs *engine)
 25{
 26	struct intel_context *ce;
 27
 28	ce = intel_context_create(engine);
 29	if (IS_ERR(ce))
 30		return ce;
 31
 32	/* We build large requests to read the registers from the ring */
 33	ce->ring_size = SZ_16K;
 34
 35	return ce;
 36}
 37
 38static int request_add_sync(struct i915_request *rq, int err)
 39{
 40	i915_request_get(rq);
 41	i915_request_add(rq);
 42	if (i915_request_wait(rq, 0, HZ / 5) < 0)
 43		err = -ETIME;
 44	i915_request_put(rq);
 45
 46	return err;
 47}
 48
 49static int request_add_spin(struct i915_request *rq, struct igt_spinner *spin)
 50{
 51	int err = 0;
 52
 53	i915_request_get(rq);
 54	i915_request_add(rq);
 55	if (spin && !igt_wait_for_spinner(spin, rq))
 56		err = -ETIME;
 57	i915_request_put(rq);
 58
 59	return err;
 60}
 61
 62static int live_mocs_init(struct live_mocs *arg, struct intel_gt *gt)
 63{
 64	unsigned int flags;
 65	int err;
 66
 67	memset(arg, 0, sizeof(*arg));
 68
 69	flags = get_mocs_settings(gt->i915, &arg->table);
 70	if (!flags)
 71		return -EINVAL;
 72
 73	if (flags & HAS_RENDER_L3CC)
 74		arg->l3cc = &arg->table;
 75
 76	if (flags & (HAS_GLOBAL_MOCS | HAS_ENGINE_MOCS))
 77		arg->mocs = &arg->table;
 78
 79	arg->scratch =
 80		__vm_create_scratch_for_read_pinned(&gt->ggtt->vm, PAGE_SIZE);
 81	if (IS_ERR(arg->scratch))
 82		return PTR_ERR(arg->scratch);
 83
 84	arg->vaddr = i915_gem_object_pin_map_unlocked(arg->scratch->obj, I915_MAP_WB);
 85	if (IS_ERR(arg->vaddr)) {
 86		err = PTR_ERR(arg->vaddr);
 87		goto err_scratch;
 88	}
 89
 90	return 0;
 91
 92err_scratch:
 93	i915_vma_unpin_and_release(&arg->scratch, 0);
 94	return err;
 95}
 96
 97static void live_mocs_fini(struct live_mocs *arg)
 98{
 99	i915_vma_unpin_and_release(&arg->scratch, I915_VMA_RELEASE_MAP);
100}
101
102static int read_regs(struct i915_request *rq,
103		     u32 addr, unsigned int count,
104		     u32 *offset)
105{
106	unsigned int i;
107	u32 *cs;
108
109	GEM_BUG_ON(!IS_ALIGNED(*offset, sizeof(u32)));
110
111	cs = intel_ring_begin(rq, 4 * count);
112	if (IS_ERR(cs))
113		return PTR_ERR(cs);
114
115	for (i = 0; i < count; i++) {
116		*cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;
117		*cs++ = addr;
118		*cs++ = *offset;
119		*cs++ = 0;
120
121		addr += sizeof(u32);
122		*offset += sizeof(u32);
123	}
124
125	intel_ring_advance(rq, cs);
126
127	return 0;
128}
129
130static int read_mocs_table(struct i915_request *rq,
131			   const struct drm_i915_mocs_table *table,
132			   u32 *offset)
133{
134	u32 addr;
135
136	if (!table)
137		return 0;
138
139	if (HAS_GLOBAL_MOCS_REGISTERS(rq->engine->i915))
140		addr = global_mocs_offset();
141	else
142		addr = mocs_offset(rq->engine);
143
144	return read_regs(rq, addr, table->n_entries, offset);
145}
146
147static int read_l3cc_table(struct i915_request *rq,
148			   const struct drm_i915_mocs_table *table,
149			   u32 *offset)
150{
151	u32 addr = i915_mmio_reg_offset(GEN9_LNCFCMOCS(0));
152
153	if (!table)
154		return 0;
155
156	return read_regs(rq, addr, (table->n_entries + 1) / 2, offset);
157}
158
159static int check_mocs_table(struct intel_engine_cs *engine,
160			    const struct drm_i915_mocs_table *table,
161			    u32 **vaddr)
162{
163	unsigned int i;
164	u32 expect;
165
166	if (!table)
167		return 0;
168
169	for_each_mocs(expect, table, i) {
170		if (**vaddr != expect) {
171			pr_err("%s: Invalid MOCS[%d] entry, found %08x, expected %08x\n",
172			       engine->name, i, **vaddr, expect);
173			return -EINVAL;
174		}
175		++*vaddr;
176	}
177
178	return 0;
179}
180
181static bool mcr_range(struct drm_i915_private *i915, u32 offset)
182{
183	/*
184	 * Registers in this range are affected by the MCR selector
185	 * which only controls CPU initiated MMIO. Routing does not
186	 * work for CS access so we cannot verify them on this path.
187	 */
188	return GRAPHICS_VER(i915) >= 8 && offset >= 0xb000 && offset <= 0xb4ff;
189}
190
191static int check_l3cc_table(struct intel_engine_cs *engine,
192			    const struct drm_i915_mocs_table *table,
193			    u32 **vaddr)
194{
195	/* Can we read the MCR range 0xb00 directly? See intel_workarounds! */
196	u32 reg = i915_mmio_reg_offset(GEN9_LNCFCMOCS(0));
197	unsigned int i;
198	u32 expect;
199
200	if (!table)
201		return 0;
202
203	for_each_l3cc(expect, table, i) {
204		if (!mcr_range(engine->i915, reg) && **vaddr != expect) {
205			pr_err("%s: Invalid L3CC[%d] entry, found %08x, expected %08x\n",
206			       engine->name, i, **vaddr, expect);
207			return -EINVAL;
208		}
209		++*vaddr;
210		reg += 4;
211	}
212
213	return 0;
214}
215
216static int check_mocs_engine(struct live_mocs *arg,
217			     struct intel_context *ce)
218{
219	struct i915_vma *vma = arg->scratch;
220	struct i915_request *rq;
221	u32 offset;
222	u32 *vaddr;
223	int err;
224
225	memset32(arg->vaddr, STACK_MAGIC, PAGE_SIZE / sizeof(u32));
226
227	rq = intel_context_create_request(ce);
228	if (IS_ERR(rq))
229		return PTR_ERR(rq);
230
231	i915_vma_lock(vma);
232	err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
233	i915_vma_unlock(vma);
234
235	/* Read the mocs tables back using SRM */
236	offset = i915_ggtt_offset(vma);
237	if (!err)
238		err = read_mocs_table(rq, arg->mocs, &offset);
239	if (!err && ce->engine->class == RENDER_CLASS)
240		err = read_l3cc_table(rq, arg->l3cc, &offset);
241	offset -= i915_ggtt_offset(vma);
242	GEM_BUG_ON(offset > PAGE_SIZE);
243
244	err = request_add_sync(rq, err);
245	if (err)
246		return err;
247
248	/* Compare the results against the expected tables */
249	vaddr = arg->vaddr;
250	if (!err)
251		err = check_mocs_table(ce->engine, arg->mocs, &vaddr);
252	if (!err && ce->engine->class == RENDER_CLASS)
253		err = check_l3cc_table(ce->engine, arg->l3cc, &vaddr);
254	if (err)
255		return err;
256
257	GEM_BUG_ON(arg->vaddr + offset != vaddr);
258	return 0;
259}
260
261static int live_mocs_kernel(void *arg)
262{
263	struct intel_gt *gt = arg;
264	struct intel_engine_cs *engine;
265	enum intel_engine_id id;
266	struct live_mocs mocs;
267	int err;
268
269	/* Basic check the system is configured with the expected mocs table */
270
271	err = live_mocs_init(&mocs, gt);
272	if (err)
273		return err;
274
275	for_each_engine(engine, gt, id) {
276		intel_engine_pm_get(engine);
277		err = check_mocs_engine(&mocs, engine->kernel_context);
278		intel_engine_pm_put(engine);
279		if (err)
280			break;
281	}
282
283	live_mocs_fini(&mocs);
284	return err;
285}
286
287static int live_mocs_clean(void *arg)
288{
289	struct intel_gt *gt = arg;
290	struct intel_engine_cs *engine;
291	enum intel_engine_id id;
292	struct live_mocs mocs;
293	int err;
294
295	/* Every new context should see the same mocs table */
296
297	err = live_mocs_init(&mocs, gt);
298	if (err)
299		return err;
300
301	for_each_engine(engine, gt, id) {
302		struct intel_context *ce;
303
304		ce = mocs_context_create(engine);
305		if (IS_ERR(ce)) {
306			err = PTR_ERR(ce);
307			break;
308		}
309
310		err = check_mocs_engine(&mocs, ce);
311		intel_context_put(ce);
312		if (err)
313			break;
314	}
315
316	live_mocs_fini(&mocs);
317	return err;
318}
319
320static int active_engine_reset(struct intel_context *ce,
321			       const char *reason,
322			       bool using_guc)
323{
324	struct igt_spinner spin;
325	struct i915_request *rq;
326	int err;
327
328	err = igt_spinner_init(&spin, ce->engine->gt);
329	if (err)
330		return err;
331
332	rq = igt_spinner_create_request(&spin, ce, MI_NOOP);
333	if (IS_ERR(rq)) {
334		igt_spinner_fini(&spin);
335		return PTR_ERR(rq);
336	}
337
338	err = request_add_spin(rq, &spin);
339	if (err == 0 && !using_guc)
340		err = intel_engine_reset(ce->engine, reason);
341
342	/* Ensure the reset happens and kills the engine */
343	if (err == 0)
344		err = intel_selftest_wait_for_rq(rq);
345
346	igt_spinner_end(&spin);
347	igt_spinner_fini(&spin);
348
349	return err;
350}
351
352static int __live_mocs_reset(struct live_mocs *mocs,
353			     struct intel_context *ce, bool using_guc)
354{
355	struct intel_gt *gt = ce->engine->gt;
356	int err;
357
358	if (intel_has_reset_engine(gt)) {
359		if (!using_guc) {
360			err = intel_engine_reset(ce->engine, "mocs");
361			if (err)
362				return err;
363
364			err = check_mocs_engine(mocs, ce);
365			if (err)
366				return err;
367		}
368
369		err = active_engine_reset(ce, "mocs", using_guc);
370		if (err)
371			return err;
372
373		err = check_mocs_engine(mocs, ce);
374		if (err)
375			return err;
376	}
377
378	if (intel_has_gpu_reset(gt)) {
379		intel_gt_reset(gt, ce->engine->mask, "mocs");
380
381		err = check_mocs_engine(mocs, ce);
382		if (err)
383			return err;
384	}
385
386	return 0;
387}
388
389static int live_mocs_reset(void *arg)
390{
391	struct intel_gt *gt = arg;
392	struct intel_engine_cs *engine;
393	enum intel_engine_id id;
394	struct live_mocs mocs;
395	int err = 0;
396
397	/* Check the mocs setup is retained over per-engine and global resets */
398
399	err = live_mocs_init(&mocs, gt);
400	if (err)
401		return err;
402
403	igt_global_reset_lock(gt);
404	for_each_engine(engine, gt, id) {
405		bool using_guc = intel_engine_uses_guc(engine);
406		struct intel_selftest_saved_policy saved;
407		struct intel_context *ce;
408		int err2;
409
410		err = intel_selftest_modify_policy(engine, &saved,
411						   SELFTEST_SCHEDULER_MODIFY_FAST_RESET);
412		if (err)
413			break;
414
415		ce = mocs_context_create(engine);
416		if (IS_ERR(ce)) {
417			err = PTR_ERR(ce);
418			goto restore;
419		}
420
421		intel_engine_pm_get(engine);
422
423		err = __live_mocs_reset(&mocs, ce, using_guc);
424
425		intel_engine_pm_put(engine);
426		intel_context_put(ce);
427
428restore:
429		err2 = intel_selftest_restore_policy(engine, &saved);
430		if (err == 0)
431			err = err2;
432		if (err)
433			break;
434	}
435	igt_global_reset_unlock(gt);
436
437	live_mocs_fini(&mocs);
438	return err;
439}
440
441int intel_mocs_live_selftests(struct drm_i915_private *i915)
442{
443	static const struct i915_subtest tests[] = {
444		SUBTEST(live_mocs_kernel),
445		SUBTEST(live_mocs_clean),
446		SUBTEST(live_mocs_reset),
447	};
448	struct drm_i915_mocs_table table;
449
450	if (!get_mocs_settings(i915, &table))
451		return 0;
452
453	return intel_gt_live_subtests(tests, to_gt(i915));
454}