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1/*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24/**
25 * DOC: Frame Buffer Compression (FBC)
26 *
27 * FBC tries to save memory bandwidth (and so power consumption) by
28 * compressing the amount of memory used by the display. It is total
29 * transparent to user space and completely handled in the kernel.
30 *
31 * The benefits of FBC are mostly visible with solid backgrounds and
32 * variation-less patterns. It comes from keeping the memory footprint small
33 * and having fewer memory pages opened and accessed for refreshing the display.
34 *
35 * i915 is responsible to reserve stolen memory for FBC and configure its
36 * offset on proper registers. The hardware takes care of all
37 * compress/decompress. However there are many known cases where we have to
38 * forcibly disable it to allow proper screen updates.
39 */
40
41#include <linux/string_helpers.h>
42
43#include <drm/drm_blend.h>
44#include <drm/drm_fourcc.h>
45
46#include "i915_drv.h"
47#include "i915_utils.h"
48#include "i915_vgpu.h"
49#include "intel_cdclk.h"
50#include "intel_de.h"
51#include "intel_display_trace.h"
52#include "intel_display_types.h"
53#include "intel_fbc.h"
54#include "intel_frontbuffer.h"
55
56#define for_each_fbc_id(__dev_priv, __fbc_id) \
57 for ((__fbc_id) = INTEL_FBC_A; (__fbc_id) < I915_MAX_FBCS; (__fbc_id)++) \
58 for_each_if(RUNTIME_INFO(__dev_priv)->fbc_mask & BIT(__fbc_id))
59
60#define for_each_intel_fbc(__dev_priv, __fbc, __fbc_id) \
61 for_each_fbc_id((__dev_priv), (__fbc_id)) \
62 for_each_if((__fbc) = (__dev_priv)->display.fbc[(__fbc_id)])
63
64struct intel_fbc_funcs {
65 void (*activate)(struct intel_fbc *fbc);
66 void (*deactivate)(struct intel_fbc *fbc);
67 bool (*is_active)(struct intel_fbc *fbc);
68 bool (*is_compressing)(struct intel_fbc *fbc);
69 void (*nuke)(struct intel_fbc *fbc);
70 void (*program_cfb)(struct intel_fbc *fbc);
71 void (*set_false_color)(struct intel_fbc *fbc, bool enable);
72};
73
74struct intel_fbc_state {
75 struct intel_plane *plane;
76 unsigned int cfb_stride;
77 unsigned int cfb_size;
78 unsigned int fence_y_offset;
79 u16 override_cfb_stride;
80 u16 interval;
81 s8 fence_id;
82};
83
84struct intel_fbc {
85 struct drm_i915_private *i915;
86 const struct intel_fbc_funcs *funcs;
87
88 /*
89 * This is always the inner lock when overlapping with
90 * struct_mutex and it's the outer lock when overlapping
91 * with stolen_lock.
92 */
93 struct mutex lock;
94 unsigned int busy_bits;
95
96 struct drm_mm_node compressed_fb;
97 struct drm_mm_node compressed_llb;
98
99 enum intel_fbc_id id;
100
101 u8 limit;
102
103 bool false_color;
104
105 bool active;
106 bool activated;
107 bool flip_pending;
108
109 bool underrun_detected;
110 struct work_struct underrun_work;
111
112 /*
113 * This structure contains everything that's relevant to program the
114 * hardware registers. When we want to figure out if we need to disable
115 * and re-enable FBC for a new configuration we just check if there's
116 * something different in the struct. The genx_fbc_activate functions
117 * are supposed to read from it in order to program the registers.
118 */
119 struct intel_fbc_state state;
120 const char *no_fbc_reason;
121};
122
123/* plane stride in pixels */
124static unsigned int intel_fbc_plane_stride(const struct intel_plane_state *plane_state)
125{
126 const struct drm_framebuffer *fb = plane_state->hw.fb;
127 unsigned int stride;
128
129 stride = plane_state->view.color_plane[0].mapping_stride;
130 if (!drm_rotation_90_or_270(plane_state->hw.rotation))
131 stride /= fb->format->cpp[0];
132
133 return stride;
134}
135
136/* plane stride based cfb stride in bytes, assuming 1:1 compression limit */
137static unsigned int _intel_fbc_cfb_stride(const struct intel_plane_state *plane_state)
138{
139 unsigned int cpp = 4; /* FBC always 4 bytes per pixel */
140
141 return intel_fbc_plane_stride(plane_state) * cpp;
142}
143
144/* minimum acceptable cfb stride in bytes, assuming 1:1 compression limit */
145static unsigned int skl_fbc_min_cfb_stride(const struct intel_plane_state *plane_state)
146{
147 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
148 unsigned int limit = 4; /* 1:4 compression limit is the worst case */
149 unsigned int cpp = 4; /* FBC always 4 bytes per pixel */
150 unsigned int width = drm_rect_width(&plane_state->uapi.src) >> 16;
151 unsigned int height = 4; /* FBC segment is 4 lines */
152 unsigned int stride;
153
154 /* minimum segment stride we can use */
155 stride = width * cpp * height / limit;
156
157 /*
158 * Wa_16011863758: icl+
159 * Avoid some hardware segment address miscalculation.
160 */
161 if (DISPLAY_VER(i915) >= 11)
162 stride += 64;
163
164 /*
165 * At least some of the platforms require each 4 line segment to
166 * be 512 byte aligned. Just do it always for simplicity.
167 */
168 stride = ALIGN(stride, 512);
169
170 /* convert back to single line equivalent with 1:1 compression limit */
171 return stride * limit / height;
172}
173
174/* properly aligned cfb stride in bytes, assuming 1:1 compression limit */
175static unsigned int intel_fbc_cfb_stride(const struct intel_plane_state *plane_state)
176{
177 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
178 unsigned int stride = _intel_fbc_cfb_stride(plane_state);
179
180 /*
181 * At least some of the platforms require each 4 line segment to
182 * be 512 byte aligned. Aligning each line to 512 bytes guarantees
183 * that regardless of the compression limit we choose later.
184 */
185 if (DISPLAY_VER(i915) >= 9)
186 return max(ALIGN(stride, 512), skl_fbc_min_cfb_stride(plane_state));
187 else
188 return stride;
189}
190
191static unsigned int intel_fbc_cfb_size(const struct intel_plane_state *plane_state)
192{
193 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
194 int lines = drm_rect_height(&plane_state->uapi.src) >> 16;
195
196 if (DISPLAY_VER(i915) == 7)
197 lines = min(lines, 2048);
198 else if (DISPLAY_VER(i915) >= 8)
199 lines = min(lines, 2560);
200
201 return lines * intel_fbc_cfb_stride(plane_state);
202}
203
204static u16 intel_fbc_override_cfb_stride(const struct intel_plane_state *plane_state)
205{
206 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
207 unsigned int stride_aligned = intel_fbc_cfb_stride(plane_state);
208 unsigned int stride = _intel_fbc_cfb_stride(plane_state);
209 const struct drm_framebuffer *fb = plane_state->hw.fb;
210
211 /*
212 * Override stride in 64 byte units per 4 line segment.
213 *
214 * Gen9 hw miscalculates cfb stride for linear as
215 * PLANE_STRIDE*512 instead of PLANE_STRIDE*64, so
216 * we always need to use the override there.
217 */
218 if (stride != stride_aligned ||
219 (DISPLAY_VER(i915) == 9 && fb->modifier == DRM_FORMAT_MOD_LINEAR))
220 return stride_aligned * 4 / 64;
221
222 return 0;
223}
224
225static u32 i8xx_fbc_ctl(struct intel_fbc *fbc)
226{
227 const struct intel_fbc_state *fbc_state = &fbc->state;
228 struct drm_i915_private *i915 = fbc->i915;
229 unsigned int cfb_stride;
230 u32 fbc_ctl;
231
232 cfb_stride = fbc_state->cfb_stride / fbc->limit;
233
234 /* FBC_CTL wants 32B or 64B units */
235 if (DISPLAY_VER(i915) == 2)
236 cfb_stride = (cfb_stride / 32) - 1;
237 else
238 cfb_stride = (cfb_stride / 64) - 1;
239
240 fbc_ctl = FBC_CTL_PERIODIC |
241 FBC_CTL_INTERVAL(fbc_state->interval) |
242 FBC_CTL_STRIDE(cfb_stride);
243
244 if (IS_I945GM(i915))
245 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
246
247 if (fbc_state->fence_id >= 0)
248 fbc_ctl |= FBC_CTL_FENCENO(fbc_state->fence_id);
249
250 return fbc_ctl;
251}
252
253static u32 i965_fbc_ctl2(struct intel_fbc *fbc)
254{
255 const struct intel_fbc_state *fbc_state = &fbc->state;
256 u32 fbc_ctl2;
257
258 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM |
259 FBC_CTL_PLANE(fbc_state->plane->i9xx_plane);
260
261 if (fbc_state->fence_id >= 0)
262 fbc_ctl2 |= FBC_CTL_CPU_FENCE_EN;
263
264 return fbc_ctl2;
265}
266
267static void i8xx_fbc_deactivate(struct intel_fbc *fbc)
268{
269 struct drm_i915_private *i915 = fbc->i915;
270 u32 fbc_ctl;
271
272 /* Disable compression */
273 fbc_ctl = intel_de_read(i915, FBC_CONTROL);
274 if ((fbc_ctl & FBC_CTL_EN) == 0)
275 return;
276
277 fbc_ctl &= ~FBC_CTL_EN;
278 intel_de_write(i915, FBC_CONTROL, fbc_ctl);
279
280 /* Wait for compressing bit to clear */
281 if (intel_de_wait_for_clear(i915, FBC_STATUS,
282 FBC_STAT_COMPRESSING, 10)) {
283 drm_dbg_kms(&i915->drm, "FBC idle timed out\n");
284 return;
285 }
286}
287
288static void i8xx_fbc_activate(struct intel_fbc *fbc)
289{
290 const struct intel_fbc_state *fbc_state = &fbc->state;
291 struct drm_i915_private *i915 = fbc->i915;
292 int i;
293
294 /* Clear old tags */
295 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
296 intel_de_write(i915, FBC_TAG(i), 0);
297
298 if (DISPLAY_VER(i915) == 4) {
299 intel_de_write(i915, FBC_CONTROL2,
300 i965_fbc_ctl2(fbc));
301 intel_de_write(i915, FBC_FENCE_OFF,
302 fbc_state->fence_y_offset);
303 }
304
305 intel_de_write(i915, FBC_CONTROL,
306 FBC_CTL_EN | i8xx_fbc_ctl(fbc));
307}
308
309static bool i8xx_fbc_is_active(struct intel_fbc *fbc)
310{
311 return intel_de_read(fbc->i915, FBC_CONTROL) & FBC_CTL_EN;
312}
313
314static bool i8xx_fbc_is_compressing(struct intel_fbc *fbc)
315{
316 return intel_de_read(fbc->i915, FBC_STATUS) &
317 (FBC_STAT_COMPRESSING | FBC_STAT_COMPRESSED);
318}
319
320static void i8xx_fbc_nuke(struct intel_fbc *fbc)
321{
322 struct intel_fbc_state *fbc_state = &fbc->state;
323 enum i9xx_plane_id i9xx_plane = fbc_state->plane->i9xx_plane;
324 struct drm_i915_private *dev_priv = fbc->i915;
325
326 spin_lock_irq(&dev_priv->uncore.lock);
327 intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane),
328 intel_de_read_fw(dev_priv, DSPADDR(i9xx_plane)));
329 spin_unlock_irq(&dev_priv->uncore.lock);
330}
331
332static void i8xx_fbc_program_cfb(struct intel_fbc *fbc)
333{
334 struct drm_i915_private *i915 = fbc->i915;
335
336 GEM_BUG_ON(range_overflows_end_t(u64, i915->dsm.start,
337 fbc->compressed_fb.start, U32_MAX));
338 GEM_BUG_ON(range_overflows_end_t(u64, i915->dsm.start,
339 fbc->compressed_llb.start, U32_MAX));
340
341 intel_de_write(i915, FBC_CFB_BASE,
342 i915->dsm.start + fbc->compressed_fb.start);
343 intel_de_write(i915, FBC_LL_BASE,
344 i915->dsm.start + fbc->compressed_llb.start);
345}
346
347static const struct intel_fbc_funcs i8xx_fbc_funcs = {
348 .activate = i8xx_fbc_activate,
349 .deactivate = i8xx_fbc_deactivate,
350 .is_active = i8xx_fbc_is_active,
351 .is_compressing = i8xx_fbc_is_compressing,
352 .nuke = i8xx_fbc_nuke,
353 .program_cfb = i8xx_fbc_program_cfb,
354};
355
356static void i965_fbc_nuke(struct intel_fbc *fbc)
357{
358 struct intel_fbc_state *fbc_state = &fbc->state;
359 enum i9xx_plane_id i9xx_plane = fbc_state->plane->i9xx_plane;
360 struct drm_i915_private *dev_priv = fbc->i915;
361
362 spin_lock_irq(&dev_priv->uncore.lock);
363 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
364 intel_de_read_fw(dev_priv, DSPSURF(i9xx_plane)));
365 spin_unlock_irq(&dev_priv->uncore.lock);
366}
367
368static const struct intel_fbc_funcs i965_fbc_funcs = {
369 .activate = i8xx_fbc_activate,
370 .deactivate = i8xx_fbc_deactivate,
371 .is_active = i8xx_fbc_is_active,
372 .is_compressing = i8xx_fbc_is_compressing,
373 .nuke = i965_fbc_nuke,
374 .program_cfb = i8xx_fbc_program_cfb,
375};
376
377static u32 g4x_dpfc_ctl_limit(struct intel_fbc *fbc)
378{
379 switch (fbc->limit) {
380 default:
381 MISSING_CASE(fbc->limit);
382 fallthrough;
383 case 1:
384 return DPFC_CTL_LIMIT_1X;
385 case 2:
386 return DPFC_CTL_LIMIT_2X;
387 case 4:
388 return DPFC_CTL_LIMIT_4X;
389 }
390}
391
392static u32 g4x_dpfc_ctl(struct intel_fbc *fbc)
393{
394 const struct intel_fbc_state *fbc_state = &fbc->state;
395 struct drm_i915_private *i915 = fbc->i915;
396 u32 dpfc_ctl;
397
398 dpfc_ctl = g4x_dpfc_ctl_limit(fbc) |
399 DPFC_CTL_PLANE_G4X(fbc_state->plane->i9xx_plane);
400
401 if (IS_G4X(i915))
402 dpfc_ctl |= DPFC_CTL_SR_EN;
403
404 if (fbc_state->fence_id >= 0) {
405 dpfc_ctl |= DPFC_CTL_FENCE_EN_G4X;
406
407 if (DISPLAY_VER(i915) < 6)
408 dpfc_ctl |= DPFC_CTL_FENCENO(fbc_state->fence_id);
409 }
410
411 return dpfc_ctl;
412}
413
414static void g4x_fbc_activate(struct intel_fbc *fbc)
415{
416 const struct intel_fbc_state *fbc_state = &fbc->state;
417 struct drm_i915_private *i915 = fbc->i915;
418
419 intel_de_write(i915, DPFC_FENCE_YOFF,
420 fbc_state->fence_y_offset);
421
422 intel_de_write(i915, DPFC_CONTROL,
423 DPFC_CTL_EN | g4x_dpfc_ctl(fbc));
424}
425
426static void g4x_fbc_deactivate(struct intel_fbc *fbc)
427{
428 struct drm_i915_private *i915 = fbc->i915;
429 u32 dpfc_ctl;
430
431 /* Disable compression */
432 dpfc_ctl = intel_de_read(i915, DPFC_CONTROL);
433 if (dpfc_ctl & DPFC_CTL_EN) {
434 dpfc_ctl &= ~DPFC_CTL_EN;
435 intel_de_write(i915, DPFC_CONTROL, dpfc_ctl);
436 }
437}
438
439static bool g4x_fbc_is_active(struct intel_fbc *fbc)
440{
441 return intel_de_read(fbc->i915, DPFC_CONTROL) & DPFC_CTL_EN;
442}
443
444static bool g4x_fbc_is_compressing(struct intel_fbc *fbc)
445{
446 return intel_de_read(fbc->i915, DPFC_STATUS) & DPFC_COMP_SEG_MASK;
447}
448
449static void g4x_fbc_program_cfb(struct intel_fbc *fbc)
450{
451 struct drm_i915_private *i915 = fbc->i915;
452
453 intel_de_write(i915, DPFC_CB_BASE, fbc->compressed_fb.start);
454}
455
456static const struct intel_fbc_funcs g4x_fbc_funcs = {
457 .activate = g4x_fbc_activate,
458 .deactivate = g4x_fbc_deactivate,
459 .is_active = g4x_fbc_is_active,
460 .is_compressing = g4x_fbc_is_compressing,
461 .nuke = i965_fbc_nuke,
462 .program_cfb = g4x_fbc_program_cfb,
463};
464
465static void ilk_fbc_activate(struct intel_fbc *fbc)
466{
467 struct intel_fbc_state *fbc_state = &fbc->state;
468 struct drm_i915_private *i915 = fbc->i915;
469
470 intel_de_write(i915, ILK_DPFC_FENCE_YOFF(fbc->id),
471 fbc_state->fence_y_offset);
472
473 intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id),
474 DPFC_CTL_EN | g4x_dpfc_ctl(fbc));
475}
476
477static void ilk_fbc_deactivate(struct intel_fbc *fbc)
478{
479 struct drm_i915_private *i915 = fbc->i915;
480 u32 dpfc_ctl;
481
482 /* Disable compression */
483 dpfc_ctl = intel_de_read(i915, ILK_DPFC_CONTROL(fbc->id));
484 if (dpfc_ctl & DPFC_CTL_EN) {
485 dpfc_ctl &= ~DPFC_CTL_EN;
486 intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl);
487 }
488}
489
490static bool ilk_fbc_is_active(struct intel_fbc *fbc)
491{
492 return intel_de_read(fbc->i915, ILK_DPFC_CONTROL(fbc->id)) & DPFC_CTL_EN;
493}
494
495static bool ilk_fbc_is_compressing(struct intel_fbc *fbc)
496{
497 return intel_de_read(fbc->i915, ILK_DPFC_STATUS(fbc->id)) & DPFC_COMP_SEG_MASK;
498}
499
500static void ilk_fbc_program_cfb(struct intel_fbc *fbc)
501{
502 struct drm_i915_private *i915 = fbc->i915;
503
504 intel_de_write(i915, ILK_DPFC_CB_BASE(fbc->id), fbc->compressed_fb.start);
505}
506
507static const struct intel_fbc_funcs ilk_fbc_funcs = {
508 .activate = ilk_fbc_activate,
509 .deactivate = ilk_fbc_deactivate,
510 .is_active = ilk_fbc_is_active,
511 .is_compressing = ilk_fbc_is_compressing,
512 .nuke = i965_fbc_nuke,
513 .program_cfb = ilk_fbc_program_cfb,
514};
515
516static void snb_fbc_program_fence(struct intel_fbc *fbc)
517{
518 const struct intel_fbc_state *fbc_state = &fbc->state;
519 struct drm_i915_private *i915 = fbc->i915;
520 u32 ctl = 0;
521
522 if (fbc_state->fence_id >= 0)
523 ctl = SNB_DPFC_FENCE_EN | SNB_DPFC_FENCENO(fbc_state->fence_id);
524
525 intel_de_write(i915, SNB_DPFC_CTL_SA, ctl);
526 intel_de_write(i915, SNB_DPFC_CPU_FENCE_OFFSET, fbc_state->fence_y_offset);
527}
528
529static void snb_fbc_activate(struct intel_fbc *fbc)
530{
531 snb_fbc_program_fence(fbc);
532
533 ilk_fbc_activate(fbc);
534}
535
536static void snb_fbc_nuke(struct intel_fbc *fbc)
537{
538 struct drm_i915_private *i915 = fbc->i915;
539
540 intel_de_write(i915, MSG_FBC_REND_STATE(fbc->id), FBC_REND_NUKE);
541 intel_de_posting_read(i915, MSG_FBC_REND_STATE(fbc->id));
542}
543
544static const struct intel_fbc_funcs snb_fbc_funcs = {
545 .activate = snb_fbc_activate,
546 .deactivate = ilk_fbc_deactivate,
547 .is_active = ilk_fbc_is_active,
548 .is_compressing = ilk_fbc_is_compressing,
549 .nuke = snb_fbc_nuke,
550 .program_cfb = ilk_fbc_program_cfb,
551};
552
553static void glk_fbc_program_cfb_stride(struct intel_fbc *fbc)
554{
555 const struct intel_fbc_state *fbc_state = &fbc->state;
556 struct drm_i915_private *i915 = fbc->i915;
557 u32 val = 0;
558
559 if (fbc_state->override_cfb_stride)
560 val |= FBC_STRIDE_OVERRIDE |
561 FBC_STRIDE(fbc_state->override_cfb_stride / fbc->limit);
562
563 intel_de_write(i915, GLK_FBC_STRIDE(fbc->id), val);
564}
565
566static void skl_fbc_program_cfb_stride(struct intel_fbc *fbc)
567{
568 const struct intel_fbc_state *fbc_state = &fbc->state;
569 struct drm_i915_private *i915 = fbc->i915;
570 u32 val = 0;
571
572 /* Display WA #0529: skl, kbl, bxt. */
573 if (fbc_state->override_cfb_stride)
574 val |= CHICKEN_FBC_STRIDE_OVERRIDE |
575 CHICKEN_FBC_STRIDE(fbc_state->override_cfb_stride / fbc->limit);
576
577 intel_de_rmw(i915, CHICKEN_MISC_4,
578 CHICKEN_FBC_STRIDE_OVERRIDE |
579 CHICKEN_FBC_STRIDE_MASK, val);
580}
581
582static u32 ivb_dpfc_ctl(struct intel_fbc *fbc)
583{
584 const struct intel_fbc_state *fbc_state = &fbc->state;
585 struct drm_i915_private *i915 = fbc->i915;
586 u32 dpfc_ctl;
587
588 dpfc_ctl = g4x_dpfc_ctl_limit(fbc);
589
590 if (IS_IVYBRIDGE(i915))
591 dpfc_ctl |= DPFC_CTL_PLANE_IVB(fbc_state->plane->i9xx_plane);
592
593 if (fbc_state->fence_id >= 0)
594 dpfc_ctl |= DPFC_CTL_FENCE_EN_IVB;
595
596 if (fbc->false_color)
597 dpfc_ctl |= DPFC_CTL_FALSE_COLOR;
598
599 return dpfc_ctl;
600}
601
602static void ivb_fbc_activate(struct intel_fbc *fbc)
603{
604 struct drm_i915_private *i915 = fbc->i915;
605
606 if (DISPLAY_VER(i915) >= 10)
607 glk_fbc_program_cfb_stride(fbc);
608 else if (DISPLAY_VER(i915) == 9)
609 skl_fbc_program_cfb_stride(fbc);
610
611 if (to_gt(i915)->ggtt->num_fences)
612 snb_fbc_program_fence(fbc);
613
614 intel_de_write(i915, ILK_DPFC_CONTROL(fbc->id),
615 DPFC_CTL_EN | ivb_dpfc_ctl(fbc));
616}
617
618static bool ivb_fbc_is_compressing(struct intel_fbc *fbc)
619{
620 return intel_de_read(fbc->i915, ILK_DPFC_STATUS2(fbc->id)) & DPFC_COMP_SEG_MASK_IVB;
621}
622
623static void ivb_fbc_set_false_color(struct intel_fbc *fbc,
624 bool enable)
625{
626 intel_de_rmw(fbc->i915, ILK_DPFC_CONTROL(fbc->id),
627 DPFC_CTL_FALSE_COLOR, enable ? DPFC_CTL_FALSE_COLOR : 0);
628}
629
630static const struct intel_fbc_funcs ivb_fbc_funcs = {
631 .activate = ivb_fbc_activate,
632 .deactivate = ilk_fbc_deactivate,
633 .is_active = ilk_fbc_is_active,
634 .is_compressing = ivb_fbc_is_compressing,
635 .nuke = snb_fbc_nuke,
636 .program_cfb = ilk_fbc_program_cfb,
637 .set_false_color = ivb_fbc_set_false_color,
638};
639
640static bool intel_fbc_hw_is_active(struct intel_fbc *fbc)
641{
642 return fbc->funcs->is_active(fbc);
643}
644
645static void intel_fbc_hw_activate(struct intel_fbc *fbc)
646{
647 trace_intel_fbc_activate(fbc->state.plane);
648
649 fbc->active = true;
650 fbc->activated = true;
651
652 fbc->funcs->activate(fbc);
653}
654
655static void intel_fbc_hw_deactivate(struct intel_fbc *fbc)
656{
657 trace_intel_fbc_deactivate(fbc->state.plane);
658
659 fbc->active = false;
660
661 fbc->funcs->deactivate(fbc);
662}
663
664static bool intel_fbc_is_compressing(struct intel_fbc *fbc)
665{
666 return fbc->funcs->is_compressing(fbc);
667}
668
669static void intel_fbc_nuke(struct intel_fbc *fbc)
670{
671 struct drm_i915_private *i915 = fbc->i915;
672
673 lockdep_assert_held(&fbc->lock);
674 drm_WARN_ON(&i915->drm, fbc->flip_pending);
675
676 trace_intel_fbc_nuke(fbc->state.plane);
677
678 fbc->funcs->nuke(fbc);
679}
680
681static void intel_fbc_activate(struct intel_fbc *fbc)
682{
683 lockdep_assert_held(&fbc->lock);
684
685 intel_fbc_hw_activate(fbc);
686 intel_fbc_nuke(fbc);
687
688 fbc->no_fbc_reason = NULL;
689}
690
691static void intel_fbc_deactivate(struct intel_fbc *fbc, const char *reason)
692{
693 lockdep_assert_held(&fbc->lock);
694
695 if (fbc->active)
696 intel_fbc_hw_deactivate(fbc);
697
698 fbc->no_fbc_reason = reason;
699}
700
701static u64 intel_fbc_cfb_base_max(struct drm_i915_private *i915)
702{
703 if (DISPLAY_VER(i915) >= 5 || IS_G4X(i915))
704 return BIT_ULL(28);
705 else
706 return BIT_ULL(32);
707}
708
709static u64 intel_fbc_stolen_end(struct drm_i915_private *i915)
710{
711 u64 end;
712
713 /* The FBC hardware for BDW/SKL doesn't have access to the stolen
714 * reserved range size, so it always assumes the maximum (8mb) is used.
715 * If we enable FBC using a CFB on that memory range we'll get FIFO
716 * underruns, even if that range is not reserved by the BIOS. */
717 if (IS_BROADWELL(i915) ||
718 (DISPLAY_VER(i915) == 9 && !IS_BROXTON(i915)))
719 end = resource_size(&i915->dsm) - 8 * 1024 * 1024;
720 else
721 end = U64_MAX;
722
723 return min(end, intel_fbc_cfb_base_max(i915));
724}
725
726static int intel_fbc_min_limit(const struct intel_plane_state *plane_state)
727{
728 return plane_state->hw.fb->format->cpp[0] == 2 ? 2 : 1;
729}
730
731static int intel_fbc_max_limit(struct drm_i915_private *i915)
732{
733 /* WaFbcOnly1to1Ratio:ctg */
734 if (IS_G4X(i915))
735 return 1;
736
737 /*
738 * FBC2 can only do 1:1, 1:2, 1:4, we limit
739 * FBC1 to the same out of convenience.
740 */
741 return 4;
742}
743
744static int find_compression_limit(struct intel_fbc *fbc,
745 unsigned int size, int min_limit)
746{
747 struct drm_i915_private *i915 = fbc->i915;
748 u64 end = intel_fbc_stolen_end(i915);
749 int ret, limit = min_limit;
750
751 size /= limit;
752
753 /* Try to over-allocate to reduce reallocations and fragmentation. */
754 ret = i915_gem_stolen_insert_node_in_range(i915, &fbc->compressed_fb,
755 size <<= 1, 4096, 0, end);
756 if (ret == 0)
757 return limit;
758
759 for (; limit <= intel_fbc_max_limit(i915); limit <<= 1) {
760 ret = i915_gem_stolen_insert_node_in_range(i915, &fbc->compressed_fb,
761 size >>= 1, 4096, 0, end);
762 if (ret == 0)
763 return limit;
764 }
765
766 return 0;
767}
768
769static int intel_fbc_alloc_cfb(struct intel_fbc *fbc,
770 unsigned int size, int min_limit)
771{
772 struct drm_i915_private *i915 = fbc->i915;
773 int ret;
774
775 drm_WARN_ON(&i915->drm,
776 drm_mm_node_allocated(&fbc->compressed_fb));
777 drm_WARN_ON(&i915->drm,
778 drm_mm_node_allocated(&fbc->compressed_llb));
779
780 if (DISPLAY_VER(i915) < 5 && !IS_G4X(i915)) {
781 ret = i915_gem_stolen_insert_node(i915, &fbc->compressed_llb,
782 4096, 4096);
783 if (ret)
784 goto err;
785 }
786
787 ret = find_compression_limit(fbc, size, min_limit);
788 if (!ret)
789 goto err_llb;
790 else if (ret > min_limit)
791 drm_info_once(&i915->drm,
792 "Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n");
793
794 fbc->limit = ret;
795
796 drm_dbg_kms(&i915->drm,
797 "reserved %llu bytes of contiguous stolen space for FBC, limit: %d\n",
798 fbc->compressed_fb.size, fbc->limit);
799
800 return 0;
801
802err_llb:
803 if (drm_mm_node_allocated(&fbc->compressed_llb))
804 i915_gem_stolen_remove_node(i915, &fbc->compressed_llb);
805err:
806 if (drm_mm_initialized(&i915->mm.stolen))
807 drm_info_once(&i915->drm, "not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size);
808 return -ENOSPC;
809}
810
811static void intel_fbc_program_cfb(struct intel_fbc *fbc)
812{
813 fbc->funcs->program_cfb(fbc);
814}
815
816static void intel_fbc_program_workarounds(struct intel_fbc *fbc)
817{
818 /* Wa_22014263786:icl,jsl,tgl,dg1,rkl,adls,adlp */
819 if (DISPLAY_VER(fbc->i915) >= 11 && !IS_DG2(fbc->i915))
820 intel_de_rmw(fbc->i915, ILK_DPFC_CHICKEN(fbc->id), 0,
821 DPFC_CHICKEN_FORCE_SLB_INVALIDATION);
822}
823
824static void __intel_fbc_cleanup_cfb(struct intel_fbc *fbc)
825{
826 struct drm_i915_private *i915 = fbc->i915;
827
828 if (WARN_ON(intel_fbc_hw_is_active(fbc)))
829 return;
830
831 if (drm_mm_node_allocated(&fbc->compressed_llb))
832 i915_gem_stolen_remove_node(i915, &fbc->compressed_llb);
833 if (drm_mm_node_allocated(&fbc->compressed_fb))
834 i915_gem_stolen_remove_node(i915, &fbc->compressed_fb);
835}
836
837void intel_fbc_cleanup(struct drm_i915_private *i915)
838{
839 struct intel_fbc *fbc;
840 enum intel_fbc_id fbc_id;
841
842 for_each_intel_fbc(i915, fbc, fbc_id) {
843 mutex_lock(&fbc->lock);
844 __intel_fbc_cleanup_cfb(fbc);
845 mutex_unlock(&fbc->lock);
846
847 kfree(fbc);
848 }
849}
850
851static bool stride_is_valid(const struct intel_plane_state *plane_state)
852{
853 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
854 const struct drm_framebuffer *fb = plane_state->hw.fb;
855 unsigned int stride = intel_fbc_plane_stride(plane_state) *
856 fb->format->cpp[0];
857
858 /* This should have been caught earlier. */
859 if (drm_WARN_ON_ONCE(&i915->drm, (stride & (64 - 1)) != 0))
860 return false;
861
862 /* Below are the additional FBC restrictions. */
863 if (stride < 512)
864 return false;
865
866 if (DISPLAY_VER(i915) == 2 || DISPLAY_VER(i915) == 3)
867 return stride == 4096 || stride == 8192;
868
869 if (DISPLAY_VER(i915) == 4 && !IS_G4X(i915) && stride < 2048)
870 return false;
871
872 /* Display WA #1105: skl,bxt,kbl,cfl,glk */
873 if ((DISPLAY_VER(i915) == 9 || IS_GEMINILAKE(i915)) &&
874 fb->modifier == DRM_FORMAT_MOD_LINEAR && stride & 511)
875 return false;
876
877 if (stride > 16384)
878 return false;
879
880 return true;
881}
882
883static bool pixel_format_is_valid(const struct intel_plane_state *plane_state)
884{
885 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
886 const struct drm_framebuffer *fb = plane_state->hw.fb;
887
888 switch (fb->format->format) {
889 case DRM_FORMAT_XRGB8888:
890 case DRM_FORMAT_XBGR8888:
891 return true;
892 case DRM_FORMAT_XRGB1555:
893 case DRM_FORMAT_RGB565:
894 /* 16bpp not supported on gen2 */
895 if (DISPLAY_VER(i915) == 2)
896 return false;
897 /* WaFbcOnly1to1Ratio:ctg */
898 if (IS_G4X(i915))
899 return false;
900 return true;
901 default:
902 return false;
903 }
904}
905
906static bool rotation_is_valid(const struct intel_plane_state *plane_state)
907{
908 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
909 const struct drm_framebuffer *fb = plane_state->hw.fb;
910 unsigned int rotation = plane_state->hw.rotation;
911
912 if (DISPLAY_VER(i915) >= 9 && fb->format->format == DRM_FORMAT_RGB565 &&
913 drm_rotation_90_or_270(rotation))
914 return false;
915 else if (DISPLAY_VER(i915) <= 4 && !IS_G4X(i915) &&
916 rotation != DRM_MODE_ROTATE_0)
917 return false;
918
919 return true;
920}
921
922/*
923 * For some reason, the hardware tracking starts looking at whatever we
924 * programmed as the display plane base address register. It does not look at
925 * the X and Y offset registers. That's why we include the src x/y offsets
926 * instead of just looking at the plane size.
927 */
928static bool intel_fbc_hw_tracking_covers_screen(const struct intel_plane_state *plane_state)
929{
930 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
931 unsigned int effective_w, effective_h, max_w, max_h;
932
933 if (DISPLAY_VER(i915) >= 10) {
934 max_w = 5120;
935 max_h = 4096;
936 } else if (DISPLAY_VER(i915) >= 8 || IS_HASWELL(i915)) {
937 max_w = 4096;
938 max_h = 4096;
939 } else if (IS_G4X(i915) || DISPLAY_VER(i915) >= 5) {
940 max_w = 4096;
941 max_h = 2048;
942 } else {
943 max_w = 2048;
944 max_h = 1536;
945 }
946
947 effective_w = plane_state->view.color_plane[0].x +
948 (drm_rect_width(&plane_state->uapi.src) >> 16);
949 effective_h = plane_state->view.color_plane[0].y +
950 (drm_rect_height(&plane_state->uapi.src) >> 16);
951
952 return effective_w <= max_w && effective_h <= max_h;
953}
954
955static bool tiling_is_valid(const struct intel_plane_state *plane_state)
956{
957 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
958 const struct drm_framebuffer *fb = plane_state->hw.fb;
959
960 switch (fb->modifier) {
961 case DRM_FORMAT_MOD_LINEAR:
962 case I915_FORMAT_MOD_Y_TILED:
963 case I915_FORMAT_MOD_Yf_TILED:
964 return DISPLAY_VER(i915) >= 9;
965 case I915_FORMAT_MOD_4_TILED:
966 case I915_FORMAT_MOD_X_TILED:
967 return true;
968 default:
969 return false;
970 }
971}
972
973static void intel_fbc_update_state(struct intel_atomic_state *state,
974 struct intel_crtc *crtc,
975 struct intel_plane *plane)
976{
977 struct drm_i915_private *i915 = to_i915(state->base.dev);
978 const struct intel_crtc_state *crtc_state =
979 intel_atomic_get_new_crtc_state(state, crtc);
980 const struct intel_plane_state *plane_state =
981 intel_atomic_get_new_plane_state(state, plane);
982 struct intel_fbc *fbc = plane->fbc;
983 struct intel_fbc_state *fbc_state = &fbc->state;
984
985 WARN_ON(plane_state->no_fbc_reason);
986 WARN_ON(fbc_state->plane && fbc_state->plane != plane);
987
988 fbc_state->plane = plane;
989
990 /* FBC1 compression interval: arbitrary choice of 1 second */
991 fbc_state->interval = drm_mode_vrefresh(&crtc_state->hw.adjusted_mode);
992
993 fbc_state->fence_y_offset = intel_plane_fence_y_offset(plane_state);
994
995 drm_WARN_ON(&i915->drm, plane_state->flags & PLANE_HAS_FENCE &&
996 !plane_state->ggtt_vma->fence);
997
998 if (plane_state->flags & PLANE_HAS_FENCE &&
999 plane_state->ggtt_vma->fence)
1000 fbc_state->fence_id = plane_state->ggtt_vma->fence->id;
1001 else
1002 fbc_state->fence_id = -1;
1003
1004 fbc_state->cfb_stride = intel_fbc_cfb_stride(plane_state);
1005 fbc_state->cfb_size = intel_fbc_cfb_size(plane_state);
1006 fbc_state->override_cfb_stride = intel_fbc_override_cfb_stride(plane_state);
1007}
1008
1009static bool intel_fbc_is_fence_ok(const struct intel_plane_state *plane_state)
1010{
1011 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
1012
1013 /*
1014 * The use of a CPU fence is one of two ways to detect writes by the
1015 * CPU to the scanout and trigger updates to the FBC.
1016 *
1017 * The other method is by software tracking (see
1018 * intel_fbc_invalidate/flush()), it will manually notify FBC and nuke
1019 * the current compressed buffer and recompress it.
1020 *
1021 * Note that is possible for a tiled surface to be unmappable (and
1022 * so have no fence associated with it) due to aperture constraints
1023 * at the time of pinning.
1024 */
1025 return DISPLAY_VER(i915) >= 9 ||
1026 (plane_state->flags & PLANE_HAS_FENCE &&
1027 plane_state->ggtt_vma->fence);
1028}
1029
1030static bool intel_fbc_is_cfb_ok(const struct intel_plane_state *plane_state)
1031{
1032 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1033 struct intel_fbc *fbc = plane->fbc;
1034
1035 return intel_fbc_min_limit(plane_state) <= fbc->limit &&
1036 intel_fbc_cfb_size(plane_state) <= fbc->compressed_fb.size * fbc->limit;
1037}
1038
1039static bool intel_fbc_is_ok(const struct intel_plane_state *plane_state)
1040{
1041 return !plane_state->no_fbc_reason &&
1042 intel_fbc_is_fence_ok(plane_state) &&
1043 intel_fbc_is_cfb_ok(plane_state);
1044}
1045
1046static int intel_fbc_check_plane(struct intel_atomic_state *state,
1047 struct intel_plane *plane)
1048{
1049 struct drm_i915_private *i915 = to_i915(state->base.dev);
1050 struct intel_plane_state *plane_state =
1051 intel_atomic_get_new_plane_state(state, plane);
1052 const struct drm_framebuffer *fb = plane_state->hw.fb;
1053 struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc);
1054 const struct intel_crtc_state *crtc_state;
1055 struct intel_fbc *fbc = plane->fbc;
1056
1057 if (!fbc)
1058 return 0;
1059
1060 if (intel_vgpu_active(i915)) {
1061 plane_state->no_fbc_reason = "VGPU active";
1062 return 0;
1063 }
1064
1065 if (!i915->params.enable_fbc) {
1066 plane_state->no_fbc_reason = "disabled per module param or by default";
1067 return 0;
1068 }
1069
1070 if (!plane_state->uapi.visible) {
1071 plane_state->no_fbc_reason = "plane not visible";
1072 return 0;
1073 }
1074
1075 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
1076
1077 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
1078 plane_state->no_fbc_reason = "interlaced mode not supported";
1079 return 0;
1080 }
1081
1082 if (crtc_state->double_wide) {
1083 plane_state->no_fbc_reason = "double wide pipe not supported";
1084 return 0;
1085 }
1086
1087 /*
1088 * Display 12+ is not supporting FBC with PSR2.
1089 * Recommendation is to keep this combination disabled
1090 * Bspec: 50422 HSD: 14010260002
1091 */
1092 if (DISPLAY_VER(i915) >= 12 && crtc_state->has_psr2) {
1093 plane_state->no_fbc_reason = "PSR2 enabled";
1094 return 0;
1095 }
1096
1097 /* Wa_14016291713 */
1098 if (IS_DISPLAY_VER(i915, 12, 13) && crtc_state->has_psr) {
1099 plane_state->no_fbc_reason = "PSR1 enabled (Wa_14016291713)";
1100 return 0;
1101 }
1102
1103 if (!pixel_format_is_valid(plane_state)) {
1104 plane_state->no_fbc_reason = "pixel format not supported";
1105 return 0;
1106 }
1107
1108 if (!tiling_is_valid(plane_state)) {
1109 plane_state->no_fbc_reason = "tiling not supported";
1110 return 0;
1111 }
1112
1113 if (!rotation_is_valid(plane_state)) {
1114 plane_state->no_fbc_reason = "rotation not supported";
1115 return 0;
1116 }
1117
1118 if (!stride_is_valid(plane_state)) {
1119 plane_state->no_fbc_reason = "stride not supported";
1120 return 0;
1121 }
1122
1123 if (plane_state->hw.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE &&
1124 fb->format->has_alpha) {
1125 plane_state->no_fbc_reason = "per-pixel alpha not supported";
1126 return 0;
1127 }
1128
1129 if (!intel_fbc_hw_tracking_covers_screen(plane_state)) {
1130 plane_state->no_fbc_reason = "plane size too big";
1131 return 0;
1132 }
1133
1134 /*
1135 * Work around a problem on GEN9+ HW, where enabling FBC on a plane
1136 * having a Y offset that isn't divisible by 4 causes FIFO underrun
1137 * and screen flicker.
1138 */
1139 if (DISPLAY_VER(i915) >= 9 &&
1140 plane_state->view.color_plane[0].y & 3) {
1141 plane_state->no_fbc_reason = "plane start Y offset misaligned";
1142 return 0;
1143 }
1144
1145 /* Wa_22010751166: icl, ehl, tgl, dg1, rkl */
1146 if (DISPLAY_VER(i915) >= 11 &&
1147 (plane_state->view.color_plane[0].y +
1148 (drm_rect_height(&plane_state->uapi.src) >> 16)) & 3) {
1149 plane_state->no_fbc_reason = "plane end Y offset misaligned";
1150 return 0;
1151 }
1152
1153 /* WaFbcExceedCdClockThreshold:hsw,bdw */
1154 if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
1155 const struct intel_cdclk_state *cdclk_state;
1156
1157 cdclk_state = intel_atomic_get_cdclk_state(state);
1158 if (IS_ERR(cdclk_state))
1159 return PTR_ERR(cdclk_state);
1160
1161 if (crtc_state->pixel_rate >= cdclk_state->logical.cdclk * 95 / 100) {
1162 plane_state->no_fbc_reason = "pixel rate too high";
1163 return 0;
1164 }
1165 }
1166
1167 plane_state->no_fbc_reason = NULL;
1168
1169 return 0;
1170}
1171
1172
1173static bool intel_fbc_can_flip_nuke(struct intel_atomic_state *state,
1174 struct intel_crtc *crtc,
1175 struct intel_plane *plane)
1176{
1177 const struct intel_crtc_state *new_crtc_state =
1178 intel_atomic_get_new_crtc_state(state, crtc);
1179 const struct intel_plane_state *old_plane_state =
1180 intel_atomic_get_old_plane_state(state, plane);
1181 const struct intel_plane_state *new_plane_state =
1182 intel_atomic_get_new_plane_state(state, plane);
1183 const struct drm_framebuffer *old_fb = old_plane_state->hw.fb;
1184 const struct drm_framebuffer *new_fb = new_plane_state->hw.fb;
1185
1186 if (intel_crtc_needs_modeset(new_crtc_state))
1187 return false;
1188
1189 if (!intel_fbc_is_ok(old_plane_state) ||
1190 !intel_fbc_is_ok(new_plane_state))
1191 return false;
1192
1193 if (old_fb->format->format != new_fb->format->format)
1194 return false;
1195
1196 if (old_fb->modifier != new_fb->modifier)
1197 return false;
1198
1199 if (intel_fbc_plane_stride(old_plane_state) !=
1200 intel_fbc_plane_stride(new_plane_state))
1201 return false;
1202
1203 if (intel_fbc_cfb_stride(old_plane_state) !=
1204 intel_fbc_cfb_stride(new_plane_state))
1205 return false;
1206
1207 if (intel_fbc_cfb_size(old_plane_state) !=
1208 intel_fbc_cfb_size(new_plane_state))
1209 return false;
1210
1211 if (intel_fbc_override_cfb_stride(old_plane_state) !=
1212 intel_fbc_override_cfb_stride(new_plane_state))
1213 return false;
1214
1215 return true;
1216}
1217
1218static bool __intel_fbc_pre_update(struct intel_atomic_state *state,
1219 struct intel_crtc *crtc,
1220 struct intel_plane *plane)
1221{
1222 struct drm_i915_private *i915 = to_i915(state->base.dev);
1223 struct intel_fbc *fbc = plane->fbc;
1224 bool need_vblank_wait = false;
1225
1226 lockdep_assert_held(&fbc->lock);
1227
1228 fbc->flip_pending = true;
1229
1230 if (intel_fbc_can_flip_nuke(state, crtc, plane))
1231 return need_vblank_wait;
1232
1233 intel_fbc_deactivate(fbc, "update pending");
1234
1235 /*
1236 * Display WA #1198: glk+
1237 * Need an extra vblank wait between FBC disable and most plane
1238 * updates. Bspec says this is only needed for plane disable, but
1239 * that is not true. Touching most plane registers will cause the
1240 * corruption to appear. Also SKL/derivatives do not seem to be
1241 * affected.
1242 *
1243 * TODO: could optimize this a bit by sampling the frame
1244 * counter when we disable FBC (if it was already done earlier)
1245 * and skipping the extra vblank wait before the plane update
1246 * if at least one frame has already passed.
1247 */
1248 if (fbc->activated && DISPLAY_VER(i915) >= 10)
1249 need_vblank_wait = true;
1250 fbc->activated = false;
1251
1252 return need_vblank_wait;
1253}
1254
1255bool intel_fbc_pre_update(struct intel_atomic_state *state,
1256 struct intel_crtc *crtc)
1257{
1258 const struct intel_plane_state *plane_state;
1259 bool need_vblank_wait = false;
1260 struct intel_plane *plane;
1261 int i;
1262
1263 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1264 struct intel_fbc *fbc = plane->fbc;
1265
1266 if (!fbc || plane->pipe != crtc->pipe)
1267 continue;
1268
1269 mutex_lock(&fbc->lock);
1270
1271 if (fbc->state.plane == plane)
1272 need_vblank_wait |= __intel_fbc_pre_update(state, crtc, plane);
1273
1274 mutex_unlock(&fbc->lock);
1275 }
1276
1277 return need_vblank_wait;
1278}
1279
1280static void __intel_fbc_disable(struct intel_fbc *fbc)
1281{
1282 struct drm_i915_private *i915 = fbc->i915;
1283 struct intel_plane *plane = fbc->state.plane;
1284
1285 lockdep_assert_held(&fbc->lock);
1286 drm_WARN_ON(&i915->drm, fbc->active);
1287
1288 drm_dbg_kms(&i915->drm, "Disabling FBC on [PLANE:%d:%s]\n",
1289 plane->base.base.id, plane->base.name);
1290
1291 __intel_fbc_cleanup_cfb(fbc);
1292
1293 fbc->state.plane = NULL;
1294 fbc->flip_pending = false;
1295 fbc->busy_bits = 0;
1296}
1297
1298static void __intel_fbc_post_update(struct intel_fbc *fbc)
1299{
1300 lockdep_assert_held(&fbc->lock);
1301
1302 fbc->flip_pending = false;
1303
1304 if (!fbc->busy_bits)
1305 intel_fbc_activate(fbc);
1306 else
1307 intel_fbc_deactivate(fbc, "frontbuffer write");
1308}
1309
1310void intel_fbc_post_update(struct intel_atomic_state *state,
1311 struct intel_crtc *crtc)
1312{
1313 const struct intel_plane_state *plane_state;
1314 struct intel_plane *plane;
1315 int i;
1316
1317 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1318 struct intel_fbc *fbc = plane->fbc;
1319
1320 if (!fbc || plane->pipe != crtc->pipe)
1321 continue;
1322
1323 mutex_lock(&fbc->lock);
1324
1325 if (fbc->state.plane == plane)
1326 __intel_fbc_post_update(fbc);
1327
1328 mutex_unlock(&fbc->lock);
1329 }
1330}
1331
1332static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc *fbc)
1333{
1334 if (fbc->state.plane)
1335 return fbc->state.plane->frontbuffer_bit;
1336 else
1337 return 0;
1338}
1339
1340static void __intel_fbc_invalidate(struct intel_fbc *fbc,
1341 unsigned int frontbuffer_bits,
1342 enum fb_op_origin origin)
1343{
1344 if (origin == ORIGIN_FLIP || origin == ORIGIN_CURSOR_UPDATE)
1345 return;
1346
1347 mutex_lock(&fbc->lock);
1348
1349 frontbuffer_bits &= intel_fbc_get_frontbuffer_bit(fbc);
1350 if (!frontbuffer_bits)
1351 goto out;
1352
1353 fbc->busy_bits |= frontbuffer_bits;
1354 intel_fbc_deactivate(fbc, "frontbuffer write");
1355
1356out:
1357 mutex_unlock(&fbc->lock);
1358}
1359
1360void intel_fbc_invalidate(struct drm_i915_private *i915,
1361 unsigned int frontbuffer_bits,
1362 enum fb_op_origin origin)
1363{
1364 struct intel_fbc *fbc;
1365 enum intel_fbc_id fbc_id;
1366
1367 for_each_intel_fbc(i915, fbc, fbc_id)
1368 __intel_fbc_invalidate(fbc, frontbuffer_bits, origin);
1369
1370}
1371
1372static void __intel_fbc_flush(struct intel_fbc *fbc,
1373 unsigned int frontbuffer_bits,
1374 enum fb_op_origin origin)
1375{
1376 mutex_lock(&fbc->lock);
1377
1378 frontbuffer_bits &= intel_fbc_get_frontbuffer_bit(fbc);
1379 if (!frontbuffer_bits)
1380 goto out;
1381
1382 fbc->busy_bits &= ~frontbuffer_bits;
1383
1384 if (origin == ORIGIN_FLIP || origin == ORIGIN_CURSOR_UPDATE)
1385 goto out;
1386
1387 if (fbc->busy_bits || fbc->flip_pending)
1388 goto out;
1389
1390 if (fbc->active)
1391 intel_fbc_nuke(fbc);
1392 else
1393 intel_fbc_activate(fbc);
1394
1395out:
1396 mutex_unlock(&fbc->lock);
1397}
1398
1399void intel_fbc_flush(struct drm_i915_private *i915,
1400 unsigned int frontbuffer_bits,
1401 enum fb_op_origin origin)
1402{
1403 struct intel_fbc *fbc;
1404 enum intel_fbc_id fbc_id;
1405
1406 for_each_intel_fbc(i915, fbc, fbc_id)
1407 __intel_fbc_flush(fbc, frontbuffer_bits, origin);
1408}
1409
1410int intel_fbc_atomic_check(struct intel_atomic_state *state)
1411{
1412 struct intel_plane_state *plane_state;
1413 struct intel_plane *plane;
1414 int i;
1415
1416 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1417 int ret;
1418
1419 ret = intel_fbc_check_plane(state, plane);
1420 if (ret)
1421 return ret;
1422 }
1423
1424 return 0;
1425}
1426
1427static void __intel_fbc_enable(struct intel_atomic_state *state,
1428 struct intel_crtc *crtc,
1429 struct intel_plane *plane)
1430{
1431 struct drm_i915_private *i915 = to_i915(state->base.dev);
1432 const struct intel_plane_state *plane_state =
1433 intel_atomic_get_new_plane_state(state, plane);
1434 struct intel_fbc *fbc = plane->fbc;
1435
1436 lockdep_assert_held(&fbc->lock);
1437
1438 if (fbc->state.plane) {
1439 if (fbc->state.plane != plane)
1440 return;
1441
1442 if (intel_fbc_is_ok(plane_state)) {
1443 intel_fbc_update_state(state, crtc, plane);
1444 return;
1445 }
1446
1447 __intel_fbc_disable(fbc);
1448 }
1449
1450 drm_WARN_ON(&i915->drm, fbc->active);
1451
1452 fbc->no_fbc_reason = plane_state->no_fbc_reason;
1453 if (fbc->no_fbc_reason)
1454 return;
1455
1456 if (!intel_fbc_is_fence_ok(plane_state)) {
1457 fbc->no_fbc_reason = "framebuffer not fenced";
1458 return;
1459 }
1460
1461 if (fbc->underrun_detected) {
1462 fbc->no_fbc_reason = "FIFO underrun";
1463 return;
1464 }
1465
1466 if (intel_fbc_alloc_cfb(fbc, intel_fbc_cfb_size(plane_state),
1467 intel_fbc_min_limit(plane_state))) {
1468 fbc->no_fbc_reason = "not enough stolen memory";
1469 return;
1470 }
1471
1472 drm_dbg_kms(&i915->drm, "Enabling FBC on [PLANE:%d:%s]\n",
1473 plane->base.base.id, plane->base.name);
1474 fbc->no_fbc_reason = "FBC enabled but not active yet\n";
1475
1476 intel_fbc_update_state(state, crtc, plane);
1477
1478 intel_fbc_program_workarounds(fbc);
1479 intel_fbc_program_cfb(fbc);
1480}
1481
1482/**
1483 * intel_fbc_disable - disable FBC if it's associated with crtc
1484 * @crtc: the CRTC
1485 *
1486 * This function disables FBC if it's associated with the provided CRTC.
1487 */
1488void intel_fbc_disable(struct intel_crtc *crtc)
1489{
1490 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
1491 struct intel_plane *plane;
1492
1493 for_each_intel_plane(&i915->drm, plane) {
1494 struct intel_fbc *fbc = plane->fbc;
1495
1496 if (!fbc || plane->pipe != crtc->pipe)
1497 continue;
1498
1499 mutex_lock(&fbc->lock);
1500 if (fbc->state.plane == plane)
1501 __intel_fbc_disable(fbc);
1502 mutex_unlock(&fbc->lock);
1503 }
1504}
1505
1506void intel_fbc_update(struct intel_atomic_state *state,
1507 struct intel_crtc *crtc)
1508{
1509 const struct intel_crtc_state *crtc_state =
1510 intel_atomic_get_new_crtc_state(state, crtc);
1511 const struct intel_plane_state *plane_state;
1512 struct intel_plane *plane;
1513 int i;
1514
1515 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1516 struct intel_fbc *fbc = plane->fbc;
1517
1518 if (!fbc || plane->pipe != crtc->pipe)
1519 continue;
1520
1521 mutex_lock(&fbc->lock);
1522
1523 if (intel_crtc_needs_fastset(crtc_state) &&
1524 plane_state->no_fbc_reason) {
1525 if (fbc->state.plane == plane)
1526 __intel_fbc_disable(fbc);
1527 } else {
1528 __intel_fbc_enable(state, crtc, plane);
1529 }
1530
1531 mutex_unlock(&fbc->lock);
1532 }
1533}
1534
1535static void intel_fbc_underrun_work_fn(struct work_struct *work)
1536{
1537 struct intel_fbc *fbc = container_of(work, typeof(*fbc), underrun_work);
1538 struct drm_i915_private *i915 = fbc->i915;
1539
1540 mutex_lock(&fbc->lock);
1541
1542 /* Maybe we were scheduled twice. */
1543 if (fbc->underrun_detected || !fbc->state.plane)
1544 goto out;
1545
1546 drm_dbg_kms(&i915->drm, "Disabling FBC due to FIFO underrun.\n");
1547 fbc->underrun_detected = true;
1548
1549 intel_fbc_deactivate(fbc, "FIFO underrun");
1550 if (!fbc->flip_pending)
1551 intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(i915, fbc->state.plane->pipe));
1552 __intel_fbc_disable(fbc);
1553out:
1554 mutex_unlock(&fbc->lock);
1555}
1556
1557static void __intel_fbc_reset_underrun(struct intel_fbc *fbc)
1558{
1559 struct drm_i915_private *i915 = fbc->i915;
1560
1561 cancel_work_sync(&fbc->underrun_work);
1562
1563 mutex_lock(&fbc->lock);
1564
1565 if (fbc->underrun_detected) {
1566 drm_dbg_kms(&i915->drm,
1567 "Re-allowing FBC after fifo underrun\n");
1568 fbc->no_fbc_reason = "FIFO underrun cleared";
1569 }
1570
1571 fbc->underrun_detected = false;
1572 mutex_unlock(&fbc->lock);
1573}
1574
1575/*
1576 * intel_fbc_reset_underrun - reset FBC fifo underrun status.
1577 * @i915: the i915 device
1578 *
1579 * See intel_fbc_handle_fifo_underrun_irq(). For automated testing we
1580 * want to re-enable FBC after an underrun to increase test coverage.
1581 */
1582void intel_fbc_reset_underrun(struct drm_i915_private *i915)
1583{
1584 struct intel_fbc *fbc;
1585 enum intel_fbc_id fbc_id;
1586
1587 for_each_intel_fbc(i915, fbc, fbc_id)
1588 __intel_fbc_reset_underrun(fbc);
1589}
1590
1591static void __intel_fbc_handle_fifo_underrun_irq(struct intel_fbc *fbc)
1592{
1593 /*
1594 * There's no guarantee that underrun_detected won't be set to true
1595 * right after this check and before the work is scheduled, but that's
1596 * not a problem since we'll check it again under the work function
1597 * while FBC is locked. This check here is just to prevent us from
1598 * unnecessarily scheduling the work, and it relies on the fact that we
1599 * never switch underrun_detect back to false after it's true.
1600 */
1601 if (READ_ONCE(fbc->underrun_detected))
1602 return;
1603
1604 schedule_work(&fbc->underrun_work);
1605}
1606
1607/**
1608 * intel_fbc_handle_fifo_underrun_irq - disable FBC when we get a FIFO underrun
1609 * @i915: i915 device
1610 *
1611 * Without FBC, most underruns are harmless and don't really cause too many
1612 * problems, except for an annoying message on dmesg. With FBC, underruns can
1613 * become black screens or even worse, especially when paired with bad
1614 * watermarks. So in order for us to be on the safe side, completely disable FBC
1615 * in case we ever detect a FIFO underrun on any pipe. An underrun on any pipe
1616 * already suggests that watermarks may be bad, so try to be as safe as
1617 * possible.
1618 *
1619 * This function is called from the IRQ handler.
1620 */
1621void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *i915)
1622{
1623 struct intel_fbc *fbc;
1624 enum intel_fbc_id fbc_id;
1625
1626 for_each_intel_fbc(i915, fbc, fbc_id)
1627 __intel_fbc_handle_fifo_underrun_irq(fbc);
1628}
1629
1630/*
1631 * The DDX driver changes its behavior depending on the value it reads from
1632 * i915.enable_fbc, so sanitize it by translating the default value into either
1633 * 0 or 1 in order to allow it to know what's going on.
1634 *
1635 * Notice that this is done at driver initialization and we still allow user
1636 * space to change the value during runtime without sanitizing it again. IGT
1637 * relies on being able to change i915.enable_fbc at runtime.
1638 */
1639static int intel_sanitize_fbc_option(struct drm_i915_private *i915)
1640{
1641 if (i915->params.enable_fbc >= 0)
1642 return !!i915->params.enable_fbc;
1643
1644 if (!HAS_FBC(i915))
1645 return 0;
1646
1647 if (IS_BROADWELL(i915) || DISPLAY_VER(i915) >= 9)
1648 return 1;
1649
1650 return 0;
1651}
1652
1653static bool need_fbc_vtd_wa(struct drm_i915_private *i915)
1654{
1655 /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */
1656 if (i915_vtd_active(i915) &&
1657 (IS_SKYLAKE(i915) || IS_BROXTON(i915))) {
1658 drm_info(&i915->drm,
1659 "Disabling framebuffer compression (FBC) to prevent screen flicker with VT-d enabled\n");
1660 return true;
1661 }
1662
1663 return false;
1664}
1665
1666void intel_fbc_add_plane(struct intel_fbc *fbc, struct intel_plane *plane)
1667{
1668 plane->fbc = fbc;
1669}
1670
1671static struct intel_fbc *intel_fbc_create(struct drm_i915_private *i915,
1672 enum intel_fbc_id fbc_id)
1673{
1674 struct intel_fbc *fbc;
1675
1676 fbc = kzalloc(sizeof(*fbc), GFP_KERNEL);
1677 if (!fbc)
1678 return NULL;
1679
1680 fbc->id = fbc_id;
1681 fbc->i915 = i915;
1682 INIT_WORK(&fbc->underrun_work, intel_fbc_underrun_work_fn);
1683 mutex_init(&fbc->lock);
1684
1685 if (DISPLAY_VER(i915) >= 7)
1686 fbc->funcs = &ivb_fbc_funcs;
1687 else if (DISPLAY_VER(i915) == 6)
1688 fbc->funcs = &snb_fbc_funcs;
1689 else if (DISPLAY_VER(i915) == 5)
1690 fbc->funcs = &ilk_fbc_funcs;
1691 else if (IS_G4X(i915))
1692 fbc->funcs = &g4x_fbc_funcs;
1693 else if (DISPLAY_VER(i915) == 4)
1694 fbc->funcs = &i965_fbc_funcs;
1695 else
1696 fbc->funcs = &i8xx_fbc_funcs;
1697
1698 return fbc;
1699}
1700
1701/**
1702 * intel_fbc_init - Initialize FBC
1703 * @i915: the i915 device
1704 *
1705 * This function might be called during PM init process.
1706 */
1707void intel_fbc_init(struct drm_i915_private *i915)
1708{
1709 enum intel_fbc_id fbc_id;
1710
1711 if (!drm_mm_initialized(&i915->mm.stolen))
1712 RUNTIME_INFO(i915)->fbc_mask = 0;
1713
1714 if (need_fbc_vtd_wa(i915))
1715 RUNTIME_INFO(i915)->fbc_mask = 0;
1716
1717 i915->params.enable_fbc = intel_sanitize_fbc_option(i915);
1718 drm_dbg_kms(&i915->drm, "Sanitized enable_fbc value: %d\n",
1719 i915->params.enable_fbc);
1720
1721 for_each_fbc_id(i915, fbc_id)
1722 i915->display.fbc[fbc_id] = intel_fbc_create(i915, fbc_id);
1723}
1724
1725/**
1726 * intel_fbc_sanitize - Sanitize FBC
1727 * @i915: the i915 device
1728 *
1729 * Make sure FBC is initially disabled since we have no
1730 * idea eg. into which parts of stolen it might be scribbling
1731 * into.
1732 */
1733void intel_fbc_sanitize(struct drm_i915_private *i915)
1734{
1735 struct intel_fbc *fbc;
1736 enum intel_fbc_id fbc_id;
1737
1738 for_each_intel_fbc(i915, fbc, fbc_id) {
1739 if (intel_fbc_hw_is_active(fbc))
1740 intel_fbc_hw_deactivate(fbc);
1741 }
1742}
1743
1744static int intel_fbc_debugfs_status_show(struct seq_file *m, void *unused)
1745{
1746 struct intel_fbc *fbc = m->private;
1747 struct drm_i915_private *i915 = fbc->i915;
1748 struct intel_plane *plane;
1749 intel_wakeref_t wakeref;
1750
1751 drm_modeset_lock_all(&i915->drm);
1752
1753 wakeref = intel_runtime_pm_get(&i915->runtime_pm);
1754 mutex_lock(&fbc->lock);
1755
1756 if (fbc->active) {
1757 seq_puts(m, "FBC enabled\n");
1758 seq_printf(m, "Compressing: %s\n",
1759 str_yes_no(intel_fbc_is_compressing(fbc)));
1760 } else {
1761 seq_printf(m, "FBC disabled: %s\n", fbc->no_fbc_reason);
1762 }
1763
1764 for_each_intel_plane(&i915->drm, plane) {
1765 const struct intel_plane_state *plane_state =
1766 to_intel_plane_state(plane->base.state);
1767
1768 if (plane->fbc != fbc)
1769 continue;
1770
1771 seq_printf(m, "%c [PLANE:%d:%s]: %s\n",
1772 fbc->state.plane == plane ? '*' : ' ',
1773 plane->base.base.id, plane->base.name,
1774 plane_state->no_fbc_reason ?: "FBC possible");
1775 }
1776
1777 mutex_unlock(&fbc->lock);
1778 intel_runtime_pm_put(&i915->runtime_pm, wakeref);
1779
1780 drm_modeset_unlock_all(&i915->drm);
1781
1782 return 0;
1783}
1784
1785DEFINE_SHOW_ATTRIBUTE(intel_fbc_debugfs_status);
1786
1787static int intel_fbc_debugfs_false_color_get(void *data, u64 *val)
1788{
1789 struct intel_fbc *fbc = data;
1790
1791 *val = fbc->false_color;
1792
1793 return 0;
1794}
1795
1796static int intel_fbc_debugfs_false_color_set(void *data, u64 val)
1797{
1798 struct intel_fbc *fbc = data;
1799
1800 mutex_lock(&fbc->lock);
1801
1802 fbc->false_color = val;
1803
1804 if (fbc->active)
1805 fbc->funcs->set_false_color(fbc, fbc->false_color);
1806
1807 mutex_unlock(&fbc->lock);
1808
1809 return 0;
1810}
1811
1812DEFINE_SIMPLE_ATTRIBUTE(intel_fbc_debugfs_false_color_fops,
1813 intel_fbc_debugfs_false_color_get,
1814 intel_fbc_debugfs_false_color_set,
1815 "%llu\n");
1816
1817static void intel_fbc_debugfs_add(struct intel_fbc *fbc,
1818 struct dentry *parent)
1819{
1820 debugfs_create_file("i915_fbc_status", 0444, parent,
1821 fbc, &intel_fbc_debugfs_status_fops);
1822
1823 if (fbc->funcs->set_false_color)
1824 debugfs_create_file("i915_fbc_false_color", 0644, parent,
1825 fbc, &intel_fbc_debugfs_false_color_fops);
1826}
1827
1828void intel_fbc_crtc_debugfs_add(struct intel_crtc *crtc)
1829{
1830 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
1831
1832 if (plane->fbc)
1833 intel_fbc_debugfs_add(plane->fbc, crtc->base.debugfs_entry);
1834}
1835
1836/* FIXME: remove this once igt is on board with per-crtc stuff */
1837void intel_fbc_debugfs_register(struct drm_i915_private *i915)
1838{
1839 struct drm_minor *minor = i915->drm.primary;
1840 struct intel_fbc *fbc;
1841
1842 fbc = i915->display.fbc[INTEL_FBC_A];
1843 if (fbc)
1844 intel_fbc_debugfs_add(fbc, minor->debugfs_root);
1845}