Loading...
1/*
2 * Copyright 2009 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26/*
27 * Authors:
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Dave Airlie
30 */
31#include <linux/seq_file.h>
32#include <linux/atomic.h>
33#include <linux/wait.h>
34#include <linux/kref.h>
35#include <linux/slab.h>
36#include <linux/firmware.h>
37#include <drm/drmP.h>
38#include "amdgpu.h"
39#include "amdgpu_trace.h"
40
41/*
42 * Fences
43 * Fences mark an event in the GPUs pipeline and are used
44 * for GPU/CPU synchronization. When the fence is written,
45 * it is expected that all buffers associated with that fence
46 * are no longer in use by the associated ring on the GPU and
47 * that the the relevant GPU caches have been flushed.
48 */
49
50struct amdgpu_fence {
51 struct fence base;
52
53 /* RB, DMA, etc. */
54 struct amdgpu_ring *ring;
55};
56
57static struct kmem_cache *amdgpu_fence_slab;
58static atomic_t amdgpu_fence_slab_ref = ATOMIC_INIT(0);
59
60/*
61 * Cast helper
62 */
63static const struct fence_ops amdgpu_fence_ops;
64static inline struct amdgpu_fence *to_amdgpu_fence(struct fence *f)
65{
66 struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base);
67
68 if (__f->base.ops == &amdgpu_fence_ops)
69 return __f;
70
71 return NULL;
72}
73
74/**
75 * amdgpu_fence_write - write a fence value
76 *
77 * @ring: ring the fence is associated with
78 * @seq: sequence number to write
79 *
80 * Writes a fence value to memory (all asics).
81 */
82static void amdgpu_fence_write(struct amdgpu_ring *ring, u32 seq)
83{
84 struct amdgpu_fence_driver *drv = &ring->fence_drv;
85
86 if (drv->cpu_addr)
87 *drv->cpu_addr = cpu_to_le32(seq);
88}
89
90/**
91 * amdgpu_fence_read - read a fence value
92 *
93 * @ring: ring the fence is associated with
94 *
95 * Reads a fence value from memory (all asics).
96 * Returns the value of the fence read from memory.
97 */
98static u32 amdgpu_fence_read(struct amdgpu_ring *ring)
99{
100 struct amdgpu_fence_driver *drv = &ring->fence_drv;
101 u32 seq = 0;
102
103 if (drv->cpu_addr)
104 seq = le32_to_cpu(*drv->cpu_addr);
105 else
106 seq = atomic_read(&drv->last_seq);
107
108 return seq;
109}
110
111/**
112 * amdgpu_fence_emit - emit a fence on the requested ring
113 *
114 * @ring: ring the fence is associated with
115 * @f: resulting fence object
116 *
117 * Emits a fence command on the requested ring (all asics).
118 * Returns 0 on success, -ENOMEM on failure.
119 */
120int amdgpu_fence_emit(struct amdgpu_ring *ring, struct fence **f)
121{
122 struct amdgpu_device *adev = ring->adev;
123 struct amdgpu_fence *fence;
124 struct fence *old, **ptr;
125 uint32_t seq;
126
127 fence = kmem_cache_alloc(amdgpu_fence_slab, GFP_KERNEL);
128 if (fence == NULL)
129 return -ENOMEM;
130
131 seq = ++ring->fence_drv.sync_seq;
132 fence->ring = ring;
133 fence_init(&fence->base, &amdgpu_fence_ops,
134 &ring->fence_drv.lock,
135 adev->fence_context + ring->idx,
136 seq);
137 amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
138 seq, AMDGPU_FENCE_FLAG_INT);
139
140 ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask];
141 /* This function can't be called concurrently anyway, otherwise
142 * emitting the fence would mess up the hardware ring buffer.
143 */
144 old = rcu_dereference_protected(*ptr, 1);
145 if (old && !fence_is_signaled(old)) {
146 DRM_INFO("rcu slot is busy\n");
147 fence_wait(old, false);
148 }
149
150 rcu_assign_pointer(*ptr, fence_get(&fence->base));
151
152 *f = &fence->base;
153
154 return 0;
155}
156
157/**
158 * amdgpu_fence_schedule_fallback - schedule fallback check
159 *
160 * @ring: pointer to struct amdgpu_ring
161 *
162 * Start a timer as fallback to our interrupts.
163 */
164static void amdgpu_fence_schedule_fallback(struct amdgpu_ring *ring)
165{
166 mod_timer(&ring->fence_drv.fallback_timer,
167 jiffies + AMDGPU_FENCE_JIFFIES_TIMEOUT);
168}
169
170/**
171 * amdgpu_fence_process - check for fence activity
172 *
173 * @ring: pointer to struct amdgpu_ring
174 *
175 * Checks the current fence value and calculates the last
176 * signalled fence value. Wakes the fence queue if the
177 * sequence number has increased.
178 */
179void amdgpu_fence_process(struct amdgpu_ring *ring)
180{
181 struct amdgpu_fence_driver *drv = &ring->fence_drv;
182 uint32_t seq, last_seq;
183 int r;
184
185 do {
186 last_seq = atomic_read(&ring->fence_drv.last_seq);
187 seq = amdgpu_fence_read(ring);
188
189 } while (atomic_cmpxchg(&drv->last_seq, last_seq, seq) != last_seq);
190
191 if (seq != ring->fence_drv.sync_seq)
192 amdgpu_fence_schedule_fallback(ring);
193
194 while (last_seq != seq) {
195 struct fence *fence, **ptr;
196
197 ptr = &drv->fences[++last_seq & drv->num_fences_mask];
198
199 /* There is always exactly one thread signaling this fence slot */
200 fence = rcu_dereference_protected(*ptr, 1);
201 rcu_assign_pointer(*ptr, NULL);
202
203 BUG_ON(!fence);
204
205 r = fence_signal(fence);
206 if (!r)
207 FENCE_TRACE(fence, "signaled from irq context\n");
208 else
209 BUG();
210
211 fence_put(fence);
212 }
213}
214
215/**
216 * amdgpu_fence_fallback - fallback for hardware interrupts
217 *
218 * @work: delayed work item
219 *
220 * Checks for fence activity.
221 */
222static void amdgpu_fence_fallback(unsigned long arg)
223{
224 struct amdgpu_ring *ring = (void *)arg;
225
226 amdgpu_fence_process(ring);
227}
228
229/**
230 * amdgpu_fence_wait_empty - wait for all fences to signal
231 *
232 * @adev: amdgpu device pointer
233 * @ring: ring index the fence is associated with
234 *
235 * Wait for all fences on the requested ring to signal (all asics).
236 * Returns 0 if the fences have passed, error for all other cases.
237 */
238int amdgpu_fence_wait_empty(struct amdgpu_ring *ring)
239{
240 uint64_t seq = ACCESS_ONCE(ring->fence_drv.sync_seq);
241 struct fence *fence, **ptr;
242 int r;
243
244 if (!seq)
245 return 0;
246
247 ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask];
248 rcu_read_lock();
249 fence = rcu_dereference(*ptr);
250 if (!fence || !fence_get_rcu(fence)) {
251 rcu_read_unlock();
252 return 0;
253 }
254 rcu_read_unlock();
255
256 r = fence_wait(fence, false);
257 fence_put(fence);
258 return r;
259}
260
261/**
262 * amdgpu_fence_count_emitted - get the count of emitted fences
263 *
264 * @ring: ring the fence is associated with
265 *
266 * Get the number of fences emitted on the requested ring (all asics).
267 * Returns the number of emitted fences on the ring. Used by the
268 * dynpm code to ring track activity.
269 */
270unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring)
271{
272 uint64_t emitted;
273
274 /* We are not protected by ring lock when reading the last sequence
275 * but it's ok to report slightly wrong fence count here.
276 */
277 amdgpu_fence_process(ring);
278 emitted = 0x100000000ull;
279 emitted -= atomic_read(&ring->fence_drv.last_seq);
280 emitted += ACCESS_ONCE(ring->fence_drv.sync_seq);
281 return lower_32_bits(emitted);
282}
283
284/**
285 * amdgpu_fence_driver_start_ring - make the fence driver
286 * ready for use on the requested ring.
287 *
288 * @ring: ring to start the fence driver on
289 * @irq_src: interrupt source to use for this ring
290 * @irq_type: interrupt type to use for this ring
291 *
292 * Make the fence driver ready for processing (all asics).
293 * Not all asics have all rings, so each asic will only
294 * start the fence driver on the rings it has.
295 * Returns 0 for success, errors for failure.
296 */
297int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
298 struct amdgpu_irq_src *irq_src,
299 unsigned irq_type)
300{
301 struct amdgpu_device *adev = ring->adev;
302 uint64_t index;
303
304 if (ring != &adev->uvd.ring) {
305 ring->fence_drv.cpu_addr = &adev->wb.wb[ring->fence_offs];
306 ring->fence_drv.gpu_addr = adev->wb.gpu_addr + (ring->fence_offs * 4);
307 } else {
308 /* put fence directly behind firmware */
309 index = ALIGN(adev->uvd.fw->size, 8);
310 ring->fence_drv.cpu_addr = adev->uvd.cpu_addr + index;
311 ring->fence_drv.gpu_addr = adev->uvd.gpu_addr + index;
312 }
313 amdgpu_fence_write(ring, atomic_read(&ring->fence_drv.last_seq));
314 amdgpu_irq_get(adev, irq_src, irq_type);
315
316 ring->fence_drv.irq_src = irq_src;
317 ring->fence_drv.irq_type = irq_type;
318 ring->fence_drv.initialized = true;
319
320 dev_info(adev->dev, "fence driver on ring %d use gpu addr 0x%016llx, "
321 "cpu addr 0x%p\n", ring->idx,
322 ring->fence_drv.gpu_addr, ring->fence_drv.cpu_addr);
323 return 0;
324}
325
326/**
327 * amdgpu_fence_driver_init_ring - init the fence driver
328 * for the requested ring.
329 *
330 * @ring: ring to init the fence driver on
331 * @num_hw_submission: number of entries on the hardware queue
332 *
333 * Init the fence driver for the requested ring (all asics).
334 * Helper function for amdgpu_fence_driver_init().
335 */
336int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
337 unsigned num_hw_submission)
338{
339 long timeout;
340 int r;
341
342 /* Check that num_hw_submission is a power of two */
343 if ((num_hw_submission & (num_hw_submission - 1)) != 0)
344 return -EINVAL;
345
346 ring->fence_drv.cpu_addr = NULL;
347 ring->fence_drv.gpu_addr = 0;
348 ring->fence_drv.sync_seq = 0;
349 atomic_set(&ring->fence_drv.last_seq, 0);
350 ring->fence_drv.initialized = false;
351
352 setup_timer(&ring->fence_drv.fallback_timer, amdgpu_fence_fallback,
353 (unsigned long)ring);
354
355 ring->fence_drv.num_fences_mask = num_hw_submission - 1;
356 spin_lock_init(&ring->fence_drv.lock);
357 ring->fence_drv.fences = kcalloc(num_hw_submission, sizeof(void *),
358 GFP_KERNEL);
359 if (!ring->fence_drv.fences)
360 return -ENOMEM;
361
362 timeout = msecs_to_jiffies(amdgpu_lockup_timeout);
363 if (timeout == 0) {
364 /*
365 * FIXME:
366 * Delayed workqueue cannot use it directly,
367 * so the scheduler will not use delayed workqueue if
368 * MAX_SCHEDULE_TIMEOUT is set.
369 * Currently keep it simple and silly.
370 */
371 timeout = MAX_SCHEDULE_TIMEOUT;
372 }
373 r = amd_sched_init(&ring->sched, &amdgpu_sched_ops,
374 num_hw_submission,
375 timeout, ring->name);
376 if (r) {
377 DRM_ERROR("Failed to create scheduler on ring %s.\n",
378 ring->name);
379 return r;
380 }
381
382 return 0;
383}
384
385/**
386 * amdgpu_fence_driver_init - init the fence driver
387 * for all possible rings.
388 *
389 * @adev: amdgpu device pointer
390 *
391 * Init the fence driver for all possible rings (all asics).
392 * Not all asics have all rings, so each asic will only
393 * start the fence driver on the rings it has using
394 * amdgpu_fence_driver_start_ring().
395 * Returns 0 for success.
396 */
397int amdgpu_fence_driver_init(struct amdgpu_device *adev)
398{
399 if (atomic_inc_return(&amdgpu_fence_slab_ref) == 1) {
400 amdgpu_fence_slab = kmem_cache_create(
401 "amdgpu_fence", sizeof(struct amdgpu_fence), 0,
402 SLAB_HWCACHE_ALIGN, NULL);
403 if (!amdgpu_fence_slab)
404 return -ENOMEM;
405 }
406 if (amdgpu_debugfs_fence_init(adev))
407 dev_err(adev->dev, "fence debugfs file creation failed\n");
408
409 return 0;
410}
411
412/**
413 * amdgpu_fence_driver_fini - tear down the fence driver
414 * for all possible rings.
415 *
416 * @adev: amdgpu device pointer
417 *
418 * Tear down the fence driver for all possible rings (all asics).
419 */
420void amdgpu_fence_driver_fini(struct amdgpu_device *adev)
421{
422 unsigned i, j;
423 int r;
424
425 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
426 struct amdgpu_ring *ring = adev->rings[i];
427
428 if (!ring || !ring->fence_drv.initialized)
429 continue;
430 r = amdgpu_fence_wait_empty(ring);
431 if (r) {
432 /* no need to trigger GPU reset as we are unloading */
433 amdgpu_fence_driver_force_completion(adev);
434 }
435 amdgpu_irq_put(adev, ring->fence_drv.irq_src,
436 ring->fence_drv.irq_type);
437 amd_sched_fini(&ring->sched);
438 del_timer_sync(&ring->fence_drv.fallback_timer);
439 for (j = 0; j <= ring->fence_drv.num_fences_mask; ++j)
440 fence_put(ring->fence_drv.fences[i]);
441 kfree(ring->fence_drv.fences);
442 ring->fence_drv.initialized = false;
443 }
444
445 if (atomic_dec_and_test(&amdgpu_fence_slab_ref))
446 kmem_cache_destroy(amdgpu_fence_slab);
447}
448
449/**
450 * amdgpu_fence_driver_suspend - suspend the fence driver
451 * for all possible rings.
452 *
453 * @adev: amdgpu device pointer
454 *
455 * Suspend the fence driver for all possible rings (all asics).
456 */
457void amdgpu_fence_driver_suspend(struct amdgpu_device *adev)
458{
459 int i, r;
460
461 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
462 struct amdgpu_ring *ring = adev->rings[i];
463 if (!ring || !ring->fence_drv.initialized)
464 continue;
465
466 /* wait for gpu to finish processing current batch */
467 r = amdgpu_fence_wait_empty(ring);
468 if (r) {
469 /* delay GPU reset to resume */
470 amdgpu_fence_driver_force_completion(adev);
471 }
472
473 /* disable the interrupt */
474 amdgpu_irq_put(adev, ring->fence_drv.irq_src,
475 ring->fence_drv.irq_type);
476 }
477}
478
479/**
480 * amdgpu_fence_driver_resume - resume the fence driver
481 * for all possible rings.
482 *
483 * @adev: amdgpu device pointer
484 *
485 * Resume the fence driver for all possible rings (all asics).
486 * Not all asics have all rings, so each asic will only
487 * start the fence driver on the rings it has using
488 * amdgpu_fence_driver_start_ring().
489 * Returns 0 for success.
490 */
491void amdgpu_fence_driver_resume(struct amdgpu_device *adev)
492{
493 int i;
494
495 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
496 struct amdgpu_ring *ring = adev->rings[i];
497 if (!ring || !ring->fence_drv.initialized)
498 continue;
499
500 /* enable the interrupt */
501 amdgpu_irq_get(adev, ring->fence_drv.irq_src,
502 ring->fence_drv.irq_type);
503 }
504}
505
506/**
507 * amdgpu_fence_driver_force_completion - force all fence waiter to complete
508 *
509 * @adev: amdgpu device pointer
510 *
511 * In case of GPU reset failure make sure no process keep waiting on fence
512 * that will never complete.
513 */
514void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev)
515{
516 int i;
517
518 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
519 struct amdgpu_ring *ring = adev->rings[i];
520 if (!ring || !ring->fence_drv.initialized)
521 continue;
522
523 amdgpu_fence_write(ring, ring->fence_drv.sync_seq);
524 }
525}
526
527/*
528 * Common fence implementation
529 */
530
531static const char *amdgpu_fence_get_driver_name(struct fence *fence)
532{
533 return "amdgpu";
534}
535
536static const char *amdgpu_fence_get_timeline_name(struct fence *f)
537{
538 struct amdgpu_fence *fence = to_amdgpu_fence(f);
539 return (const char *)fence->ring->name;
540}
541
542/**
543 * amdgpu_fence_enable_signaling - enable signalling on fence
544 * @fence: fence
545 *
546 * This function is called with fence_queue lock held, and adds a callback
547 * to fence_queue that checks if this fence is signaled, and if so it
548 * signals the fence and removes itself.
549 */
550static bool amdgpu_fence_enable_signaling(struct fence *f)
551{
552 struct amdgpu_fence *fence = to_amdgpu_fence(f);
553 struct amdgpu_ring *ring = fence->ring;
554
555 if (!timer_pending(&ring->fence_drv.fallback_timer))
556 amdgpu_fence_schedule_fallback(ring);
557
558 FENCE_TRACE(&fence->base, "armed on ring %i!\n", ring->idx);
559
560 return true;
561}
562
563/**
564 * amdgpu_fence_free - free up the fence memory
565 *
566 * @rcu: RCU callback head
567 *
568 * Free up the fence memory after the RCU grace period.
569 */
570static void amdgpu_fence_free(struct rcu_head *rcu)
571{
572 struct fence *f = container_of(rcu, struct fence, rcu);
573 struct amdgpu_fence *fence = to_amdgpu_fence(f);
574 kmem_cache_free(amdgpu_fence_slab, fence);
575}
576
577/**
578 * amdgpu_fence_release - callback that fence can be freed
579 *
580 * @fence: fence
581 *
582 * This function is called when the reference count becomes zero.
583 * It just RCU schedules freeing up the fence.
584 */
585static void amdgpu_fence_release(struct fence *f)
586{
587 call_rcu(&f->rcu, amdgpu_fence_free);
588}
589
590static const struct fence_ops amdgpu_fence_ops = {
591 .get_driver_name = amdgpu_fence_get_driver_name,
592 .get_timeline_name = amdgpu_fence_get_timeline_name,
593 .enable_signaling = amdgpu_fence_enable_signaling,
594 .wait = fence_default_wait,
595 .release = amdgpu_fence_release,
596};
597
598/*
599 * Fence debugfs
600 */
601#if defined(CONFIG_DEBUG_FS)
602static int amdgpu_debugfs_fence_info(struct seq_file *m, void *data)
603{
604 struct drm_info_node *node = (struct drm_info_node *)m->private;
605 struct drm_device *dev = node->minor->dev;
606 struct amdgpu_device *adev = dev->dev_private;
607 int i;
608
609 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
610 struct amdgpu_ring *ring = adev->rings[i];
611 if (!ring || !ring->fence_drv.initialized)
612 continue;
613
614 amdgpu_fence_process(ring);
615
616 seq_printf(m, "--- ring %d (%s) ---\n", i, ring->name);
617 seq_printf(m, "Last signaled fence 0x%08x\n",
618 atomic_read(&ring->fence_drv.last_seq));
619 seq_printf(m, "Last emitted 0x%08x\n",
620 ring->fence_drv.sync_seq);
621 }
622 return 0;
623}
624
625/**
626 * amdgpu_debugfs_gpu_reset - manually trigger a gpu reset
627 *
628 * Manually trigger a gpu reset at the next fence wait.
629 */
630static int amdgpu_debugfs_gpu_reset(struct seq_file *m, void *data)
631{
632 struct drm_info_node *node = (struct drm_info_node *) m->private;
633 struct drm_device *dev = node->minor->dev;
634 struct amdgpu_device *adev = dev->dev_private;
635
636 seq_printf(m, "gpu reset\n");
637 amdgpu_gpu_reset(adev);
638
639 return 0;
640}
641
642static struct drm_info_list amdgpu_debugfs_fence_list[] = {
643 {"amdgpu_fence_info", &amdgpu_debugfs_fence_info, 0, NULL},
644 {"amdgpu_gpu_reset", &amdgpu_debugfs_gpu_reset, 0, NULL}
645};
646#endif
647
648int amdgpu_debugfs_fence_init(struct amdgpu_device *adev)
649{
650#if defined(CONFIG_DEBUG_FS)
651 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_fence_list, 2);
652#else
653 return 0;
654#endif
655}
656
1/*
2 * Copyright 2009 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26/*
27 * Authors:
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Dave Airlie
30 */
31#include <linux/seq_file.h>
32#include <linux/atomic.h>
33#include <linux/wait.h>
34#include <linux/kref.h>
35#include <linux/slab.h>
36#include <linux/firmware.h>
37#include <linux/pm_runtime.h>
38
39#include <drm/drm_drv.h>
40#include "amdgpu.h"
41#include "amdgpu_trace.h"
42#include "amdgpu_reset.h"
43
44/*
45 * Fences
46 * Fences mark an event in the GPUs pipeline and are used
47 * for GPU/CPU synchronization. When the fence is written,
48 * it is expected that all buffers associated with that fence
49 * are no longer in use by the associated ring on the GPU and
50 * that the relevant GPU caches have been flushed.
51 */
52
53struct amdgpu_fence {
54 struct dma_fence base;
55
56 /* RB, DMA, etc. */
57 struct amdgpu_ring *ring;
58 ktime_t start_timestamp;
59};
60
61static struct kmem_cache *amdgpu_fence_slab;
62
63int amdgpu_fence_slab_init(void)
64{
65 amdgpu_fence_slab = kmem_cache_create(
66 "amdgpu_fence", sizeof(struct amdgpu_fence), 0,
67 SLAB_HWCACHE_ALIGN, NULL);
68 if (!amdgpu_fence_slab)
69 return -ENOMEM;
70 return 0;
71}
72
73void amdgpu_fence_slab_fini(void)
74{
75 rcu_barrier();
76 kmem_cache_destroy(amdgpu_fence_slab);
77}
78/*
79 * Cast helper
80 */
81static const struct dma_fence_ops amdgpu_fence_ops;
82static const struct dma_fence_ops amdgpu_job_fence_ops;
83static inline struct amdgpu_fence *to_amdgpu_fence(struct dma_fence *f)
84{
85 struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base);
86
87 if (__f->base.ops == &amdgpu_fence_ops ||
88 __f->base.ops == &amdgpu_job_fence_ops)
89 return __f;
90
91 return NULL;
92}
93
94/**
95 * amdgpu_fence_write - write a fence value
96 *
97 * @ring: ring the fence is associated with
98 * @seq: sequence number to write
99 *
100 * Writes a fence value to memory (all asics).
101 */
102static void amdgpu_fence_write(struct amdgpu_ring *ring, u32 seq)
103{
104 struct amdgpu_fence_driver *drv = &ring->fence_drv;
105
106 if (drv->cpu_addr)
107 *drv->cpu_addr = cpu_to_le32(seq);
108}
109
110/**
111 * amdgpu_fence_read - read a fence value
112 *
113 * @ring: ring the fence is associated with
114 *
115 * Reads a fence value from memory (all asics).
116 * Returns the value of the fence read from memory.
117 */
118static u32 amdgpu_fence_read(struct amdgpu_ring *ring)
119{
120 struct amdgpu_fence_driver *drv = &ring->fence_drv;
121 u32 seq = 0;
122
123 if (drv->cpu_addr)
124 seq = le32_to_cpu(*drv->cpu_addr);
125 else
126 seq = atomic_read(&drv->last_seq);
127
128 return seq;
129}
130
131/**
132 * amdgpu_fence_emit - emit a fence on the requested ring
133 *
134 * @ring: ring the fence is associated with
135 * @f: resulting fence object
136 * @job: job the fence is embedded in
137 * @flags: flags to pass into the subordinate .emit_fence() call
138 *
139 * Emits a fence command on the requested ring (all asics).
140 * Returns 0 on success, -ENOMEM on failure.
141 */
142int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **f, struct amdgpu_job *job,
143 unsigned flags)
144{
145 struct amdgpu_device *adev = ring->adev;
146 struct dma_fence *fence;
147 struct amdgpu_fence *am_fence;
148 struct dma_fence __rcu **ptr;
149 uint32_t seq;
150 int r;
151
152 if (job == NULL) {
153 /* create a sperate hw fence */
154 am_fence = kmem_cache_alloc(amdgpu_fence_slab, GFP_ATOMIC);
155 if (am_fence == NULL)
156 return -ENOMEM;
157 fence = &am_fence->base;
158 am_fence->ring = ring;
159 } else {
160 /* take use of job-embedded fence */
161 fence = &job->hw_fence;
162 }
163
164 seq = ++ring->fence_drv.sync_seq;
165 if (job && job->job_run_counter) {
166 /* reinit seq for resubmitted jobs */
167 fence->seqno = seq;
168 /* TO be inline with external fence creation and other drivers */
169 dma_fence_get(fence);
170 } else {
171 if (job) {
172 dma_fence_init(fence, &amdgpu_job_fence_ops,
173 &ring->fence_drv.lock,
174 adev->fence_context + ring->idx, seq);
175 /* Against remove in amdgpu_job_{free, free_cb} */
176 dma_fence_get(fence);
177 }
178 else
179 dma_fence_init(fence, &amdgpu_fence_ops,
180 &ring->fence_drv.lock,
181 adev->fence_context + ring->idx, seq);
182 }
183
184 amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
185 seq, flags | AMDGPU_FENCE_FLAG_INT);
186 pm_runtime_get_noresume(adev_to_drm(adev)->dev);
187 ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask];
188 if (unlikely(rcu_dereference_protected(*ptr, 1))) {
189 struct dma_fence *old;
190
191 rcu_read_lock();
192 old = dma_fence_get_rcu_safe(ptr);
193 rcu_read_unlock();
194
195 if (old) {
196 r = dma_fence_wait(old, false);
197 dma_fence_put(old);
198 if (r)
199 return r;
200 }
201 }
202
203 to_amdgpu_fence(fence)->start_timestamp = ktime_get();
204
205 /* This function can't be called concurrently anyway, otherwise
206 * emitting the fence would mess up the hardware ring buffer.
207 */
208 rcu_assign_pointer(*ptr, dma_fence_get(fence));
209
210 *f = fence;
211
212 return 0;
213}
214
215/**
216 * amdgpu_fence_emit_polling - emit a fence on the requeste ring
217 *
218 * @ring: ring the fence is associated with
219 * @s: resulting sequence number
220 * @timeout: the timeout for waiting in usecs
221 *
222 * Emits a fence command on the requested ring (all asics).
223 * Used For polling fence.
224 * Returns 0 on success, -ENOMEM on failure.
225 */
226int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s,
227 uint32_t timeout)
228{
229 uint32_t seq;
230 signed long r;
231
232 if (!s)
233 return -EINVAL;
234
235 seq = ++ring->fence_drv.sync_seq;
236 r = amdgpu_fence_wait_polling(ring,
237 seq - ring->fence_drv.num_fences_mask,
238 timeout);
239 if (r < 1)
240 return -ETIMEDOUT;
241
242 amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
243 seq, 0);
244
245 *s = seq;
246
247 return 0;
248}
249
250/**
251 * amdgpu_fence_schedule_fallback - schedule fallback check
252 *
253 * @ring: pointer to struct amdgpu_ring
254 *
255 * Start a timer as fallback to our interrupts.
256 */
257static void amdgpu_fence_schedule_fallback(struct amdgpu_ring *ring)
258{
259 mod_timer(&ring->fence_drv.fallback_timer,
260 jiffies + AMDGPU_FENCE_JIFFIES_TIMEOUT);
261}
262
263/**
264 * amdgpu_fence_process - check for fence activity
265 *
266 * @ring: pointer to struct amdgpu_ring
267 *
268 * Checks the current fence value and calculates the last
269 * signalled fence value. Wakes the fence queue if the
270 * sequence number has increased.
271 *
272 * Returns true if fence was processed
273 */
274bool amdgpu_fence_process(struct amdgpu_ring *ring)
275{
276 struct amdgpu_fence_driver *drv = &ring->fence_drv;
277 struct amdgpu_device *adev = ring->adev;
278 uint32_t seq, last_seq;
279
280 do {
281 last_seq = atomic_read(&ring->fence_drv.last_seq);
282 seq = amdgpu_fence_read(ring);
283
284 } while (atomic_cmpxchg(&drv->last_seq, last_seq, seq) != last_seq);
285
286 if (del_timer(&ring->fence_drv.fallback_timer) &&
287 seq != ring->fence_drv.sync_seq)
288 amdgpu_fence_schedule_fallback(ring);
289
290 if (unlikely(seq == last_seq))
291 return false;
292
293 last_seq &= drv->num_fences_mask;
294 seq &= drv->num_fences_mask;
295
296 do {
297 struct dma_fence *fence, **ptr;
298
299 ++last_seq;
300 last_seq &= drv->num_fences_mask;
301 ptr = &drv->fences[last_seq];
302
303 /* There is always exactly one thread signaling this fence slot */
304 fence = rcu_dereference_protected(*ptr, 1);
305 RCU_INIT_POINTER(*ptr, NULL);
306
307 if (!fence)
308 continue;
309
310 dma_fence_signal(fence);
311 dma_fence_put(fence);
312 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
313 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
314 } while (last_seq != seq);
315
316 return true;
317}
318
319/**
320 * amdgpu_fence_fallback - fallback for hardware interrupts
321 *
322 * @t: timer context used to obtain the pointer to ring structure
323 *
324 * Checks for fence activity.
325 */
326static void amdgpu_fence_fallback(struct timer_list *t)
327{
328 struct amdgpu_ring *ring = from_timer(ring, t,
329 fence_drv.fallback_timer);
330
331 if (amdgpu_fence_process(ring))
332 DRM_WARN("Fence fallback timer expired on ring %s\n", ring->name);
333}
334
335/**
336 * amdgpu_fence_wait_empty - wait for all fences to signal
337 *
338 * @ring: ring index the fence is associated with
339 *
340 * Wait for all fences on the requested ring to signal (all asics).
341 * Returns 0 if the fences have passed, error for all other cases.
342 */
343int amdgpu_fence_wait_empty(struct amdgpu_ring *ring)
344{
345 uint64_t seq = READ_ONCE(ring->fence_drv.sync_seq);
346 struct dma_fence *fence, **ptr;
347 int r;
348
349 if (!seq)
350 return 0;
351
352 ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask];
353 rcu_read_lock();
354 fence = rcu_dereference(*ptr);
355 if (!fence || !dma_fence_get_rcu(fence)) {
356 rcu_read_unlock();
357 return 0;
358 }
359 rcu_read_unlock();
360
361 r = dma_fence_wait(fence, false);
362 dma_fence_put(fence);
363 return r;
364}
365
366/**
367 * amdgpu_fence_wait_polling - busy wait for givn sequence number
368 *
369 * @ring: ring index the fence is associated with
370 * @wait_seq: sequence number to wait
371 * @timeout: the timeout for waiting in usecs
372 *
373 * Wait for all fences on the requested ring to signal (all asics).
374 * Returns left time if no timeout, 0 or minus if timeout.
375 */
376signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring,
377 uint32_t wait_seq,
378 signed long timeout)
379{
380 uint32_t seq;
381
382 do {
383 seq = amdgpu_fence_read(ring);
384 udelay(5);
385 timeout -= 5;
386 } while ((int32_t)(wait_seq - seq) > 0 && timeout > 0);
387
388 return timeout > 0 ? timeout : 0;
389}
390/**
391 * amdgpu_fence_count_emitted - get the count of emitted fences
392 *
393 * @ring: ring the fence is associated with
394 *
395 * Get the number of fences emitted on the requested ring (all asics).
396 * Returns the number of emitted fences on the ring. Used by the
397 * dynpm code to ring track activity.
398 */
399unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring)
400{
401 uint64_t emitted;
402
403 /* We are not protected by ring lock when reading the last sequence
404 * but it's ok to report slightly wrong fence count here.
405 */
406 emitted = 0x100000000ull;
407 emitted -= atomic_read(&ring->fence_drv.last_seq);
408 emitted += READ_ONCE(ring->fence_drv.sync_seq);
409 return lower_32_bits(emitted);
410}
411
412/**
413 * amdgpu_fence_last_unsignaled_time_us - the time fence emitted until now
414 * @ring: ring the fence is associated with
415 *
416 * Find the earliest fence unsignaled until now, calculate the time delta
417 * between the time fence emitted and now.
418 */
419u64 amdgpu_fence_last_unsignaled_time_us(struct amdgpu_ring *ring)
420{
421 struct amdgpu_fence_driver *drv = &ring->fence_drv;
422 struct dma_fence *fence;
423 uint32_t last_seq, sync_seq;
424
425 last_seq = atomic_read(&ring->fence_drv.last_seq);
426 sync_seq = READ_ONCE(ring->fence_drv.sync_seq);
427 if (last_seq == sync_seq)
428 return 0;
429
430 ++last_seq;
431 last_seq &= drv->num_fences_mask;
432 fence = drv->fences[last_seq];
433 if (!fence)
434 return 0;
435
436 return ktime_us_delta(ktime_get(),
437 to_amdgpu_fence(fence)->start_timestamp);
438}
439
440/**
441 * amdgpu_fence_update_start_timestamp - update the timestamp of the fence
442 * @ring: ring the fence is associated with
443 * @seq: the fence seq number to update.
444 * @timestamp: the start timestamp to update.
445 *
446 * The function called at the time the fence and related ib is about to
447 * resubmit to gpu in MCBP scenario. Thus we do not consider race condition
448 * with amdgpu_fence_process to modify the same fence.
449 */
450void amdgpu_fence_update_start_timestamp(struct amdgpu_ring *ring, uint32_t seq, ktime_t timestamp)
451{
452 struct amdgpu_fence_driver *drv = &ring->fence_drv;
453 struct dma_fence *fence;
454
455 seq &= drv->num_fences_mask;
456 fence = drv->fences[seq];
457 if (!fence)
458 return;
459
460 to_amdgpu_fence(fence)->start_timestamp = timestamp;
461}
462
463/**
464 * amdgpu_fence_driver_start_ring - make the fence driver
465 * ready for use on the requested ring.
466 *
467 * @ring: ring to start the fence driver on
468 * @irq_src: interrupt source to use for this ring
469 * @irq_type: interrupt type to use for this ring
470 *
471 * Make the fence driver ready for processing (all asics).
472 * Not all asics have all rings, so each asic will only
473 * start the fence driver on the rings it has.
474 * Returns 0 for success, errors for failure.
475 */
476int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
477 struct amdgpu_irq_src *irq_src,
478 unsigned irq_type)
479{
480 struct amdgpu_device *adev = ring->adev;
481 uint64_t index;
482
483 if (ring->funcs->type != AMDGPU_RING_TYPE_UVD) {
484 ring->fence_drv.cpu_addr = ring->fence_cpu_addr;
485 ring->fence_drv.gpu_addr = ring->fence_gpu_addr;
486 } else {
487 /* put fence directly behind firmware */
488 index = ALIGN(adev->uvd.fw->size, 8);
489 ring->fence_drv.cpu_addr = adev->uvd.inst[ring->me].cpu_addr + index;
490 ring->fence_drv.gpu_addr = adev->uvd.inst[ring->me].gpu_addr + index;
491 }
492 amdgpu_fence_write(ring, atomic_read(&ring->fence_drv.last_seq));
493
494 ring->fence_drv.irq_src = irq_src;
495 ring->fence_drv.irq_type = irq_type;
496 ring->fence_drv.initialized = true;
497
498 DRM_DEV_DEBUG(adev->dev, "fence driver on ring %s use gpu addr 0x%016llx\n",
499 ring->name, ring->fence_drv.gpu_addr);
500 return 0;
501}
502
503/**
504 * amdgpu_fence_driver_init_ring - init the fence driver
505 * for the requested ring.
506 *
507 * @ring: ring to init the fence driver on
508 *
509 * Init the fence driver for the requested ring (all asics).
510 * Helper function for amdgpu_fence_driver_init().
511 */
512int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring)
513{
514 struct amdgpu_device *adev = ring->adev;
515
516 if (!adev)
517 return -EINVAL;
518
519 if (!is_power_of_2(ring->num_hw_submission))
520 return -EINVAL;
521
522 ring->fence_drv.cpu_addr = NULL;
523 ring->fence_drv.gpu_addr = 0;
524 ring->fence_drv.sync_seq = 0;
525 atomic_set(&ring->fence_drv.last_seq, 0);
526 ring->fence_drv.initialized = false;
527
528 timer_setup(&ring->fence_drv.fallback_timer, amdgpu_fence_fallback, 0);
529
530 ring->fence_drv.num_fences_mask = ring->num_hw_submission * 2 - 1;
531 spin_lock_init(&ring->fence_drv.lock);
532 ring->fence_drv.fences = kcalloc(ring->num_hw_submission * 2, sizeof(void *),
533 GFP_KERNEL);
534
535 if (!ring->fence_drv.fences)
536 return -ENOMEM;
537
538 return 0;
539}
540
541/**
542 * amdgpu_fence_driver_sw_init - init the fence driver
543 * for all possible rings.
544 *
545 * @adev: amdgpu device pointer
546 *
547 * Init the fence driver for all possible rings (all asics).
548 * Not all asics have all rings, so each asic will only
549 * start the fence driver on the rings it has using
550 * amdgpu_fence_driver_start_ring().
551 * Returns 0 for success.
552 */
553int amdgpu_fence_driver_sw_init(struct amdgpu_device *adev)
554{
555 return 0;
556}
557
558/**
559 * amdgpu_fence_driver_hw_fini - tear down the fence driver
560 * for all possible rings.
561 *
562 * @adev: amdgpu device pointer
563 *
564 * Tear down the fence driver for all possible rings (all asics).
565 */
566void amdgpu_fence_driver_hw_fini(struct amdgpu_device *adev)
567{
568 int i, r;
569
570 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
571 struct amdgpu_ring *ring = adev->rings[i];
572
573 if (!ring || !ring->fence_drv.initialized)
574 continue;
575
576 /* You can't wait for HW to signal if it's gone */
577 if (!drm_dev_is_unplugged(adev_to_drm(adev)))
578 r = amdgpu_fence_wait_empty(ring);
579 else
580 r = -ENODEV;
581 /* no need to trigger GPU reset as we are unloading */
582 if (r)
583 amdgpu_fence_driver_force_completion(ring);
584
585 if (ring->fence_drv.irq_src)
586 amdgpu_irq_put(adev, ring->fence_drv.irq_src,
587 ring->fence_drv.irq_type);
588
589 del_timer_sync(&ring->fence_drv.fallback_timer);
590 }
591}
592
593/* Will either stop and flush handlers for amdgpu interrupt or reanble it */
594void amdgpu_fence_driver_isr_toggle(struct amdgpu_device *adev, bool stop)
595{
596 int i;
597
598 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
599 struct amdgpu_ring *ring = adev->rings[i];
600
601 if (!ring || !ring->fence_drv.initialized || !ring->fence_drv.irq_src)
602 continue;
603
604 if (stop)
605 disable_irq(adev->irq.irq);
606 else
607 enable_irq(adev->irq.irq);
608 }
609}
610
611void amdgpu_fence_driver_sw_fini(struct amdgpu_device *adev)
612{
613 unsigned int i, j;
614
615 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
616 struct amdgpu_ring *ring = adev->rings[i];
617
618 if (!ring || !ring->fence_drv.initialized)
619 continue;
620
621 /*
622 * Notice we check for sched.ops since there's some
623 * override on the meaning of sched.ready by amdgpu.
624 * The natural check would be sched.ready, which is
625 * set as drm_sched_init() finishes...
626 */
627 if (ring->sched.ops)
628 drm_sched_fini(&ring->sched);
629
630 for (j = 0; j <= ring->fence_drv.num_fences_mask; ++j)
631 dma_fence_put(ring->fence_drv.fences[j]);
632 kfree(ring->fence_drv.fences);
633 ring->fence_drv.fences = NULL;
634 ring->fence_drv.initialized = false;
635 }
636}
637
638/**
639 * amdgpu_fence_driver_hw_init - enable the fence driver
640 * for all possible rings.
641 *
642 * @adev: amdgpu device pointer
643 *
644 * Enable the fence driver for all possible rings (all asics).
645 * Not all asics have all rings, so each asic will only
646 * start the fence driver on the rings it has using
647 * amdgpu_fence_driver_start_ring().
648 * Returns 0 for success.
649 */
650void amdgpu_fence_driver_hw_init(struct amdgpu_device *adev)
651{
652 int i;
653
654 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
655 struct amdgpu_ring *ring = adev->rings[i];
656 if (!ring || !ring->fence_drv.initialized)
657 continue;
658
659 /* enable the interrupt */
660 if (ring->fence_drv.irq_src)
661 amdgpu_irq_get(adev, ring->fence_drv.irq_src,
662 ring->fence_drv.irq_type);
663 }
664}
665
666/**
667 * amdgpu_fence_driver_clear_job_fences - clear job embedded fences of ring
668 *
669 * @ring: fence of the ring to be cleared
670 *
671 */
672void amdgpu_fence_driver_clear_job_fences(struct amdgpu_ring *ring)
673{
674 int i;
675 struct dma_fence *old, **ptr;
676
677 for (i = 0; i <= ring->fence_drv.num_fences_mask; i++) {
678 ptr = &ring->fence_drv.fences[i];
679 old = rcu_dereference_protected(*ptr, 1);
680 if (old && old->ops == &amdgpu_job_fence_ops) {
681 RCU_INIT_POINTER(*ptr, NULL);
682 dma_fence_put(old);
683 }
684 }
685}
686
687/**
688 * amdgpu_fence_driver_force_completion - force signal latest fence of ring
689 *
690 * @ring: fence of the ring to signal
691 *
692 */
693void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring)
694{
695 amdgpu_fence_write(ring, ring->fence_drv.sync_seq);
696 amdgpu_fence_process(ring);
697}
698
699/*
700 * Common fence implementation
701 */
702
703static const char *amdgpu_fence_get_driver_name(struct dma_fence *fence)
704{
705 return "amdgpu";
706}
707
708static const char *amdgpu_fence_get_timeline_name(struct dma_fence *f)
709{
710 return (const char *)to_amdgpu_fence(f)->ring->name;
711}
712
713static const char *amdgpu_job_fence_get_timeline_name(struct dma_fence *f)
714{
715 struct amdgpu_job *job = container_of(f, struct amdgpu_job, hw_fence);
716
717 return (const char *)to_amdgpu_ring(job->base.sched)->name;
718}
719
720/**
721 * amdgpu_fence_enable_signaling - enable signalling on fence
722 * @f: fence
723 *
724 * This function is called with fence_queue lock held, and adds a callback
725 * to fence_queue that checks if this fence is signaled, and if so it
726 * signals the fence and removes itself.
727 */
728static bool amdgpu_fence_enable_signaling(struct dma_fence *f)
729{
730 if (!timer_pending(&to_amdgpu_fence(f)->ring->fence_drv.fallback_timer))
731 amdgpu_fence_schedule_fallback(to_amdgpu_fence(f)->ring);
732
733 return true;
734}
735
736/**
737 * amdgpu_job_fence_enable_signaling - enable signalling on job fence
738 * @f: fence
739 *
740 * This is the simliar function with amdgpu_fence_enable_signaling above, it
741 * only handles the job embedded fence.
742 */
743static bool amdgpu_job_fence_enable_signaling(struct dma_fence *f)
744{
745 struct amdgpu_job *job = container_of(f, struct amdgpu_job, hw_fence);
746
747 if (!timer_pending(&to_amdgpu_ring(job->base.sched)->fence_drv.fallback_timer))
748 amdgpu_fence_schedule_fallback(to_amdgpu_ring(job->base.sched));
749
750 return true;
751}
752
753/**
754 * amdgpu_fence_free - free up the fence memory
755 *
756 * @rcu: RCU callback head
757 *
758 * Free up the fence memory after the RCU grace period.
759 */
760static void amdgpu_fence_free(struct rcu_head *rcu)
761{
762 struct dma_fence *f = container_of(rcu, struct dma_fence, rcu);
763
764 /* free fence_slab if it's separated fence*/
765 kmem_cache_free(amdgpu_fence_slab, to_amdgpu_fence(f));
766}
767
768/**
769 * amdgpu_job_fence_free - free up the job with embedded fence
770 *
771 * @rcu: RCU callback head
772 *
773 * Free up the job with embedded fence after the RCU grace period.
774 */
775static void amdgpu_job_fence_free(struct rcu_head *rcu)
776{
777 struct dma_fence *f = container_of(rcu, struct dma_fence, rcu);
778
779 /* free job if fence has a parent job */
780 kfree(container_of(f, struct amdgpu_job, hw_fence));
781}
782
783/**
784 * amdgpu_fence_release - callback that fence can be freed
785 *
786 * @f: fence
787 *
788 * This function is called when the reference count becomes zero.
789 * It just RCU schedules freeing up the fence.
790 */
791static void amdgpu_fence_release(struct dma_fence *f)
792{
793 call_rcu(&f->rcu, amdgpu_fence_free);
794}
795
796/**
797 * amdgpu_job_fence_release - callback that job embedded fence can be freed
798 *
799 * @f: fence
800 *
801 * This is the simliar function with amdgpu_fence_release above, it
802 * only handles the job embedded fence.
803 */
804static void amdgpu_job_fence_release(struct dma_fence *f)
805{
806 call_rcu(&f->rcu, amdgpu_job_fence_free);
807}
808
809static const struct dma_fence_ops amdgpu_fence_ops = {
810 .get_driver_name = amdgpu_fence_get_driver_name,
811 .get_timeline_name = amdgpu_fence_get_timeline_name,
812 .enable_signaling = amdgpu_fence_enable_signaling,
813 .release = amdgpu_fence_release,
814};
815
816static const struct dma_fence_ops amdgpu_job_fence_ops = {
817 .get_driver_name = amdgpu_fence_get_driver_name,
818 .get_timeline_name = amdgpu_job_fence_get_timeline_name,
819 .enable_signaling = amdgpu_job_fence_enable_signaling,
820 .release = amdgpu_job_fence_release,
821};
822
823/*
824 * Fence debugfs
825 */
826#if defined(CONFIG_DEBUG_FS)
827static int amdgpu_debugfs_fence_info_show(struct seq_file *m, void *unused)
828{
829 struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
830 int i;
831
832 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
833 struct amdgpu_ring *ring = adev->rings[i];
834 if (!ring || !ring->fence_drv.initialized)
835 continue;
836
837 amdgpu_fence_process(ring);
838
839 seq_printf(m, "--- ring %d (%s) ---\n", i, ring->name);
840 seq_printf(m, "Last signaled fence 0x%08x\n",
841 atomic_read(&ring->fence_drv.last_seq));
842 seq_printf(m, "Last emitted 0x%08x\n",
843 ring->fence_drv.sync_seq);
844
845 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX ||
846 ring->funcs->type == AMDGPU_RING_TYPE_SDMA) {
847 seq_printf(m, "Last signaled trailing fence 0x%08x\n",
848 le32_to_cpu(*ring->trail_fence_cpu_addr));
849 seq_printf(m, "Last emitted 0x%08x\n",
850 ring->trail_seq);
851 }
852
853 if (ring->funcs->type != AMDGPU_RING_TYPE_GFX)
854 continue;
855
856 /* set in CP_VMID_PREEMPT and preemption occurred */
857 seq_printf(m, "Last preempted 0x%08x\n",
858 le32_to_cpu(*(ring->fence_drv.cpu_addr + 2)));
859 /* set in CP_VMID_RESET and reset occurred */
860 seq_printf(m, "Last reset 0x%08x\n",
861 le32_to_cpu(*(ring->fence_drv.cpu_addr + 4)));
862 /* Both preemption and reset occurred */
863 seq_printf(m, "Last both 0x%08x\n",
864 le32_to_cpu(*(ring->fence_drv.cpu_addr + 6)));
865 }
866 return 0;
867}
868
869/*
870 * amdgpu_debugfs_gpu_recover - manually trigger a gpu reset & recover
871 *
872 * Manually trigger a gpu reset at the next fence wait.
873 */
874static int gpu_recover_get(void *data, u64 *val)
875{
876 struct amdgpu_device *adev = (struct amdgpu_device *)data;
877 struct drm_device *dev = adev_to_drm(adev);
878 int r;
879
880 r = pm_runtime_get_sync(dev->dev);
881 if (r < 0) {
882 pm_runtime_put_autosuspend(dev->dev);
883 return 0;
884 }
885
886 if (amdgpu_reset_domain_schedule(adev->reset_domain, &adev->reset_work))
887 flush_work(&adev->reset_work);
888
889 *val = atomic_read(&adev->reset_domain->reset_res);
890
891 pm_runtime_mark_last_busy(dev->dev);
892 pm_runtime_put_autosuspend(dev->dev);
893
894 return 0;
895}
896
897DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_fence_info);
898DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_debugfs_gpu_recover_fops, gpu_recover_get, NULL,
899 "%lld\n");
900
901static void amdgpu_debugfs_reset_work(struct work_struct *work)
902{
903 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
904 reset_work);
905
906 struct amdgpu_reset_context reset_context;
907 memset(&reset_context, 0, sizeof(reset_context));
908
909 reset_context.method = AMD_RESET_METHOD_NONE;
910 reset_context.reset_req_dev = adev;
911 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
912
913 amdgpu_device_gpu_recover(adev, NULL, &reset_context);
914}
915
916#endif
917
918void amdgpu_debugfs_fence_init(struct amdgpu_device *adev)
919{
920#if defined(CONFIG_DEBUG_FS)
921 struct drm_minor *minor = adev_to_drm(adev)->primary;
922 struct dentry *root = minor->debugfs_root;
923
924 debugfs_create_file("amdgpu_fence_info", 0444, root, adev,
925 &amdgpu_debugfs_fence_info_fops);
926
927 if (!amdgpu_sriov_vf(adev)) {
928
929 INIT_WORK(&adev->reset_work, amdgpu_debugfs_reset_work);
930 debugfs_create_file("amdgpu_gpu_recover", 0444, root, adev,
931 &amdgpu_debugfs_gpu_recover_fops);
932 }
933#endif
934}
935