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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 * Copyright (C) 2014 Kevin Cernekee <cernekee@gmail.com>
8 */
9
10#include <linux/init.h>
11#include <linux/bitops.h>
12#include <linux/bootmem.h>
13#include <linux/clk-provider.h>
14#include <linux/ioport.h>
15#include <linux/kernel.h>
16#include <linux/io.h>
17#include <linux/of.h>
18#include <linux/of_fdt.h>
19#include <linux/of_platform.h>
20#include <linux/smp.h>
21#include <asm/addrspace.h>
22#include <asm/bmips.h>
23#include <asm/bootinfo.h>
24#include <asm/cpu-type.h>
25#include <asm/mipsregs.h>
26#include <asm/prom.h>
27#include <asm/smp-ops.h>
28#include <asm/time.h>
29#include <asm/traps.h>
30
31#define RELO_NORMAL_VEC BIT(18)
32
33#define REG_BCM6328_OTP ((void __iomem *)CKSEG1ADDR(0x1000062c))
34#define BCM6328_TP1_DISABLED BIT(9)
35
36static const unsigned long kbase = VMLINUX_LOAD_ADDRESS & 0xfff00000;
37
38struct bmips_quirk {
39 const char *compatible;
40 void (*quirk_fn)(void);
41};
42
43static void kbase_setup(void)
44{
45 __raw_writel(kbase | RELO_NORMAL_VEC,
46 BMIPS_GET_CBR() + BMIPS_RELO_VECTOR_CONTROL_1);
47 ebase = kbase;
48}
49
50static void bcm3384_viper_quirks(void)
51{
52 /*
53 * Some experimental CM boxes are set up to let CM own the Viper TP0
54 * and let Linux own TP1. This requires moving the kernel
55 * load address to a non-conflicting region (e.g. via
56 * CONFIG_PHYSICAL_START) and supplying an alternate DTB.
57 * If we detect this condition, we need to move the MIPS exception
58 * vectors up to an area that we own.
59 *
60 * This is distinct from the OTHER special case mentioned in
61 * smp-bmips.c (boot on TP1, but enable SMP, then TP0 becomes our
62 * logical CPU#1). For the Viper TP1 case, SMP is off limits.
63 *
64 * Also note that many BMIPS435x CPUs do not have a
65 * BMIPS_RELO_VECTOR_CONTROL_1 register, so it isn't safe to just
66 * write VMLINUX_LOAD_ADDRESS into that register on every SoC.
67 */
68 board_ebase_setup = &kbase_setup;
69 bmips_smp_enabled = 0;
70}
71
72static void bcm63xx_fixup_cpu1(void)
73{
74 /*
75 * The bootloader has set up the CPU1 reset vector at
76 * 0xa000_0200.
77 * This conflicts with the special interrupt vector (IV).
78 * The bootloader has also set up CPU1 to respond to the wrong
79 * IPI interrupt.
80 * Here we will start up CPU1 in the background and ask it to
81 * reconfigure itself then go back to sleep.
82 */
83 memcpy((void *)0xa0000200, &bmips_smp_movevec, 0x20);
84 __sync();
85 set_c0_cause(C_SW0);
86 cpumask_set_cpu(1, &bmips_booted_mask);
87}
88
89static void bcm6328_quirks(void)
90{
91 /* Check CPU1 status in OTP (it is usually disabled) */
92 if (__raw_readl(REG_BCM6328_OTP) & BCM6328_TP1_DISABLED)
93 bmips_smp_enabled = 0;
94 else
95 bcm63xx_fixup_cpu1();
96}
97
98static void bcm6368_quirks(void)
99{
100 bcm63xx_fixup_cpu1();
101}
102
103static const struct bmips_quirk bmips_quirk_list[] = {
104 { "brcm,bcm3384-viper", &bcm3384_viper_quirks },
105 { "brcm,bcm33843-viper", &bcm3384_viper_quirks },
106 { "brcm,bcm6328", &bcm6328_quirks },
107 { "brcm,bcm6368", &bcm6368_quirks },
108 { "brcm,bcm63168", &bcm6368_quirks },
109 { },
110};
111
112void __init prom_init(void)
113{
114 register_bmips_smp_ops();
115}
116
117void __init prom_free_prom_memory(void)
118{
119}
120
121const char *get_system_type(void)
122{
123 return "Generic BMIPS kernel";
124}
125
126void __init plat_time_init(void)
127{
128 struct device_node *np;
129 u32 freq;
130
131 np = of_find_node_by_name(NULL, "cpus");
132 if (!np)
133 panic("missing 'cpus' DT node");
134 if (of_property_read_u32(np, "mips-hpt-frequency", &freq) < 0)
135 panic("missing 'mips-hpt-frequency' property");
136 of_node_put(np);
137
138 mips_hpt_frequency = freq;
139}
140
141void __init plat_mem_setup(void)
142{
143 void *dtb;
144 const struct bmips_quirk *q;
145
146 set_io_port_base(0);
147 ioport_resource.start = 0;
148 ioport_resource.end = ~0;
149
150 /* intended to somewhat resemble ARM; see Documentation/arm/Booting */
151 if (fw_arg0 == 0 && fw_arg1 == 0xffffffff)
152 dtb = phys_to_virt(fw_arg2);
153 else if (fw_arg0 == -2) /* UHI interface */
154 dtb = (void *)fw_arg1;
155 else if (__dtb_start != __dtb_end)
156 dtb = (void *)__dtb_start;
157 else
158 panic("no dtb found");
159
160 __dt_setup_arch(dtb);
161
162 for (q = bmips_quirk_list; q->quirk_fn; q++) {
163 if (of_flat_dt_is_compatible(of_get_flat_dt_root(),
164 q->compatible)) {
165 q->quirk_fn();
166 }
167 }
168}
169
170void __init device_tree_init(void)
171{
172 struct device_node *np;
173
174 unflatten_and_copy_device_tree();
175
176 /* Disable SMP boot unless both CPUs are listed in DT and !disabled */
177 np = of_find_node_by_name(NULL, "cpus");
178 if (np && of_get_available_child_count(np) <= 1)
179 bmips_smp_enabled = 0;
180 of_node_put(np);
181}
182
183int __init plat_of_setup(void)
184{
185 return __dt_register_buses("simple-bus", NULL);
186}
187
188arch_initcall(plat_of_setup);
189
190static int __init plat_dev_init(void)
191{
192 of_clk_init(NULL);
193 return 0;
194}
195
196device_initcall(plat_dev_init);
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 * Copyright (C) 2014 Kevin Cernekee <cernekee@gmail.com>
8 */
9
10#include <linux/init.h>
11#include <linux/bitops.h>
12#include <linux/memblock.h>
13#include <linux/ioport.h>
14#include <linux/kernel.h>
15#include <linux/io.h>
16#include <linux/of.h>
17#include <linux/of_clk.h>
18#include <linux/of_fdt.h>
19#include <linux/of_platform.h>
20#include <linux/libfdt.h>
21#include <linux/smp.h>
22#include <asm/addrspace.h>
23#include <asm/bmips.h>
24#include <asm/bootinfo.h>
25#include <asm/cpu-type.h>
26#include <asm/mipsregs.h>
27#include <asm/prom.h>
28#include <asm/smp-ops.h>
29#include <asm/time.h>
30#include <asm/traps.h>
31#include <asm/fw/cfe/cfe_api.h>
32
33#define RELO_NORMAL_VEC BIT(18)
34
35#define REG_BCM6328_OTP ((void __iomem *)CKSEG1ADDR(0x1000062c))
36#define BCM6328_TP1_DISABLED BIT(9)
37
38static const unsigned long kbase = VMLINUX_LOAD_ADDRESS & 0xfff00000;
39
40struct bmips_quirk {
41 const char *compatible;
42 void (*quirk_fn)(void);
43};
44
45static void kbase_setup(void)
46{
47 __raw_writel(kbase | RELO_NORMAL_VEC,
48 BMIPS_GET_CBR() + BMIPS_RELO_VECTOR_CONTROL_1);
49 ebase = kbase;
50}
51
52static void bcm3384_viper_quirks(void)
53{
54 /*
55 * Some experimental CM boxes are set up to let CM own the Viper TP0
56 * and let Linux own TP1. This requires moving the kernel
57 * load address to a non-conflicting region (e.g. via
58 * CONFIG_PHYSICAL_START) and supplying an alternate DTB.
59 * If we detect this condition, we need to move the MIPS exception
60 * vectors up to an area that we own.
61 *
62 * This is distinct from the OTHER special case mentioned in
63 * smp-bmips.c (boot on TP1, but enable SMP, then TP0 becomes our
64 * logical CPU#1). For the Viper TP1 case, SMP is off limits.
65 *
66 * Also note that many BMIPS435x CPUs do not have a
67 * BMIPS_RELO_VECTOR_CONTROL_1 register, so it isn't safe to just
68 * write VMLINUX_LOAD_ADDRESS into that register on every SoC.
69 */
70 board_ebase_setup = &kbase_setup;
71 bmips_smp_enabled = 0;
72}
73
74static void bcm63xx_fixup_cpu1(void)
75{
76 /*
77 * The bootloader has set up the CPU1 reset vector at
78 * 0xa000_0200.
79 * This conflicts with the special interrupt vector (IV).
80 * The bootloader has also set up CPU1 to respond to the wrong
81 * IPI interrupt.
82 * Here we will start up CPU1 in the background and ask it to
83 * reconfigure itself then go back to sleep.
84 */
85 memcpy((void *)0xa0000200, &bmips_smp_movevec, 0x20);
86 __sync();
87 set_c0_cause(C_SW0);
88 cpumask_set_cpu(1, &bmips_booted_mask);
89}
90
91static void bcm6328_quirks(void)
92{
93 /* Check CPU1 status in OTP (it is usually disabled) */
94 if (__raw_readl(REG_BCM6328_OTP) & BCM6328_TP1_DISABLED)
95 bmips_smp_enabled = 0;
96 else
97 bcm63xx_fixup_cpu1();
98}
99
100static void bcm6358_quirks(void)
101{
102 /*
103 * BCM3368/BCM6358 need special handling for their shared TLB, so
104 * disable SMP for now
105 */
106 bmips_smp_enabled = 0;
107}
108
109static void bcm6368_quirks(void)
110{
111 bcm63xx_fixup_cpu1();
112}
113
114static const struct bmips_quirk bmips_quirk_list[] = {
115 { "brcm,bcm3368", &bcm6358_quirks },
116 { "brcm,bcm3384-viper", &bcm3384_viper_quirks },
117 { "brcm,bcm33843-viper", &bcm3384_viper_quirks },
118 { "brcm,bcm6328", &bcm6328_quirks },
119 { "brcm,bcm6358", &bcm6358_quirks },
120 { "brcm,bcm6362", &bcm6368_quirks },
121 { "brcm,bcm6368", &bcm6368_quirks },
122 { "brcm,bcm63168", &bcm6368_quirks },
123 { "brcm,bcm63268", &bcm6368_quirks },
124 { },
125};
126
127static void __init bmips_init_cfe(void)
128{
129 cfe_seal = fw_arg3;
130
131 if (cfe_seal != CFE_EPTSEAL)
132 return;
133
134 cfe_init(fw_arg0, fw_arg2);
135}
136
137void __init prom_init(void)
138{
139 bmips_init_cfe();
140 bmips_cpu_setup();
141 register_bmips_smp_ops();
142}
143
144const char *get_system_type(void)
145{
146 return "Generic BMIPS kernel";
147}
148
149void __init plat_time_init(void)
150{
151 struct device_node *np;
152 u32 freq;
153
154 np = of_find_node_by_name(NULL, "cpus");
155 if (!np)
156 panic("missing 'cpus' DT node");
157 if (of_property_read_u32(np, "mips-hpt-frequency", &freq) < 0)
158 panic("missing 'mips-hpt-frequency' property");
159 of_node_put(np);
160
161 mips_hpt_frequency = freq;
162}
163
164void __init plat_mem_setup(void)
165{
166 void *dtb;
167 const struct bmips_quirk *q;
168
169 set_io_port_base(0);
170 ioport_resource.start = 0;
171 ioport_resource.end = ~0;
172
173 /* intended to somewhat resemble ARM; see Documentation/arm/booting.rst */
174 if (fw_arg0 == 0 && fw_arg1 == 0xffffffff)
175 dtb = phys_to_virt(fw_arg2);
176 else
177 dtb = get_fdt();
178
179 if (!dtb)
180 cfe_die("no dtb found");
181
182 __dt_setup_arch(dtb);
183
184 for (q = bmips_quirk_list; q->quirk_fn; q++) {
185 if (of_flat_dt_is_compatible(of_get_flat_dt_root(),
186 q->compatible)) {
187 q->quirk_fn();
188 }
189 }
190}
191
192void __init device_tree_init(void)
193{
194 struct device_node *np;
195
196 unflatten_and_copy_device_tree();
197
198 /* Disable SMP boot unless both CPUs are listed in DT and !disabled */
199 np = of_find_node_by_name(NULL, "cpus");
200 if (np && of_get_available_child_count(np) <= 1)
201 bmips_smp_enabled = 0;
202 of_node_put(np);
203}
204
205static int __init plat_dev_init(void)
206{
207 of_clk_init(NULL);
208 return 0;
209}
210
211arch_initcall(plat_dev_init);