1#ifndef __ARCH_ARM_FAULT_H
 2#define __ARCH_ARM_FAULT_H
 3
 4/*
 5 * Fault status register encodings.  We steal bit 31 for our own purposes.
 6 */
 7#define FSR_LNX_PF		(1 << 31)
 
 8#define FSR_WRITE		(1 << 11)
 9#define FSR_FS4			(1 << 10)
10#define FSR_FS3_0		(15)
11#define FSR_FS5_0		(0x3f)
12
13#ifdef CONFIG_ARM_LPAE
 
 
 
 
 
14static inline int fsr_fs(unsigned int fsr)
15{
16	return fsr & FSR_FS5_0;
17}
18#else
 
 
 
 
 
 
19static inline int fsr_fs(unsigned int fsr)
20{
21	return (fsr & FSR_FS3_0) | (fsr & FSR_FS4) >> 6;
22}
23#endif
24
25void do_bad_area(unsigned long addr, unsigned int fsr, struct pt_regs *regs);
26unsigned long search_exception_table(unsigned long addr);
27void early_abt_enable(void);
28
29#endif	/* __ARCH_ARM_FAULT_H */

 1/* SPDX-License-Identifier: GPL-2.0 */
 2#ifndef __ARCH_ARM_FAULT_H
 3#define __ARCH_ARM_FAULT_H
 4
 5/*
 6 * Fault status register encodings.  We steal bit 31 for our own purposes.
 7 */
 8#define FSR_LNX_PF		(1 << 31)
 9#define FSR_CM			(1 << 13)
10#define FSR_WRITE		(1 << 11)
11#define FSR_FS4			(1 << 10)
12#define FSR_FS3_0		(15)
13#define FSR_FS5_0		(0x3f)
14
15#ifdef CONFIG_ARM_LPAE
16#define FSR_FS_AEA		17
17#define FS_TRANS_NOLL		0x4
18#define FS_PERM_NOLL		0xC
19#define FS_MMU_NOLL_MASK	0x3C
20
21static inline int fsr_fs(unsigned int fsr)
22{
23	return fsr & FSR_FS5_0;
24}
25#else
26#define FSR_FS_AEA		22
27#define FS_L1_TRANS		0x5
28#define FS_L2_TRANS		0x7
29#define FS_L1_PERM		0xD
30#define FS_L2_PERM		0xF
31
32static inline int fsr_fs(unsigned int fsr)
33{
34	return (fsr & FSR_FS3_0) | (fsr & FSR_FS4) >> 6;
35}
36#endif
37
38void do_bad_area(unsigned long addr, unsigned int fsr, struct pt_regs *regs);
 
39void early_abt_enable(void);
40
41#endif	/* __ARCH_ARM_FAULT_H */