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1/**
2 * core.c - DesignWare USB3 DRD Controller Core file
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#include <linux/version.h>
23#include <linux/module.h>
24#include <linux/kernel.h>
25#include <linux/slab.h>
26#include <linux/spinlock.h>
27#include <linux/platform_device.h>
28#include <linux/pm_runtime.h>
29#include <linux/interrupt.h>
30#include <linux/ioport.h>
31#include <linux/io.h>
32#include <linux/list.h>
33#include <linux/delay.h>
34#include <linux/dma-mapping.h>
35#include <linux/of.h>
36#include <linux/acpi.h>
37#include <linux/pinctrl/consumer.h>
38
39#include <linux/usb/ch9.h>
40#include <linux/usb/gadget.h>
41#include <linux/usb/of.h>
42#include <linux/usb/otg.h>
43
44#include "platform_data.h"
45#include "core.h"
46#include "gadget.h"
47#include "io.h"
48
49#include "debug.h"
50
51/* -------------------------------------------------------------------------- */
52
53void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
54{
55 u32 reg;
56
57 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
58 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
59 reg |= DWC3_GCTL_PRTCAPDIR(mode);
60 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
61}
62
63/**
64 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
65 * @dwc: pointer to our context structure
66 */
67static int dwc3_core_soft_reset(struct dwc3 *dwc)
68{
69 u32 reg;
70 int retries = 1000;
71 int ret;
72
73 usb_phy_init(dwc->usb2_phy);
74 usb_phy_init(dwc->usb3_phy);
75 ret = phy_init(dwc->usb2_generic_phy);
76 if (ret < 0)
77 return ret;
78
79 ret = phy_init(dwc->usb3_generic_phy);
80 if (ret < 0) {
81 phy_exit(dwc->usb2_generic_phy);
82 return ret;
83 }
84
85 /*
86 * We're resetting only the device side because, if we're in host mode,
87 * XHCI driver will reset the host block. If dwc3 was configured for
88 * host-only mode, then we can return early.
89 */
90 if (dwc->dr_mode == USB_DR_MODE_HOST)
91 return 0;
92
93 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
94 reg |= DWC3_DCTL_CSFTRST;
95 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
96
97 do {
98 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
99 if (!(reg & DWC3_DCTL_CSFTRST))
100 return 0;
101
102 udelay(1);
103 } while (--retries);
104
105 return -ETIMEDOUT;
106}
107
108/**
109 * dwc3_soft_reset - Issue soft reset
110 * @dwc: Pointer to our controller context structure
111 */
112static int dwc3_soft_reset(struct dwc3 *dwc)
113{
114 unsigned long timeout;
115 u32 reg;
116
117 timeout = jiffies + msecs_to_jiffies(500);
118 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
119 do {
120 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
121 if (!(reg & DWC3_DCTL_CSFTRST))
122 break;
123
124 if (time_after(jiffies, timeout)) {
125 dev_err(dwc->dev, "Reset Timed Out\n");
126 return -ETIMEDOUT;
127 }
128
129 cpu_relax();
130 } while (true);
131
132 return 0;
133}
134
135/*
136 * dwc3_frame_length_adjustment - Adjusts frame length if required
137 * @dwc3: Pointer to our controller context structure
138 * @fladj: Value of GFLADJ_30MHZ to adjust frame length
139 */
140static void dwc3_frame_length_adjustment(struct dwc3 *dwc, u32 fladj)
141{
142 u32 reg;
143 u32 dft;
144
145 if (dwc->revision < DWC3_REVISION_250A)
146 return;
147
148 if (fladj == 0)
149 return;
150
151 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
152 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
153 if (!dev_WARN_ONCE(dwc->dev, dft == fladj,
154 "request value same as default, ignoring\n")) {
155 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
156 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | fladj;
157 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
158 }
159}
160
161/**
162 * dwc3_free_one_event_buffer - Frees one event buffer
163 * @dwc: Pointer to our controller context structure
164 * @evt: Pointer to event buffer to be freed
165 */
166static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
167 struct dwc3_event_buffer *evt)
168{
169 dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
170}
171
172/**
173 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
174 * @dwc: Pointer to our controller context structure
175 * @length: size of the event buffer
176 *
177 * Returns a pointer to the allocated event buffer structure on success
178 * otherwise ERR_PTR(errno).
179 */
180static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
181 unsigned length)
182{
183 struct dwc3_event_buffer *evt;
184
185 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
186 if (!evt)
187 return ERR_PTR(-ENOMEM);
188
189 evt->dwc = dwc;
190 evt->length = length;
191 evt->buf = dma_alloc_coherent(dwc->dev, length,
192 &evt->dma, GFP_KERNEL);
193 if (!evt->buf)
194 return ERR_PTR(-ENOMEM);
195
196 return evt;
197}
198
199/**
200 * dwc3_free_event_buffers - frees all allocated event buffers
201 * @dwc: Pointer to our controller context structure
202 */
203static void dwc3_free_event_buffers(struct dwc3 *dwc)
204{
205 struct dwc3_event_buffer *evt;
206 int i;
207
208 for (i = 0; i < dwc->num_event_buffers; i++) {
209 evt = dwc->ev_buffs[i];
210 if (evt)
211 dwc3_free_one_event_buffer(dwc, evt);
212 }
213}
214
215/**
216 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
217 * @dwc: pointer to our controller context structure
218 * @length: size of event buffer
219 *
220 * Returns 0 on success otherwise negative errno. In the error case, dwc
221 * may contain some buffers allocated but not all which were requested.
222 */
223static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
224{
225 int num;
226 int i;
227
228 num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
229 dwc->num_event_buffers = num;
230
231 dwc->ev_buffs = devm_kzalloc(dwc->dev, sizeof(*dwc->ev_buffs) * num,
232 GFP_KERNEL);
233 if (!dwc->ev_buffs)
234 return -ENOMEM;
235
236 for (i = 0; i < num; i++) {
237 struct dwc3_event_buffer *evt;
238
239 evt = dwc3_alloc_one_event_buffer(dwc, length);
240 if (IS_ERR(evt)) {
241 dev_err(dwc->dev, "can't allocate event buffer\n");
242 return PTR_ERR(evt);
243 }
244 dwc->ev_buffs[i] = evt;
245 }
246
247 return 0;
248}
249
250/**
251 * dwc3_event_buffers_setup - setup our allocated event buffers
252 * @dwc: pointer to our controller context structure
253 *
254 * Returns 0 on success otherwise negative errno.
255 */
256static int dwc3_event_buffers_setup(struct dwc3 *dwc)
257{
258 struct dwc3_event_buffer *evt;
259 int n;
260
261 for (n = 0; n < dwc->num_event_buffers; n++) {
262 evt = dwc->ev_buffs[n];
263 dwc3_trace(trace_dwc3_core,
264 "Event buf %p dma %08llx length %d\n",
265 evt->buf, (unsigned long long) evt->dma,
266 evt->length);
267
268 evt->lpos = 0;
269
270 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
271 lower_32_bits(evt->dma));
272 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
273 upper_32_bits(evt->dma));
274 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
275 DWC3_GEVNTSIZ_SIZE(evt->length));
276 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
277 }
278
279 return 0;
280}
281
282static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
283{
284 struct dwc3_event_buffer *evt;
285 int n;
286
287 for (n = 0; n < dwc->num_event_buffers; n++) {
288 evt = dwc->ev_buffs[n];
289
290 evt->lpos = 0;
291
292 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
293 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
294 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK
295 | DWC3_GEVNTSIZ_SIZE(0));
296 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
297 }
298}
299
300static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
301{
302 if (!dwc->has_hibernation)
303 return 0;
304
305 if (!dwc->nr_scratch)
306 return 0;
307
308 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
309 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
310 if (!dwc->scratchbuf)
311 return -ENOMEM;
312
313 return 0;
314}
315
316static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
317{
318 dma_addr_t scratch_addr;
319 u32 param;
320 int ret;
321
322 if (!dwc->has_hibernation)
323 return 0;
324
325 if (!dwc->nr_scratch)
326 return 0;
327
328 /* should never fall here */
329 if (!WARN_ON(dwc->scratchbuf))
330 return 0;
331
332 scratch_addr = dma_map_single(dwc->dev, dwc->scratchbuf,
333 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
334 DMA_BIDIRECTIONAL);
335 if (dma_mapping_error(dwc->dev, scratch_addr)) {
336 dev_err(dwc->dev, "failed to map scratch buffer\n");
337 ret = -EFAULT;
338 goto err0;
339 }
340
341 dwc->scratch_addr = scratch_addr;
342
343 param = lower_32_bits(scratch_addr);
344
345 ret = dwc3_send_gadget_generic_command(dwc,
346 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
347 if (ret < 0)
348 goto err1;
349
350 param = upper_32_bits(scratch_addr);
351
352 ret = dwc3_send_gadget_generic_command(dwc,
353 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
354 if (ret < 0)
355 goto err1;
356
357 return 0;
358
359err1:
360 dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
361 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
362
363err0:
364 return ret;
365}
366
367static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
368{
369 if (!dwc->has_hibernation)
370 return;
371
372 if (!dwc->nr_scratch)
373 return;
374
375 /* should never fall here */
376 if (!WARN_ON(dwc->scratchbuf))
377 return;
378
379 dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
380 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
381 kfree(dwc->scratchbuf);
382}
383
384static void dwc3_core_num_eps(struct dwc3 *dwc)
385{
386 struct dwc3_hwparams *parms = &dwc->hwparams;
387
388 dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
389 dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
390
391 dwc3_trace(trace_dwc3_core, "found %d IN and %d OUT endpoints",
392 dwc->num_in_eps, dwc->num_out_eps);
393}
394
395static void dwc3_cache_hwparams(struct dwc3 *dwc)
396{
397 struct dwc3_hwparams *parms = &dwc->hwparams;
398
399 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
400 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
401 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
402 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
403 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
404 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
405 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
406 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
407 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
408}
409
410/**
411 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
412 * @dwc: Pointer to our controller context structure
413 *
414 * Returns 0 on success. The USB PHY interfaces are configured but not
415 * initialized. The PHY interfaces and the PHYs get initialized together with
416 * the core in dwc3_core_init.
417 */
418static int dwc3_phy_setup(struct dwc3 *dwc)
419{
420 u32 reg;
421 int ret;
422
423 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
424
425 /*
426 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
427 * to '0' during coreConsultant configuration. So default value
428 * will be '0' when the core is reset. Application needs to set it
429 * to '1' after the core initialization is completed.
430 */
431 if (dwc->revision > DWC3_REVISION_194A)
432 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
433
434 if (dwc->u2ss_inp3_quirk)
435 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
436
437 if (dwc->req_p1p2p3_quirk)
438 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
439
440 if (dwc->del_p1p2p3_quirk)
441 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
442
443 if (dwc->del_phy_power_chg_quirk)
444 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
445
446 if (dwc->lfps_filter_quirk)
447 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
448
449 if (dwc->rx_detect_poll_quirk)
450 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
451
452 if (dwc->tx_de_emphasis_quirk)
453 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
454
455 if (dwc->dis_u3_susphy_quirk)
456 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
457
458 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
459
460 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
461
462 /* Select the HS PHY interface */
463 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
464 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
465 if (dwc->hsphy_interface &&
466 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
467 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
468 break;
469 } else if (dwc->hsphy_interface &&
470 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
471 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
472 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
473 } else {
474 /* Relying on default value. */
475 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
476 break;
477 }
478 /* FALLTHROUGH */
479 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
480 /* Making sure the interface and PHY are operational */
481 ret = dwc3_soft_reset(dwc);
482 if (ret)
483 return ret;
484
485 udelay(1);
486
487 ret = dwc3_ulpi_init(dwc);
488 if (ret)
489 return ret;
490 /* FALLTHROUGH */
491 default:
492 break;
493 }
494
495 /*
496 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
497 * '0' during coreConsultant configuration. So default value will
498 * be '0' when the core is reset. Application needs to set it to
499 * '1' after the core initialization is completed.
500 */
501 if (dwc->revision > DWC3_REVISION_194A)
502 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
503
504 if (dwc->dis_u2_susphy_quirk)
505 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
506
507 if (dwc->dis_enblslpm_quirk)
508 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
509
510 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
511
512 return 0;
513}
514
515/**
516 * dwc3_core_init - Low-level initialization of DWC3 Core
517 * @dwc: Pointer to our controller context structure
518 *
519 * Returns 0 on success otherwise negative errno.
520 */
521static int dwc3_core_init(struct dwc3 *dwc)
522{
523 u32 hwparams4 = dwc->hwparams.hwparams4;
524 u32 reg;
525 int ret;
526
527 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
528 /* This should read as U3 followed by revision number */
529 if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) {
530 /* Detected DWC_usb3 IP */
531 dwc->revision = reg;
532 } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) {
533 /* Detected DWC_usb31 IP */
534 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
535 dwc->revision |= DWC3_REVISION_IS_DWC31;
536 } else {
537 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
538 ret = -ENODEV;
539 goto err0;
540 }
541
542 /*
543 * Write Linux Version Code to our GUID register so it's easy to figure
544 * out which kernel version a bug was found.
545 */
546 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
547
548 /* Handle USB2.0-only core configuration */
549 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
550 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
551 if (dwc->maximum_speed == USB_SPEED_SUPER)
552 dwc->maximum_speed = USB_SPEED_HIGH;
553 }
554
555 /* issue device SoftReset too */
556 ret = dwc3_soft_reset(dwc);
557 if (ret)
558 goto err0;
559
560 ret = dwc3_core_soft_reset(dwc);
561 if (ret)
562 goto err0;
563
564 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
565 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
566
567 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
568 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
569 /**
570 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
571 * issue which would cause xHCI compliance tests to fail.
572 *
573 * Because of that we cannot enable clock gating on such
574 * configurations.
575 *
576 * Refers to:
577 *
578 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
579 * SOF/ITP Mode Used
580 */
581 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
582 dwc->dr_mode == USB_DR_MODE_OTG) &&
583 (dwc->revision >= DWC3_REVISION_210A &&
584 dwc->revision <= DWC3_REVISION_250A))
585 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
586 else
587 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
588 break;
589 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
590 /* enable hibernation here */
591 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
592
593 /*
594 * REVISIT Enabling this bit so that host-mode hibernation
595 * will work. Device-mode hibernation is not yet implemented.
596 */
597 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
598 break;
599 default:
600 dwc3_trace(trace_dwc3_core, "No power optimization available\n");
601 }
602
603 /* check if current dwc3 is on simulation board */
604 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
605 dwc3_trace(trace_dwc3_core,
606 "running on FPGA platform\n");
607 dwc->is_fpga = true;
608 }
609
610 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
611 "disable_scramble cannot be used on non-FPGA builds\n");
612
613 if (dwc->disable_scramble_quirk && dwc->is_fpga)
614 reg |= DWC3_GCTL_DISSCRAMBLE;
615 else
616 reg &= ~DWC3_GCTL_DISSCRAMBLE;
617
618 if (dwc->u2exit_lfps_quirk)
619 reg |= DWC3_GCTL_U2EXIT_LFPS;
620
621 /*
622 * WORKAROUND: DWC3 revisions <1.90a have a bug
623 * where the device can fail to connect at SuperSpeed
624 * and falls back to high-speed mode which causes
625 * the device to enter a Connect/Disconnect loop
626 */
627 if (dwc->revision < DWC3_REVISION_190A)
628 reg |= DWC3_GCTL_U2RSTECN;
629
630 dwc3_core_num_eps(dwc);
631
632 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
633
634 ret = dwc3_alloc_scratch_buffers(dwc);
635 if (ret)
636 goto err1;
637
638 ret = dwc3_setup_scratch_buffers(dwc);
639 if (ret)
640 goto err2;
641
642 return 0;
643
644err2:
645 dwc3_free_scratch_buffers(dwc);
646
647err1:
648 usb_phy_shutdown(dwc->usb2_phy);
649 usb_phy_shutdown(dwc->usb3_phy);
650 phy_exit(dwc->usb2_generic_phy);
651 phy_exit(dwc->usb3_generic_phy);
652
653err0:
654 return ret;
655}
656
657static void dwc3_core_exit(struct dwc3 *dwc)
658{
659 dwc3_free_scratch_buffers(dwc);
660 usb_phy_shutdown(dwc->usb2_phy);
661 usb_phy_shutdown(dwc->usb3_phy);
662 phy_exit(dwc->usb2_generic_phy);
663 phy_exit(dwc->usb3_generic_phy);
664}
665
666static int dwc3_core_get_phy(struct dwc3 *dwc)
667{
668 struct device *dev = dwc->dev;
669 struct device_node *node = dev->of_node;
670 int ret;
671
672 if (node) {
673 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
674 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
675 } else {
676 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
677 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
678 }
679
680 if (IS_ERR(dwc->usb2_phy)) {
681 ret = PTR_ERR(dwc->usb2_phy);
682 if (ret == -ENXIO || ret == -ENODEV) {
683 dwc->usb2_phy = NULL;
684 } else if (ret == -EPROBE_DEFER) {
685 return ret;
686 } else {
687 dev_err(dev, "no usb2 phy configured\n");
688 return ret;
689 }
690 }
691
692 if (IS_ERR(dwc->usb3_phy)) {
693 ret = PTR_ERR(dwc->usb3_phy);
694 if (ret == -ENXIO || ret == -ENODEV) {
695 dwc->usb3_phy = NULL;
696 } else if (ret == -EPROBE_DEFER) {
697 return ret;
698 } else {
699 dev_err(dev, "no usb3 phy configured\n");
700 return ret;
701 }
702 }
703
704 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
705 if (IS_ERR(dwc->usb2_generic_phy)) {
706 ret = PTR_ERR(dwc->usb2_generic_phy);
707 if (ret == -ENOSYS || ret == -ENODEV) {
708 dwc->usb2_generic_phy = NULL;
709 } else if (ret == -EPROBE_DEFER) {
710 return ret;
711 } else {
712 dev_err(dev, "no usb2 phy configured\n");
713 return ret;
714 }
715 }
716
717 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
718 if (IS_ERR(dwc->usb3_generic_phy)) {
719 ret = PTR_ERR(dwc->usb3_generic_phy);
720 if (ret == -ENOSYS || ret == -ENODEV) {
721 dwc->usb3_generic_phy = NULL;
722 } else if (ret == -EPROBE_DEFER) {
723 return ret;
724 } else {
725 dev_err(dev, "no usb3 phy configured\n");
726 return ret;
727 }
728 }
729
730 return 0;
731}
732
733static int dwc3_core_init_mode(struct dwc3 *dwc)
734{
735 struct device *dev = dwc->dev;
736 int ret;
737
738 switch (dwc->dr_mode) {
739 case USB_DR_MODE_PERIPHERAL:
740 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
741 ret = dwc3_gadget_init(dwc);
742 if (ret) {
743 dev_err(dev, "failed to initialize gadget\n");
744 return ret;
745 }
746 break;
747 case USB_DR_MODE_HOST:
748 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
749 ret = dwc3_host_init(dwc);
750 if (ret) {
751 dev_err(dev, "failed to initialize host\n");
752 return ret;
753 }
754 break;
755 case USB_DR_MODE_OTG:
756 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
757 ret = dwc3_host_init(dwc);
758 if (ret) {
759 dev_err(dev, "failed to initialize host\n");
760 return ret;
761 }
762
763 ret = dwc3_gadget_init(dwc);
764 if (ret) {
765 dev_err(dev, "failed to initialize gadget\n");
766 return ret;
767 }
768 break;
769 default:
770 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
771 return -EINVAL;
772 }
773
774 return 0;
775}
776
777static void dwc3_core_exit_mode(struct dwc3 *dwc)
778{
779 switch (dwc->dr_mode) {
780 case USB_DR_MODE_PERIPHERAL:
781 dwc3_gadget_exit(dwc);
782 break;
783 case USB_DR_MODE_HOST:
784 dwc3_host_exit(dwc);
785 break;
786 case USB_DR_MODE_OTG:
787 dwc3_host_exit(dwc);
788 dwc3_gadget_exit(dwc);
789 break;
790 default:
791 /* do nothing */
792 break;
793 }
794}
795
796#define DWC3_ALIGN_MASK (16 - 1)
797
798static int dwc3_probe(struct platform_device *pdev)
799{
800 struct device *dev = &pdev->dev;
801 struct dwc3_platform_data *pdata = dev_get_platdata(dev);
802 struct resource *res;
803 struct dwc3 *dwc;
804 u8 lpm_nyet_threshold;
805 u8 tx_de_emphasis;
806 u8 hird_threshold;
807 u32 fladj = 0;
808
809 int ret;
810
811 void __iomem *regs;
812 void *mem;
813
814 mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
815 if (!mem)
816 return -ENOMEM;
817
818 dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
819 dwc->mem = mem;
820 dwc->dev = dev;
821
822 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
823 if (!res) {
824 dev_err(dev, "missing IRQ\n");
825 return -ENODEV;
826 }
827 dwc->xhci_resources[1].start = res->start;
828 dwc->xhci_resources[1].end = res->end;
829 dwc->xhci_resources[1].flags = res->flags;
830 dwc->xhci_resources[1].name = res->name;
831
832 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
833 if (!res) {
834 dev_err(dev, "missing memory resource\n");
835 return -ENODEV;
836 }
837
838 dwc->xhci_resources[0].start = res->start;
839 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
840 DWC3_XHCI_REGS_END;
841 dwc->xhci_resources[0].flags = res->flags;
842 dwc->xhci_resources[0].name = res->name;
843
844 res->start += DWC3_GLOBALS_REGS_START;
845
846 /*
847 * Request memory region but exclude xHCI regs,
848 * since it will be requested by the xhci-plat driver.
849 */
850 regs = devm_ioremap_resource(dev, res);
851 if (IS_ERR(regs)) {
852 ret = PTR_ERR(regs);
853 goto err0;
854 }
855
856 dwc->regs = regs;
857 dwc->regs_size = resource_size(res);
858
859 /* default to highest possible threshold */
860 lpm_nyet_threshold = 0xff;
861
862 /* default to -3.5dB de-emphasis */
863 tx_de_emphasis = 1;
864
865 /*
866 * default to assert utmi_sleep_n and use maximum allowed HIRD
867 * threshold value of 0b1100
868 */
869 hird_threshold = 12;
870
871 dwc->maximum_speed = usb_get_maximum_speed(dev);
872 dwc->dr_mode = usb_get_dr_mode(dev);
873
874 dwc->has_lpm_erratum = device_property_read_bool(dev,
875 "snps,has-lpm-erratum");
876 device_property_read_u8(dev, "snps,lpm-nyet-threshold",
877 &lpm_nyet_threshold);
878 dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
879 "snps,is-utmi-l1-suspend");
880 device_property_read_u8(dev, "snps,hird-threshold",
881 &hird_threshold);
882 dwc->usb3_lpm_capable = device_property_read_bool(dev,
883 "snps,usb3_lpm_capable");
884
885 dwc->needs_fifo_resize = device_property_read_bool(dev,
886 "tx-fifo-resize");
887
888 dwc->disable_scramble_quirk = device_property_read_bool(dev,
889 "snps,disable_scramble_quirk");
890 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
891 "snps,u2exit_lfps_quirk");
892 dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
893 "snps,u2ss_inp3_quirk");
894 dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
895 "snps,req_p1p2p3_quirk");
896 dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
897 "snps,del_p1p2p3_quirk");
898 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
899 "snps,del_phy_power_chg_quirk");
900 dwc->lfps_filter_quirk = device_property_read_bool(dev,
901 "snps,lfps_filter_quirk");
902 dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
903 "snps,rx_detect_poll_quirk");
904 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
905 "snps,dis_u3_susphy_quirk");
906 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
907 "snps,dis_u2_susphy_quirk");
908 dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
909 "snps,dis_enblslpm_quirk");
910
911 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
912 "snps,tx_de_emphasis_quirk");
913 device_property_read_u8(dev, "snps,tx_de_emphasis",
914 &tx_de_emphasis);
915 device_property_read_string(dev, "snps,hsphy_interface",
916 &dwc->hsphy_interface);
917 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
918 &fladj);
919
920 if (pdata) {
921 dwc->maximum_speed = pdata->maximum_speed;
922 dwc->has_lpm_erratum = pdata->has_lpm_erratum;
923 if (pdata->lpm_nyet_threshold)
924 lpm_nyet_threshold = pdata->lpm_nyet_threshold;
925 dwc->is_utmi_l1_suspend = pdata->is_utmi_l1_suspend;
926 if (pdata->hird_threshold)
927 hird_threshold = pdata->hird_threshold;
928
929 dwc->needs_fifo_resize = pdata->tx_fifo_resize;
930 dwc->usb3_lpm_capable = pdata->usb3_lpm_capable;
931 dwc->dr_mode = pdata->dr_mode;
932
933 dwc->disable_scramble_quirk = pdata->disable_scramble_quirk;
934 dwc->u2exit_lfps_quirk = pdata->u2exit_lfps_quirk;
935 dwc->u2ss_inp3_quirk = pdata->u2ss_inp3_quirk;
936 dwc->req_p1p2p3_quirk = pdata->req_p1p2p3_quirk;
937 dwc->del_p1p2p3_quirk = pdata->del_p1p2p3_quirk;
938 dwc->del_phy_power_chg_quirk = pdata->del_phy_power_chg_quirk;
939 dwc->lfps_filter_quirk = pdata->lfps_filter_quirk;
940 dwc->rx_detect_poll_quirk = pdata->rx_detect_poll_quirk;
941 dwc->dis_u3_susphy_quirk = pdata->dis_u3_susphy_quirk;
942 dwc->dis_u2_susphy_quirk = pdata->dis_u2_susphy_quirk;
943 dwc->dis_enblslpm_quirk = pdata->dis_enblslpm_quirk;
944
945 dwc->tx_de_emphasis_quirk = pdata->tx_de_emphasis_quirk;
946 if (pdata->tx_de_emphasis)
947 tx_de_emphasis = pdata->tx_de_emphasis;
948
949 dwc->hsphy_interface = pdata->hsphy_interface;
950 fladj = pdata->fladj_value;
951 }
952
953 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
954 dwc->tx_de_emphasis = tx_de_emphasis;
955
956 dwc->hird_threshold = hird_threshold
957 | (dwc->is_utmi_l1_suspend << 4);
958
959 platform_set_drvdata(pdev, dwc);
960 dwc3_cache_hwparams(dwc);
961
962 ret = dwc3_phy_setup(dwc);
963 if (ret)
964 goto err0;
965
966 ret = dwc3_core_get_phy(dwc);
967 if (ret)
968 goto err0;
969
970 spin_lock_init(&dwc->lock);
971
972 if (!dev->dma_mask) {
973 dev->dma_mask = dev->parent->dma_mask;
974 dev->dma_parms = dev->parent->dma_parms;
975 dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask);
976 }
977
978 pm_runtime_enable(dev);
979 pm_runtime_get_sync(dev);
980 pm_runtime_forbid(dev);
981
982 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
983 if (ret) {
984 dev_err(dwc->dev, "failed to allocate event buffers\n");
985 ret = -ENOMEM;
986 goto err1;
987 }
988
989 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
990 dwc->dr_mode = USB_DR_MODE_HOST;
991 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
992 dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
993
994 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
995 dwc->dr_mode = USB_DR_MODE_OTG;
996
997 ret = dwc3_core_init(dwc);
998 if (ret) {
999 dev_err(dev, "failed to initialize core\n");
1000 goto err1;
1001 }
1002
1003 /* Check the maximum_speed parameter */
1004 switch (dwc->maximum_speed) {
1005 case USB_SPEED_LOW:
1006 case USB_SPEED_FULL:
1007 case USB_SPEED_HIGH:
1008 case USB_SPEED_SUPER:
1009 case USB_SPEED_SUPER_PLUS:
1010 break;
1011 default:
1012 dev_err(dev, "invalid maximum_speed parameter %d\n",
1013 dwc->maximum_speed);
1014 /* fall through */
1015 case USB_SPEED_UNKNOWN:
1016 /* default to superspeed */
1017 dwc->maximum_speed = USB_SPEED_SUPER;
1018
1019 /*
1020 * default to superspeed plus if we are capable.
1021 */
1022 if (dwc3_is_usb31(dwc) &&
1023 (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
1024 DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1025 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1026
1027 break;
1028 }
1029
1030 /* Adjust Frame Length */
1031 dwc3_frame_length_adjustment(dwc, fladj);
1032
1033 usb_phy_set_suspend(dwc->usb2_phy, 0);
1034 usb_phy_set_suspend(dwc->usb3_phy, 0);
1035 ret = phy_power_on(dwc->usb2_generic_phy);
1036 if (ret < 0)
1037 goto err2;
1038
1039 ret = phy_power_on(dwc->usb3_generic_phy);
1040 if (ret < 0)
1041 goto err3;
1042
1043 ret = dwc3_event_buffers_setup(dwc);
1044 if (ret) {
1045 dev_err(dwc->dev, "failed to setup event buffers\n");
1046 goto err4;
1047 }
1048
1049 ret = dwc3_core_init_mode(dwc);
1050 if (ret)
1051 goto err5;
1052
1053 ret = dwc3_debugfs_init(dwc);
1054 if (ret) {
1055 dev_err(dev, "failed to initialize debugfs\n");
1056 goto err6;
1057 }
1058
1059 pm_runtime_allow(dev);
1060
1061 return 0;
1062
1063err6:
1064 dwc3_core_exit_mode(dwc);
1065
1066err5:
1067 dwc3_event_buffers_cleanup(dwc);
1068
1069err4:
1070 phy_power_off(dwc->usb3_generic_phy);
1071
1072err3:
1073 phy_power_off(dwc->usb2_generic_phy);
1074
1075err2:
1076 usb_phy_set_suspend(dwc->usb2_phy, 1);
1077 usb_phy_set_suspend(dwc->usb3_phy, 1);
1078 dwc3_core_exit(dwc);
1079
1080err1:
1081 dwc3_free_event_buffers(dwc);
1082 dwc3_ulpi_exit(dwc);
1083
1084err0:
1085 /*
1086 * restore res->start back to its original value so that, in case the
1087 * probe is deferred, we don't end up getting error in request the
1088 * memory region the next time probe is called.
1089 */
1090 res->start -= DWC3_GLOBALS_REGS_START;
1091
1092 return ret;
1093}
1094
1095static int dwc3_remove(struct platform_device *pdev)
1096{
1097 struct dwc3 *dwc = platform_get_drvdata(pdev);
1098 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1099
1100 /*
1101 * restore res->start back to its original value so that, in case the
1102 * probe is deferred, we don't end up getting error in request the
1103 * memory region the next time probe is called.
1104 */
1105 res->start -= DWC3_GLOBALS_REGS_START;
1106
1107 dwc3_debugfs_exit(dwc);
1108 dwc3_core_exit_mode(dwc);
1109 dwc3_event_buffers_cleanup(dwc);
1110 dwc3_free_event_buffers(dwc);
1111
1112 usb_phy_set_suspend(dwc->usb2_phy, 1);
1113 usb_phy_set_suspend(dwc->usb3_phy, 1);
1114 phy_power_off(dwc->usb2_generic_phy);
1115 phy_power_off(dwc->usb3_generic_phy);
1116
1117 dwc3_core_exit(dwc);
1118 dwc3_ulpi_exit(dwc);
1119
1120 pm_runtime_put_sync(&pdev->dev);
1121 pm_runtime_disable(&pdev->dev);
1122
1123 return 0;
1124}
1125
1126#ifdef CONFIG_PM_SLEEP
1127static int dwc3_suspend(struct device *dev)
1128{
1129 struct dwc3 *dwc = dev_get_drvdata(dev);
1130 unsigned long flags;
1131
1132 spin_lock_irqsave(&dwc->lock, flags);
1133
1134 switch (dwc->dr_mode) {
1135 case USB_DR_MODE_PERIPHERAL:
1136 case USB_DR_MODE_OTG:
1137 dwc3_gadget_suspend(dwc);
1138 /* FALLTHROUGH */
1139 case USB_DR_MODE_HOST:
1140 default:
1141 dwc3_event_buffers_cleanup(dwc);
1142 break;
1143 }
1144
1145 dwc->gctl = dwc3_readl(dwc->regs, DWC3_GCTL);
1146 spin_unlock_irqrestore(&dwc->lock, flags);
1147
1148 usb_phy_shutdown(dwc->usb3_phy);
1149 usb_phy_shutdown(dwc->usb2_phy);
1150 phy_exit(dwc->usb2_generic_phy);
1151 phy_exit(dwc->usb3_generic_phy);
1152
1153 usb_phy_set_suspend(dwc->usb2_phy, 1);
1154 usb_phy_set_suspend(dwc->usb3_phy, 1);
1155 WARN_ON(phy_power_off(dwc->usb2_generic_phy) < 0);
1156 WARN_ON(phy_power_off(dwc->usb3_generic_phy) < 0);
1157
1158 pinctrl_pm_select_sleep_state(dev);
1159
1160 return 0;
1161}
1162
1163static int dwc3_resume(struct device *dev)
1164{
1165 struct dwc3 *dwc = dev_get_drvdata(dev);
1166 unsigned long flags;
1167 int ret;
1168
1169 pinctrl_pm_select_default_state(dev);
1170
1171 usb_phy_set_suspend(dwc->usb2_phy, 0);
1172 usb_phy_set_suspend(dwc->usb3_phy, 0);
1173 ret = phy_power_on(dwc->usb2_generic_phy);
1174 if (ret < 0)
1175 return ret;
1176
1177 ret = phy_power_on(dwc->usb3_generic_phy);
1178 if (ret < 0)
1179 goto err_usb2phy_power;
1180
1181 usb_phy_init(dwc->usb3_phy);
1182 usb_phy_init(dwc->usb2_phy);
1183 ret = phy_init(dwc->usb2_generic_phy);
1184 if (ret < 0)
1185 goto err_usb3phy_power;
1186
1187 ret = phy_init(dwc->usb3_generic_phy);
1188 if (ret < 0)
1189 goto err_usb2phy_init;
1190
1191 spin_lock_irqsave(&dwc->lock, flags);
1192
1193 dwc3_event_buffers_setup(dwc);
1194 dwc3_writel(dwc->regs, DWC3_GCTL, dwc->gctl);
1195
1196 switch (dwc->dr_mode) {
1197 case USB_DR_MODE_PERIPHERAL:
1198 case USB_DR_MODE_OTG:
1199 dwc3_gadget_resume(dwc);
1200 /* FALLTHROUGH */
1201 case USB_DR_MODE_HOST:
1202 default:
1203 /* do nothing */
1204 break;
1205 }
1206
1207 spin_unlock_irqrestore(&dwc->lock, flags);
1208
1209 pm_runtime_disable(dev);
1210 pm_runtime_set_active(dev);
1211 pm_runtime_enable(dev);
1212
1213 return 0;
1214
1215err_usb2phy_init:
1216 phy_exit(dwc->usb2_generic_phy);
1217
1218err_usb3phy_power:
1219 phy_power_off(dwc->usb3_generic_phy);
1220
1221err_usb2phy_power:
1222 phy_power_off(dwc->usb2_generic_phy);
1223
1224 return ret;
1225}
1226
1227static const struct dev_pm_ops dwc3_dev_pm_ops = {
1228 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1229};
1230
1231#define DWC3_PM_OPS &(dwc3_dev_pm_ops)
1232#else
1233#define DWC3_PM_OPS NULL
1234#endif
1235
1236#ifdef CONFIG_OF
1237static const struct of_device_id of_dwc3_match[] = {
1238 {
1239 .compatible = "snps,dwc3"
1240 },
1241 {
1242 .compatible = "synopsys,dwc3"
1243 },
1244 { },
1245};
1246MODULE_DEVICE_TABLE(of, of_dwc3_match);
1247#endif
1248
1249#ifdef CONFIG_ACPI
1250
1251#define ACPI_ID_INTEL_BSW "808622B7"
1252
1253static const struct acpi_device_id dwc3_acpi_match[] = {
1254 { ACPI_ID_INTEL_BSW, 0 },
1255 { },
1256};
1257MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1258#endif
1259
1260static struct platform_driver dwc3_driver = {
1261 .probe = dwc3_probe,
1262 .remove = dwc3_remove,
1263 .driver = {
1264 .name = "dwc3",
1265 .of_match_table = of_match_ptr(of_dwc3_match),
1266 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
1267 .pm = DWC3_PM_OPS,
1268 },
1269};
1270
1271module_platform_driver(dwc3_driver);
1272
1273MODULE_ALIAS("platform:dwc3");
1274MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1275MODULE_LICENSE("GPL v2");
1276MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * core.c - DesignWare USB3 DRD Controller Core file
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11#include <linux/clk.h>
12#include <linux/version.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/slab.h>
16#include <linux/spinlock.h>
17#include <linux/platform_device.h>
18#include <linux/pm_runtime.h>
19#include <linux/interrupt.h>
20#include <linux/ioport.h>
21#include <linux/io.h>
22#include <linux/list.h>
23#include <linux/delay.h>
24#include <linux/dma-mapping.h>
25#include <linux/of.h>
26#include <linux/of_graph.h>
27#include <linux/acpi.h>
28#include <linux/pinctrl/consumer.h>
29#include <linux/reset.h>
30#include <linux/bitfield.h>
31
32#include <linux/usb/ch9.h>
33#include <linux/usb/gadget.h>
34#include <linux/usb/of.h>
35#include <linux/usb/otg.h>
36
37#include "core.h"
38#include "gadget.h"
39#include "io.h"
40
41#include "debug.h"
42#include "../host/xhci-ext-caps.h"
43
44#define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
45
46/**
47 * dwc3_get_dr_mode - Validates and sets dr_mode
48 * @dwc: pointer to our context structure
49 */
50static int dwc3_get_dr_mode(struct dwc3 *dwc)
51{
52 enum usb_dr_mode mode;
53 struct device *dev = dwc->dev;
54 unsigned int hw_mode;
55
56 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
57 dwc->dr_mode = USB_DR_MODE_OTG;
58
59 mode = dwc->dr_mode;
60 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
61
62 switch (hw_mode) {
63 case DWC3_GHWPARAMS0_MODE_GADGET:
64 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
65 dev_err(dev,
66 "Controller does not support host mode.\n");
67 return -EINVAL;
68 }
69 mode = USB_DR_MODE_PERIPHERAL;
70 break;
71 case DWC3_GHWPARAMS0_MODE_HOST:
72 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
73 dev_err(dev,
74 "Controller does not support device mode.\n");
75 return -EINVAL;
76 }
77 mode = USB_DR_MODE_HOST;
78 break;
79 default:
80 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
81 mode = USB_DR_MODE_HOST;
82 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
83 mode = USB_DR_MODE_PERIPHERAL;
84
85 /*
86 * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG
87 * mode. If the controller supports DRD but the dr_mode is not
88 * specified or set to OTG, then set the mode to peripheral.
89 */
90 if (mode == USB_DR_MODE_OTG && !dwc->edev &&
91 (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) ||
92 !device_property_read_bool(dwc->dev, "usb-role-switch")) &&
93 !DWC3_VER_IS_PRIOR(DWC3, 330A))
94 mode = USB_DR_MODE_PERIPHERAL;
95 }
96
97 if (mode != dwc->dr_mode) {
98 dev_warn(dev,
99 "Configuration mismatch. dr_mode forced to %s\n",
100 mode == USB_DR_MODE_HOST ? "host" : "gadget");
101
102 dwc->dr_mode = mode;
103 }
104
105 return 0;
106}
107
108void dwc3_enable_susphy(struct dwc3 *dwc, bool enable)
109{
110 u32 reg;
111 int i;
112
113 for (i = 0; i < dwc->num_usb3_ports; i++) {
114 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(i));
115 if (enable && !dwc->dis_u3_susphy_quirk)
116 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
117 else
118 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
119
120 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(i), reg);
121 }
122
123 for (i = 0; i < dwc->num_usb2_ports; i++) {
124 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i));
125 if (enable && !dwc->dis_u2_susphy_quirk)
126 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
127 else
128 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
129
130 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg);
131 }
132}
133
134void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode, bool ignore_susphy)
135{
136 unsigned int hw_mode;
137 u32 reg;
138
139 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
140
141 /*
142 * For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE and
143 * GUSB2PHYCFG.SUSPHY should be cleared during mode switching,
144 * and they can be set after core initialization.
145 */
146 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
147 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD && !ignore_susphy) {
148 if (DWC3_GCTL_PRTCAP(reg) != mode)
149 dwc3_enable_susphy(dwc, false);
150 }
151
152 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
153 reg |= DWC3_GCTL_PRTCAPDIR(mode);
154 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
155
156 dwc->current_dr_role = mode;
157}
158
159static void __dwc3_set_mode(struct work_struct *work)
160{
161 struct dwc3 *dwc = work_to_dwc(work);
162 unsigned long flags;
163 int ret;
164 u32 reg;
165 u32 desired_dr_role;
166 int i;
167
168 mutex_lock(&dwc->mutex);
169 spin_lock_irqsave(&dwc->lock, flags);
170 desired_dr_role = dwc->desired_dr_role;
171 spin_unlock_irqrestore(&dwc->lock, flags);
172
173 pm_runtime_get_sync(dwc->dev);
174
175 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
176 dwc3_otg_update(dwc, 0);
177
178 if (!desired_dr_role)
179 goto out;
180
181 if (desired_dr_role == dwc->current_dr_role)
182 goto out;
183
184 if (desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
185 goto out;
186
187 switch (dwc->current_dr_role) {
188 case DWC3_GCTL_PRTCAP_HOST:
189 dwc3_host_exit(dwc);
190 break;
191 case DWC3_GCTL_PRTCAP_DEVICE:
192 dwc3_gadget_exit(dwc);
193 dwc3_event_buffers_cleanup(dwc);
194 break;
195 case DWC3_GCTL_PRTCAP_OTG:
196 dwc3_otg_exit(dwc);
197 spin_lock_irqsave(&dwc->lock, flags);
198 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
199 spin_unlock_irqrestore(&dwc->lock, flags);
200 dwc3_otg_update(dwc, 1);
201 break;
202 default:
203 break;
204 }
205
206 /*
207 * When current_dr_role is not set, there's no role switching.
208 * Only perform GCTL.CoreSoftReset when there's DRD role switching.
209 */
210 if (dwc->current_dr_role && ((DWC3_IP_IS(DWC3) ||
211 DWC3_VER_IS_PRIOR(DWC31, 190A)) &&
212 desired_dr_role != DWC3_GCTL_PRTCAP_OTG)) {
213 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
214 reg |= DWC3_GCTL_CORESOFTRESET;
215 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
216
217 /*
218 * Wait for internal clocks to synchronized. DWC_usb31 and
219 * DWC_usb32 may need at least 50ms (less for DWC_usb3). To
220 * keep it consistent across different IPs, let's wait up to
221 * 100ms before clearing GCTL.CORESOFTRESET.
222 */
223 msleep(100);
224
225 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
226 reg &= ~DWC3_GCTL_CORESOFTRESET;
227 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
228 }
229
230 spin_lock_irqsave(&dwc->lock, flags);
231
232 dwc3_set_prtcap(dwc, desired_dr_role, false);
233
234 spin_unlock_irqrestore(&dwc->lock, flags);
235
236 switch (desired_dr_role) {
237 case DWC3_GCTL_PRTCAP_HOST:
238 ret = dwc3_host_init(dwc);
239 if (ret) {
240 dev_err(dwc->dev, "failed to initialize host\n");
241 } else {
242 if (dwc->usb2_phy)
243 otg_set_vbus(dwc->usb2_phy->otg, true);
244
245 for (i = 0; i < dwc->num_usb2_ports; i++)
246 phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST);
247 for (i = 0; i < dwc->num_usb3_ports; i++)
248 phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST);
249
250 if (dwc->dis_split_quirk) {
251 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
252 reg |= DWC3_GUCTL3_SPLITDISABLE;
253 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
254 }
255 }
256 break;
257 case DWC3_GCTL_PRTCAP_DEVICE:
258 dwc3_core_soft_reset(dwc);
259
260 dwc3_event_buffers_setup(dwc);
261
262 if (dwc->usb2_phy)
263 otg_set_vbus(dwc->usb2_phy->otg, false);
264 phy_set_mode(dwc->usb2_generic_phy[0], PHY_MODE_USB_DEVICE);
265 phy_set_mode(dwc->usb3_generic_phy[0], PHY_MODE_USB_DEVICE);
266
267 ret = dwc3_gadget_init(dwc);
268 if (ret)
269 dev_err(dwc->dev, "failed to initialize peripheral\n");
270 break;
271 case DWC3_GCTL_PRTCAP_OTG:
272 dwc3_otg_init(dwc);
273 dwc3_otg_update(dwc, 0);
274 break;
275 default:
276 break;
277 }
278
279out:
280 pm_runtime_mark_last_busy(dwc->dev);
281 pm_runtime_put_autosuspend(dwc->dev);
282 mutex_unlock(&dwc->mutex);
283}
284
285void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
286{
287 unsigned long flags;
288
289 if (dwc->dr_mode != USB_DR_MODE_OTG)
290 return;
291
292 spin_lock_irqsave(&dwc->lock, flags);
293 dwc->desired_dr_role = mode;
294 spin_unlock_irqrestore(&dwc->lock, flags);
295
296 queue_work(system_freezable_wq, &dwc->drd_work);
297}
298
299u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
300{
301 struct dwc3 *dwc = dep->dwc;
302 u32 reg;
303
304 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
305 DWC3_GDBGFIFOSPACE_NUM(dep->number) |
306 DWC3_GDBGFIFOSPACE_TYPE(type));
307
308 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
309
310 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
311}
312
313/**
314 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
315 * @dwc: pointer to our context structure
316 */
317int dwc3_core_soft_reset(struct dwc3 *dwc)
318{
319 u32 reg;
320 int retries = 1000;
321
322 /*
323 * We're resetting only the device side because, if we're in host mode,
324 * XHCI driver will reset the host block. If dwc3 was configured for
325 * host-only mode, then we can return early.
326 */
327 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
328 return 0;
329
330 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
331 reg |= DWC3_DCTL_CSFTRST;
332 reg &= ~DWC3_DCTL_RUN_STOP;
333 dwc3_gadget_dctl_write_safe(dwc, reg);
334
335 /*
336 * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit
337 * is cleared only after all the clocks are synchronized. This can
338 * take a little more than 50ms. Set the polling rate at 20ms
339 * for 10 times instead.
340 */
341 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
342 retries = 10;
343
344 do {
345 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
346 if (!(reg & DWC3_DCTL_CSFTRST))
347 goto done;
348
349 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
350 msleep(20);
351 else
352 udelay(1);
353 } while (--retries);
354
355 dev_warn(dwc->dev, "DWC3 controller soft reset failed.\n");
356 return -ETIMEDOUT;
357
358done:
359 /*
360 * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit
361 * is cleared, we must wait at least 50ms before accessing the PHY
362 * domain (synchronization delay).
363 */
364 if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A))
365 msleep(50);
366
367 return 0;
368}
369
370/*
371 * dwc3_frame_length_adjustment - Adjusts frame length if required
372 * @dwc3: Pointer to our controller context structure
373 */
374static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
375{
376 u32 reg;
377 u32 dft;
378
379 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
380 return;
381
382 if (dwc->fladj == 0)
383 return;
384
385 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
386 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
387 if (dft != dwc->fladj) {
388 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
389 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
390 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
391 }
392}
393
394/**
395 * dwc3_ref_clk_period - Reference clock period configuration
396 * Default reference clock period depends on hardware
397 * configuration. For systems with reference clock that differs
398 * from the default, this will set clock period in DWC3_GUCTL
399 * register.
400 * @dwc: Pointer to our controller context structure
401 */
402static void dwc3_ref_clk_period(struct dwc3 *dwc)
403{
404 unsigned long period;
405 unsigned long fladj;
406 unsigned long decr;
407 unsigned long rate;
408 u32 reg;
409
410 if (dwc->ref_clk) {
411 rate = clk_get_rate(dwc->ref_clk);
412 if (!rate)
413 return;
414 period = NSEC_PER_SEC / rate;
415 } else if (dwc->ref_clk_per) {
416 period = dwc->ref_clk_per;
417 rate = NSEC_PER_SEC / period;
418 } else {
419 return;
420 }
421
422 reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
423 reg &= ~DWC3_GUCTL_REFCLKPER_MASK;
424 reg |= FIELD_PREP(DWC3_GUCTL_REFCLKPER_MASK, period);
425 dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
426
427 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
428 return;
429
430 /*
431 * The calculation below is
432 *
433 * 125000 * (NSEC_PER_SEC / (rate * period) - 1)
434 *
435 * but rearranged for fixed-point arithmetic. The division must be
436 * 64-bit because 125000 * NSEC_PER_SEC doesn't fit in 32 bits (and
437 * neither does rate * period).
438 *
439 * Note that rate * period ~= NSEC_PER_SECOND, minus the number of
440 * nanoseconds of error caused by the truncation which happened during
441 * the division when calculating rate or period (whichever one was
442 * derived from the other). We first calculate the relative error, then
443 * scale it to units of 8 ppm.
444 */
445 fladj = div64_u64(125000ULL * NSEC_PER_SEC, (u64)rate * period);
446 fladj -= 125000;
447
448 /*
449 * The documented 240MHz constant is scaled by 2 to get PLS1 as well.
450 */
451 decr = 480000000 / rate;
452
453 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
454 reg &= ~DWC3_GFLADJ_REFCLK_FLADJ_MASK
455 & ~DWC3_GFLADJ_240MHZDECR
456 & ~DWC3_GFLADJ_240MHZDECR_PLS1;
457 reg |= FIELD_PREP(DWC3_GFLADJ_REFCLK_FLADJ_MASK, fladj)
458 | FIELD_PREP(DWC3_GFLADJ_240MHZDECR, decr >> 1)
459 | FIELD_PREP(DWC3_GFLADJ_240MHZDECR_PLS1, decr & 1);
460
461 if (dwc->gfladj_refclk_lpm_sel)
462 reg |= DWC3_GFLADJ_REFCLK_LPM_SEL;
463
464 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
465}
466
467/**
468 * dwc3_free_one_event_buffer - Frees one event buffer
469 * @dwc: Pointer to our controller context structure
470 * @evt: Pointer to event buffer to be freed
471 */
472static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
473 struct dwc3_event_buffer *evt)
474{
475 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
476}
477
478/**
479 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
480 * @dwc: Pointer to our controller context structure
481 * @length: size of the event buffer
482 *
483 * Returns a pointer to the allocated event buffer structure on success
484 * otherwise ERR_PTR(errno).
485 */
486static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
487 unsigned int length)
488{
489 struct dwc3_event_buffer *evt;
490
491 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
492 if (!evt)
493 return ERR_PTR(-ENOMEM);
494
495 evt->dwc = dwc;
496 evt->length = length;
497 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
498 if (!evt->cache)
499 return ERR_PTR(-ENOMEM);
500
501 evt->buf = dma_alloc_coherent(dwc->sysdev, length,
502 &evt->dma, GFP_KERNEL);
503 if (!evt->buf)
504 return ERR_PTR(-ENOMEM);
505
506 return evt;
507}
508
509/**
510 * dwc3_free_event_buffers - frees all allocated event buffers
511 * @dwc: Pointer to our controller context structure
512 */
513static void dwc3_free_event_buffers(struct dwc3 *dwc)
514{
515 struct dwc3_event_buffer *evt;
516
517 evt = dwc->ev_buf;
518 if (evt)
519 dwc3_free_one_event_buffer(dwc, evt);
520}
521
522/**
523 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
524 * @dwc: pointer to our controller context structure
525 * @length: size of event buffer
526 *
527 * Returns 0 on success otherwise negative errno. In the error case, dwc
528 * may contain some buffers allocated but not all which were requested.
529 */
530static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned int length)
531{
532 struct dwc3_event_buffer *evt;
533 unsigned int hw_mode;
534
535 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
536 if (hw_mode == DWC3_GHWPARAMS0_MODE_HOST) {
537 dwc->ev_buf = NULL;
538 return 0;
539 }
540
541 evt = dwc3_alloc_one_event_buffer(dwc, length);
542 if (IS_ERR(evt)) {
543 dev_err(dwc->dev, "can't allocate event buffer\n");
544 return PTR_ERR(evt);
545 }
546 dwc->ev_buf = evt;
547
548 return 0;
549}
550
551/**
552 * dwc3_event_buffers_setup - setup our allocated event buffers
553 * @dwc: pointer to our controller context structure
554 *
555 * Returns 0 on success otherwise negative errno.
556 */
557int dwc3_event_buffers_setup(struct dwc3 *dwc)
558{
559 struct dwc3_event_buffer *evt;
560 u32 reg;
561
562 if (!dwc->ev_buf)
563 return 0;
564
565 evt = dwc->ev_buf;
566 evt->lpos = 0;
567 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
568 lower_32_bits(evt->dma));
569 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
570 upper_32_bits(evt->dma));
571 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
572 DWC3_GEVNTSIZ_SIZE(evt->length));
573
574 /* Clear any stale event */
575 reg = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
576 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), reg);
577 return 0;
578}
579
580void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
581{
582 struct dwc3_event_buffer *evt;
583 u32 reg;
584
585 if (!dwc->ev_buf)
586 return;
587 /*
588 * Exynos platforms may not be able to access event buffer if the
589 * controller failed to halt on dwc3_core_exit().
590 */
591 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
592 if (!(reg & DWC3_DSTS_DEVCTRLHLT))
593 return;
594
595 evt = dwc->ev_buf;
596
597 evt->lpos = 0;
598
599 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
600 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
601 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
602 | DWC3_GEVNTSIZ_SIZE(0));
603
604 /* Clear any stale event */
605 reg = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
606 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), reg);
607}
608
609static void dwc3_core_num_eps(struct dwc3 *dwc)
610{
611 struct dwc3_hwparams *parms = &dwc->hwparams;
612
613 dwc->num_eps = DWC3_NUM_EPS(parms);
614}
615
616static void dwc3_cache_hwparams(struct dwc3 *dwc)
617{
618 struct dwc3_hwparams *parms = &dwc->hwparams;
619
620 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
621 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
622 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
623 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
624 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
625 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
626 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
627 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
628 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
629
630 if (DWC3_IP_IS(DWC32))
631 parms->hwparams9 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS9);
632}
633
634static void dwc3_config_soc_bus(struct dwc3 *dwc)
635{
636 if (dwc->gsbuscfg0_reqinfo != DWC3_GSBUSCFG0_REQINFO_UNSPECIFIED) {
637 u32 reg;
638
639 reg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
640 reg &= ~DWC3_GSBUSCFG0_REQINFO(~0);
641 reg |= DWC3_GSBUSCFG0_REQINFO(dwc->gsbuscfg0_reqinfo);
642 dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, reg);
643 }
644}
645
646static int dwc3_core_ulpi_init(struct dwc3 *dwc)
647{
648 int intf;
649 int ret = 0;
650
651 intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
652
653 if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
654 (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
655 dwc->hsphy_interface &&
656 !strncmp(dwc->hsphy_interface, "ulpi", 4)))
657 ret = dwc3_ulpi_init(dwc);
658
659 return ret;
660}
661
662static int dwc3_ss_phy_setup(struct dwc3 *dwc, int index)
663{
664 u32 reg;
665
666 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(index));
667
668 /*
669 * Make sure UX_EXIT_PX is cleared as that causes issues with some
670 * PHYs. Also, this bit is not supposed to be used in normal operation.
671 */
672 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
673
674 /* Ensure the GUSB3PIPECTL.SUSPENDENABLE is cleared prior to phy init. */
675 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
676
677 if (dwc->u2ss_inp3_quirk)
678 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
679
680 if (dwc->dis_rxdet_inp3_quirk)
681 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
682
683 if (dwc->req_p1p2p3_quirk)
684 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
685
686 if (dwc->del_p1p2p3_quirk)
687 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
688
689 if (dwc->del_phy_power_chg_quirk)
690 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
691
692 if (dwc->lfps_filter_quirk)
693 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
694
695 if (dwc->rx_detect_poll_quirk)
696 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
697
698 if (dwc->tx_de_emphasis_quirk)
699 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
700
701 if (dwc->dis_del_phy_power_chg_quirk)
702 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
703
704 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(index), reg);
705
706 return 0;
707}
708
709static int dwc3_hs_phy_setup(struct dwc3 *dwc, int index)
710{
711 u32 reg;
712
713 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(index));
714
715 /* Select the HS PHY interface */
716 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
717 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
718 if (dwc->hsphy_interface &&
719 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
720 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
721 break;
722 } else if (dwc->hsphy_interface &&
723 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
724 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
725 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(index), reg);
726 } else {
727 /* Relying on default value. */
728 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
729 break;
730 }
731 fallthrough;
732 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
733 default:
734 break;
735 }
736
737 switch (dwc->hsphy_mode) {
738 case USBPHY_INTERFACE_MODE_UTMI:
739 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
740 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
741 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
742 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
743 break;
744 case USBPHY_INTERFACE_MODE_UTMIW:
745 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
746 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
747 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
748 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
749 break;
750 default:
751 break;
752 }
753
754 /* Ensure the GUSB2PHYCFG.SUSPHY is cleared prior to phy init. */
755 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
756
757 if (dwc->dis_enblslpm_quirk)
758 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
759 else
760 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM;
761
762 if (dwc->dis_u2_freeclk_exists_quirk || dwc->gfladj_refclk_lpm_sel)
763 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
764
765 /*
766 * Some ULPI USB PHY does not support internal VBUS supply, to drive
767 * the CPEN pin requires the configuration of the ULPI DRVVBUSEXTERNAL
768 * bit of OTG_CTRL register. Controller configures the USB2 PHY
769 * ULPIEXTVBUSDRV bit[17] of the GUSB2PHYCFG register to drive vBus
770 * with an external supply.
771 */
772 if (dwc->ulpi_ext_vbus_drv)
773 reg |= DWC3_GUSB2PHYCFG_ULPIEXTVBUSDRV;
774
775 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(index), reg);
776
777 return 0;
778}
779
780/**
781 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
782 * @dwc: Pointer to our controller context structure
783 *
784 * Returns 0 on success. The USB PHY interfaces are configured but not
785 * initialized. The PHY interfaces and the PHYs get initialized together with
786 * the core in dwc3_core_init.
787 */
788static int dwc3_phy_setup(struct dwc3 *dwc)
789{
790 int i;
791 int ret;
792
793 for (i = 0; i < dwc->num_usb3_ports; i++) {
794 ret = dwc3_ss_phy_setup(dwc, i);
795 if (ret)
796 return ret;
797 }
798
799 for (i = 0; i < dwc->num_usb2_ports; i++) {
800 ret = dwc3_hs_phy_setup(dwc, i);
801 if (ret)
802 return ret;
803 }
804
805 return 0;
806}
807
808static int dwc3_phy_init(struct dwc3 *dwc)
809{
810 int ret;
811 int i;
812 int j;
813
814 usb_phy_init(dwc->usb2_phy);
815 usb_phy_init(dwc->usb3_phy);
816
817 for (i = 0; i < dwc->num_usb2_ports; i++) {
818 ret = phy_init(dwc->usb2_generic_phy[i]);
819 if (ret < 0)
820 goto err_exit_usb2_phy;
821 }
822
823 for (j = 0; j < dwc->num_usb3_ports; j++) {
824 ret = phy_init(dwc->usb3_generic_phy[j]);
825 if (ret < 0)
826 goto err_exit_usb3_phy;
827 }
828
829 /*
830 * Above DWC_usb3.0 1.94a, it is recommended to set
831 * DWC3_GUSB3PIPECTL_SUSPHY and DWC3_GUSB2PHYCFG_SUSPHY to '0' during
832 * coreConsultant configuration. So default value will be '0' when the
833 * core is reset. Application needs to set it to '1' after the core
834 * initialization is completed.
835 *
836 * Certain phy requires to be in P0 power state during initialization.
837 * Make sure GUSB3PIPECTL.SUSPENDENABLE and GUSB2PHYCFG.SUSPHY are clear
838 * prior to phy init to maintain in the P0 state.
839 *
840 * After phy initialization, some phy operations can only be executed
841 * while in lower P states. Ensure GUSB3PIPECTL.SUSPENDENABLE and
842 * GUSB2PHYCFG.SUSPHY are set soon after initialization to avoid
843 * blocking phy ops.
844 */
845 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
846 dwc3_enable_susphy(dwc, true);
847
848 return 0;
849
850err_exit_usb3_phy:
851 while (--j >= 0)
852 phy_exit(dwc->usb3_generic_phy[j]);
853
854err_exit_usb2_phy:
855 while (--i >= 0)
856 phy_exit(dwc->usb2_generic_phy[i]);
857
858 usb_phy_shutdown(dwc->usb3_phy);
859 usb_phy_shutdown(dwc->usb2_phy);
860
861 return ret;
862}
863
864static void dwc3_phy_exit(struct dwc3 *dwc)
865{
866 int i;
867
868 for (i = 0; i < dwc->num_usb3_ports; i++)
869 phy_exit(dwc->usb3_generic_phy[i]);
870
871 for (i = 0; i < dwc->num_usb2_ports; i++)
872 phy_exit(dwc->usb2_generic_phy[i]);
873
874 usb_phy_shutdown(dwc->usb3_phy);
875 usb_phy_shutdown(dwc->usb2_phy);
876}
877
878static int dwc3_phy_power_on(struct dwc3 *dwc)
879{
880 int ret;
881 int i;
882 int j;
883
884 usb_phy_set_suspend(dwc->usb2_phy, 0);
885 usb_phy_set_suspend(dwc->usb3_phy, 0);
886
887 for (i = 0; i < dwc->num_usb2_ports; i++) {
888 ret = phy_power_on(dwc->usb2_generic_phy[i]);
889 if (ret < 0)
890 goto err_power_off_usb2_phy;
891 }
892
893 for (j = 0; j < dwc->num_usb3_ports; j++) {
894 ret = phy_power_on(dwc->usb3_generic_phy[j]);
895 if (ret < 0)
896 goto err_power_off_usb3_phy;
897 }
898
899 return 0;
900
901err_power_off_usb3_phy:
902 while (--j >= 0)
903 phy_power_off(dwc->usb3_generic_phy[j]);
904
905err_power_off_usb2_phy:
906 while (--i >= 0)
907 phy_power_off(dwc->usb2_generic_phy[i]);
908
909 usb_phy_set_suspend(dwc->usb3_phy, 1);
910 usb_phy_set_suspend(dwc->usb2_phy, 1);
911
912 return ret;
913}
914
915static void dwc3_phy_power_off(struct dwc3 *dwc)
916{
917 int i;
918
919 for (i = 0; i < dwc->num_usb3_ports; i++)
920 phy_power_off(dwc->usb3_generic_phy[i]);
921
922 for (i = 0; i < dwc->num_usb2_ports; i++)
923 phy_power_off(dwc->usb2_generic_phy[i]);
924
925 usb_phy_set_suspend(dwc->usb3_phy, 1);
926 usb_phy_set_suspend(dwc->usb2_phy, 1);
927}
928
929static int dwc3_clk_enable(struct dwc3 *dwc)
930{
931 int ret;
932
933 ret = clk_prepare_enable(dwc->bus_clk);
934 if (ret)
935 return ret;
936
937 ret = clk_prepare_enable(dwc->ref_clk);
938 if (ret)
939 goto disable_bus_clk;
940
941 ret = clk_prepare_enable(dwc->susp_clk);
942 if (ret)
943 goto disable_ref_clk;
944
945 ret = clk_prepare_enable(dwc->utmi_clk);
946 if (ret)
947 goto disable_susp_clk;
948
949 ret = clk_prepare_enable(dwc->pipe_clk);
950 if (ret)
951 goto disable_utmi_clk;
952
953 return 0;
954
955disable_utmi_clk:
956 clk_disable_unprepare(dwc->utmi_clk);
957disable_susp_clk:
958 clk_disable_unprepare(dwc->susp_clk);
959disable_ref_clk:
960 clk_disable_unprepare(dwc->ref_clk);
961disable_bus_clk:
962 clk_disable_unprepare(dwc->bus_clk);
963 return ret;
964}
965
966static void dwc3_clk_disable(struct dwc3 *dwc)
967{
968 clk_disable_unprepare(dwc->pipe_clk);
969 clk_disable_unprepare(dwc->utmi_clk);
970 clk_disable_unprepare(dwc->susp_clk);
971 clk_disable_unprepare(dwc->ref_clk);
972 clk_disable_unprepare(dwc->bus_clk);
973}
974
975static void dwc3_core_exit(struct dwc3 *dwc)
976{
977 dwc3_event_buffers_cleanup(dwc);
978 dwc3_phy_power_off(dwc);
979 dwc3_phy_exit(dwc);
980 dwc3_clk_disable(dwc);
981 reset_control_assert(dwc->reset);
982}
983
984static bool dwc3_core_is_valid(struct dwc3 *dwc)
985{
986 u32 reg;
987
988 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
989 dwc->ip = DWC3_GSNPS_ID(reg);
990
991 /* This should read as U3 followed by revision number */
992 if (DWC3_IP_IS(DWC3)) {
993 dwc->revision = reg;
994 } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) {
995 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
996 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE);
997 } else {
998 return false;
999 }
1000
1001 return true;
1002}
1003
1004static void dwc3_core_setup_global_control(struct dwc3 *dwc)
1005{
1006 unsigned int power_opt;
1007 unsigned int hw_mode;
1008 u32 reg;
1009
1010 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
1011 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
1012 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
1013 power_opt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
1014
1015 switch (power_opt) {
1016 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
1017 /**
1018 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
1019 * issue which would cause xHCI compliance tests to fail.
1020 *
1021 * Because of that we cannot enable clock gating on such
1022 * configurations.
1023 *
1024 * Refers to:
1025 *
1026 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
1027 * SOF/ITP Mode Used
1028 */
1029 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
1030 dwc->dr_mode == USB_DR_MODE_OTG) &&
1031 DWC3_VER_IS_WITHIN(DWC3, 210A, 250A))
1032 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
1033 else
1034 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
1035 break;
1036 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
1037 /*
1038 * REVISIT Enabling this bit so that host-mode hibernation
1039 * will work. Device-mode hibernation is not yet implemented.
1040 */
1041 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
1042 break;
1043 default:
1044 /* nothing */
1045 break;
1046 }
1047
1048 /*
1049 * This is a workaround for STAR#4846132, which only affects
1050 * DWC_usb31 version2.00a operating in host mode.
1051 *
1052 * There is a problem in DWC_usb31 version 2.00a operating
1053 * in host mode that would cause a CSR read timeout When CSR
1054 * read coincides with RAM Clock Gating Entry. By disable
1055 * Clock Gating, sacrificing power consumption for normal
1056 * operation.
1057 */
1058 if (power_opt != DWC3_GHWPARAMS1_EN_PWROPT_NO &&
1059 hw_mode != DWC3_GHWPARAMS0_MODE_GADGET && DWC3_VER_IS(DWC31, 200A))
1060 reg |= DWC3_GCTL_DSBLCLKGTNG;
1061
1062 /* check if current dwc3 is on simulation board */
1063 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
1064 dev_info(dwc->dev, "Running with FPGA optimizations\n");
1065 dwc->is_fpga = true;
1066 }
1067
1068 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
1069 "disable_scramble cannot be used on non-FPGA builds\n");
1070
1071 if (dwc->disable_scramble_quirk && dwc->is_fpga)
1072 reg |= DWC3_GCTL_DISSCRAMBLE;
1073 else
1074 reg &= ~DWC3_GCTL_DISSCRAMBLE;
1075
1076 if (dwc->u2exit_lfps_quirk)
1077 reg |= DWC3_GCTL_U2EXIT_LFPS;
1078
1079 /*
1080 * WORKAROUND: DWC3 revisions <1.90a have a bug
1081 * where the device can fail to connect at SuperSpeed
1082 * and falls back to high-speed mode which causes
1083 * the device to enter a Connect/Disconnect loop
1084 */
1085 if (DWC3_VER_IS_PRIOR(DWC3, 190A))
1086 reg |= DWC3_GCTL_U2RSTECN;
1087
1088 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
1089}
1090
1091static int dwc3_core_get_phy(struct dwc3 *dwc);
1092static int dwc3_core_ulpi_init(struct dwc3 *dwc);
1093
1094/* set global incr burst type configuration registers */
1095static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
1096{
1097 struct device *dev = dwc->dev;
1098 /* incrx_mode : for INCR burst type. */
1099 bool incrx_mode;
1100 /* incrx_size : for size of INCRX burst. */
1101 u32 incrx_size;
1102 u32 *vals;
1103 u32 cfg;
1104 int ntype;
1105 int ret;
1106 int i;
1107
1108 cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
1109
1110 /*
1111 * Handle property "snps,incr-burst-type-adjustment".
1112 * Get the number of value from this property:
1113 * result <= 0, means this property is not supported.
1114 * result = 1, means INCRx burst mode supported.
1115 * result > 1, means undefined length burst mode supported.
1116 */
1117 ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment");
1118 if (ntype <= 0)
1119 return;
1120
1121 vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
1122 if (!vals)
1123 return;
1124
1125 /* Get INCR burst type, and parse it */
1126 ret = device_property_read_u32_array(dev,
1127 "snps,incr-burst-type-adjustment", vals, ntype);
1128 if (ret) {
1129 kfree(vals);
1130 dev_err(dev, "Error to get property\n");
1131 return;
1132 }
1133
1134 incrx_size = *vals;
1135
1136 if (ntype > 1) {
1137 /* INCRX (undefined length) burst mode */
1138 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
1139 for (i = 1; i < ntype; i++) {
1140 if (vals[i] > incrx_size)
1141 incrx_size = vals[i];
1142 }
1143 } else {
1144 /* INCRX burst mode */
1145 incrx_mode = INCRX_BURST_MODE;
1146 }
1147
1148 kfree(vals);
1149
1150 /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
1151 cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
1152 if (incrx_mode)
1153 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
1154 switch (incrx_size) {
1155 case 256:
1156 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
1157 break;
1158 case 128:
1159 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
1160 break;
1161 case 64:
1162 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
1163 break;
1164 case 32:
1165 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
1166 break;
1167 case 16:
1168 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
1169 break;
1170 case 8:
1171 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
1172 break;
1173 case 4:
1174 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
1175 break;
1176 case 1:
1177 break;
1178 default:
1179 dev_err(dev, "Invalid property\n");
1180 break;
1181 }
1182
1183 dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
1184}
1185
1186static void dwc3_set_power_down_clk_scale(struct dwc3 *dwc)
1187{
1188 u32 scale;
1189 u32 reg;
1190
1191 if (!dwc->susp_clk)
1192 return;
1193
1194 /*
1195 * The power down scale field specifies how many suspend_clk
1196 * periods fit into a 16KHz clock period. When performing
1197 * the division, round up the remainder.
1198 *
1199 * The power down scale value is calculated using the fastest
1200 * frequency of the suspend_clk. If it isn't fixed (but within
1201 * the accuracy requirement), the driver may not know the max
1202 * rate of the suspend_clk, so only update the power down scale
1203 * if the default is less than the calculated value from
1204 * clk_get_rate() or if the default is questionably high
1205 * (3x or more) to be within the requirement.
1206 */
1207 scale = DIV_ROUND_UP(clk_get_rate(dwc->susp_clk), 16000);
1208 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
1209 if ((reg & DWC3_GCTL_PWRDNSCALE_MASK) < DWC3_GCTL_PWRDNSCALE(scale) ||
1210 (reg & DWC3_GCTL_PWRDNSCALE_MASK) > DWC3_GCTL_PWRDNSCALE(scale*3)) {
1211 reg &= ~(DWC3_GCTL_PWRDNSCALE_MASK);
1212 reg |= DWC3_GCTL_PWRDNSCALE(scale);
1213 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
1214 }
1215}
1216
1217static void dwc3_config_threshold(struct dwc3 *dwc)
1218{
1219 u32 reg;
1220 u8 rx_thr_num;
1221 u8 rx_maxburst;
1222 u8 tx_thr_num;
1223 u8 tx_maxburst;
1224
1225 /*
1226 * Must config both number of packets and max burst settings to enable
1227 * RX and/or TX threshold.
1228 */
1229 if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) {
1230 rx_thr_num = dwc->rx_thr_num_pkt_prd;
1231 rx_maxburst = dwc->rx_max_burst_prd;
1232 tx_thr_num = dwc->tx_thr_num_pkt_prd;
1233 tx_maxburst = dwc->tx_max_burst_prd;
1234
1235 if (rx_thr_num && rx_maxburst) {
1236 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1237 reg |= DWC31_RXTHRNUMPKTSEL_PRD;
1238
1239 reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
1240 reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
1241
1242 reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
1243 reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
1244
1245 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1246 }
1247
1248 if (tx_thr_num && tx_maxburst) {
1249 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1250 reg |= DWC31_TXTHRNUMPKTSEL_PRD;
1251
1252 reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
1253 reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
1254
1255 reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
1256 reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
1257
1258 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1259 }
1260 }
1261
1262 rx_thr_num = dwc->rx_thr_num_pkt;
1263 rx_maxburst = dwc->rx_max_burst;
1264 tx_thr_num = dwc->tx_thr_num_pkt;
1265 tx_maxburst = dwc->tx_max_burst;
1266
1267 if (DWC3_IP_IS(DWC3)) {
1268 if (rx_thr_num && rx_maxburst) {
1269 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1270 reg |= DWC3_GRXTHRCFG_PKTCNTSEL;
1271
1272 reg &= ~DWC3_GRXTHRCFG_RXPKTCNT(~0);
1273 reg |= DWC3_GRXTHRCFG_RXPKTCNT(rx_thr_num);
1274
1275 reg &= ~DWC3_GRXTHRCFG_MAXRXBURSTSIZE(~0);
1276 reg |= DWC3_GRXTHRCFG_MAXRXBURSTSIZE(rx_maxburst);
1277
1278 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1279 }
1280
1281 if (tx_thr_num && tx_maxburst) {
1282 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1283 reg |= DWC3_GTXTHRCFG_PKTCNTSEL;
1284
1285 reg &= ~DWC3_GTXTHRCFG_TXPKTCNT(~0);
1286 reg |= DWC3_GTXTHRCFG_TXPKTCNT(tx_thr_num);
1287
1288 reg &= ~DWC3_GTXTHRCFG_MAXTXBURSTSIZE(~0);
1289 reg |= DWC3_GTXTHRCFG_MAXTXBURSTSIZE(tx_maxburst);
1290
1291 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1292 }
1293 } else {
1294 if (rx_thr_num && rx_maxburst) {
1295 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1296 reg |= DWC31_GRXTHRCFG_PKTCNTSEL;
1297
1298 reg &= ~DWC31_GRXTHRCFG_RXPKTCNT(~0);
1299 reg |= DWC31_GRXTHRCFG_RXPKTCNT(rx_thr_num);
1300
1301 reg &= ~DWC31_GRXTHRCFG_MAXRXBURSTSIZE(~0);
1302 reg |= DWC31_GRXTHRCFG_MAXRXBURSTSIZE(rx_maxburst);
1303
1304 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1305 }
1306
1307 if (tx_thr_num && tx_maxburst) {
1308 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1309 reg |= DWC31_GTXTHRCFG_PKTCNTSEL;
1310
1311 reg &= ~DWC31_GTXTHRCFG_TXPKTCNT(~0);
1312 reg |= DWC31_GTXTHRCFG_TXPKTCNT(tx_thr_num);
1313
1314 reg &= ~DWC31_GTXTHRCFG_MAXTXBURSTSIZE(~0);
1315 reg |= DWC31_GTXTHRCFG_MAXTXBURSTSIZE(tx_maxburst);
1316
1317 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1318 }
1319 }
1320}
1321
1322/**
1323 * dwc3_core_init - Low-level initialization of DWC3 Core
1324 * @dwc: Pointer to our controller context structure
1325 *
1326 * Returns 0 on success otherwise negative errno.
1327 */
1328static int dwc3_core_init(struct dwc3 *dwc)
1329{
1330 unsigned int hw_mode;
1331 u32 reg;
1332 int ret;
1333
1334 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
1335
1336 /*
1337 * Write Linux Version Code to our GUID register so it's easy to figure
1338 * out which kernel version a bug was found.
1339 */
1340 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
1341
1342 ret = dwc3_phy_setup(dwc);
1343 if (ret)
1344 return ret;
1345
1346 if (!dwc->ulpi_ready) {
1347 ret = dwc3_core_ulpi_init(dwc);
1348 if (ret) {
1349 if (ret == -ETIMEDOUT) {
1350 dwc3_core_soft_reset(dwc);
1351 ret = -EPROBE_DEFER;
1352 }
1353 return ret;
1354 }
1355 dwc->ulpi_ready = true;
1356 }
1357
1358 if (!dwc->phys_ready) {
1359 ret = dwc3_core_get_phy(dwc);
1360 if (ret)
1361 goto err_exit_ulpi;
1362 dwc->phys_ready = true;
1363 }
1364
1365 ret = dwc3_phy_init(dwc);
1366 if (ret)
1367 goto err_exit_ulpi;
1368
1369 ret = dwc3_core_soft_reset(dwc);
1370 if (ret)
1371 goto err_exit_phy;
1372
1373 dwc3_core_setup_global_control(dwc);
1374 dwc3_core_num_eps(dwc);
1375
1376 /* Set power down scale of suspend_clk */
1377 dwc3_set_power_down_clk_scale(dwc);
1378
1379 /* Adjust Frame Length */
1380 dwc3_frame_length_adjustment(dwc);
1381
1382 /* Adjust Reference Clock Period */
1383 dwc3_ref_clk_period(dwc);
1384
1385 dwc3_set_incr_burst_type(dwc);
1386
1387 dwc3_config_soc_bus(dwc);
1388
1389 ret = dwc3_phy_power_on(dwc);
1390 if (ret)
1391 goto err_exit_phy;
1392
1393 ret = dwc3_event_buffers_setup(dwc);
1394 if (ret) {
1395 dev_err(dwc->dev, "failed to setup event buffers\n");
1396 goto err_power_off_phy;
1397 }
1398
1399 /*
1400 * ENDXFER polling is available on version 3.10a and later of
1401 * the DWC_usb3 controller. It is NOT available in the
1402 * DWC_usb31 controller.
1403 */
1404 if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) {
1405 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
1406 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
1407 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
1408 }
1409
1410 /*
1411 * STAR 9001285599: This issue affects DWC_usb3 version 3.20a
1412 * only. If the PM TIMER ECM is enabled through GUCTL2[19], the
1413 * link compliance test (TD7.21) may fail. If the ECN is not
1414 * enabled (GUCTL2[19] = 0), the controller will use the old timer
1415 * value (5us), which is still acceptable for the link compliance
1416 * test. Therefore, do not enable PM TIMER ECM in 3.20a by
1417 * setting GUCTL2[19] by default; instead, use GUCTL2[19] = 0.
1418 */
1419 if (DWC3_VER_IS(DWC3, 320A)) {
1420 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
1421 reg &= ~DWC3_GUCTL2_LC_TIMER;
1422 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
1423 }
1424
1425 /*
1426 * When configured in HOST mode, after issuing U3/L2 exit controller
1427 * fails to send proper CRC checksum in CRC5 field. Because of this
1428 * behaviour Transaction Error is generated, resulting in reset and
1429 * re-enumeration of usb device attached. All the termsel, xcvrsel,
1430 * opmode becomes 0 during end of resume. Enabling bit 10 of GUCTL1
1431 * will correct this problem. This option is to support certain
1432 * legacy ULPI PHYs.
1433 */
1434 if (dwc->resume_hs_terminations) {
1435 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
1436 reg |= DWC3_GUCTL1_RESUME_OPMODE_HS_HOST;
1437 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1438 }
1439
1440 if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) {
1441 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
1442
1443 /*
1444 * Enable hardware control of sending remote wakeup
1445 * in HS when the device is in the L1 state.
1446 */
1447 if (!DWC3_VER_IS_PRIOR(DWC3, 290A))
1448 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
1449
1450 /*
1451 * Decouple USB 2.0 L1 & L2 events which will allow for
1452 * gadget driver to only receive U3/L2 suspend & wakeup
1453 * events and prevent the more frequent L1 LPM transitions
1454 * from interrupting the driver.
1455 */
1456 if (!DWC3_VER_IS_PRIOR(DWC3, 300A))
1457 reg |= DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT;
1458
1459 if (dwc->dis_tx_ipgap_linecheck_quirk)
1460 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
1461
1462 if (dwc->parkmode_disable_ss_quirk)
1463 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
1464
1465 if (dwc->parkmode_disable_hs_quirk)
1466 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_HS;
1467
1468 if (DWC3_VER_IS_WITHIN(DWC3, 290A, ANY)) {
1469 if (dwc->maximum_speed == USB_SPEED_FULL ||
1470 dwc->maximum_speed == USB_SPEED_HIGH)
1471 reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK;
1472 else
1473 reg &= ~DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK;
1474 }
1475
1476 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1477 }
1478
1479 dwc3_config_threshold(dwc);
1480
1481 /*
1482 * Modify this for all supported Super Speed ports when
1483 * multiport support is added.
1484 */
1485 if (hw_mode != DWC3_GHWPARAMS0_MODE_GADGET &&
1486 (DWC3_IP_IS(DWC31)) &&
1487 dwc->maximum_speed == USB_SPEED_SUPER) {
1488 int i;
1489
1490 for (i = 0; i < dwc->num_usb3_ports; i++) {
1491 reg = dwc3_readl(dwc->regs, DWC3_LLUCTL(i));
1492 reg |= DWC3_LLUCTL_FORCE_GEN1;
1493 dwc3_writel(dwc->regs, DWC3_LLUCTL(i), reg);
1494 }
1495 }
1496
1497 return 0;
1498
1499err_power_off_phy:
1500 dwc3_phy_power_off(dwc);
1501err_exit_phy:
1502 dwc3_phy_exit(dwc);
1503err_exit_ulpi:
1504 dwc3_ulpi_exit(dwc);
1505
1506 return ret;
1507}
1508
1509static int dwc3_core_get_phy(struct dwc3 *dwc)
1510{
1511 struct device *dev = dwc->dev;
1512 struct device_node *node = dev->of_node;
1513 char phy_name[9];
1514 int ret;
1515 u8 i;
1516
1517 if (node) {
1518 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
1519 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
1520 } else {
1521 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
1522 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
1523 }
1524
1525 if (IS_ERR(dwc->usb2_phy)) {
1526 ret = PTR_ERR(dwc->usb2_phy);
1527 if (ret == -ENXIO || ret == -ENODEV)
1528 dwc->usb2_phy = NULL;
1529 else
1530 return dev_err_probe(dev, ret, "no usb2 phy configured\n");
1531 }
1532
1533 if (IS_ERR(dwc->usb3_phy)) {
1534 ret = PTR_ERR(dwc->usb3_phy);
1535 if (ret == -ENXIO || ret == -ENODEV)
1536 dwc->usb3_phy = NULL;
1537 else
1538 return dev_err_probe(dev, ret, "no usb3 phy configured\n");
1539 }
1540
1541 for (i = 0; i < dwc->num_usb2_ports; i++) {
1542 if (dwc->num_usb2_ports == 1)
1543 snprintf(phy_name, sizeof(phy_name), "usb2-phy");
1544 else
1545 snprintf(phy_name, sizeof(phy_name), "usb2-%u", i);
1546
1547 dwc->usb2_generic_phy[i] = devm_phy_get(dev, phy_name);
1548 if (IS_ERR(dwc->usb2_generic_phy[i])) {
1549 ret = PTR_ERR(dwc->usb2_generic_phy[i]);
1550 if (ret == -ENOSYS || ret == -ENODEV)
1551 dwc->usb2_generic_phy[i] = NULL;
1552 else
1553 return dev_err_probe(dev, ret, "failed to lookup phy %s\n",
1554 phy_name);
1555 }
1556 }
1557
1558 for (i = 0; i < dwc->num_usb3_ports; i++) {
1559 if (dwc->num_usb3_ports == 1)
1560 snprintf(phy_name, sizeof(phy_name), "usb3-phy");
1561 else
1562 snprintf(phy_name, sizeof(phy_name), "usb3-%u", i);
1563
1564 dwc->usb3_generic_phy[i] = devm_phy_get(dev, phy_name);
1565 if (IS_ERR(dwc->usb3_generic_phy[i])) {
1566 ret = PTR_ERR(dwc->usb3_generic_phy[i]);
1567 if (ret == -ENOSYS || ret == -ENODEV)
1568 dwc->usb3_generic_phy[i] = NULL;
1569 else
1570 return dev_err_probe(dev, ret, "failed to lookup phy %s\n",
1571 phy_name);
1572 }
1573 }
1574
1575 return 0;
1576}
1577
1578static int dwc3_core_init_mode(struct dwc3 *dwc)
1579{
1580 struct device *dev = dwc->dev;
1581 int ret;
1582 int i;
1583
1584 switch (dwc->dr_mode) {
1585 case USB_DR_MODE_PERIPHERAL:
1586 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE, false);
1587
1588 if (dwc->usb2_phy)
1589 otg_set_vbus(dwc->usb2_phy->otg, false);
1590 phy_set_mode(dwc->usb2_generic_phy[0], PHY_MODE_USB_DEVICE);
1591 phy_set_mode(dwc->usb3_generic_phy[0], PHY_MODE_USB_DEVICE);
1592
1593 ret = dwc3_gadget_init(dwc);
1594 if (ret)
1595 return dev_err_probe(dev, ret, "failed to initialize gadget\n");
1596 break;
1597 case USB_DR_MODE_HOST:
1598 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST, false);
1599
1600 if (dwc->usb2_phy)
1601 otg_set_vbus(dwc->usb2_phy->otg, true);
1602 for (i = 0; i < dwc->num_usb2_ports; i++)
1603 phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST);
1604 for (i = 0; i < dwc->num_usb3_ports; i++)
1605 phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST);
1606
1607 ret = dwc3_host_init(dwc);
1608 if (ret)
1609 return dev_err_probe(dev, ret, "failed to initialize host\n");
1610 break;
1611 case USB_DR_MODE_OTG:
1612 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
1613 ret = dwc3_drd_init(dwc);
1614 if (ret)
1615 return dev_err_probe(dev, ret, "failed to initialize dual-role\n");
1616 break;
1617 default:
1618 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
1619 return -EINVAL;
1620 }
1621
1622 return 0;
1623}
1624
1625static void dwc3_core_exit_mode(struct dwc3 *dwc)
1626{
1627 switch (dwc->dr_mode) {
1628 case USB_DR_MODE_PERIPHERAL:
1629 dwc3_gadget_exit(dwc);
1630 break;
1631 case USB_DR_MODE_HOST:
1632 dwc3_host_exit(dwc);
1633 break;
1634 case USB_DR_MODE_OTG:
1635 dwc3_drd_exit(dwc);
1636 break;
1637 default:
1638 /* do nothing */
1639 break;
1640 }
1641
1642 /* de-assert DRVVBUS for HOST and OTG mode */
1643 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE, true);
1644}
1645
1646static void dwc3_get_software_properties(struct dwc3 *dwc)
1647{
1648 struct device *tmpdev;
1649 u16 gsbuscfg0_reqinfo;
1650 int ret;
1651
1652 dwc->gsbuscfg0_reqinfo = DWC3_GSBUSCFG0_REQINFO_UNSPECIFIED;
1653
1654 /*
1655 * Iterate over all parent nodes for finding swnode properties
1656 * and non-DT (non-ABI) properties.
1657 */
1658 for (tmpdev = dwc->dev; tmpdev; tmpdev = tmpdev->parent) {
1659 ret = device_property_read_u16(tmpdev,
1660 "snps,gsbuscfg0-reqinfo",
1661 &gsbuscfg0_reqinfo);
1662 if (!ret)
1663 dwc->gsbuscfg0_reqinfo = gsbuscfg0_reqinfo;
1664 }
1665}
1666
1667static void dwc3_get_properties(struct dwc3 *dwc)
1668{
1669 struct device *dev = dwc->dev;
1670 u8 lpm_nyet_threshold;
1671 u8 tx_de_emphasis;
1672 u8 hird_threshold;
1673 u8 rx_thr_num_pkt = 0;
1674 u8 rx_max_burst = 0;
1675 u8 tx_thr_num_pkt = 0;
1676 u8 tx_max_burst = 0;
1677 u8 rx_thr_num_pkt_prd = 0;
1678 u8 rx_max_burst_prd = 0;
1679 u8 tx_thr_num_pkt_prd = 0;
1680 u8 tx_max_burst_prd = 0;
1681 u8 tx_fifo_resize_max_num;
1682
1683 /* default to highest possible threshold */
1684 lpm_nyet_threshold = 0xf;
1685
1686 /* default to -3.5dB de-emphasis */
1687 tx_de_emphasis = 1;
1688
1689 /*
1690 * default to assert utmi_sleep_n and use maximum allowed HIRD
1691 * threshold value of 0b1100
1692 */
1693 hird_threshold = 12;
1694
1695 /*
1696 * default to a TXFIFO size large enough to fit 6 max packets. This
1697 * allows for systems with larger bus latencies to have some headroom
1698 * for endpoints that have a large bMaxBurst value.
1699 */
1700 tx_fifo_resize_max_num = 6;
1701
1702 dwc->maximum_speed = usb_get_maximum_speed(dev);
1703 dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev);
1704 dwc->dr_mode = usb_get_dr_mode(dev);
1705 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
1706
1707 dwc->sysdev_is_parent = device_property_read_bool(dev,
1708 "linux,sysdev_is_parent");
1709 if (dwc->sysdev_is_parent)
1710 dwc->sysdev = dwc->dev->parent;
1711 else
1712 dwc->sysdev = dwc->dev;
1713
1714 dwc->sys_wakeup = device_may_wakeup(dwc->sysdev);
1715
1716 dwc->has_lpm_erratum = device_property_read_bool(dev,
1717 "snps,has-lpm-erratum");
1718 device_property_read_u8(dev, "snps,lpm-nyet-threshold",
1719 &lpm_nyet_threshold);
1720 dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1721 "snps,is-utmi-l1-suspend");
1722 device_property_read_u8(dev, "snps,hird-threshold",
1723 &hird_threshold);
1724 dwc->dis_start_transfer_quirk = device_property_read_bool(dev,
1725 "snps,dis-start-transfer-quirk");
1726 dwc->usb3_lpm_capable = device_property_read_bool(dev,
1727 "snps,usb3_lpm_capable");
1728 dwc->usb2_lpm_disable = device_property_read_bool(dev,
1729 "snps,usb2-lpm-disable");
1730 dwc->usb2_gadget_lpm_disable = device_property_read_bool(dev,
1731 "snps,usb2-gadget-lpm-disable");
1732 device_property_read_u8(dev, "snps,rx-thr-num-pkt",
1733 &rx_thr_num_pkt);
1734 device_property_read_u8(dev, "snps,rx-max-burst",
1735 &rx_max_burst);
1736 device_property_read_u8(dev, "snps,tx-thr-num-pkt",
1737 &tx_thr_num_pkt);
1738 device_property_read_u8(dev, "snps,tx-max-burst",
1739 &tx_max_burst);
1740 device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
1741 &rx_thr_num_pkt_prd);
1742 device_property_read_u8(dev, "snps,rx-max-burst-prd",
1743 &rx_max_burst_prd);
1744 device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
1745 &tx_thr_num_pkt_prd);
1746 device_property_read_u8(dev, "snps,tx-max-burst-prd",
1747 &tx_max_burst_prd);
1748 dwc->do_fifo_resize = device_property_read_bool(dev,
1749 "tx-fifo-resize");
1750 if (dwc->do_fifo_resize)
1751 device_property_read_u8(dev, "tx-fifo-max-num",
1752 &tx_fifo_resize_max_num);
1753
1754 dwc->disable_scramble_quirk = device_property_read_bool(dev,
1755 "snps,disable_scramble_quirk");
1756 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1757 "snps,u2exit_lfps_quirk");
1758 dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1759 "snps,u2ss_inp3_quirk");
1760 dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1761 "snps,req_p1p2p3_quirk");
1762 dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1763 "snps,del_p1p2p3_quirk");
1764 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1765 "snps,del_phy_power_chg_quirk");
1766 dwc->lfps_filter_quirk = device_property_read_bool(dev,
1767 "snps,lfps_filter_quirk");
1768 dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1769 "snps,rx_detect_poll_quirk");
1770 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1771 "snps,dis_u3_susphy_quirk");
1772 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1773 "snps,dis_u2_susphy_quirk");
1774 dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1775 "snps,dis_enblslpm_quirk");
1776 dwc->dis_u1_entry_quirk = device_property_read_bool(dev,
1777 "snps,dis-u1-entry-quirk");
1778 dwc->dis_u2_entry_quirk = device_property_read_bool(dev,
1779 "snps,dis-u2-entry-quirk");
1780 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1781 "snps,dis_rxdet_inp3_quirk");
1782 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1783 "snps,dis-u2-freeclk-exists-quirk");
1784 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1785 "snps,dis-del-phy-power-chg-quirk");
1786 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1787 "snps,dis-tx-ipgap-linecheck-quirk");
1788 dwc->resume_hs_terminations = device_property_read_bool(dev,
1789 "snps,resume-hs-terminations");
1790 dwc->ulpi_ext_vbus_drv = device_property_read_bool(dev,
1791 "snps,ulpi-ext-vbus-drv");
1792 dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
1793 "snps,parkmode-disable-ss-quirk");
1794 dwc->parkmode_disable_hs_quirk = device_property_read_bool(dev,
1795 "snps,parkmode-disable-hs-quirk");
1796 dwc->gfladj_refclk_lpm_sel = device_property_read_bool(dev,
1797 "snps,gfladj-refclk-lpm-sel-quirk");
1798
1799 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1800 "snps,tx_de_emphasis_quirk");
1801 device_property_read_u8(dev, "snps,tx_de_emphasis",
1802 &tx_de_emphasis);
1803 device_property_read_string(dev, "snps,hsphy_interface",
1804 &dwc->hsphy_interface);
1805 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1806 &dwc->fladj);
1807 device_property_read_u32(dev, "snps,ref-clock-period-ns",
1808 &dwc->ref_clk_per);
1809
1810 dwc->dis_metastability_quirk = device_property_read_bool(dev,
1811 "snps,dis_metastability_quirk");
1812
1813 dwc->dis_split_quirk = device_property_read_bool(dev,
1814 "snps,dis-split-quirk");
1815
1816 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1817 dwc->tx_de_emphasis = tx_de_emphasis;
1818
1819 dwc->hird_threshold = hird_threshold;
1820
1821 dwc->rx_thr_num_pkt = rx_thr_num_pkt;
1822 dwc->rx_max_burst = rx_max_burst;
1823
1824 dwc->tx_thr_num_pkt = tx_thr_num_pkt;
1825 dwc->tx_max_burst = tx_max_burst;
1826
1827 dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
1828 dwc->rx_max_burst_prd = rx_max_burst_prd;
1829
1830 dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
1831 dwc->tx_max_burst_prd = tx_max_burst_prd;
1832
1833 dwc->tx_fifo_resize_max_num = tx_fifo_resize_max_num;
1834}
1835
1836/* check whether the core supports IMOD */
1837bool dwc3_has_imod(struct dwc3 *dwc)
1838{
1839 return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) ||
1840 DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) ||
1841 DWC3_IP_IS(DWC32);
1842}
1843
1844static void dwc3_check_params(struct dwc3 *dwc)
1845{
1846 struct device *dev = dwc->dev;
1847 unsigned int hwparam_gen =
1848 DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3);
1849
1850 /*
1851 * Enable IMOD for all supporting controllers.
1852 *
1853 * Particularly, DWC_usb3 v3.00a must enable this feature for
1854 * the following reason:
1855 *
1856 * Workaround for STAR 9000961433 which affects only version
1857 * 3.00a of the DWC_usb3 core. This prevents the controller
1858 * interrupt from being masked while handling events. IMOD
1859 * allows us to work around this issue. Enable it for the
1860 * affected version.
1861 */
1862 if (dwc3_has_imod((dwc)))
1863 dwc->imod_interval = 1;
1864
1865 /* Check the maximum_speed parameter */
1866 switch (dwc->maximum_speed) {
1867 case USB_SPEED_FULL:
1868 case USB_SPEED_HIGH:
1869 break;
1870 case USB_SPEED_SUPER:
1871 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS)
1872 dev_warn(dev, "UDC doesn't support Gen 1\n");
1873 break;
1874 case USB_SPEED_SUPER_PLUS:
1875 if ((DWC3_IP_IS(DWC32) &&
1876 hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) ||
1877 (!DWC3_IP_IS(DWC32) &&
1878 hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1879 dev_warn(dev, "UDC doesn't support SSP\n");
1880 break;
1881 default:
1882 dev_err(dev, "invalid maximum_speed parameter %d\n",
1883 dwc->maximum_speed);
1884 fallthrough;
1885 case USB_SPEED_UNKNOWN:
1886 switch (hwparam_gen) {
1887 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1888 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1889 break;
1890 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1891 if (DWC3_IP_IS(DWC32))
1892 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1893 else
1894 dwc->maximum_speed = USB_SPEED_SUPER;
1895 break;
1896 case DWC3_GHWPARAMS3_SSPHY_IFC_DIS:
1897 dwc->maximum_speed = USB_SPEED_HIGH;
1898 break;
1899 default:
1900 dwc->maximum_speed = USB_SPEED_SUPER;
1901 break;
1902 }
1903 break;
1904 }
1905
1906 /*
1907 * Currently the controller does not have visibility into the HW
1908 * parameter to determine the maximum number of lanes the HW supports.
1909 * If the number of lanes is not specified in the device property, then
1910 * set the default to support dual-lane for DWC_usb32 and single-lane
1911 * for DWC_usb31 for super-speed-plus.
1912 */
1913 if (dwc->maximum_speed == USB_SPEED_SUPER_PLUS) {
1914 switch (dwc->max_ssp_rate) {
1915 case USB_SSP_GEN_2x1:
1916 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_GEN1)
1917 dev_warn(dev, "UDC only supports Gen 1\n");
1918 break;
1919 case USB_SSP_GEN_1x2:
1920 case USB_SSP_GEN_2x2:
1921 if (DWC3_IP_IS(DWC31))
1922 dev_warn(dev, "UDC only supports single lane\n");
1923 break;
1924 case USB_SSP_GEN_UNKNOWN:
1925 default:
1926 switch (hwparam_gen) {
1927 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1928 if (DWC3_IP_IS(DWC32))
1929 dwc->max_ssp_rate = USB_SSP_GEN_2x2;
1930 else
1931 dwc->max_ssp_rate = USB_SSP_GEN_2x1;
1932 break;
1933 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1934 if (DWC3_IP_IS(DWC32))
1935 dwc->max_ssp_rate = USB_SSP_GEN_1x2;
1936 break;
1937 }
1938 break;
1939 }
1940 }
1941}
1942
1943static struct extcon_dev *dwc3_get_extcon(struct dwc3 *dwc)
1944{
1945 struct device *dev = dwc->dev;
1946 struct device_node *np_phy;
1947 struct extcon_dev *edev = NULL;
1948 const char *name;
1949
1950 if (device_property_present(dev, "extcon"))
1951 return extcon_get_edev_by_phandle(dev, 0);
1952
1953 /*
1954 * Device tree platforms should get extcon via phandle.
1955 * On ACPI platforms, we get the name from a device property.
1956 * This device property is for kernel internal use only and
1957 * is expected to be set by the glue code.
1958 */
1959 if (device_property_read_string(dev, "linux,extcon-name", &name) == 0)
1960 return extcon_get_extcon_dev(name);
1961
1962 /*
1963 * Check explicitly if "usb-role-switch" is used since
1964 * extcon_find_edev_by_node() can not be used to check the absence of
1965 * an extcon device. In the absence of an device it will always return
1966 * EPROBE_DEFER.
1967 */
1968 if (IS_ENABLED(CONFIG_USB_ROLE_SWITCH) &&
1969 device_property_read_bool(dev, "usb-role-switch"))
1970 return NULL;
1971
1972 /*
1973 * Try to get an extcon device from the USB PHY controller's "port"
1974 * node. Check if it has the "port" node first, to avoid printing the
1975 * error message from underlying code, as it's a valid case: extcon
1976 * device (and "port" node) may be missing in case of "usb-role-switch"
1977 * or OTG mode.
1978 */
1979 np_phy = of_parse_phandle(dev->of_node, "phys", 0);
1980 if (of_graph_is_present(np_phy)) {
1981 struct device_node *np_conn;
1982
1983 np_conn = of_graph_get_remote_node(np_phy, -1, -1);
1984 if (np_conn)
1985 edev = extcon_find_edev_by_node(np_conn);
1986 of_node_put(np_conn);
1987 }
1988 of_node_put(np_phy);
1989
1990 return edev;
1991}
1992
1993static int dwc3_get_clocks(struct dwc3 *dwc)
1994{
1995 struct device *dev = dwc->dev;
1996
1997 if (!dev->of_node)
1998 return 0;
1999
2000 /*
2001 * Clocks are optional, but new DT platforms should support all clocks
2002 * as required by the DT-binding.
2003 * Some devices have different clock names in legacy device trees,
2004 * check for them to retain backwards compatibility.
2005 */
2006 dwc->bus_clk = devm_clk_get_optional(dev, "bus_early");
2007 if (IS_ERR(dwc->bus_clk)) {
2008 return dev_err_probe(dev, PTR_ERR(dwc->bus_clk),
2009 "could not get bus clock\n");
2010 }
2011
2012 if (dwc->bus_clk == NULL) {
2013 dwc->bus_clk = devm_clk_get_optional(dev, "bus_clk");
2014 if (IS_ERR(dwc->bus_clk)) {
2015 return dev_err_probe(dev, PTR_ERR(dwc->bus_clk),
2016 "could not get bus clock\n");
2017 }
2018 }
2019
2020 dwc->ref_clk = devm_clk_get_optional(dev, "ref");
2021 if (IS_ERR(dwc->ref_clk)) {
2022 return dev_err_probe(dev, PTR_ERR(dwc->ref_clk),
2023 "could not get ref clock\n");
2024 }
2025
2026 if (dwc->ref_clk == NULL) {
2027 dwc->ref_clk = devm_clk_get_optional(dev, "ref_clk");
2028 if (IS_ERR(dwc->ref_clk)) {
2029 return dev_err_probe(dev, PTR_ERR(dwc->ref_clk),
2030 "could not get ref clock\n");
2031 }
2032 }
2033
2034 dwc->susp_clk = devm_clk_get_optional(dev, "suspend");
2035 if (IS_ERR(dwc->susp_clk)) {
2036 return dev_err_probe(dev, PTR_ERR(dwc->susp_clk),
2037 "could not get suspend clock\n");
2038 }
2039
2040 if (dwc->susp_clk == NULL) {
2041 dwc->susp_clk = devm_clk_get_optional(dev, "suspend_clk");
2042 if (IS_ERR(dwc->susp_clk)) {
2043 return dev_err_probe(dev, PTR_ERR(dwc->susp_clk),
2044 "could not get suspend clock\n");
2045 }
2046 }
2047
2048 /* specific to Rockchip RK3588 */
2049 dwc->utmi_clk = devm_clk_get_optional(dev, "utmi");
2050 if (IS_ERR(dwc->utmi_clk)) {
2051 return dev_err_probe(dev, PTR_ERR(dwc->utmi_clk),
2052 "could not get utmi clock\n");
2053 }
2054
2055 /* specific to Rockchip RK3588 */
2056 dwc->pipe_clk = devm_clk_get_optional(dev, "pipe");
2057 if (IS_ERR(dwc->pipe_clk)) {
2058 return dev_err_probe(dev, PTR_ERR(dwc->pipe_clk),
2059 "could not get pipe clock\n");
2060 }
2061
2062 return 0;
2063}
2064
2065static int dwc3_get_num_ports(struct dwc3 *dwc)
2066{
2067 void __iomem *base;
2068 u8 major_revision;
2069 u32 offset;
2070 u32 val;
2071
2072 /*
2073 * Remap xHCI address space to access XHCI ext cap regs since it is
2074 * needed to get information on number of ports present.
2075 */
2076 base = ioremap(dwc->xhci_resources[0].start,
2077 resource_size(&dwc->xhci_resources[0]));
2078 if (!base)
2079 return -ENOMEM;
2080
2081 offset = 0;
2082 do {
2083 offset = xhci_find_next_ext_cap(base, offset,
2084 XHCI_EXT_CAPS_PROTOCOL);
2085 if (!offset)
2086 break;
2087
2088 val = readl(base + offset);
2089 major_revision = XHCI_EXT_PORT_MAJOR(val);
2090
2091 val = readl(base + offset + 0x08);
2092 if (major_revision == 0x03) {
2093 dwc->num_usb3_ports += XHCI_EXT_PORT_COUNT(val);
2094 } else if (major_revision <= 0x02) {
2095 dwc->num_usb2_ports += XHCI_EXT_PORT_COUNT(val);
2096 } else {
2097 dev_warn(dwc->dev, "unrecognized port major revision %d\n",
2098 major_revision);
2099 }
2100 } while (1);
2101
2102 dev_dbg(dwc->dev, "hs-ports: %u ss-ports: %u\n",
2103 dwc->num_usb2_ports, dwc->num_usb3_ports);
2104
2105 iounmap(base);
2106
2107 if (dwc->num_usb2_ports > DWC3_USB2_MAX_PORTS ||
2108 dwc->num_usb3_ports > DWC3_USB3_MAX_PORTS)
2109 return -EINVAL;
2110
2111 return 0;
2112}
2113
2114static struct power_supply *dwc3_get_usb_power_supply(struct dwc3 *dwc)
2115{
2116 struct power_supply *usb_psy;
2117 const char *usb_psy_name;
2118 int ret;
2119
2120 ret = device_property_read_string(dwc->dev, "usb-psy-name", &usb_psy_name);
2121 if (ret < 0)
2122 return NULL;
2123
2124 usb_psy = power_supply_get_by_name(usb_psy_name);
2125 if (!usb_psy)
2126 return ERR_PTR(-EPROBE_DEFER);
2127
2128 return usb_psy;
2129}
2130
2131static int dwc3_probe(struct platform_device *pdev)
2132{
2133 struct device *dev = &pdev->dev;
2134 struct resource *res, dwc_res;
2135 unsigned int hw_mode;
2136 void __iomem *regs;
2137 struct dwc3 *dwc;
2138 int ret;
2139
2140 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
2141 if (!dwc)
2142 return -ENOMEM;
2143
2144 dwc->dev = dev;
2145
2146 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2147 if (!res) {
2148 dev_err(dev, "missing memory resource\n");
2149 return -ENODEV;
2150 }
2151
2152 dwc->xhci_resources[0].start = res->start;
2153 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
2154 DWC3_XHCI_REGS_END;
2155 dwc->xhci_resources[0].flags = res->flags;
2156 dwc->xhci_resources[0].name = res->name;
2157
2158 /*
2159 * Request memory region but exclude xHCI regs,
2160 * since it will be requested by the xhci-plat driver.
2161 */
2162 dwc_res = *res;
2163 dwc_res.start += DWC3_GLOBALS_REGS_START;
2164
2165 if (dev->of_node) {
2166 struct device_node *parent = of_get_parent(dev->of_node);
2167
2168 if (of_device_is_compatible(parent, "realtek,rtd-dwc3")) {
2169 dwc_res.start -= DWC3_GLOBALS_REGS_START;
2170 dwc_res.start += DWC3_RTK_RTD_GLOBALS_REGS_START;
2171 }
2172
2173 of_node_put(parent);
2174 }
2175
2176 regs = devm_ioremap_resource(dev, &dwc_res);
2177 if (IS_ERR(regs))
2178 return PTR_ERR(regs);
2179
2180 dwc->regs = regs;
2181 dwc->regs_size = resource_size(&dwc_res);
2182
2183 dwc3_get_properties(dwc);
2184
2185 dwc3_get_software_properties(dwc);
2186
2187 dwc->usb_psy = dwc3_get_usb_power_supply(dwc);
2188 if (IS_ERR(dwc->usb_psy))
2189 return dev_err_probe(dev, PTR_ERR(dwc->usb_psy), "couldn't get usb power supply\n");
2190
2191 dwc->reset = devm_reset_control_array_get_optional_shared(dev);
2192 if (IS_ERR(dwc->reset)) {
2193 ret = PTR_ERR(dwc->reset);
2194 goto err_put_psy;
2195 }
2196
2197 ret = dwc3_get_clocks(dwc);
2198 if (ret)
2199 goto err_put_psy;
2200
2201 ret = reset_control_deassert(dwc->reset);
2202 if (ret)
2203 goto err_put_psy;
2204
2205 ret = dwc3_clk_enable(dwc);
2206 if (ret)
2207 goto err_assert_reset;
2208
2209 if (!dwc3_core_is_valid(dwc)) {
2210 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
2211 ret = -ENODEV;
2212 goto err_disable_clks;
2213 }
2214
2215 platform_set_drvdata(pdev, dwc);
2216 dwc3_cache_hwparams(dwc);
2217
2218 if (!dwc->sysdev_is_parent &&
2219 DWC3_GHWPARAMS0_AWIDTH(dwc->hwparams.hwparams0) == 64) {
2220 ret = dma_set_mask_and_coherent(dwc->sysdev, DMA_BIT_MASK(64));
2221 if (ret)
2222 goto err_disable_clks;
2223 }
2224
2225 /*
2226 * Currently only DWC3 controllers that are host-only capable
2227 * can have more than one port.
2228 */
2229 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
2230 if (hw_mode == DWC3_GHWPARAMS0_MODE_HOST) {
2231 ret = dwc3_get_num_ports(dwc);
2232 if (ret)
2233 goto err_disable_clks;
2234 } else {
2235 dwc->num_usb2_ports = 1;
2236 dwc->num_usb3_ports = 1;
2237 }
2238
2239 spin_lock_init(&dwc->lock);
2240 mutex_init(&dwc->mutex);
2241
2242 pm_runtime_get_noresume(dev);
2243 pm_runtime_set_active(dev);
2244 pm_runtime_use_autosuspend(dev);
2245 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
2246 pm_runtime_enable(dev);
2247
2248 pm_runtime_forbid(dev);
2249
2250 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
2251 if (ret) {
2252 dev_err(dwc->dev, "failed to allocate event buffers\n");
2253 ret = -ENOMEM;
2254 goto err_allow_rpm;
2255 }
2256
2257 dwc->edev = dwc3_get_extcon(dwc);
2258 if (IS_ERR(dwc->edev)) {
2259 ret = dev_err_probe(dwc->dev, PTR_ERR(dwc->edev), "failed to get extcon\n");
2260 goto err_free_event_buffers;
2261 }
2262
2263 ret = dwc3_get_dr_mode(dwc);
2264 if (ret)
2265 goto err_free_event_buffers;
2266
2267 ret = dwc3_core_init(dwc);
2268 if (ret) {
2269 dev_err_probe(dev, ret, "failed to initialize core\n");
2270 goto err_free_event_buffers;
2271 }
2272
2273 dwc3_check_params(dwc);
2274 dwc3_debugfs_init(dwc);
2275
2276 ret = dwc3_core_init_mode(dwc);
2277 if (ret)
2278 goto err_exit_debugfs;
2279
2280 pm_runtime_put(dev);
2281
2282 dma_set_max_seg_size(dev, UINT_MAX);
2283
2284 return 0;
2285
2286err_exit_debugfs:
2287 dwc3_debugfs_exit(dwc);
2288 dwc3_event_buffers_cleanup(dwc);
2289 dwc3_phy_power_off(dwc);
2290 dwc3_phy_exit(dwc);
2291 dwc3_ulpi_exit(dwc);
2292err_free_event_buffers:
2293 dwc3_free_event_buffers(dwc);
2294err_allow_rpm:
2295 pm_runtime_allow(dev);
2296 pm_runtime_disable(dev);
2297 pm_runtime_dont_use_autosuspend(dev);
2298 pm_runtime_set_suspended(dev);
2299 pm_runtime_put_noidle(dev);
2300err_disable_clks:
2301 dwc3_clk_disable(dwc);
2302err_assert_reset:
2303 reset_control_assert(dwc->reset);
2304err_put_psy:
2305 if (dwc->usb_psy)
2306 power_supply_put(dwc->usb_psy);
2307
2308 return ret;
2309}
2310
2311static void dwc3_remove(struct platform_device *pdev)
2312{
2313 struct dwc3 *dwc = platform_get_drvdata(pdev);
2314
2315 pm_runtime_get_sync(&pdev->dev);
2316
2317 dwc3_core_exit_mode(dwc);
2318 dwc3_debugfs_exit(dwc);
2319
2320 dwc3_core_exit(dwc);
2321 dwc3_ulpi_exit(dwc);
2322
2323 pm_runtime_allow(&pdev->dev);
2324 pm_runtime_disable(&pdev->dev);
2325 pm_runtime_dont_use_autosuspend(&pdev->dev);
2326 pm_runtime_put_noidle(&pdev->dev);
2327 /*
2328 * HACK: Clear the driver data, which is currently accessed by parent
2329 * glue drivers, before allowing the parent to suspend.
2330 */
2331 platform_set_drvdata(pdev, NULL);
2332 pm_runtime_set_suspended(&pdev->dev);
2333
2334 dwc3_free_event_buffers(dwc);
2335
2336 if (dwc->usb_psy)
2337 power_supply_put(dwc->usb_psy);
2338}
2339
2340#ifdef CONFIG_PM
2341static int dwc3_core_init_for_resume(struct dwc3 *dwc)
2342{
2343 int ret;
2344
2345 ret = reset_control_deassert(dwc->reset);
2346 if (ret)
2347 return ret;
2348
2349 ret = dwc3_clk_enable(dwc);
2350 if (ret)
2351 goto assert_reset;
2352
2353 ret = dwc3_core_init(dwc);
2354 if (ret)
2355 goto disable_clks;
2356
2357 return 0;
2358
2359disable_clks:
2360 dwc3_clk_disable(dwc);
2361assert_reset:
2362 reset_control_assert(dwc->reset);
2363
2364 return ret;
2365}
2366
2367static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
2368{
2369 u32 reg;
2370 int i;
2371
2372 if (!pm_runtime_suspended(dwc->dev) && !PMSG_IS_AUTO(msg)) {
2373 dwc->susphy_state = (dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)) &
2374 DWC3_GUSB2PHYCFG_SUSPHY) ||
2375 (dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)) &
2376 DWC3_GUSB3PIPECTL_SUSPHY);
2377 /*
2378 * TI AM62 platform requires SUSPHY to be
2379 * enabled for system suspend to work.
2380 */
2381 if (!dwc->susphy_state)
2382 dwc3_enable_susphy(dwc, true);
2383 }
2384
2385 switch (dwc->current_dr_role) {
2386 case DWC3_GCTL_PRTCAP_DEVICE:
2387 if (pm_runtime_suspended(dwc->dev))
2388 break;
2389 dwc3_gadget_suspend(dwc);
2390 synchronize_irq(dwc->irq_gadget);
2391 dwc3_core_exit(dwc);
2392 break;
2393 case DWC3_GCTL_PRTCAP_HOST:
2394 if (!PMSG_IS_AUTO(msg) && !device_may_wakeup(dwc->dev)) {
2395 dwc3_core_exit(dwc);
2396 break;
2397 }
2398
2399 /* Let controller to suspend HSPHY before PHY driver suspends */
2400 if (dwc->dis_u2_susphy_quirk ||
2401 dwc->dis_enblslpm_quirk) {
2402 for (i = 0; i < dwc->num_usb2_ports; i++) {
2403 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i));
2404 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM |
2405 DWC3_GUSB2PHYCFG_SUSPHY;
2406 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg);
2407 }
2408
2409 /* Give some time for USB2 PHY to suspend */
2410 usleep_range(5000, 6000);
2411 }
2412
2413 for (i = 0; i < dwc->num_usb2_ports; i++)
2414 phy_pm_runtime_put_sync(dwc->usb2_generic_phy[i]);
2415 for (i = 0; i < dwc->num_usb3_ports; i++)
2416 phy_pm_runtime_put_sync(dwc->usb3_generic_phy[i]);
2417 break;
2418 case DWC3_GCTL_PRTCAP_OTG:
2419 /* do nothing during runtime_suspend */
2420 if (PMSG_IS_AUTO(msg))
2421 break;
2422
2423 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
2424 dwc3_gadget_suspend(dwc);
2425 synchronize_irq(dwc->irq_gadget);
2426 }
2427
2428 dwc3_otg_exit(dwc);
2429 dwc3_core_exit(dwc);
2430 break;
2431 default:
2432 /* do nothing */
2433 break;
2434 }
2435
2436 return 0;
2437}
2438
2439static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
2440{
2441 int ret;
2442 u32 reg;
2443 int i;
2444
2445 switch (dwc->current_dr_role) {
2446 case DWC3_GCTL_PRTCAP_DEVICE:
2447 ret = dwc3_core_init_for_resume(dwc);
2448 if (ret)
2449 return ret;
2450
2451 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE, true);
2452 dwc3_gadget_resume(dwc);
2453 break;
2454 case DWC3_GCTL_PRTCAP_HOST:
2455 if (!PMSG_IS_AUTO(msg) && !device_may_wakeup(dwc->dev)) {
2456 ret = dwc3_core_init_for_resume(dwc);
2457 if (ret)
2458 return ret;
2459 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST, true);
2460 break;
2461 }
2462 /* Restore GUSB2PHYCFG bits that were modified in suspend */
2463 for (i = 0; i < dwc->num_usb2_ports; i++) {
2464 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i));
2465 if (dwc->dis_u2_susphy_quirk)
2466 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
2467
2468 if (dwc->dis_enblslpm_quirk)
2469 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
2470
2471 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg);
2472 }
2473
2474 for (i = 0; i < dwc->num_usb2_ports; i++)
2475 phy_pm_runtime_get_sync(dwc->usb2_generic_phy[i]);
2476 for (i = 0; i < dwc->num_usb3_ports; i++)
2477 phy_pm_runtime_get_sync(dwc->usb3_generic_phy[i]);
2478 break;
2479 case DWC3_GCTL_PRTCAP_OTG:
2480 /* nothing to do on runtime_resume */
2481 if (PMSG_IS_AUTO(msg))
2482 break;
2483
2484 ret = dwc3_core_init_for_resume(dwc);
2485 if (ret)
2486 return ret;
2487
2488 dwc3_set_prtcap(dwc, dwc->current_dr_role, true);
2489
2490 dwc3_otg_init(dwc);
2491 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
2492 dwc3_otg_host_init(dwc);
2493 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
2494 dwc3_gadget_resume(dwc);
2495 }
2496
2497 break;
2498 default:
2499 /* do nothing */
2500 break;
2501 }
2502
2503 if (!PMSG_IS_AUTO(msg)) {
2504 /* restore SUSPHY state to that before system suspend. */
2505 dwc3_enable_susphy(dwc, dwc->susphy_state);
2506 }
2507
2508 return 0;
2509}
2510
2511static int dwc3_runtime_checks(struct dwc3 *dwc)
2512{
2513 switch (dwc->current_dr_role) {
2514 case DWC3_GCTL_PRTCAP_DEVICE:
2515 if (dwc->connected)
2516 return -EBUSY;
2517 break;
2518 case DWC3_GCTL_PRTCAP_HOST:
2519 default:
2520 /* do nothing */
2521 break;
2522 }
2523
2524 return 0;
2525}
2526
2527static int dwc3_runtime_suspend(struct device *dev)
2528{
2529 struct dwc3 *dwc = dev_get_drvdata(dev);
2530 int ret;
2531
2532 if (dwc3_runtime_checks(dwc))
2533 return -EBUSY;
2534
2535 ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
2536 if (ret)
2537 return ret;
2538
2539 return 0;
2540}
2541
2542static int dwc3_runtime_resume(struct device *dev)
2543{
2544 struct dwc3 *dwc = dev_get_drvdata(dev);
2545 int ret;
2546
2547 ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
2548 if (ret)
2549 return ret;
2550
2551 switch (dwc->current_dr_role) {
2552 case DWC3_GCTL_PRTCAP_DEVICE:
2553 if (dwc->pending_events) {
2554 pm_runtime_put(dwc->dev);
2555 dwc->pending_events = false;
2556 enable_irq(dwc->irq_gadget);
2557 }
2558 break;
2559 case DWC3_GCTL_PRTCAP_HOST:
2560 default:
2561 /* do nothing */
2562 break;
2563 }
2564
2565 pm_runtime_mark_last_busy(dev);
2566
2567 return 0;
2568}
2569
2570static int dwc3_runtime_idle(struct device *dev)
2571{
2572 struct dwc3 *dwc = dev_get_drvdata(dev);
2573
2574 switch (dwc->current_dr_role) {
2575 case DWC3_GCTL_PRTCAP_DEVICE:
2576 if (dwc3_runtime_checks(dwc))
2577 return -EBUSY;
2578 break;
2579 case DWC3_GCTL_PRTCAP_HOST:
2580 default:
2581 /* do nothing */
2582 break;
2583 }
2584
2585 pm_runtime_mark_last_busy(dev);
2586 pm_runtime_autosuspend(dev);
2587
2588 return 0;
2589}
2590#endif /* CONFIG_PM */
2591
2592#ifdef CONFIG_PM_SLEEP
2593static int dwc3_suspend(struct device *dev)
2594{
2595 struct dwc3 *dwc = dev_get_drvdata(dev);
2596 int ret;
2597
2598 ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
2599 if (ret)
2600 return ret;
2601
2602 pinctrl_pm_select_sleep_state(dev);
2603
2604 return 0;
2605}
2606
2607static int dwc3_resume(struct device *dev)
2608{
2609 struct dwc3 *dwc = dev_get_drvdata(dev);
2610 int ret = 0;
2611
2612 pinctrl_pm_select_default_state(dev);
2613
2614 pm_runtime_disable(dev);
2615 ret = pm_runtime_set_active(dev);
2616 if (ret)
2617 goto out;
2618
2619 ret = dwc3_resume_common(dwc, PMSG_RESUME);
2620 if (ret)
2621 pm_runtime_set_suspended(dev);
2622
2623out:
2624 pm_runtime_enable(dev);
2625
2626 return ret;
2627}
2628
2629static void dwc3_complete(struct device *dev)
2630{
2631 struct dwc3 *dwc = dev_get_drvdata(dev);
2632 u32 reg;
2633
2634 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST &&
2635 dwc->dis_split_quirk) {
2636 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
2637 reg |= DWC3_GUCTL3_SPLITDISABLE;
2638 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
2639 }
2640}
2641#else
2642#define dwc3_complete NULL
2643#endif /* CONFIG_PM_SLEEP */
2644
2645static const struct dev_pm_ops dwc3_dev_pm_ops = {
2646 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
2647 .complete = dwc3_complete,
2648
2649 /*
2650 * Runtime suspend halts the controller on disconnection. It relies on
2651 * platforms with custom connection notification to start the controller
2652 * again.
2653 */
2654 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
2655 dwc3_runtime_idle)
2656};
2657
2658#ifdef CONFIG_OF
2659static const struct of_device_id of_dwc3_match[] = {
2660 {
2661 .compatible = "snps,dwc3"
2662 },
2663 {
2664 .compatible = "synopsys,dwc3"
2665 },
2666 { },
2667};
2668MODULE_DEVICE_TABLE(of, of_dwc3_match);
2669#endif
2670
2671#ifdef CONFIG_ACPI
2672
2673#define ACPI_ID_INTEL_BSW "808622B7"
2674
2675static const struct acpi_device_id dwc3_acpi_match[] = {
2676 { ACPI_ID_INTEL_BSW, 0 },
2677 { },
2678};
2679MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
2680#endif
2681
2682static struct platform_driver dwc3_driver = {
2683 .probe = dwc3_probe,
2684 .remove = dwc3_remove,
2685 .driver = {
2686 .name = "dwc3",
2687 .of_match_table = of_match_ptr(of_dwc3_match),
2688 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
2689 .pm = &dwc3_dev_pm_ops,
2690 },
2691};
2692
2693module_platform_driver(dwc3_driver);
2694
2695MODULE_ALIAS("platform:dwc3");
2696MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
2697MODULE_LICENSE("GPL v2");
2698MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");