1// SPDX-License-Identifier: GPL-2.0
  2// LPC variant I/O for Microchip EC
  3//
  4// Copyright (C) 2016 Google, Inc
  5
  6#include <linux/delay.h>
  7#include <linux/io.h>
  8#include <linux/mutex.h>
  9#include <linux/types.h>
 10
 11#include "cros_ec_lpc_mec.h"
 12
 13#define ACPI_LOCK_DELAY_MS 500
 14
 15/*
 16 * This mutex must be held while accessing the EMI unit. We can't rely on the
 17 * EC mutex because memmap data may be accessed without it being held.
 18 */
 19static DEFINE_MUTEX(io_mutex);
 20/*
 21 * An alternative mutex to be used when the ACPI AML code may also
 22 * access memmap data.  When set, this mutex is used in preference to
 23 * io_mutex.
 24 */
 25static acpi_handle aml_mutex;
 26
 27static u16 mec_emi_base, mec_emi_end;
 28
 29/**
 30 * cros_ec_lpc_mec_lock() - Acquire mutex for EMI
 31 *
 32 * @return: Negative error code, or zero for success
 33 */
 34static int cros_ec_lpc_mec_lock(void)
 35{
 36	bool success;
 37
 38	if (!aml_mutex) {
 39		mutex_lock(&io_mutex);
 40		return 0;
 41	}
 42
 43	success = ACPI_SUCCESS(acpi_acquire_mutex(aml_mutex,
 44						  NULL, ACPI_LOCK_DELAY_MS));
 45	if (!success)
 46		return -EBUSY;
 47
 48	return 0;
 49}
 50
 51/**
 52 * cros_ec_lpc_mec_unlock() - Release mutex for EMI
 53 *
 54 * @return: Negative error code, or zero for success
 55 */
 56static int cros_ec_lpc_mec_unlock(void)
 57{
 58	bool success;
 59
 60	if (!aml_mutex) {
 61		mutex_unlock(&io_mutex);
 62		return 0;
 63	}
 64
 65	success = ACPI_SUCCESS(acpi_release_mutex(aml_mutex, NULL));
 66	if (!success)
 67		return -EBUSY;
 68
 69	return 0;
 70}
 71
 72/**
 73 * cros_ec_lpc_mec_emi_write_address() - Initialize EMI at a given address.
 74 *
 75 * @addr: Starting read / write address
 76 * @access_type: Type of access, typically 32-bit auto-increment
 77 */
 78static void cros_ec_lpc_mec_emi_write_address(u16 addr,
 79			enum cros_ec_lpc_mec_emi_access_mode access_type)
 80{
 81	outb((addr & 0xfc) | access_type, MEC_EMI_EC_ADDRESS_B0(mec_emi_base));
 82	outb((addr >> 8) & 0x7f, MEC_EMI_EC_ADDRESS_B1(mec_emi_base));
 83}
 84
 85/**
 86 * cros_ec_lpc_mec_in_range() - Determine if addresses are in MEC EMI range.
 87 *
 88 * @offset: Address offset
 89 * @length: Number of bytes to check
 90 *
 91 * Return: 1 if in range, 0 if not, and -EINVAL on failure
 92 *         such as the mec range not being initialized
 93 */
 94int cros_ec_lpc_mec_in_range(unsigned int offset, unsigned int length)
 95{
 96	if (WARN_ON(mec_emi_base == 0 || mec_emi_end == 0))
 97		return -EINVAL;
 98
 99	if (offset >= mec_emi_base && offset < mec_emi_end) {
100		if (WARN_ON(offset + length - 1 >= mec_emi_end))
101			return -EINVAL;
102		return 1;
103	}
104
105	if (WARN_ON(offset + length > mec_emi_base && offset < mec_emi_end))
106		return -EINVAL;
107
108	return 0;
109}
110
111/**
112 * cros_ec_lpc_io_bytes_mec() - Read / write bytes to MEC EMI port.
113 *
114 * @io_type: MEC_IO_READ or MEC_IO_WRITE, depending on request
115 * @offset:  Base read / write address
116 * @length:  Number of bytes to read / write
117 * @buf:     Destination / source buffer
118 *
119 * @return:  A negative error code on error, or 8-bit checksum of all
120 *           bytes read / written
121 */
122int cros_ec_lpc_io_bytes_mec(enum cros_ec_lpc_mec_io_type io_type,
123			     unsigned int offset, unsigned int length,
124			     u8 *buf)
125{
126	int i = 0;
127	int io_addr;
128	u8 sum = 0;
129	enum cros_ec_lpc_mec_emi_access_mode access, new_access;
130	int ret;
131
132	if (length == 0)
133		return 0;
134
135	/* Return checksum of 0 if window is not initialized */
136	WARN_ON(mec_emi_base == 0 || mec_emi_end == 0);
137	if (mec_emi_base == 0 || mec_emi_end == 0)
138		return 0;
139
140	/*
141	 * Long access cannot be used on misaligned data since reading B0 loads
142	 * the data register and writing B3 flushes.
143	 */
144	if (offset & 0x3 || length < 4)
145		access = ACCESS_TYPE_BYTE;
146	else
147		access = ACCESS_TYPE_LONG_AUTO_INCREMENT;
148
149	ret = cros_ec_lpc_mec_lock();
150	if (ret)
151		return ret;
152
153	/* Initialize I/O at desired address */
154	cros_ec_lpc_mec_emi_write_address(offset, access);
155
156	/* Skip bytes in case of misaligned offset */
157	io_addr = MEC_EMI_EC_DATA_B0(mec_emi_base) + (offset & 0x3);
158	while (i < length) {
159		while (io_addr <= MEC_EMI_EC_DATA_B3(mec_emi_base)) {
160			if (io_type == MEC_IO_READ)
161				buf[i] = inb(io_addr++);
162			else
163				outb(buf[i], io_addr++);
164
165			sum += buf[i++];
166			offset++;
167
168			/* Extra bounds check in case of misaligned length */
169			if (i == length)
170				goto done;
171		}
172
173		/*
174		 * Use long auto-increment access except for misaligned write,
175		 * since writing B3 triggers the flush.
176		 */
177		if (length - i < 4 && io_type == MEC_IO_WRITE)
178			new_access = ACCESS_TYPE_BYTE;
179		else
180			new_access = ACCESS_TYPE_LONG_AUTO_INCREMENT;
181
182		if (new_access != access ||
183		    access != ACCESS_TYPE_LONG_AUTO_INCREMENT) {
184			access = new_access;
185			cros_ec_lpc_mec_emi_write_address(offset, access);
186		}
187
188		/* Access [B0, B3] on each loop pass */
189		io_addr = MEC_EMI_EC_DATA_B0(mec_emi_base);
190	}
191
192done:
193	ret = cros_ec_lpc_mec_unlock();
194	if (ret)
195		return ret;
196
197	return sum;
198}
199EXPORT_SYMBOL(cros_ec_lpc_io_bytes_mec);
200
201void cros_ec_lpc_mec_init(unsigned int base, unsigned int end)
202{
203	mec_emi_base = base;
204	mec_emi_end = end;
205}
206EXPORT_SYMBOL(cros_ec_lpc_mec_init);
207
208int cros_ec_lpc_mec_acpi_mutex(struct acpi_device *adev, const char *pathname)
209{
210	int status;
211
212	if (!adev)
213		return -ENOENT;
214
215	status = acpi_get_handle(adev->handle, pathname, &aml_mutex);
216	if (ACPI_FAILURE(status))
217		return -ENOENT;
218
219	return 0;
220}
221EXPORT_SYMBOL(cros_ec_lpc_mec_acpi_mutex);