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1/*
2 * Copyright (C) STMicroelectronics SA 2014
3 * Authors: Benjamin Gaignard <benjamin.gaignard@st.com>
4 * Fabien Dessenne <fabien.dessenne@st.com>
5 * for STMicroelectronics.
6 * License terms: GNU General Public License (GPL), version 2
7 */
8
9#include <drm/drm_atomic.h>
10#include <drm/drm_fb_cma_helper.h>
11#include <drm/drm_gem_cma_helper.h>
12
13#include "sti_compositor.h"
14#include "sti_gdp.h"
15#include "sti_plane.h"
16#include "sti_vtg.h"
17
18#define ALPHASWITCH BIT(6)
19#define ENA_COLOR_FILL BIT(8)
20#define BIGNOTLITTLE BIT(23)
21#define WAIT_NEXT_VSYNC BIT(31)
22
23/* GDP color formats */
24#define GDP_RGB565 0x00
25#define GDP_RGB888 0x01
26#define GDP_RGB888_32 0x02
27#define GDP_XBGR8888 (GDP_RGB888_32 | BIGNOTLITTLE | ALPHASWITCH)
28#define GDP_ARGB8565 0x04
29#define GDP_ARGB8888 0x05
30#define GDP_ABGR8888 (GDP_ARGB8888 | BIGNOTLITTLE | ALPHASWITCH)
31#define GDP_ARGB1555 0x06
32#define GDP_ARGB4444 0x07
33
34#define GDP2STR(fmt) { GDP_ ## fmt, #fmt }
35
36static struct gdp_format_to_str {
37 int format;
38 char name[20];
39} gdp_format_to_str[] = {
40 GDP2STR(RGB565),
41 GDP2STR(RGB888),
42 GDP2STR(RGB888_32),
43 GDP2STR(XBGR8888),
44 GDP2STR(ARGB8565),
45 GDP2STR(ARGB8888),
46 GDP2STR(ABGR8888),
47 GDP2STR(ARGB1555),
48 GDP2STR(ARGB4444)
49 };
50
51#define GAM_GDP_CTL_OFFSET 0x00
52#define GAM_GDP_AGC_OFFSET 0x04
53#define GAM_GDP_VPO_OFFSET 0x0C
54#define GAM_GDP_VPS_OFFSET 0x10
55#define GAM_GDP_PML_OFFSET 0x14
56#define GAM_GDP_PMP_OFFSET 0x18
57#define GAM_GDP_SIZE_OFFSET 0x1C
58#define GAM_GDP_NVN_OFFSET 0x24
59#define GAM_GDP_KEY1_OFFSET 0x28
60#define GAM_GDP_KEY2_OFFSET 0x2C
61#define GAM_GDP_PPT_OFFSET 0x34
62#define GAM_GDP_CML_OFFSET 0x3C
63#define GAM_GDP_MST_OFFSET 0x68
64
65#define GAM_GDP_ALPHARANGE_255 BIT(5)
66#define GAM_GDP_AGC_FULL_RANGE 0x00808080
67#define GAM_GDP_PPT_IGNORE (BIT(1) | BIT(0))
68#define GAM_GDP_SIZE_MAX 0x7FF
69
70#define GDP_NODE_NB_BANK 2
71#define GDP_NODE_PER_FIELD 2
72
73struct sti_gdp_node {
74 u32 gam_gdp_ctl;
75 u32 gam_gdp_agc;
76 u32 reserved1;
77 u32 gam_gdp_vpo;
78 u32 gam_gdp_vps;
79 u32 gam_gdp_pml;
80 u32 gam_gdp_pmp;
81 u32 gam_gdp_size;
82 u32 reserved2;
83 u32 gam_gdp_nvn;
84 u32 gam_gdp_key1;
85 u32 gam_gdp_key2;
86 u32 reserved3;
87 u32 gam_gdp_ppt;
88 u32 reserved4;
89 u32 gam_gdp_cml;
90};
91
92struct sti_gdp_node_list {
93 struct sti_gdp_node *top_field;
94 dma_addr_t top_field_paddr;
95 struct sti_gdp_node *btm_field;
96 dma_addr_t btm_field_paddr;
97};
98
99/**
100 * STI GDP structure
101 *
102 * @sti_plane: sti_plane structure
103 * @dev: driver device
104 * @regs: gdp registers
105 * @clk_pix: pixel clock for the current gdp
106 * @clk_main_parent: gdp parent clock if main path used
107 * @clk_aux_parent: gdp parent clock if aux path used
108 * @vtg_field_nb: callback for VTG FIELD (top or bottom) notification
109 * @is_curr_top: true if the current node processed is the top field
110 * @node_list: array of node list
111 * @vtg: registered vtg
112 */
113struct sti_gdp {
114 struct sti_plane plane;
115 struct device *dev;
116 void __iomem *regs;
117 struct clk *clk_pix;
118 struct clk *clk_main_parent;
119 struct clk *clk_aux_parent;
120 struct notifier_block vtg_field_nb;
121 bool is_curr_top;
122 struct sti_gdp_node_list node_list[GDP_NODE_NB_BANK];
123 struct sti_vtg *vtg;
124};
125
126#define to_sti_gdp(x) container_of(x, struct sti_gdp, plane)
127
128static const uint32_t gdp_supported_formats[] = {
129 DRM_FORMAT_XRGB8888,
130 DRM_FORMAT_XBGR8888,
131 DRM_FORMAT_ARGB8888,
132 DRM_FORMAT_ABGR8888,
133 DRM_FORMAT_ARGB4444,
134 DRM_FORMAT_ARGB1555,
135 DRM_FORMAT_RGB565,
136 DRM_FORMAT_RGB888,
137};
138
139#define DBGFS_DUMP(reg) seq_printf(s, "\n %-25s 0x%08X", #reg, \
140 readl(gdp->regs + reg ## _OFFSET))
141
142static void gdp_dbg_ctl(struct seq_file *s, int val)
143{
144 int i;
145
146 seq_puts(s, "\tColor:");
147 for (i = 0; i < ARRAY_SIZE(gdp_format_to_str); i++) {
148 if (gdp_format_to_str[i].format == (val & 0x1F)) {
149 seq_printf(s, gdp_format_to_str[i].name);
150 break;
151 }
152 }
153 if (i == ARRAY_SIZE(gdp_format_to_str))
154 seq_puts(s, "<UNKNOWN>");
155
156 seq_printf(s, "\tWaitNextVsync:%d", val & WAIT_NEXT_VSYNC ? 1 : 0);
157}
158
159static void gdp_dbg_vpo(struct seq_file *s, int val)
160{
161 seq_printf(s, "\txdo:%4d\tydo:%4d", val & 0xFFFF, (val >> 16) & 0xFFFF);
162}
163
164static void gdp_dbg_vps(struct seq_file *s, int val)
165{
166 seq_printf(s, "\txds:%4d\tyds:%4d", val & 0xFFFF, (val >> 16) & 0xFFFF);
167}
168
169static void gdp_dbg_size(struct seq_file *s, int val)
170{
171 seq_printf(s, "\t%d x %d", val & 0xFFFF, (val >> 16) & 0xFFFF);
172}
173
174static void gdp_dbg_nvn(struct seq_file *s, struct sti_gdp *gdp, int val)
175{
176 void *base = NULL;
177 unsigned int i;
178
179 for (i = 0; i < GDP_NODE_NB_BANK; i++) {
180 if (gdp->node_list[i].top_field_paddr == val) {
181 base = gdp->node_list[i].top_field;
182 break;
183 }
184 if (gdp->node_list[i].btm_field_paddr == val) {
185 base = gdp->node_list[i].btm_field;
186 break;
187 }
188 }
189
190 if (base)
191 seq_printf(s, "\tVirt @: %p", base);
192}
193
194static void gdp_dbg_ppt(struct seq_file *s, int val)
195{
196 if (val & GAM_GDP_PPT_IGNORE)
197 seq_puts(s, "\tNot displayed on mixer!");
198}
199
200static void gdp_dbg_mst(struct seq_file *s, int val)
201{
202 if (val & 1)
203 seq_puts(s, "\tBUFFER UNDERFLOW!");
204}
205
206static int gdp_dbg_show(struct seq_file *s, void *data)
207{
208 struct drm_info_node *node = s->private;
209 struct sti_gdp *gdp = (struct sti_gdp *)node->info_ent->data;
210 struct drm_device *dev = node->minor->dev;
211 struct drm_plane *drm_plane = &gdp->plane.drm_plane;
212 struct drm_crtc *crtc = drm_plane->crtc;
213 int ret;
214
215 ret = mutex_lock_interruptible(&dev->struct_mutex);
216 if (ret)
217 return ret;
218
219 seq_printf(s, "%s: (vaddr = 0x%p)",
220 sti_plane_to_str(&gdp->plane), gdp->regs);
221
222 DBGFS_DUMP(GAM_GDP_CTL);
223 gdp_dbg_ctl(s, readl(gdp->regs + GAM_GDP_CTL_OFFSET));
224 DBGFS_DUMP(GAM_GDP_AGC);
225 DBGFS_DUMP(GAM_GDP_VPO);
226 gdp_dbg_vpo(s, readl(gdp->regs + GAM_GDP_VPO_OFFSET));
227 DBGFS_DUMP(GAM_GDP_VPS);
228 gdp_dbg_vps(s, readl(gdp->regs + GAM_GDP_VPS_OFFSET));
229 DBGFS_DUMP(GAM_GDP_PML);
230 DBGFS_DUMP(GAM_GDP_PMP);
231 DBGFS_DUMP(GAM_GDP_SIZE);
232 gdp_dbg_size(s, readl(gdp->regs + GAM_GDP_SIZE_OFFSET));
233 DBGFS_DUMP(GAM_GDP_NVN);
234 gdp_dbg_nvn(s, gdp, readl(gdp->regs + GAM_GDP_NVN_OFFSET));
235 DBGFS_DUMP(GAM_GDP_KEY1);
236 DBGFS_DUMP(GAM_GDP_KEY2);
237 DBGFS_DUMP(GAM_GDP_PPT);
238 gdp_dbg_ppt(s, readl(gdp->regs + GAM_GDP_PPT_OFFSET));
239 DBGFS_DUMP(GAM_GDP_CML);
240 DBGFS_DUMP(GAM_GDP_MST);
241 gdp_dbg_mst(s, readl(gdp->regs + GAM_GDP_MST_OFFSET));
242
243 seq_puts(s, "\n\n");
244 if (!crtc)
245 seq_puts(s, " Not connected to any DRM CRTC\n");
246 else
247 seq_printf(s, " Connected to DRM CRTC #%d (%s)\n",
248 crtc->base.id, sti_mixer_to_str(to_sti_mixer(crtc)));
249
250 mutex_unlock(&dev->struct_mutex);
251 return 0;
252}
253
254static void gdp_node_dump_node(struct seq_file *s, struct sti_gdp_node *node)
255{
256 seq_printf(s, "\t@:0x%p", node);
257 seq_printf(s, "\n\tCTL 0x%08X", node->gam_gdp_ctl);
258 gdp_dbg_ctl(s, node->gam_gdp_ctl);
259 seq_printf(s, "\n\tAGC 0x%08X", node->gam_gdp_agc);
260 seq_printf(s, "\n\tVPO 0x%08X", node->gam_gdp_vpo);
261 gdp_dbg_vpo(s, node->gam_gdp_vpo);
262 seq_printf(s, "\n\tVPS 0x%08X", node->gam_gdp_vps);
263 gdp_dbg_vps(s, node->gam_gdp_vps);
264 seq_printf(s, "\n\tPML 0x%08X", node->gam_gdp_pml);
265 seq_printf(s, "\n\tPMP 0x%08X", node->gam_gdp_pmp);
266 seq_printf(s, "\n\tSIZE 0x%08X", node->gam_gdp_size);
267 gdp_dbg_size(s, node->gam_gdp_size);
268 seq_printf(s, "\n\tNVN 0x%08X", node->gam_gdp_nvn);
269 seq_printf(s, "\n\tKEY1 0x%08X", node->gam_gdp_key1);
270 seq_printf(s, "\n\tKEY2 0x%08X", node->gam_gdp_key2);
271 seq_printf(s, "\n\tPPT 0x%08X", node->gam_gdp_ppt);
272 gdp_dbg_ppt(s, node->gam_gdp_ppt);
273 seq_printf(s, "\n\tCML 0x%08X", node->gam_gdp_cml);
274 seq_puts(s, "\n");
275}
276
277static int gdp_node_dbg_show(struct seq_file *s, void *arg)
278{
279 struct drm_info_node *node = s->private;
280 struct sti_gdp *gdp = (struct sti_gdp *)node->info_ent->data;
281 struct drm_device *dev = node->minor->dev;
282 unsigned int b;
283 int ret;
284
285 ret = mutex_lock_interruptible(&dev->struct_mutex);
286 if (ret)
287 return ret;
288
289 for (b = 0; b < GDP_NODE_NB_BANK; b++) {
290 seq_printf(s, "\n%s[%d].top", sti_plane_to_str(&gdp->plane), b);
291 gdp_node_dump_node(s, gdp->node_list[b].top_field);
292 seq_printf(s, "\n%s[%d].btm", sti_plane_to_str(&gdp->plane), b);
293 gdp_node_dump_node(s, gdp->node_list[b].btm_field);
294 }
295
296 mutex_unlock(&dev->struct_mutex);
297 return 0;
298}
299
300static struct drm_info_list gdp0_debugfs_files[] = {
301 { "gdp0", gdp_dbg_show, 0, NULL },
302 { "gdp0_node", gdp_node_dbg_show, 0, NULL },
303};
304
305static struct drm_info_list gdp1_debugfs_files[] = {
306 { "gdp1", gdp_dbg_show, 0, NULL },
307 { "gdp1_node", gdp_node_dbg_show, 0, NULL },
308};
309
310static struct drm_info_list gdp2_debugfs_files[] = {
311 { "gdp2", gdp_dbg_show, 0, NULL },
312 { "gdp2_node", gdp_node_dbg_show, 0, NULL },
313};
314
315static struct drm_info_list gdp3_debugfs_files[] = {
316 { "gdp3", gdp_dbg_show, 0, NULL },
317 { "gdp3_node", gdp_node_dbg_show, 0, NULL },
318};
319
320static int gdp_debugfs_init(struct sti_gdp *gdp, struct drm_minor *minor)
321{
322 unsigned int i;
323 struct drm_info_list *gdp_debugfs_files;
324 int nb_files;
325
326 switch (gdp->plane.desc) {
327 case STI_GDP_0:
328 gdp_debugfs_files = gdp0_debugfs_files;
329 nb_files = ARRAY_SIZE(gdp0_debugfs_files);
330 break;
331 case STI_GDP_1:
332 gdp_debugfs_files = gdp1_debugfs_files;
333 nb_files = ARRAY_SIZE(gdp1_debugfs_files);
334 break;
335 case STI_GDP_2:
336 gdp_debugfs_files = gdp2_debugfs_files;
337 nb_files = ARRAY_SIZE(gdp2_debugfs_files);
338 break;
339 case STI_GDP_3:
340 gdp_debugfs_files = gdp3_debugfs_files;
341 nb_files = ARRAY_SIZE(gdp3_debugfs_files);
342 break;
343 default:
344 return -EINVAL;
345 }
346
347 for (i = 0; i < nb_files; i++)
348 gdp_debugfs_files[i].data = gdp;
349
350 return drm_debugfs_create_files(gdp_debugfs_files,
351 nb_files,
352 minor->debugfs_root, minor);
353}
354
355static int sti_gdp_fourcc2format(int fourcc)
356{
357 switch (fourcc) {
358 case DRM_FORMAT_XRGB8888:
359 return GDP_RGB888_32;
360 case DRM_FORMAT_XBGR8888:
361 return GDP_XBGR8888;
362 case DRM_FORMAT_ARGB8888:
363 return GDP_ARGB8888;
364 case DRM_FORMAT_ABGR8888:
365 return GDP_ABGR8888;
366 case DRM_FORMAT_ARGB4444:
367 return GDP_ARGB4444;
368 case DRM_FORMAT_ARGB1555:
369 return GDP_ARGB1555;
370 case DRM_FORMAT_RGB565:
371 return GDP_RGB565;
372 case DRM_FORMAT_RGB888:
373 return GDP_RGB888;
374 }
375 return -1;
376}
377
378static int sti_gdp_get_alpharange(int format)
379{
380 switch (format) {
381 case GDP_ARGB8565:
382 case GDP_ARGB8888:
383 case GDP_ABGR8888:
384 return GAM_GDP_ALPHARANGE_255;
385 }
386 return 0;
387}
388
389/**
390 * sti_gdp_get_free_nodes
391 * @gdp: gdp pointer
392 *
393 * Look for a GDP node list that is not currently read by the HW.
394 *
395 * RETURNS:
396 * Pointer to the free GDP node list
397 */
398static struct sti_gdp_node_list *sti_gdp_get_free_nodes(struct sti_gdp *gdp)
399{
400 int hw_nvn;
401 unsigned int i;
402
403 hw_nvn = readl(gdp->regs + GAM_GDP_NVN_OFFSET);
404 if (!hw_nvn)
405 goto end;
406
407 for (i = 0; i < GDP_NODE_NB_BANK; i++)
408 if ((hw_nvn != gdp->node_list[i].btm_field_paddr) &&
409 (hw_nvn != gdp->node_list[i].top_field_paddr))
410 return &gdp->node_list[i];
411
412 /* in hazardious cases restart with the first node */
413 DRM_ERROR("inconsistent NVN for %s: 0x%08X\n",
414 sti_plane_to_str(&gdp->plane), hw_nvn);
415
416end:
417 return &gdp->node_list[0];
418}
419
420/**
421 * sti_gdp_get_current_nodes
422 * @gdp: gdp pointer
423 *
424 * Look for GDP nodes that are currently read by the HW.
425 *
426 * RETURNS:
427 * Pointer to the current GDP node list
428 */
429static
430struct sti_gdp_node_list *sti_gdp_get_current_nodes(struct sti_gdp *gdp)
431{
432 int hw_nvn;
433 unsigned int i;
434
435 hw_nvn = readl(gdp->regs + GAM_GDP_NVN_OFFSET);
436 if (!hw_nvn)
437 goto end;
438
439 for (i = 0; i < GDP_NODE_NB_BANK; i++)
440 if ((hw_nvn == gdp->node_list[i].btm_field_paddr) ||
441 (hw_nvn == gdp->node_list[i].top_field_paddr))
442 return &gdp->node_list[i];
443
444end:
445 DRM_DEBUG_DRIVER("Warning, NVN 0x%08X for %s does not match any node\n",
446 hw_nvn, sti_plane_to_str(&gdp->plane));
447
448 return NULL;
449}
450
451/**
452 * sti_gdp_disable
453 * @gdp: gdp pointer
454 *
455 * Disable a GDP.
456 */
457static void sti_gdp_disable(struct sti_gdp *gdp)
458{
459 unsigned int i;
460
461 DRM_DEBUG_DRIVER("%s\n", sti_plane_to_str(&gdp->plane));
462
463 /* Set the nodes as 'to be ignored on mixer' */
464 for (i = 0; i < GDP_NODE_NB_BANK; i++) {
465 gdp->node_list[i].top_field->gam_gdp_ppt |= GAM_GDP_PPT_IGNORE;
466 gdp->node_list[i].btm_field->gam_gdp_ppt |= GAM_GDP_PPT_IGNORE;
467 }
468
469 if (sti_vtg_unregister_client(gdp->vtg, &gdp->vtg_field_nb))
470 DRM_DEBUG_DRIVER("Warning: cannot unregister VTG notifier\n");
471
472 if (gdp->clk_pix)
473 clk_disable_unprepare(gdp->clk_pix);
474
475 gdp->plane.status = STI_PLANE_DISABLED;
476}
477
478/**
479 * sti_gdp_field_cb
480 * @nb: notifier block
481 * @event: event message
482 * @data: private data
483 *
484 * Handle VTG top field and bottom field event.
485 *
486 * RETURNS:
487 * 0 on success.
488 */
489int sti_gdp_field_cb(struct notifier_block *nb,
490 unsigned long event, void *data)
491{
492 struct sti_gdp *gdp = container_of(nb, struct sti_gdp, vtg_field_nb);
493
494 if (gdp->plane.status == STI_PLANE_FLUSHING) {
495 /* disable need to be synchronize on vsync event */
496 DRM_DEBUG_DRIVER("Vsync event received => disable %s\n",
497 sti_plane_to_str(&gdp->plane));
498
499 sti_gdp_disable(gdp);
500 }
501
502 switch (event) {
503 case VTG_TOP_FIELD_EVENT:
504 gdp->is_curr_top = true;
505 break;
506 case VTG_BOTTOM_FIELD_EVENT:
507 gdp->is_curr_top = false;
508 break;
509 default:
510 DRM_ERROR("unsupported event: %lu\n", event);
511 break;
512 }
513
514 return 0;
515}
516
517static void sti_gdp_init(struct sti_gdp *gdp)
518{
519 struct device_node *np = gdp->dev->of_node;
520 dma_addr_t dma_addr;
521 void *base;
522 unsigned int i, size;
523
524 /* Allocate all the nodes within a single memory page */
525 size = sizeof(struct sti_gdp_node) *
526 GDP_NODE_PER_FIELD * GDP_NODE_NB_BANK;
527 base = dma_alloc_wc(gdp->dev, size, &dma_addr, GFP_KERNEL | GFP_DMA);
528
529 if (!base) {
530 DRM_ERROR("Failed to allocate memory for GDP node\n");
531 return;
532 }
533 memset(base, 0, size);
534
535 for (i = 0; i < GDP_NODE_NB_BANK; i++) {
536 if (dma_addr & 0xF) {
537 DRM_ERROR("Mem alignment failed\n");
538 return;
539 }
540 gdp->node_list[i].top_field = base;
541 gdp->node_list[i].top_field_paddr = dma_addr;
542
543 DRM_DEBUG_DRIVER("node[%d].top_field=%p\n", i, base);
544 base += sizeof(struct sti_gdp_node);
545 dma_addr += sizeof(struct sti_gdp_node);
546
547 if (dma_addr & 0xF) {
548 DRM_ERROR("Mem alignment failed\n");
549 return;
550 }
551 gdp->node_list[i].btm_field = base;
552 gdp->node_list[i].btm_field_paddr = dma_addr;
553 DRM_DEBUG_DRIVER("node[%d].btm_field=%p\n", i, base);
554 base += sizeof(struct sti_gdp_node);
555 dma_addr += sizeof(struct sti_gdp_node);
556 }
557
558 if (of_device_is_compatible(np, "st,stih407-compositor")) {
559 /* GDP of STiH407 chip have its own pixel clock */
560 char *clk_name;
561
562 switch (gdp->plane.desc) {
563 case STI_GDP_0:
564 clk_name = "pix_gdp1";
565 break;
566 case STI_GDP_1:
567 clk_name = "pix_gdp2";
568 break;
569 case STI_GDP_2:
570 clk_name = "pix_gdp3";
571 break;
572 case STI_GDP_3:
573 clk_name = "pix_gdp4";
574 break;
575 default:
576 DRM_ERROR("GDP id not recognized\n");
577 return;
578 }
579
580 gdp->clk_pix = devm_clk_get(gdp->dev, clk_name);
581 if (IS_ERR(gdp->clk_pix))
582 DRM_ERROR("Cannot get %s clock\n", clk_name);
583
584 gdp->clk_main_parent = devm_clk_get(gdp->dev, "main_parent");
585 if (IS_ERR(gdp->clk_main_parent))
586 DRM_ERROR("Cannot get main_parent clock\n");
587
588 gdp->clk_aux_parent = devm_clk_get(gdp->dev, "aux_parent");
589 if (IS_ERR(gdp->clk_aux_parent))
590 DRM_ERROR("Cannot get aux_parent clock\n");
591 }
592}
593
594/**
595 * sti_gdp_get_dst
596 * @dev: device
597 * @dst: requested destination size
598 * @src: source size
599 *
600 * Return the cropped / clamped destination size
601 *
602 * RETURNS:
603 * cropped / clamped destination size
604 */
605static int sti_gdp_get_dst(struct device *dev, int dst, int src)
606{
607 if (dst == src)
608 return dst;
609
610 if (dst < src) {
611 dev_dbg(dev, "WARNING: GDP scale not supported, will crop\n");
612 return dst;
613 }
614
615 dev_dbg(dev, "WARNING: GDP scale not supported, will clamp\n");
616 return src;
617}
618
619static int sti_gdp_atomic_check(struct drm_plane *drm_plane,
620 struct drm_plane_state *state)
621{
622 struct sti_plane *plane = to_sti_plane(drm_plane);
623 struct sti_gdp *gdp = to_sti_gdp(plane);
624 struct drm_crtc *crtc = state->crtc;
625 struct sti_compositor *compo = dev_get_drvdata(gdp->dev);
626 struct drm_framebuffer *fb = state->fb;
627 bool first_prepare = plane->status == STI_PLANE_DISABLED ? true : false;
628 struct drm_crtc_state *crtc_state;
629 struct sti_mixer *mixer;
630 struct drm_display_mode *mode;
631 int dst_x, dst_y, dst_w, dst_h;
632 int src_x, src_y, src_w, src_h;
633 int format;
634
635 /* no need for further checks if the plane is being disabled */
636 if (!crtc || !fb)
637 return 0;
638
639 mixer = to_sti_mixer(crtc);
640 crtc_state = drm_atomic_get_crtc_state(state->state, crtc);
641 mode = &crtc_state->mode;
642 dst_x = state->crtc_x;
643 dst_y = state->crtc_y;
644 dst_w = clamp_val(state->crtc_w, 0, mode->crtc_hdisplay - dst_x);
645 dst_h = clamp_val(state->crtc_h, 0, mode->crtc_vdisplay - dst_y);
646 /* src_x are in 16.16 format */
647 src_x = state->src_x >> 16;
648 src_y = state->src_y >> 16;
649 src_w = clamp_val(state->src_w >> 16, 0, GAM_GDP_SIZE_MAX);
650 src_h = clamp_val(state->src_h >> 16, 0, GAM_GDP_SIZE_MAX);
651
652 format = sti_gdp_fourcc2format(fb->pixel_format);
653 if (format == -1) {
654 DRM_ERROR("Format not supported by GDP %.4s\n",
655 (char *)&fb->pixel_format);
656 return -EINVAL;
657 }
658
659 if (!drm_fb_cma_get_gem_obj(fb, 0)) {
660 DRM_ERROR("Can't get CMA GEM object for fb\n");
661 return -EINVAL;
662 }
663
664 if (first_prepare) {
665 /* Register gdp callback */
666 gdp->vtg = mixer->id == STI_MIXER_MAIN ?
667 compo->vtg_main : compo->vtg_aux;
668 if (sti_vtg_register_client(gdp->vtg,
669 &gdp->vtg_field_nb, crtc)) {
670 DRM_ERROR("Cannot register VTG notifier\n");
671 return -EINVAL;
672 }
673
674 /* Set and enable gdp clock */
675 if (gdp->clk_pix) {
676 struct clk *clkp;
677 int rate = mode->clock * 1000;
678 int res;
679
680 /*
681 * According to the mixer used, the gdp pixel clock
682 * should have a different parent clock.
683 */
684 if (mixer->id == STI_MIXER_MAIN)
685 clkp = gdp->clk_main_parent;
686 else
687 clkp = gdp->clk_aux_parent;
688
689 if (clkp)
690 clk_set_parent(gdp->clk_pix, clkp);
691
692 res = clk_set_rate(gdp->clk_pix, rate);
693 if (res < 0) {
694 DRM_ERROR("Cannot set rate (%dHz) for gdp\n",
695 rate);
696 return -EINVAL;
697 }
698
699 if (clk_prepare_enable(gdp->clk_pix)) {
700 DRM_ERROR("Failed to prepare/enable gdp\n");
701 return -EINVAL;
702 }
703 }
704 }
705
706 DRM_DEBUG_KMS("CRTC:%d (%s) drm plane:%d (%s)\n",
707 crtc->base.id, sti_mixer_to_str(mixer),
708 drm_plane->base.id, sti_plane_to_str(plane));
709 DRM_DEBUG_KMS("%s dst=(%dx%d)@(%d,%d) - src=(%dx%d)@(%d,%d)\n",
710 sti_plane_to_str(plane),
711 dst_w, dst_h, dst_x, dst_y,
712 src_w, src_h, src_x, src_y);
713
714 return 0;
715}
716
717static void sti_gdp_atomic_update(struct drm_plane *drm_plane,
718 struct drm_plane_state *oldstate)
719{
720 struct drm_plane_state *state = drm_plane->state;
721 struct sti_plane *plane = to_sti_plane(drm_plane);
722 struct sti_gdp *gdp = to_sti_gdp(plane);
723 struct drm_crtc *crtc = state->crtc;
724 struct drm_framebuffer *fb = state->fb;
725 struct drm_display_mode *mode;
726 int dst_x, dst_y, dst_w, dst_h;
727 int src_x, src_y, src_w, src_h;
728 struct drm_gem_cma_object *cma_obj;
729 struct sti_gdp_node_list *list;
730 struct sti_gdp_node_list *curr_list;
731 struct sti_gdp_node *top_field, *btm_field;
732 u32 dma_updated_top;
733 u32 dma_updated_btm;
734 int format;
735 unsigned int depth, bpp;
736 u32 ydo, xdo, yds, xds;
737
738 if (!crtc || !fb)
739 return;
740
741 mode = &crtc->mode;
742 dst_x = state->crtc_x;
743 dst_y = state->crtc_y;
744 dst_w = clamp_val(state->crtc_w, 0, mode->crtc_hdisplay - dst_x);
745 dst_h = clamp_val(state->crtc_h, 0, mode->crtc_vdisplay - dst_y);
746 /* src_x are in 16.16 format */
747 src_x = state->src_x >> 16;
748 src_y = state->src_y >> 16;
749 src_w = clamp_val(state->src_w >> 16, 0, GAM_GDP_SIZE_MAX);
750 src_h = clamp_val(state->src_h >> 16, 0, GAM_GDP_SIZE_MAX);
751
752 list = sti_gdp_get_free_nodes(gdp);
753 top_field = list->top_field;
754 btm_field = list->btm_field;
755
756 dev_dbg(gdp->dev, "%s %s top_node:0x%p btm_node:0x%p\n", __func__,
757 sti_plane_to_str(plane), top_field, btm_field);
758
759 /* build the top field */
760 top_field->gam_gdp_agc = GAM_GDP_AGC_FULL_RANGE;
761 top_field->gam_gdp_ctl = WAIT_NEXT_VSYNC;
762 format = sti_gdp_fourcc2format(fb->pixel_format);
763 top_field->gam_gdp_ctl |= format;
764 top_field->gam_gdp_ctl |= sti_gdp_get_alpharange(format);
765 top_field->gam_gdp_ppt &= ~GAM_GDP_PPT_IGNORE;
766
767 cma_obj = drm_fb_cma_get_gem_obj(fb, 0);
768
769 DRM_DEBUG_DRIVER("drm FB:%d format:%.4s phys@:0x%lx\n", fb->base.id,
770 (char *)&fb->pixel_format,
771 (unsigned long)cma_obj->paddr);
772
773 /* pixel memory location */
774 drm_fb_get_bpp_depth(fb->pixel_format, &depth, &bpp);
775 top_field->gam_gdp_pml = (u32)cma_obj->paddr + fb->offsets[0];
776 top_field->gam_gdp_pml += src_x * (bpp >> 3);
777 top_field->gam_gdp_pml += src_y * fb->pitches[0];
778
779 /* output parameters (clamped / cropped) */
780 dst_w = sti_gdp_get_dst(gdp->dev, dst_w, src_w);
781 dst_h = sti_gdp_get_dst(gdp->dev, dst_h, src_h);
782 ydo = sti_vtg_get_line_number(*mode, dst_y);
783 yds = sti_vtg_get_line_number(*mode, dst_y + dst_h - 1);
784 xdo = sti_vtg_get_pixel_number(*mode, dst_x);
785 xds = sti_vtg_get_pixel_number(*mode, dst_x + dst_w - 1);
786 top_field->gam_gdp_vpo = (ydo << 16) | xdo;
787 top_field->gam_gdp_vps = (yds << 16) | xds;
788
789 /* input parameters */
790 src_w = dst_w;
791 top_field->gam_gdp_pmp = fb->pitches[0];
792 top_field->gam_gdp_size = src_h << 16 | src_w;
793
794 /* Same content and chained together */
795 memcpy(btm_field, top_field, sizeof(*btm_field));
796 top_field->gam_gdp_nvn = list->btm_field_paddr;
797 btm_field->gam_gdp_nvn = list->top_field_paddr;
798
799 /* Interlaced mode */
800 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
801 btm_field->gam_gdp_pml = top_field->gam_gdp_pml +
802 fb->pitches[0];
803
804 /* Update the NVN field of the 'right' field of the current GDP node
805 * (being used by the HW) with the address of the updated ('free') top
806 * field GDP node.
807 * - In interlaced mode the 'right' field is the bottom field as we
808 * update frames starting from their top field
809 * - In progressive mode, we update both bottom and top fields which
810 * are equal nodes.
811 * At the next VSYNC, the updated node list will be used by the HW.
812 */
813 curr_list = sti_gdp_get_current_nodes(gdp);
814 dma_updated_top = list->top_field_paddr;
815 dma_updated_btm = list->btm_field_paddr;
816
817 dev_dbg(gdp->dev, "Current NVN:0x%X\n",
818 readl(gdp->regs + GAM_GDP_NVN_OFFSET));
819 dev_dbg(gdp->dev, "Posted buff: %lx current buff: %x\n",
820 (unsigned long)cma_obj->paddr,
821 readl(gdp->regs + GAM_GDP_PML_OFFSET));
822
823 if (!curr_list) {
824 /* First update or invalid node should directly write in the
825 * hw register */
826 DRM_DEBUG_DRIVER("%s first update (or invalid node)",
827 sti_plane_to_str(plane));
828
829 writel(gdp->is_curr_top ?
830 dma_updated_btm : dma_updated_top,
831 gdp->regs + GAM_GDP_NVN_OFFSET);
832 goto end;
833 }
834
835 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
836 if (gdp->is_curr_top) {
837 /* Do not update in the middle of the frame, but
838 * postpone the update after the bottom field has
839 * been displayed */
840 curr_list->btm_field->gam_gdp_nvn = dma_updated_top;
841 } else {
842 /* Direct update to avoid one frame delay */
843 writel(dma_updated_top,
844 gdp->regs + GAM_GDP_NVN_OFFSET);
845 }
846 } else {
847 /* Direct update for progressive to avoid one frame delay */
848 writel(dma_updated_top, gdp->regs + GAM_GDP_NVN_OFFSET);
849 }
850
851end:
852 sti_plane_update_fps(plane, true, false);
853
854 plane->status = STI_PLANE_UPDATED;
855}
856
857static void sti_gdp_atomic_disable(struct drm_plane *drm_plane,
858 struct drm_plane_state *oldstate)
859{
860 struct sti_plane *plane = to_sti_plane(drm_plane);
861
862 if (!drm_plane->crtc) {
863 DRM_DEBUG_DRIVER("drm plane:%d not enabled\n",
864 drm_plane->base.id);
865 return;
866 }
867
868 DRM_DEBUG_DRIVER("CRTC:%d (%s) drm plane:%d (%s)\n",
869 drm_plane->crtc->base.id,
870 sti_mixer_to_str(to_sti_mixer(drm_plane->crtc)),
871 drm_plane->base.id, sti_plane_to_str(plane));
872
873 plane->status = STI_PLANE_DISABLING;
874}
875
876static const struct drm_plane_helper_funcs sti_gdp_helpers_funcs = {
877 .atomic_check = sti_gdp_atomic_check,
878 .atomic_update = sti_gdp_atomic_update,
879 .atomic_disable = sti_gdp_atomic_disable,
880};
881
882struct drm_plane *sti_gdp_create(struct drm_device *drm_dev,
883 struct device *dev, int desc,
884 void __iomem *baseaddr,
885 unsigned int possible_crtcs,
886 enum drm_plane_type type)
887{
888 struct sti_gdp *gdp;
889 int res;
890
891 gdp = devm_kzalloc(dev, sizeof(*gdp), GFP_KERNEL);
892 if (!gdp) {
893 DRM_ERROR("Failed to allocate memory for GDP\n");
894 return NULL;
895 }
896
897 gdp->dev = dev;
898 gdp->regs = baseaddr;
899 gdp->plane.desc = desc;
900 gdp->plane.status = STI_PLANE_DISABLED;
901
902 gdp->vtg_field_nb.notifier_call = sti_gdp_field_cb;
903
904 sti_gdp_init(gdp);
905
906 res = drm_universal_plane_init(drm_dev, &gdp->plane.drm_plane,
907 possible_crtcs,
908 &sti_plane_helpers_funcs,
909 gdp_supported_formats,
910 ARRAY_SIZE(gdp_supported_formats),
911 type, NULL);
912 if (res) {
913 DRM_ERROR("Failed to initialize universal plane\n");
914 goto err;
915 }
916
917 drm_plane_helper_add(&gdp->plane.drm_plane, &sti_gdp_helpers_funcs);
918
919 sti_plane_init_property(&gdp->plane, type);
920
921 if (gdp_debugfs_init(gdp, drm_dev->primary))
922 DRM_ERROR("GDP debugfs setup failed\n");
923
924 return &gdp->plane.drm_plane;
925
926err:
927 devm_kfree(dev, gdp);
928 return NULL;
929}
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) STMicroelectronics SA 2014
4 * Authors: Benjamin Gaignard <benjamin.gaignard@st.com>
5 * Fabien Dessenne <fabien.dessenne@st.com>
6 * for STMicroelectronics.
7 */
8
9#include <linux/dma-mapping.h>
10#include <linux/of.h>
11#include <linux/seq_file.h>
12
13#include <drm/drm_atomic.h>
14#include <drm/drm_device.h>
15#include <drm/drm_fb_dma_helper.h>
16#include <drm/drm_fourcc.h>
17#include <drm/drm_framebuffer.h>
18#include <drm/drm_gem_dma_helper.h>
19
20#include "sti_compositor.h"
21#include "sti_gdp.h"
22#include "sti_plane.h"
23#include "sti_vtg.h"
24
25#define ALPHASWITCH BIT(6)
26#define ENA_COLOR_FILL BIT(8)
27#define BIGNOTLITTLE BIT(23)
28#define WAIT_NEXT_VSYNC BIT(31)
29
30/* GDP color formats */
31#define GDP_RGB565 0x00
32#define GDP_RGB888 0x01
33#define GDP_RGB888_32 0x02
34#define GDP_XBGR8888 (GDP_RGB888_32 | BIGNOTLITTLE | ALPHASWITCH)
35#define GDP_ARGB8565 0x04
36#define GDP_ARGB8888 0x05
37#define GDP_ABGR8888 (GDP_ARGB8888 | BIGNOTLITTLE | ALPHASWITCH)
38#define GDP_ARGB1555 0x06
39#define GDP_ARGB4444 0x07
40
41#define GDP2STR(fmt) { GDP_ ## fmt, #fmt }
42
43static struct gdp_format_to_str {
44 int format;
45 char name[20];
46} gdp_format_to_str[] = {
47 GDP2STR(RGB565),
48 GDP2STR(RGB888),
49 GDP2STR(RGB888_32),
50 GDP2STR(XBGR8888),
51 GDP2STR(ARGB8565),
52 GDP2STR(ARGB8888),
53 GDP2STR(ABGR8888),
54 GDP2STR(ARGB1555),
55 GDP2STR(ARGB4444)
56 };
57
58#define GAM_GDP_CTL_OFFSET 0x00
59#define GAM_GDP_AGC_OFFSET 0x04
60#define GAM_GDP_VPO_OFFSET 0x0C
61#define GAM_GDP_VPS_OFFSET 0x10
62#define GAM_GDP_PML_OFFSET 0x14
63#define GAM_GDP_PMP_OFFSET 0x18
64#define GAM_GDP_SIZE_OFFSET 0x1C
65#define GAM_GDP_NVN_OFFSET 0x24
66#define GAM_GDP_KEY1_OFFSET 0x28
67#define GAM_GDP_KEY2_OFFSET 0x2C
68#define GAM_GDP_PPT_OFFSET 0x34
69#define GAM_GDP_CML_OFFSET 0x3C
70#define GAM_GDP_MST_OFFSET 0x68
71
72#define GAM_GDP_ALPHARANGE_255 BIT(5)
73#define GAM_GDP_AGC_FULL_RANGE 0x00808080
74#define GAM_GDP_PPT_IGNORE (BIT(1) | BIT(0))
75
76#define GAM_GDP_SIZE_MAX_WIDTH 3840
77#define GAM_GDP_SIZE_MAX_HEIGHT 2160
78
79#define GDP_NODE_NB_BANK 2
80#define GDP_NODE_PER_FIELD 2
81
82struct sti_gdp_node {
83 u32 gam_gdp_ctl;
84 u32 gam_gdp_agc;
85 u32 reserved1;
86 u32 gam_gdp_vpo;
87 u32 gam_gdp_vps;
88 u32 gam_gdp_pml;
89 u32 gam_gdp_pmp;
90 u32 gam_gdp_size;
91 u32 reserved2;
92 u32 gam_gdp_nvn;
93 u32 gam_gdp_key1;
94 u32 gam_gdp_key2;
95 u32 reserved3;
96 u32 gam_gdp_ppt;
97 u32 reserved4;
98 u32 gam_gdp_cml;
99};
100
101struct sti_gdp_node_list {
102 struct sti_gdp_node *top_field;
103 dma_addr_t top_field_paddr;
104 struct sti_gdp_node *btm_field;
105 dma_addr_t btm_field_paddr;
106};
107
108/*
109 * STI GDP structure
110 *
111 * @sti_plane: sti_plane structure
112 * @dev: driver device
113 * @regs: gdp registers
114 * @clk_pix: pixel clock for the current gdp
115 * @clk_main_parent: gdp parent clock if main path used
116 * @clk_aux_parent: gdp parent clock if aux path used
117 * @vtg_field_nb: callback for VTG FIELD (top or bottom) notification
118 * @is_curr_top: true if the current node processed is the top field
119 * @node_list: array of node list
120 * @vtg: registered vtg
121 */
122struct sti_gdp {
123 struct sti_plane plane;
124 struct device *dev;
125 void __iomem *regs;
126 struct clk *clk_pix;
127 struct clk *clk_main_parent;
128 struct clk *clk_aux_parent;
129 struct notifier_block vtg_field_nb;
130 bool is_curr_top;
131 struct sti_gdp_node_list node_list[GDP_NODE_NB_BANK];
132 struct sti_vtg *vtg;
133};
134
135#define to_sti_gdp(x) container_of(x, struct sti_gdp, plane)
136
137static const uint32_t gdp_supported_formats[] = {
138 DRM_FORMAT_XRGB8888,
139 DRM_FORMAT_XBGR8888,
140 DRM_FORMAT_ARGB8888,
141 DRM_FORMAT_ABGR8888,
142 DRM_FORMAT_ARGB4444,
143 DRM_FORMAT_ARGB1555,
144 DRM_FORMAT_RGB565,
145 DRM_FORMAT_RGB888,
146};
147
148#define DBGFS_DUMP(reg) seq_printf(s, "\n %-25s 0x%08X", #reg, \
149 readl(gdp->regs + reg ## _OFFSET))
150
151static void gdp_dbg_ctl(struct seq_file *s, int val)
152{
153 int i;
154
155 seq_puts(s, "\tColor:");
156 for (i = 0; i < ARRAY_SIZE(gdp_format_to_str); i++) {
157 if (gdp_format_to_str[i].format == (val & 0x1F)) {
158 seq_puts(s, gdp_format_to_str[i].name);
159 break;
160 }
161 }
162 if (i == ARRAY_SIZE(gdp_format_to_str))
163 seq_puts(s, "<UNKNOWN>");
164
165 seq_printf(s, "\tWaitNextVsync:%d", val & WAIT_NEXT_VSYNC ? 1 : 0);
166}
167
168static void gdp_dbg_vpo(struct seq_file *s, int val)
169{
170 seq_printf(s, "\txdo:%4d\tydo:%4d", val & 0xFFFF, (val >> 16) & 0xFFFF);
171}
172
173static void gdp_dbg_vps(struct seq_file *s, int val)
174{
175 seq_printf(s, "\txds:%4d\tyds:%4d", val & 0xFFFF, (val >> 16) & 0xFFFF);
176}
177
178static void gdp_dbg_size(struct seq_file *s, int val)
179{
180 seq_printf(s, "\t%d x %d", val & 0xFFFF, (val >> 16) & 0xFFFF);
181}
182
183static void gdp_dbg_nvn(struct seq_file *s, struct sti_gdp *gdp, int val)
184{
185 void *base = NULL;
186 unsigned int i;
187
188 for (i = 0; i < GDP_NODE_NB_BANK; i++) {
189 if (gdp->node_list[i].top_field_paddr == val) {
190 base = gdp->node_list[i].top_field;
191 break;
192 }
193 if (gdp->node_list[i].btm_field_paddr == val) {
194 base = gdp->node_list[i].btm_field;
195 break;
196 }
197 }
198
199 if (base)
200 seq_printf(s, "\tVirt @: %p", base);
201}
202
203static void gdp_dbg_ppt(struct seq_file *s, int val)
204{
205 if (val & GAM_GDP_PPT_IGNORE)
206 seq_puts(s, "\tNot displayed on mixer!");
207}
208
209static void gdp_dbg_mst(struct seq_file *s, int val)
210{
211 if (val & 1)
212 seq_puts(s, "\tBUFFER UNDERFLOW!");
213}
214
215static int gdp_dbg_show(struct seq_file *s, void *data)
216{
217 struct drm_info_node *node = s->private;
218 struct sti_gdp *gdp = (struct sti_gdp *)node->info_ent->data;
219 struct drm_plane *drm_plane = &gdp->plane.drm_plane;
220 struct drm_crtc *crtc;
221
222 drm_modeset_lock(&drm_plane->mutex, NULL);
223 crtc = drm_plane->state->crtc;
224 drm_modeset_unlock(&drm_plane->mutex);
225
226 seq_printf(s, "%s: (vaddr = 0x%p)",
227 sti_plane_to_str(&gdp->plane), gdp->regs);
228
229 DBGFS_DUMP(GAM_GDP_CTL);
230 gdp_dbg_ctl(s, readl(gdp->regs + GAM_GDP_CTL_OFFSET));
231 DBGFS_DUMP(GAM_GDP_AGC);
232 DBGFS_DUMP(GAM_GDP_VPO);
233 gdp_dbg_vpo(s, readl(gdp->regs + GAM_GDP_VPO_OFFSET));
234 DBGFS_DUMP(GAM_GDP_VPS);
235 gdp_dbg_vps(s, readl(gdp->regs + GAM_GDP_VPS_OFFSET));
236 DBGFS_DUMP(GAM_GDP_PML);
237 DBGFS_DUMP(GAM_GDP_PMP);
238 DBGFS_DUMP(GAM_GDP_SIZE);
239 gdp_dbg_size(s, readl(gdp->regs + GAM_GDP_SIZE_OFFSET));
240 DBGFS_DUMP(GAM_GDP_NVN);
241 gdp_dbg_nvn(s, gdp, readl(gdp->regs + GAM_GDP_NVN_OFFSET));
242 DBGFS_DUMP(GAM_GDP_KEY1);
243 DBGFS_DUMP(GAM_GDP_KEY2);
244 DBGFS_DUMP(GAM_GDP_PPT);
245 gdp_dbg_ppt(s, readl(gdp->regs + GAM_GDP_PPT_OFFSET));
246 DBGFS_DUMP(GAM_GDP_CML);
247 DBGFS_DUMP(GAM_GDP_MST);
248 gdp_dbg_mst(s, readl(gdp->regs + GAM_GDP_MST_OFFSET));
249
250 seq_puts(s, "\n\n");
251 if (!crtc)
252 seq_puts(s, " Not connected to any DRM CRTC\n");
253 else
254 seq_printf(s, " Connected to DRM CRTC #%d (%s)\n",
255 crtc->base.id, sti_mixer_to_str(to_sti_mixer(crtc)));
256
257 return 0;
258}
259
260static void gdp_node_dump_node(struct seq_file *s, struct sti_gdp_node *node)
261{
262 seq_printf(s, "\t@:0x%p", node);
263 seq_printf(s, "\n\tCTL 0x%08X", node->gam_gdp_ctl);
264 gdp_dbg_ctl(s, node->gam_gdp_ctl);
265 seq_printf(s, "\n\tAGC 0x%08X", node->gam_gdp_agc);
266 seq_printf(s, "\n\tVPO 0x%08X", node->gam_gdp_vpo);
267 gdp_dbg_vpo(s, node->gam_gdp_vpo);
268 seq_printf(s, "\n\tVPS 0x%08X", node->gam_gdp_vps);
269 gdp_dbg_vps(s, node->gam_gdp_vps);
270 seq_printf(s, "\n\tPML 0x%08X", node->gam_gdp_pml);
271 seq_printf(s, "\n\tPMP 0x%08X", node->gam_gdp_pmp);
272 seq_printf(s, "\n\tSIZE 0x%08X", node->gam_gdp_size);
273 gdp_dbg_size(s, node->gam_gdp_size);
274 seq_printf(s, "\n\tNVN 0x%08X", node->gam_gdp_nvn);
275 seq_printf(s, "\n\tKEY1 0x%08X", node->gam_gdp_key1);
276 seq_printf(s, "\n\tKEY2 0x%08X", node->gam_gdp_key2);
277 seq_printf(s, "\n\tPPT 0x%08X", node->gam_gdp_ppt);
278 gdp_dbg_ppt(s, node->gam_gdp_ppt);
279 seq_printf(s, "\n\tCML 0x%08X\n", node->gam_gdp_cml);
280}
281
282static int gdp_node_dbg_show(struct seq_file *s, void *arg)
283{
284 struct drm_info_node *node = s->private;
285 struct sti_gdp *gdp = (struct sti_gdp *)node->info_ent->data;
286 unsigned int b;
287
288 for (b = 0; b < GDP_NODE_NB_BANK; b++) {
289 seq_printf(s, "\n%s[%d].top", sti_plane_to_str(&gdp->plane), b);
290 gdp_node_dump_node(s, gdp->node_list[b].top_field);
291 seq_printf(s, "\n%s[%d].btm", sti_plane_to_str(&gdp->plane), b);
292 gdp_node_dump_node(s, gdp->node_list[b].btm_field);
293 }
294
295 return 0;
296}
297
298static struct drm_info_list gdp0_debugfs_files[] = {
299 { "gdp0", gdp_dbg_show, 0, NULL },
300 { "gdp0_node", gdp_node_dbg_show, 0, NULL },
301};
302
303static struct drm_info_list gdp1_debugfs_files[] = {
304 { "gdp1", gdp_dbg_show, 0, NULL },
305 { "gdp1_node", gdp_node_dbg_show, 0, NULL },
306};
307
308static struct drm_info_list gdp2_debugfs_files[] = {
309 { "gdp2", gdp_dbg_show, 0, NULL },
310 { "gdp2_node", gdp_node_dbg_show, 0, NULL },
311};
312
313static struct drm_info_list gdp3_debugfs_files[] = {
314 { "gdp3", gdp_dbg_show, 0, NULL },
315 { "gdp3_node", gdp_node_dbg_show, 0, NULL },
316};
317
318static int gdp_debugfs_init(struct sti_gdp *gdp, struct drm_minor *minor)
319{
320 unsigned int i;
321 struct drm_info_list *gdp_debugfs_files;
322 int nb_files;
323
324 switch (gdp->plane.desc) {
325 case STI_GDP_0:
326 gdp_debugfs_files = gdp0_debugfs_files;
327 nb_files = ARRAY_SIZE(gdp0_debugfs_files);
328 break;
329 case STI_GDP_1:
330 gdp_debugfs_files = gdp1_debugfs_files;
331 nb_files = ARRAY_SIZE(gdp1_debugfs_files);
332 break;
333 case STI_GDP_2:
334 gdp_debugfs_files = gdp2_debugfs_files;
335 nb_files = ARRAY_SIZE(gdp2_debugfs_files);
336 break;
337 case STI_GDP_3:
338 gdp_debugfs_files = gdp3_debugfs_files;
339 nb_files = ARRAY_SIZE(gdp3_debugfs_files);
340 break;
341 default:
342 return -EINVAL;
343 }
344
345 for (i = 0; i < nb_files; i++)
346 gdp_debugfs_files[i].data = gdp;
347
348 drm_debugfs_create_files(gdp_debugfs_files,
349 nb_files,
350 minor->debugfs_root, minor);
351 return 0;
352}
353
354static int sti_gdp_fourcc2format(int fourcc)
355{
356 switch (fourcc) {
357 case DRM_FORMAT_XRGB8888:
358 return GDP_RGB888_32;
359 case DRM_FORMAT_XBGR8888:
360 return GDP_XBGR8888;
361 case DRM_FORMAT_ARGB8888:
362 return GDP_ARGB8888;
363 case DRM_FORMAT_ABGR8888:
364 return GDP_ABGR8888;
365 case DRM_FORMAT_ARGB4444:
366 return GDP_ARGB4444;
367 case DRM_FORMAT_ARGB1555:
368 return GDP_ARGB1555;
369 case DRM_FORMAT_RGB565:
370 return GDP_RGB565;
371 case DRM_FORMAT_RGB888:
372 return GDP_RGB888;
373 }
374 return -1;
375}
376
377static int sti_gdp_get_alpharange(int format)
378{
379 switch (format) {
380 case GDP_ARGB8565:
381 case GDP_ARGB8888:
382 case GDP_ABGR8888:
383 return GAM_GDP_ALPHARANGE_255;
384 }
385 return 0;
386}
387
388/**
389 * sti_gdp_get_free_nodes
390 * @gdp: gdp pointer
391 *
392 * Look for a GDP node list that is not currently read by the HW.
393 *
394 * RETURNS:
395 * Pointer to the free GDP node list
396 */
397static struct sti_gdp_node_list *sti_gdp_get_free_nodes(struct sti_gdp *gdp)
398{
399 int hw_nvn;
400 unsigned int i;
401
402 hw_nvn = readl(gdp->regs + GAM_GDP_NVN_OFFSET);
403 if (!hw_nvn)
404 goto end;
405
406 for (i = 0; i < GDP_NODE_NB_BANK; i++)
407 if ((hw_nvn != gdp->node_list[i].btm_field_paddr) &&
408 (hw_nvn != gdp->node_list[i].top_field_paddr))
409 return &gdp->node_list[i];
410
411 /* in hazardous cases restart with the first node */
412 DRM_ERROR("inconsistent NVN for %s: 0x%08X\n",
413 sti_plane_to_str(&gdp->plane), hw_nvn);
414
415end:
416 return &gdp->node_list[0];
417}
418
419/**
420 * sti_gdp_get_current_nodes
421 * @gdp: gdp pointer
422 *
423 * Look for GDP nodes that are currently read by the HW.
424 *
425 * RETURNS:
426 * Pointer to the current GDP node list
427 */
428static
429struct sti_gdp_node_list *sti_gdp_get_current_nodes(struct sti_gdp *gdp)
430{
431 int hw_nvn;
432 unsigned int i;
433
434 hw_nvn = readl(gdp->regs + GAM_GDP_NVN_OFFSET);
435 if (!hw_nvn)
436 goto end;
437
438 for (i = 0; i < GDP_NODE_NB_BANK; i++)
439 if ((hw_nvn == gdp->node_list[i].btm_field_paddr) ||
440 (hw_nvn == gdp->node_list[i].top_field_paddr))
441 return &gdp->node_list[i];
442
443end:
444 DRM_DEBUG_DRIVER("Warning, NVN 0x%08X for %s does not match any node\n",
445 hw_nvn, sti_plane_to_str(&gdp->plane));
446
447 return NULL;
448}
449
450/**
451 * sti_gdp_disable
452 * @gdp: gdp pointer
453 *
454 * Disable a GDP.
455 */
456static void sti_gdp_disable(struct sti_gdp *gdp)
457{
458 unsigned int i;
459
460 DRM_DEBUG_DRIVER("%s\n", sti_plane_to_str(&gdp->plane));
461
462 /* Set the nodes as 'to be ignored on mixer' */
463 for (i = 0; i < GDP_NODE_NB_BANK; i++) {
464 gdp->node_list[i].top_field->gam_gdp_ppt |= GAM_GDP_PPT_IGNORE;
465 gdp->node_list[i].btm_field->gam_gdp_ppt |= GAM_GDP_PPT_IGNORE;
466 }
467
468 if (sti_vtg_unregister_client(gdp->vtg, &gdp->vtg_field_nb))
469 DRM_DEBUG_DRIVER("Warning: cannot unregister VTG notifier\n");
470
471 if (gdp->clk_pix)
472 clk_disable_unprepare(gdp->clk_pix);
473
474 gdp->plane.status = STI_PLANE_DISABLED;
475 gdp->vtg = NULL;
476}
477
478/**
479 * sti_gdp_field_cb
480 * @nb: notifier block
481 * @event: event message
482 * @data: private data
483 *
484 * Handle VTG top field and bottom field event.
485 *
486 * RETURNS:
487 * 0 on success.
488 */
489static int sti_gdp_field_cb(struct notifier_block *nb,
490 unsigned long event, void *data)
491{
492 struct sti_gdp *gdp = container_of(nb, struct sti_gdp, vtg_field_nb);
493
494 if (gdp->plane.status == STI_PLANE_FLUSHING) {
495 /* disable need to be synchronize on vsync event */
496 DRM_DEBUG_DRIVER("Vsync event received => disable %s\n",
497 sti_plane_to_str(&gdp->plane));
498
499 sti_gdp_disable(gdp);
500 }
501
502 switch (event) {
503 case VTG_TOP_FIELD_EVENT:
504 gdp->is_curr_top = true;
505 break;
506 case VTG_BOTTOM_FIELD_EVENT:
507 gdp->is_curr_top = false;
508 break;
509 default:
510 DRM_ERROR("unsupported event: %lu\n", event);
511 break;
512 }
513
514 return 0;
515}
516
517static void sti_gdp_init(struct sti_gdp *gdp)
518{
519 struct device_node *np = gdp->dev->of_node;
520 dma_addr_t dma_addr;
521 void *base;
522 unsigned int i, size;
523
524 /* Allocate all the nodes within a single memory page */
525 size = sizeof(struct sti_gdp_node) *
526 GDP_NODE_PER_FIELD * GDP_NODE_NB_BANK;
527 base = dma_alloc_wc(gdp->dev, size, &dma_addr, GFP_KERNEL);
528
529 if (!base) {
530 DRM_ERROR("Failed to allocate memory for GDP node\n");
531 return;
532 }
533 memset(base, 0, size);
534
535 for (i = 0; i < GDP_NODE_NB_BANK; i++) {
536 if (dma_addr & 0xF) {
537 DRM_ERROR("Mem alignment failed\n");
538 return;
539 }
540 gdp->node_list[i].top_field = base;
541 gdp->node_list[i].top_field_paddr = dma_addr;
542
543 DRM_DEBUG_DRIVER("node[%d].top_field=%p\n", i, base);
544 base += sizeof(struct sti_gdp_node);
545 dma_addr += sizeof(struct sti_gdp_node);
546
547 if (dma_addr & 0xF) {
548 DRM_ERROR("Mem alignment failed\n");
549 return;
550 }
551 gdp->node_list[i].btm_field = base;
552 gdp->node_list[i].btm_field_paddr = dma_addr;
553 DRM_DEBUG_DRIVER("node[%d].btm_field=%p\n", i, base);
554 base += sizeof(struct sti_gdp_node);
555 dma_addr += sizeof(struct sti_gdp_node);
556 }
557
558 if (of_device_is_compatible(np, "st,stih407-compositor")) {
559 /* GDP of STiH407 chip have its own pixel clock */
560 char *clk_name;
561
562 switch (gdp->plane.desc) {
563 case STI_GDP_0:
564 clk_name = "pix_gdp1";
565 break;
566 case STI_GDP_1:
567 clk_name = "pix_gdp2";
568 break;
569 case STI_GDP_2:
570 clk_name = "pix_gdp3";
571 break;
572 case STI_GDP_3:
573 clk_name = "pix_gdp4";
574 break;
575 default:
576 DRM_ERROR("GDP id not recognized\n");
577 return;
578 }
579
580 gdp->clk_pix = devm_clk_get(gdp->dev, clk_name);
581 if (IS_ERR(gdp->clk_pix))
582 DRM_ERROR("Cannot get %s clock\n", clk_name);
583
584 gdp->clk_main_parent = devm_clk_get(gdp->dev, "main_parent");
585 if (IS_ERR(gdp->clk_main_parent))
586 DRM_ERROR("Cannot get main_parent clock\n");
587
588 gdp->clk_aux_parent = devm_clk_get(gdp->dev, "aux_parent");
589 if (IS_ERR(gdp->clk_aux_parent))
590 DRM_ERROR("Cannot get aux_parent clock\n");
591 }
592}
593
594/**
595 * sti_gdp_get_dst
596 * @dev: device
597 * @dst: requested destination size
598 * @src: source size
599 *
600 * Return the cropped / clamped destination size
601 *
602 * RETURNS:
603 * cropped / clamped destination size
604 */
605static int sti_gdp_get_dst(struct device *dev, int dst, int src)
606{
607 if (dst == src)
608 return dst;
609
610 if (dst < src) {
611 dev_dbg(dev, "WARNING: GDP scale not supported, will crop\n");
612 return dst;
613 }
614
615 dev_dbg(dev, "WARNING: GDP scale not supported, will clamp\n");
616 return src;
617}
618
619static int sti_gdp_atomic_check(struct drm_plane *drm_plane,
620 struct drm_atomic_state *state)
621{
622 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
623 drm_plane);
624 struct sti_plane *plane = to_sti_plane(drm_plane);
625 struct sti_gdp *gdp = to_sti_gdp(plane);
626 struct drm_crtc *crtc = new_plane_state->crtc;
627 struct drm_framebuffer *fb = new_plane_state->fb;
628 struct drm_crtc_state *crtc_state;
629 struct sti_mixer *mixer;
630 struct drm_display_mode *mode;
631 int dst_x, dst_y, dst_w, dst_h;
632 int src_x, src_y, src_w, src_h;
633 int format;
634
635 /* no need for further checks if the plane is being disabled */
636 if (!crtc || !fb)
637 return 0;
638
639 mixer = to_sti_mixer(crtc);
640 crtc_state = drm_atomic_get_crtc_state(state, crtc);
641 if (IS_ERR(crtc_state))
642 return PTR_ERR(crtc_state);
643
644 mode = &crtc_state->mode;
645 dst_x = new_plane_state->crtc_x;
646 dst_y = new_plane_state->crtc_y;
647 dst_w = clamp_val(new_plane_state->crtc_w, 0, mode->hdisplay - dst_x);
648 dst_h = clamp_val(new_plane_state->crtc_h, 0, mode->vdisplay - dst_y);
649 /* src_x are in 16.16 format */
650 src_x = new_plane_state->src_x >> 16;
651 src_y = new_plane_state->src_y >> 16;
652 src_w = clamp_val(new_plane_state->src_w >> 16, 0,
653 GAM_GDP_SIZE_MAX_WIDTH);
654 src_h = clamp_val(new_plane_state->src_h >> 16, 0,
655 GAM_GDP_SIZE_MAX_HEIGHT);
656
657 format = sti_gdp_fourcc2format(fb->format->format);
658 if (format == -1) {
659 DRM_ERROR("Format not supported by GDP %.4s\n",
660 (char *)&fb->format->format);
661 return -EINVAL;
662 }
663
664 if (!drm_fb_dma_get_gem_obj(fb, 0)) {
665 DRM_ERROR("Can't get DMA GEM object for fb\n");
666 return -EINVAL;
667 }
668
669 /* Set gdp clock */
670 if (mode->clock && gdp->clk_pix) {
671 struct clk *clkp;
672 int rate = mode->clock * 1000;
673 int res;
674
675 /*
676 * According to the mixer used, the gdp pixel clock
677 * should have a different parent clock.
678 */
679 if (mixer->id == STI_MIXER_MAIN)
680 clkp = gdp->clk_main_parent;
681 else
682 clkp = gdp->clk_aux_parent;
683
684 if (clkp)
685 clk_set_parent(gdp->clk_pix, clkp);
686
687 res = clk_set_rate(gdp->clk_pix, rate);
688 if (res < 0) {
689 DRM_ERROR("Cannot set rate (%dHz) for gdp\n",
690 rate);
691 return -EINVAL;
692 }
693 }
694
695 DRM_DEBUG_KMS("CRTC:%d (%s) drm plane:%d (%s)\n",
696 crtc->base.id, sti_mixer_to_str(mixer),
697 drm_plane->base.id, sti_plane_to_str(plane));
698 DRM_DEBUG_KMS("%s dst=(%dx%d)@(%d,%d) - src=(%dx%d)@(%d,%d)\n",
699 sti_plane_to_str(plane),
700 dst_w, dst_h, dst_x, dst_y,
701 src_w, src_h, src_x, src_y);
702
703 return 0;
704}
705
706static void sti_gdp_atomic_update(struct drm_plane *drm_plane,
707 struct drm_atomic_state *state)
708{
709 struct drm_plane_state *oldstate = drm_atomic_get_old_plane_state(state,
710 drm_plane);
711 struct drm_plane_state *newstate = drm_atomic_get_new_plane_state(state,
712 drm_plane);
713 struct sti_plane *plane = to_sti_plane(drm_plane);
714 struct sti_gdp *gdp = to_sti_gdp(plane);
715 struct drm_crtc *crtc = newstate->crtc;
716 struct drm_framebuffer *fb = newstate->fb;
717 struct drm_display_mode *mode;
718 int dst_x, dst_y, dst_w, dst_h;
719 int src_x, src_y, src_w, src_h;
720 struct drm_gem_dma_object *dma_obj;
721 struct sti_gdp_node_list *list;
722 struct sti_gdp_node_list *curr_list;
723 struct sti_gdp_node *top_field, *btm_field;
724 u32 dma_updated_top;
725 u32 dma_updated_btm;
726 int format;
727 unsigned int bpp;
728 u32 ydo, xdo, yds, xds;
729
730 if (!crtc || !fb)
731 return;
732
733 if ((oldstate->fb == newstate->fb) &&
734 (oldstate->crtc_x == newstate->crtc_x) &&
735 (oldstate->crtc_y == newstate->crtc_y) &&
736 (oldstate->crtc_w == newstate->crtc_w) &&
737 (oldstate->crtc_h == newstate->crtc_h) &&
738 (oldstate->src_x == newstate->src_x) &&
739 (oldstate->src_y == newstate->src_y) &&
740 (oldstate->src_w == newstate->src_w) &&
741 (oldstate->src_h == newstate->src_h)) {
742 /* No change since last update, do not post cmd */
743 DRM_DEBUG_DRIVER("No change, not posting cmd\n");
744 plane->status = STI_PLANE_UPDATED;
745 return;
746 }
747
748 if (!gdp->vtg) {
749 struct sti_compositor *compo = dev_get_drvdata(gdp->dev);
750 struct sti_mixer *mixer = to_sti_mixer(crtc);
751
752 /* Register gdp callback */
753 gdp->vtg = compo->vtg[mixer->id];
754 sti_vtg_register_client(gdp->vtg, &gdp->vtg_field_nb, crtc);
755 clk_prepare_enable(gdp->clk_pix);
756 }
757
758 mode = &crtc->mode;
759 dst_x = newstate->crtc_x;
760 dst_y = newstate->crtc_y;
761 dst_w = clamp_val(newstate->crtc_w, 0, mode->hdisplay - dst_x);
762 dst_h = clamp_val(newstate->crtc_h, 0, mode->vdisplay - dst_y);
763 /* src_x are in 16.16 format */
764 src_x = newstate->src_x >> 16;
765 src_y = newstate->src_y >> 16;
766 src_w = clamp_val(newstate->src_w >> 16, 0, GAM_GDP_SIZE_MAX_WIDTH);
767 src_h = clamp_val(newstate->src_h >> 16, 0, GAM_GDP_SIZE_MAX_HEIGHT);
768
769 list = sti_gdp_get_free_nodes(gdp);
770 top_field = list->top_field;
771 btm_field = list->btm_field;
772
773 dev_dbg(gdp->dev, "%s %s top_node:0x%p btm_node:0x%p\n", __func__,
774 sti_plane_to_str(plane), top_field, btm_field);
775
776 /* build the top field */
777 top_field->gam_gdp_agc = GAM_GDP_AGC_FULL_RANGE;
778 top_field->gam_gdp_ctl = WAIT_NEXT_VSYNC;
779 format = sti_gdp_fourcc2format(fb->format->format);
780 top_field->gam_gdp_ctl |= format;
781 top_field->gam_gdp_ctl |= sti_gdp_get_alpharange(format);
782 top_field->gam_gdp_ppt &= ~GAM_GDP_PPT_IGNORE;
783
784 dma_obj = drm_fb_dma_get_gem_obj(fb, 0);
785
786 DRM_DEBUG_DRIVER("drm FB:%d format:%.4s phys@:0x%lx\n", fb->base.id,
787 (char *)&fb->format->format,
788 (unsigned long) dma_obj->dma_addr);
789
790 /* pixel memory location */
791 bpp = fb->format->cpp[0];
792 top_field->gam_gdp_pml = (u32) dma_obj->dma_addr + fb->offsets[0];
793 top_field->gam_gdp_pml += src_x * bpp;
794 top_field->gam_gdp_pml += src_y * fb->pitches[0];
795
796 /* output parameters (clamped / cropped) */
797 dst_w = sti_gdp_get_dst(gdp->dev, dst_w, src_w);
798 dst_h = sti_gdp_get_dst(gdp->dev, dst_h, src_h);
799 ydo = sti_vtg_get_line_number(*mode, dst_y);
800 yds = sti_vtg_get_line_number(*mode, dst_y + dst_h - 1);
801 xdo = sti_vtg_get_pixel_number(*mode, dst_x);
802 xds = sti_vtg_get_pixel_number(*mode, dst_x + dst_w - 1);
803 top_field->gam_gdp_vpo = (ydo << 16) | xdo;
804 top_field->gam_gdp_vps = (yds << 16) | xds;
805
806 /* input parameters */
807 src_w = dst_w;
808 top_field->gam_gdp_pmp = fb->pitches[0];
809 top_field->gam_gdp_size = src_h << 16 | src_w;
810
811 /* Same content and chained together */
812 memcpy(btm_field, top_field, sizeof(*btm_field));
813 top_field->gam_gdp_nvn = list->btm_field_paddr;
814 btm_field->gam_gdp_nvn = list->top_field_paddr;
815
816 /* Interlaced mode */
817 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
818 btm_field->gam_gdp_pml = top_field->gam_gdp_pml +
819 fb->pitches[0];
820
821 /* Update the NVN field of the 'right' field of the current GDP node
822 * (being used by the HW) with the address of the updated ('free') top
823 * field GDP node.
824 * - In interlaced mode the 'right' field is the bottom field as we
825 * update frames starting from their top field
826 * - In progressive mode, we update both bottom and top fields which
827 * are equal nodes.
828 * At the next VSYNC, the updated node list will be used by the HW.
829 */
830 curr_list = sti_gdp_get_current_nodes(gdp);
831 dma_updated_top = list->top_field_paddr;
832 dma_updated_btm = list->btm_field_paddr;
833
834 dev_dbg(gdp->dev, "Current NVN:0x%X\n",
835 readl(gdp->regs + GAM_GDP_NVN_OFFSET));
836 dev_dbg(gdp->dev, "Posted buff: %lx current buff: %x\n",
837 (unsigned long) dma_obj->dma_addr,
838 readl(gdp->regs + GAM_GDP_PML_OFFSET));
839
840 if (!curr_list) {
841 /* First update or invalid node should directly write in the
842 * hw register */
843 DRM_DEBUG_DRIVER("%s first update (or invalid node)\n",
844 sti_plane_to_str(plane));
845
846 writel(gdp->is_curr_top ?
847 dma_updated_btm : dma_updated_top,
848 gdp->regs + GAM_GDP_NVN_OFFSET);
849 goto end;
850 }
851
852 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
853 if (gdp->is_curr_top) {
854 /* Do not update in the middle of the frame, but
855 * postpone the update after the bottom field has
856 * been displayed */
857 curr_list->btm_field->gam_gdp_nvn = dma_updated_top;
858 } else {
859 /* Direct update to avoid one frame delay */
860 writel(dma_updated_top,
861 gdp->regs + GAM_GDP_NVN_OFFSET);
862 }
863 } else {
864 /* Direct update for progressive to avoid one frame delay */
865 writel(dma_updated_top, gdp->regs + GAM_GDP_NVN_OFFSET);
866 }
867
868end:
869 sti_plane_update_fps(plane, true, false);
870
871 plane->status = STI_PLANE_UPDATED;
872}
873
874static void sti_gdp_atomic_disable(struct drm_plane *drm_plane,
875 struct drm_atomic_state *state)
876{
877 struct drm_plane_state *oldstate = drm_atomic_get_old_plane_state(state,
878 drm_plane);
879 struct sti_plane *plane = to_sti_plane(drm_plane);
880
881 if (!oldstate->crtc) {
882 DRM_DEBUG_DRIVER("drm plane:%d not enabled\n",
883 drm_plane->base.id);
884 return;
885 }
886
887 DRM_DEBUG_DRIVER("CRTC:%d (%s) drm plane:%d (%s)\n",
888 oldstate->crtc->base.id,
889 sti_mixer_to_str(to_sti_mixer(oldstate->crtc)),
890 drm_plane->base.id, sti_plane_to_str(plane));
891
892 plane->status = STI_PLANE_DISABLING;
893}
894
895static const struct drm_plane_helper_funcs sti_gdp_helpers_funcs = {
896 .atomic_check = sti_gdp_atomic_check,
897 .atomic_update = sti_gdp_atomic_update,
898 .atomic_disable = sti_gdp_atomic_disable,
899};
900
901static int sti_gdp_late_register(struct drm_plane *drm_plane)
902{
903 struct sti_plane *plane = to_sti_plane(drm_plane);
904 struct sti_gdp *gdp = to_sti_gdp(plane);
905
906 return gdp_debugfs_init(gdp, drm_plane->dev->primary);
907}
908
909static const struct drm_plane_funcs sti_gdp_plane_helpers_funcs = {
910 .update_plane = drm_atomic_helper_update_plane,
911 .disable_plane = drm_atomic_helper_disable_plane,
912 .destroy = drm_plane_cleanup,
913 .reset = drm_atomic_helper_plane_reset,
914 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
915 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
916 .late_register = sti_gdp_late_register,
917};
918
919struct drm_plane *sti_gdp_create(struct drm_device *drm_dev,
920 struct device *dev, int desc,
921 void __iomem *baseaddr,
922 unsigned int possible_crtcs,
923 enum drm_plane_type type)
924{
925 struct sti_gdp *gdp;
926 int res;
927
928 gdp = devm_kzalloc(dev, sizeof(*gdp), GFP_KERNEL);
929 if (!gdp) {
930 DRM_ERROR("Failed to allocate memory for GDP\n");
931 return NULL;
932 }
933
934 gdp->dev = dev;
935 gdp->regs = baseaddr;
936 gdp->plane.desc = desc;
937 gdp->plane.status = STI_PLANE_DISABLED;
938
939 gdp->vtg_field_nb.notifier_call = sti_gdp_field_cb;
940
941 sti_gdp_init(gdp);
942
943 res = drm_universal_plane_init(drm_dev, &gdp->plane.drm_plane,
944 possible_crtcs,
945 &sti_gdp_plane_helpers_funcs,
946 gdp_supported_formats,
947 ARRAY_SIZE(gdp_supported_formats),
948 NULL, type, NULL);
949 if (res) {
950 DRM_ERROR("Failed to initialize universal plane\n");
951 goto err;
952 }
953
954 drm_plane_helper_add(&gdp->plane.drm_plane, &sti_gdp_helpers_funcs);
955
956 sti_plane_init_property(&gdp->plane, type);
957
958 return &gdp->plane.drm_plane;
959
960err:
961 devm_kfree(dev, gdp);
962 return NULL;
963}