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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Rockchip SoC DP (Display Port) interface driver.
4 *
5 * Copyright (C) Fuzhou Rockchip Electronics Co., Ltd.
6 * Author: Andy Yan <andy.yan@rock-chips.com>
7 * Yakir Yang <ykk@rock-chips.com>
8 * Jeff Chen <jeff.chen@rock-chips.com>
9 */
10
11#include <linux/component.h>
12#include <linux/mfd/syscon.h>
13#include <linux/of.h>
14#include <linux/of_graph.h>
15#include <linux/platform_device.h>
16#include <linux/pm_runtime.h>
17#include <linux/regmap.h>
18#include <linux/reset.h>
19#include <linux/clk.h>
20
21#include <video/of_videomode.h>
22#include <video/videomode.h>
23
24#include <drm/display/drm_dp_helper.h>
25#include <drm/drm_atomic.h>
26#include <drm/drm_atomic_helper.h>
27#include <drm/bridge/analogix_dp.h>
28#include <drm/drm_of.h>
29#include <drm/drm_panel.h>
30#include <drm/drm_probe_helper.h>
31#include <drm/drm_simple_kms_helper.h>
32
33#include "rockchip_drm_drv.h"
34
35#define RK3288_GRF_SOC_CON6 0x25c
36#define RK3288_EDP_LCDC_SEL BIT(5)
37#define RK3399_GRF_SOC_CON20 0x6250
38#define RK3399_EDP_LCDC_SEL BIT(5)
39
40#define HIWORD_UPDATE(val, mask) (val | (mask) << 16)
41
42#define PSR_WAIT_LINE_FLAG_TIMEOUT_MS 100
43
44/**
45 * struct rockchip_dp_chip_data - splite the grf setting of kind of chips
46 * @lcdsel_grf_reg: grf register offset of lcdc select
47 * @lcdsel_big: reg value of selecting vop big for eDP
48 * @lcdsel_lit: reg value of selecting vop little for eDP
49 * @chip_type: specific chip type
50 */
51struct rockchip_dp_chip_data {
52 u32 lcdsel_grf_reg;
53 u32 lcdsel_big;
54 u32 lcdsel_lit;
55 u32 chip_type;
56};
57
58struct rockchip_dp_device {
59 struct drm_device *drm_dev;
60 struct device *dev;
61 struct rockchip_encoder encoder;
62 struct drm_display_mode mode;
63
64 struct clk *pclk;
65 struct clk *grfclk;
66 struct regmap *grf;
67 struct reset_control *rst;
68
69 const struct rockchip_dp_chip_data *data;
70
71 struct analogix_dp_device *adp;
72 struct analogix_dp_plat_data plat_data;
73};
74
75static struct rockchip_dp_device *encoder_to_dp(struct drm_encoder *encoder)
76{
77 struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
78
79 return container_of(rkencoder, struct rockchip_dp_device, encoder);
80}
81
82static struct rockchip_dp_device *pdata_encoder_to_dp(struct analogix_dp_plat_data *plat_data)
83{
84 return container_of(plat_data, struct rockchip_dp_device, plat_data);
85}
86
87static int rockchip_dp_pre_init(struct rockchip_dp_device *dp)
88{
89 reset_control_assert(dp->rst);
90 usleep_range(10, 20);
91 reset_control_deassert(dp->rst);
92
93 return 0;
94}
95
96static int rockchip_dp_poweron(struct analogix_dp_plat_data *plat_data)
97{
98 struct rockchip_dp_device *dp = pdata_encoder_to_dp(plat_data);
99 int ret;
100
101 ret = clk_prepare_enable(dp->pclk);
102 if (ret < 0) {
103 DRM_DEV_ERROR(dp->dev, "failed to enable pclk %d\n", ret);
104 return ret;
105 }
106
107 ret = rockchip_dp_pre_init(dp);
108 if (ret < 0) {
109 DRM_DEV_ERROR(dp->dev, "failed to dp pre init %d\n", ret);
110 clk_disable_unprepare(dp->pclk);
111 return ret;
112 }
113
114 return ret;
115}
116
117static int rockchip_dp_powerdown(struct analogix_dp_plat_data *plat_data)
118{
119 struct rockchip_dp_device *dp = pdata_encoder_to_dp(plat_data);
120
121 clk_disable_unprepare(dp->pclk);
122
123 return 0;
124}
125
126static int rockchip_dp_get_modes(struct analogix_dp_plat_data *plat_data,
127 struct drm_connector *connector)
128{
129 struct drm_display_info *di = &connector->display_info;
130 /* VOP couldn't output YUV video format for eDP rightly */
131 u32 mask = DRM_COLOR_FORMAT_YCBCR444 | DRM_COLOR_FORMAT_YCBCR422;
132
133 if ((di->color_formats & mask)) {
134 DRM_DEBUG_KMS("Swapping display color format from YUV to RGB\n");
135 di->color_formats &= ~mask;
136 di->color_formats |= DRM_COLOR_FORMAT_RGB444;
137 di->bpc = 8;
138 }
139
140 return 0;
141}
142
143static bool
144rockchip_dp_drm_encoder_mode_fixup(struct drm_encoder *encoder,
145 const struct drm_display_mode *mode,
146 struct drm_display_mode *adjusted_mode)
147{
148 /* do nothing */
149 return true;
150}
151
152static void rockchip_dp_drm_encoder_mode_set(struct drm_encoder *encoder,
153 struct drm_display_mode *mode,
154 struct drm_display_mode *adjusted)
155{
156 /* do nothing */
157}
158
159static
160struct drm_crtc *rockchip_dp_drm_get_new_crtc(struct drm_encoder *encoder,
161 struct drm_atomic_state *state)
162{
163 struct drm_connector *connector;
164 struct drm_connector_state *conn_state;
165
166 connector = drm_atomic_get_new_connector_for_encoder(state, encoder);
167 if (!connector)
168 return NULL;
169
170 conn_state = drm_atomic_get_new_connector_state(state, connector);
171 if (!conn_state)
172 return NULL;
173
174 return conn_state->crtc;
175}
176
177static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder,
178 struct drm_atomic_state *state)
179{
180 struct rockchip_dp_device *dp = encoder_to_dp(encoder);
181 struct drm_crtc *crtc;
182 struct drm_crtc_state *old_crtc_state;
183 int ret;
184 u32 val;
185
186 crtc = rockchip_dp_drm_get_new_crtc(encoder, state);
187 if (!crtc)
188 return;
189
190 old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc);
191 /* Coming back from self refresh, nothing to do */
192 if (old_crtc_state && old_crtc_state->self_refresh_active)
193 return;
194
195 ret = drm_of_encoder_active_endpoint_id(dp->dev->of_node, encoder);
196 if (ret < 0)
197 return;
198
199 if (ret)
200 val = dp->data->lcdsel_lit;
201 else
202 val = dp->data->lcdsel_big;
203
204 DRM_DEV_DEBUG(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG");
205
206 ret = clk_prepare_enable(dp->grfclk);
207 if (ret < 0) {
208 DRM_DEV_ERROR(dp->dev, "failed to enable grfclk %d\n", ret);
209 return;
210 }
211
212 ret = regmap_write(dp->grf, dp->data->lcdsel_grf_reg, val);
213 if (ret != 0)
214 DRM_DEV_ERROR(dp->dev, "Could not write to GRF: %d\n", ret);
215
216 clk_disable_unprepare(dp->grfclk);
217}
218
219static void rockchip_dp_drm_encoder_disable(struct drm_encoder *encoder,
220 struct drm_atomic_state *state)
221{
222 struct rockchip_dp_device *dp = encoder_to_dp(encoder);
223 struct drm_crtc *crtc;
224 struct drm_crtc_state *new_crtc_state = NULL;
225 int ret;
226
227 crtc = rockchip_dp_drm_get_new_crtc(encoder, state);
228 /* No crtc means we're doing a full shutdown */
229 if (!crtc)
230 return;
231
232 new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
233 /* If we're not entering self-refresh, no need to wait for vact */
234 if (!new_crtc_state || !new_crtc_state->self_refresh_active)
235 return;
236
237 ret = rockchip_drm_wait_vact_end(crtc, PSR_WAIT_LINE_FLAG_TIMEOUT_MS);
238 if (ret)
239 DRM_DEV_ERROR(dp->dev, "line flag irq timed out\n");
240}
241
242static int
243rockchip_dp_drm_encoder_atomic_check(struct drm_encoder *encoder,
244 struct drm_crtc_state *crtc_state,
245 struct drm_connector_state *conn_state)
246{
247 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
248 struct drm_display_info *di = &conn_state->connector->display_info;
249
250 /*
251 * The hardware IC designed that VOP must output the RGB10 video
252 * format to eDP controller, and if eDP panel only support RGB8,
253 * then eDP controller should cut down the video data, not via VOP
254 * controller, that's why we need to hardcode the VOP output mode
255 * to RGA10 here.
256 */
257
258 s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
259 s->output_type = DRM_MODE_CONNECTOR_eDP;
260 s->output_bpc = di->bpc;
261
262 return 0;
263}
264
265static const struct drm_encoder_helper_funcs rockchip_dp_encoder_helper_funcs = {
266 .mode_fixup = rockchip_dp_drm_encoder_mode_fixup,
267 .mode_set = rockchip_dp_drm_encoder_mode_set,
268 .atomic_enable = rockchip_dp_drm_encoder_enable,
269 .atomic_disable = rockchip_dp_drm_encoder_disable,
270 .atomic_check = rockchip_dp_drm_encoder_atomic_check,
271};
272
273static int rockchip_dp_of_probe(struct rockchip_dp_device *dp)
274{
275 struct device *dev = dp->dev;
276 struct device_node *np = dev->of_node;
277
278 dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
279 if (IS_ERR(dp->grf)) {
280 DRM_DEV_ERROR(dev, "failed to get rockchip,grf property\n");
281 return PTR_ERR(dp->grf);
282 }
283
284 dp->grfclk = devm_clk_get(dev, "grf");
285 if (PTR_ERR(dp->grfclk) == -ENOENT) {
286 dp->grfclk = NULL;
287 } else if (PTR_ERR(dp->grfclk) == -EPROBE_DEFER) {
288 return -EPROBE_DEFER;
289 } else if (IS_ERR(dp->grfclk)) {
290 DRM_DEV_ERROR(dev, "failed to get grf clock\n");
291 return PTR_ERR(dp->grfclk);
292 }
293
294 dp->pclk = devm_clk_get(dev, "pclk");
295 if (IS_ERR(dp->pclk)) {
296 DRM_DEV_ERROR(dev, "failed to get pclk property\n");
297 return PTR_ERR(dp->pclk);
298 }
299
300 dp->rst = devm_reset_control_get(dev, "dp");
301 if (IS_ERR(dp->rst)) {
302 DRM_DEV_ERROR(dev, "failed to get dp reset control\n");
303 return PTR_ERR(dp->rst);
304 }
305
306 return 0;
307}
308
309static int rockchip_dp_drm_create_encoder(struct rockchip_dp_device *dp)
310{
311 struct drm_encoder *encoder = &dp->encoder.encoder;
312 struct drm_device *drm_dev = dp->drm_dev;
313 struct device *dev = dp->dev;
314 int ret;
315
316 encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev,
317 dev->of_node);
318 DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);
319
320 ret = drm_simple_encoder_init(drm_dev, encoder,
321 DRM_MODE_ENCODER_TMDS);
322 if (ret) {
323 DRM_ERROR("failed to initialize encoder with drm\n");
324 return ret;
325 }
326
327 drm_encoder_helper_add(encoder, &rockchip_dp_encoder_helper_funcs);
328
329 return 0;
330}
331
332static int rockchip_dp_bind(struct device *dev, struct device *master,
333 void *data)
334{
335 struct rockchip_dp_device *dp = dev_get_drvdata(dev);
336 struct drm_device *drm_dev = data;
337 int ret;
338
339 dp->drm_dev = drm_dev;
340
341 ret = rockchip_dp_drm_create_encoder(dp);
342 if (ret) {
343 DRM_ERROR("failed to create drm encoder\n");
344 return ret;
345 }
346
347 rockchip_drm_encoder_set_crtc_endpoint_id(&dp->encoder,
348 dev->of_node, 0, 0);
349
350 dp->plat_data.encoder = &dp->encoder.encoder;
351
352 ret = analogix_dp_bind(dp->adp, drm_dev);
353 if (ret)
354 goto err_cleanup_encoder;
355
356 return 0;
357err_cleanup_encoder:
358 dp->encoder.encoder.funcs->destroy(&dp->encoder.encoder);
359 return ret;
360}
361
362static void rockchip_dp_unbind(struct device *dev, struct device *master,
363 void *data)
364{
365 struct rockchip_dp_device *dp = dev_get_drvdata(dev);
366
367 analogix_dp_unbind(dp->adp);
368 dp->encoder.encoder.funcs->destroy(&dp->encoder.encoder);
369}
370
371static const struct component_ops rockchip_dp_component_ops = {
372 .bind = rockchip_dp_bind,
373 .unbind = rockchip_dp_unbind,
374};
375
376static int rockchip_dp_probe(struct platform_device *pdev)
377{
378 struct device *dev = &pdev->dev;
379 const struct rockchip_dp_chip_data *dp_data;
380 struct drm_panel *panel = NULL;
381 struct rockchip_dp_device *dp;
382 int ret;
383
384 dp_data = of_device_get_match_data(dev);
385 if (!dp_data)
386 return -ENODEV;
387
388 ret = drm_of_find_panel_or_bridge(dev->of_node, 1, 0, &panel, NULL);
389 if (ret < 0)
390 return ret;
391
392 dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
393 if (!dp)
394 return -ENOMEM;
395
396 dp->dev = dev;
397 dp->adp = ERR_PTR(-ENODEV);
398 dp->data = dp_data;
399 dp->plat_data.panel = panel;
400 dp->plat_data.dev_type = dp->data->chip_type;
401 dp->plat_data.power_on = rockchip_dp_poweron;
402 dp->plat_data.power_off = rockchip_dp_powerdown;
403 dp->plat_data.get_modes = rockchip_dp_get_modes;
404
405 ret = rockchip_dp_of_probe(dp);
406 if (ret < 0)
407 return ret;
408
409 platform_set_drvdata(pdev, dp);
410
411 dp->adp = analogix_dp_probe(dev, &dp->plat_data);
412 if (IS_ERR(dp->adp))
413 return PTR_ERR(dp->adp);
414
415 ret = component_add(dev, &rockchip_dp_component_ops);
416 if (ret)
417 return ret;
418
419 return 0;
420}
421
422static void rockchip_dp_remove(struct platform_device *pdev)
423{
424 component_del(&pdev->dev, &rockchip_dp_component_ops);
425}
426
427static int rockchip_dp_suspend(struct device *dev)
428{
429 struct rockchip_dp_device *dp = dev_get_drvdata(dev);
430
431 if (IS_ERR(dp->adp))
432 return 0;
433
434 return analogix_dp_suspend(dp->adp);
435}
436
437static int rockchip_dp_resume(struct device *dev)
438{
439 struct rockchip_dp_device *dp = dev_get_drvdata(dev);
440
441 if (IS_ERR(dp->adp))
442 return 0;
443
444 return analogix_dp_resume(dp->adp);
445}
446
447static DEFINE_RUNTIME_DEV_PM_OPS(rockchip_dp_pm_ops, rockchip_dp_suspend,
448 rockchip_dp_resume, NULL);
449
450static const struct rockchip_dp_chip_data rk3399_edp = {
451 .lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
452 .lcdsel_big = HIWORD_UPDATE(0, RK3399_EDP_LCDC_SEL),
453 .lcdsel_lit = HIWORD_UPDATE(RK3399_EDP_LCDC_SEL, RK3399_EDP_LCDC_SEL),
454 .chip_type = RK3399_EDP,
455};
456
457static const struct rockchip_dp_chip_data rk3288_dp = {
458 .lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
459 .lcdsel_big = HIWORD_UPDATE(0, RK3288_EDP_LCDC_SEL),
460 .lcdsel_lit = HIWORD_UPDATE(RK3288_EDP_LCDC_SEL, RK3288_EDP_LCDC_SEL),
461 .chip_type = RK3288_DP,
462};
463
464static const struct of_device_id rockchip_dp_dt_ids[] = {
465 {.compatible = "rockchip,rk3288-dp", .data = &rk3288_dp },
466 {.compatible = "rockchip,rk3399-edp", .data = &rk3399_edp },
467 {}
468};
469MODULE_DEVICE_TABLE(of, rockchip_dp_dt_ids);
470
471struct platform_driver rockchip_dp_driver = {
472 .probe = rockchip_dp_probe,
473 .remove = rockchip_dp_remove,
474 .driver = {
475 .name = "rockchip-dp",
476 .pm = pm_ptr(&rockchip_dp_pm_ops),
477 .of_match_table = rockchip_dp_dt_ids,
478 },
479};