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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2015 MediaTek Inc.
4 * Author: YT SHEN <yt.shen@mediatek.com>
5 */
6
7#include <linux/component.h>
8#include <linux/module.h>
9#include <linux/of.h>
10#include <linux/of_platform.h>
11#include <linux/platform_device.h>
12#include <linux/pm_runtime.h>
13#include <linux/dma-mapping.h>
14
15#include <drm/drm_atomic.h>
16#include <drm/drm_atomic_helper.h>
17#include <drm/drm_client_setup.h>
18#include <drm/drm_drv.h>
19#include <drm/drm_fbdev_dma.h>
20#include <drm/drm_fourcc.h>
21#include <drm/drm_gem.h>
22#include <drm/drm_gem_framebuffer_helper.h>
23#include <drm/drm_ioctl.h>
24#include <drm/drm_of.h>
25#include <drm/drm_probe_helper.h>
26#include <drm/drm_vblank.h>
27
28#include "mtk_crtc.h"
29#include "mtk_ddp_comp.h"
30#include "mtk_disp_drv.h"
31#include "mtk_drm_drv.h"
32#include "mtk_gem.h"
33
34#define DRIVER_NAME "mediatek"
35#define DRIVER_DESC "Mediatek SoC DRM"
36#define DRIVER_DATE "20150513"
37#define DRIVER_MAJOR 1
38#define DRIVER_MINOR 0
39
40static const struct drm_mode_config_helper_funcs mtk_drm_mode_config_helpers = {
41 .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm,
42};
43
44static struct drm_framebuffer *
45mtk_drm_mode_fb_create(struct drm_device *dev,
46 struct drm_file *file,
47 const struct drm_mode_fb_cmd2 *cmd)
48{
49 const struct drm_format_info *info = drm_get_format_info(dev, cmd);
50
51 if (info->num_planes != 1)
52 return ERR_PTR(-EINVAL);
53
54 return drm_gem_fb_create(dev, file, cmd);
55}
56
57static const struct drm_mode_config_funcs mtk_drm_mode_config_funcs = {
58 .fb_create = mtk_drm_mode_fb_create,
59 .atomic_check = drm_atomic_helper_check,
60 .atomic_commit = drm_atomic_helper_commit,
61};
62
63static const unsigned int mt2701_mtk_ddp_main[] = {
64 DDP_COMPONENT_OVL0,
65 DDP_COMPONENT_RDMA0,
66 DDP_COMPONENT_COLOR0,
67 DDP_COMPONENT_BLS,
68 DDP_COMPONENT_DSI0,
69};
70
71static const unsigned int mt2701_mtk_ddp_ext[] = {
72 DDP_COMPONENT_RDMA1,
73 DDP_COMPONENT_DPI0,
74};
75
76static const unsigned int mt7623_mtk_ddp_main[] = {
77 DDP_COMPONENT_OVL0,
78 DDP_COMPONENT_RDMA0,
79 DDP_COMPONENT_COLOR0,
80 DDP_COMPONENT_BLS,
81 DDP_COMPONENT_DPI0,
82};
83
84static const unsigned int mt7623_mtk_ddp_ext[] = {
85 DDP_COMPONENT_RDMA1,
86 DDP_COMPONENT_DSI0,
87};
88
89static const unsigned int mt2712_mtk_ddp_main[] = {
90 DDP_COMPONENT_OVL0,
91 DDP_COMPONENT_COLOR0,
92 DDP_COMPONENT_AAL0,
93 DDP_COMPONENT_OD0,
94 DDP_COMPONENT_RDMA0,
95 DDP_COMPONENT_DPI0,
96 DDP_COMPONENT_PWM0,
97};
98
99static const unsigned int mt2712_mtk_ddp_ext[] = {
100 DDP_COMPONENT_OVL1,
101 DDP_COMPONENT_COLOR1,
102 DDP_COMPONENT_AAL1,
103 DDP_COMPONENT_OD1,
104 DDP_COMPONENT_RDMA1,
105 DDP_COMPONENT_DPI1,
106 DDP_COMPONENT_PWM1,
107};
108
109static const unsigned int mt2712_mtk_ddp_third[] = {
110 DDP_COMPONENT_RDMA2,
111 DDP_COMPONENT_DSI3,
112 DDP_COMPONENT_PWM2,
113};
114
115static unsigned int mt8167_mtk_ddp_main[] = {
116 DDP_COMPONENT_OVL0,
117 DDP_COMPONENT_COLOR0,
118 DDP_COMPONENT_CCORR,
119 DDP_COMPONENT_AAL0,
120 DDP_COMPONENT_GAMMA,
121 DDP_COMPONENT_DITHER0,
122 DDP_COMPONENT_RDMA0,
123 DDP_COMPONENT_DSI0,
124};
125
126static const unsigned int mt8173_mtk_ddp_main[] = {
127 DDP_COMPONENT_OVL0,
128 DDP_COMPONENT_COLOR0,
129 DDP_COMPONENT_AAL0,
130 DDP_COMPONENT_OD0,
131 DDP_COMPONENT_RDMA0,
132 DDP_COMPONENT_UFOE,
133 DDP_COMPONENT_DSI0,
134 DDP_COMPONENT_PWM0,
135};
136
137static const unsigned int mt8173_mtk_ddp_ext[] = {
138 DDP_COMPONENT_OVL1,
139 DDP_COMPONENT_COLOR1,
140 DDP_COMPONENT_GAMMA,
141 DDP_COMPONENT_RDMA1,
142 DDP_COMPONENT_DPI0,
143};
144
145static const unsigned int mt8183_mtk_ddp_main[] = {
146 DDP_COMPONENT_OVL0,
147 DDP_COMPONENT_OVL_2L0,
148 DDP_COMPONENT_RDMA0,
149 DDP_COMPONENT_COLOR0,
150 DDP_COMPONENT_CCORR,
151 DDP_COMPONENT_AAL0,
152 DDP_COMPONENT_GAMMA,
153 DDP_COMPONENT_DITHER0,
154 DDP_COMPONENT_DSI0,
155};
156
157static const unsigned int mt8183_mtk_ddp_ext[] = {
158 DDP_COMPONENT_OVL_2L1,
159 DDP_COMPONENT_RDMA1,
160 DDP_COMPONENT_DPI0,
161};
162
163static const unsigned int mt8186_mtk_ddp_main[] = {
164 DDP_COMPONENT_OVL0,
165 DDP_COMPONENT_RDMA0,
166 DDP_COMPONENT_COLOR0,
167 DDP_COMPONENT_CCORR,
168 DDP_COMPONENT_AAL0,
169 DDP_COMPONENT_GAMMA,
170 DDP_COMPONENT_POSTMASK0,
171 DDP_COMPONENT_DITHER0,
172 DDP_COMPONENT_DSI0,
173};
174
175static const unsigned int mt8186_mtk_ddp_ext[] = {
176 DDP_COMPONENT_OVL_2L0,
177 DDP_COMPONENT_RDMA1,
178 DDP_COMPONENT_DPI0,
179};
180
181static const unsigned int mt8188_mtk_ddp_main[] = {
182 DDP_COMPONENT_OVL0,
183 DDP_COMPONENT_RDMA0,
184 DDP_COMPONENT_COLOR0,
185 DDP_COMPONENT_CCORR,
186 DDP_COMPONENT_AAL0,
187 DDP_COMPONENT_GAMMA,
188 DDP_COMPONENT_POSTMASK0,
189 DDP_COMPONENT_DITHER0,
190};
191
192static const struct mtk_drm_route mt8188_mtk_ddp_main_routes[] = {
193 {0, DDP_COMPONENT_DP_INTF0},
194 {0, DDP_COMPONENT_DSI0},
195};
196
197static const unsigned int mt8192_mtk_ddp_main[] = {
198 DDP_COMPONENT_OVL0,
199 DDP_COMPONENT_OVL_2L0,
200 DDP_COMPONENT_RDMA0,
201 DDP_COMPONENT_COLOR0,
202 DDP_COMPONENT_CCORR,
203 DDP_COMPONENT_AAL0,
204 DDP_COMPONENT_GAMMA,
205 DDP_COMPONENT_POSTMASK0,
206 DDP_COMPONENT_DITHER0,
207 DDP_COMPONENT_DSI0,
208};
209
210static const unsigned int mt8192_mtk_ddp_ext[] = {
211 DDP_COMPONENT_OVL_2L2,
212 DDP_COMPONENT_RDMA4,
213 DDP_COMPONENT_DPI0,
214};
215
216static const unsigned int mt8195_mtk_ddp_main[] = {
217 DDP_COMPONENT_OVL0,
218 DDP_COMPONENT_RDMA0,
219 DDP_COMPONENT_COLOR0,
220 DDP_COMPONENT_CCORR,
221 DDP_COMPONENT_AAL0,
222 DDP_COMPONENT_GAMMA,
223 DDP_COMPONENT_DITHER0,
224 DDP_COMPONENT_DSC0,
225 DDP_COMPONENT_MERGE0,
226 DDP_COMPONENT_DP_INTF0,
227};
228
229static const unsigned int mt8195_mtk_ddp_ext[] = {
230 DDP_COMPONENT_DRM_OVL_ADAPTOR,
231 DDP_COMPONENT_MERGE5,
232 DDP_COMPONENT_DP_INTF1,
233};
234
235static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
236 .main_path = mt2701_mtk_ddp_main,
237 .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
238 .ext_path = mt2701_mtk_ddp_ext,
239 .ext_len = ARRAY_SIZE(mt2701_mtk_ddp_ext),
240 .shadow_register = true,
241 .mmsys_dev_num = 1,
242};
243
244static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
245 .main_path = mt7623_mtk_ddp_main,
246 .main_len = ARRAY_SIZE(mt7623_mtk_ddp_main),
247 .ext_path = mt7623_mtk_ddp_ext,
248 .ext_len = ARRAY_SIZE(mt7623_mtk_ddp_ext),
249 .shadow_register = true,
250 .mmsys_dev_num = 1,
251};
252
253static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
254 .main_path = mt2712_mtk_ddp_main,
255 .main_len = ARRAY_SIZE(mt2712_mtk_ddp_main),
256 .ext_path = mt2712_mtk_ddp_ext,
257 .ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext),
258 .third_path = mt2712_mtk_ddp_third,
259 .third_len = ARRAY_SIZE(mt2712_mtk_ddp_third),
260 .mmsys_dev_num = 1,
261};
262
263static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
264 .main_path = mt8167_mtk_ddp_main,
265 .main_len = ARRAY_SIZE(mt8167_mtk_ddp_main),
266 .mmsys_dev_num = 1,
267};
268
269static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
270 .main_path = mt8173_mtk_ddp_main,
271 .main_len = ARRAY_SIZE(mt8173_mtk_ddp_main),
272 .ext_path = mt8173_mtk_ddp_ext,
273 .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
274 .mmsys_dev_num = 1,
275};
276
277static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
278 .main_path = mt8183_mtk_ddp_main,
279 .main_len = ARRAY_SIZE(mt8183_mtk_ddp_main),
280 .ext_path = mt8183_mtk_ddp_ext,
281 .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
282 .mmsys_dev_num = 1,
283};
284
285static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
286 .main_path = mt8186_mtk_ddp_main,
287 .main_len = ARRAY_SIZE(mt8186_mtk_ddp_main),
288 .ext_path = mt8186_mtk_ddp_ext,
289 .ext_len = ARRAY_SIZE(mt8186_mtk_ddp_ext),
290 .mmsys_dev_num = 1,
291};
292
293static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = {
294 .main_path = mt8188_mtk_ddp_main,
295 .main_len = ARRAY_SIZE(mt8188_mtk_ddp_main),
296 .conn_routes = mt8188_mtk_ddp_main_routes,
297 .num_conn_routes = ARRAY_SIZE(mt8188_mtk_ddp_main_routes),
298 .mmsys_dev_num = 2,
299 .max_width = 8191,
300 .min_width = 1,
301 .min_height = 1,
302};
303
304static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
305 .main_path = mt8192_mtk_ddp_main,
306 .main_len = ARRAY_SIZE(mt8192_mtk_ddp_main),
307 .ext_path = mt8192_mtk_ddp_ext,
308 .ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext),
309 .mmsys_dev_num = 1,
310};
311
312static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
313 .main_path = mt8195_mtk_ddp_main,
314 .main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
315 .mmsys_dev_num = 2,
316 .max_width = 8191,
317 .min_width = 1,
318 .min_height = 1,
319};
320
321static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
322 .ext_path = mt8195_mtk_ddp_ext,
323 .ext_len = ARRAY_SIZE(mt8195_mtk_ddp_ext),
324 .mmsys_id = 1,
325 .mmsys_dev_num = 2,
326 .max_width = 8191,
327 .min_width = 2, /* 2-pixel align when ethdr is bypassed */
328 .min_height = 1,
329};
330
331static const struct of_device_id mtk_drm_of_ids[] = {
332 { .compatible = "mediatek,mt2701-mmsys",
333 .data = &mt2701_mmsys_driver_data},
334 { .compatible = "mediatek,mt7623-mmsys",
335 .data = &mt7623_mmsys_driver_data},
336 { .compatible = "mediatek,mt2712-mmsys",
337 .data = &mt2712_mmsys_driver_data},
338 { .compatible = "mediatek,mt8167-mmsys",
339 .data = &mt8167_mmsys_driver_data},
340 { .compatible = "mediatek,mt8173-mmsys",
341 .data = &mt8173_mmsys_driver_data},
342 { .compatible = "mediatek,mt8183-mmsys",
343 .data = &mt8183_mmsys_driver_data},
344 { .compatible = "mediatek,mt8186-mmsys",
345 .data = &mt8186_mmsys_driver_data},
346 { .compatible = "mediatek,mt8188-vdosys0",
347 .data = &mt8188_vdosys0_driver_data},
348 { .compatible = "mediatek,mt8188-vdosys1",
349 .data = &mt8195_vdosys1_driver_data},
350 { .compatible = "mediatek,mt8192-mmsys",
351 .data = &mt8192_mmsys_driver_data},
352 { .compatible = "mediatek,mt8195-mmsys",
353 .data = &mt8195_vdosys0_driver_data},
354 { .compatible = "mediatek,mt8195-vdosys0",
355 .data = &mt8195_vdosys0_driver_data},
356 { .compatible = "mediatek,mt8195-vdosys1",
357 .data = &mt8195_vdosys1_driver_data},
358 { }
359};
360MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
361
362static int mtk_drm_match(struct device *dev, void *data)
363{
364 if (!strncmp(dev_name(dev), "mediatek-drm", sizeof("mediatek-drm") - 1))
365 return true;
366 return false;
367}
368
369static bool mtk_drm_get_all_drm_priv(struct device *dev)
370{
371 struct mtk_drm_private *drm_priv = dev_get_drvdata(dev);
372 struct mtk_drm_private *all_drm_priv[MAX_CRTC];
373 struct mtk_drm_private *temp_drm_priv;
374 struct device_node *phandle = dev->parent->of_node;
375 const struct of_device_id *of_id;
376 struct device_node *node;
377 struct device *drm_dev;
378 unsigned int cnt = 0;
379 int i, j;
380
381 for_each_child_of_node(phandle->parent, node) {
382 struct platform_device *pdev;
383
384 of_id = of_match_node(mtk_drm_of_ids, node);
385 if (!of_id)
386 continue;
387
388 pdev = of_find_device_by_node(node);
389 if (!pdev)
390 continue;
391
392 drm_dev = device_find_child(&pdev->dev, NULL, mtk_drm_match);
393 if (!drm_dev)
394 continue;
395
396 temp_drm_priv = dev_get_drvdata(drm_dev);
397 if (!temp_drm_priv)
398 continue;
399
400 if (temp_drm_priv->data->main_len)
401 all_drm_priv[CRTC_MAIN] = temp_drm_priv;
402 else if (temp_drm_priv->data->ext_len)
403 all_drm_priv[CRTC_EXT] = temp_drm_priv;
404 else if (temp_drm_priv->data->third_len)
405 all_drm_priv[CRTC_THIRD] = temp_drm_priv;
406
407 if (temp_drm_priv->mtk_drm_bound)
408 cnt++;
409
410 if (cnt == MAX_CRTC) {
411 of_node_put(node);
412 break;
413 }
414 }
415
416 if (drm_priv->data->mmsys_dev_num == cnt) {
417 for (i = 0; i < cnt; i++)
418 for (j = 0; j < cnt; j++)
419 all_drm_priv[j]->all_drm_private[i] = all_drm_priv[i];
420
421 return true;
422 }
423
424 return false;
425}
426
427static bool mtk_drm_find_mmsys_comp(struct mtk_drm_private *private, int comp_id)
428{
429 const struct mtk_mmsys_driver_data *drv_data = private->data;
430 int i;
431
432 if (drv_data->main_path)
433 for (i = 0; i < drv_data->main_len; i++)
434 if (drv_data->main_path[i] == comp_id)
435 return true;
436
437 if (drv_data->ext_path)
438 for (i = 0; i < drv_data->ext_len; i++)
439 if (drv_data->ext_path[i] == comp_id)
440 return true;
441
442 if (drv_data->third_path)
443 for (i = 0; i < drv_data->third_len; i++)
444 if (drv_data->third_path[i] == comp_id)
445 return true;
446
447 if (drv_data->num_conn_routes)
448 for (i = 0; i < drv_data->num_conn_routes; i++)
449 if (drv_data->conn_routes[i].route_ddp == comp_id)
450 return true;
451
452 return false;
453}
454
455static int mtk_drm_kms_init(struct drm_device *drm)
456{
457 struct mtk_drm_private *private = drm->dev_private;
458 struct mtk_drm_private *priv_n;
459 struct device *dma_dev = NULL;
460 struct drm_crtc *crtc;
461 int ret, i, j;
462
463 if (drm_firmware_drivers_only())
464 return -ENODEV;
465
466 ret = drmm_mode_config_init(drm);
467 if (ret)
468 goto put_mutex_dev;
469
470 drm->mode_config.min_width = 64;
471 drm->mode_config.min_height = 64;
472
473 /*
474 * set max width and height as default value(4096x4096).
475 * this value would be used to check framebuffer size limitation
476 * at drm_mode_addfb().
477 */
478 drm->mode_config.max_width = 4096;
479 drm->mode_config.max_height = 4096;
480 drm->mode_config.funcs = &mtk_drm_mode_config_funcs;
481 drm->mode_config.helper_private = &mtk_drm_mode_config_helpers;
482
483 for (i = 0; i < private->data->mmsys_dev_num; i++) {
484 drm->dev_private = private->all_drm_private[i];
485 ret = component_bind_all(private->all_drm_private[i]->dev, drm);
486 if (ret)
487 goto put_mutex_dev;
488 }
489
490 /*
491 * Ensure internal panels are at the top of the connector list before
492 * crtc creation.
493 */
494 drm_helper_move_panel_connectors_to_head(drm);
495
496 /*
497 * 1. We currently support two fixed data streams, each optional,
498 * and each statically assigned to a crtc:
499 * OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0 ...
500 * 2. For multi mmsys architecture, crtc path data are located in
501 * different drm private data structures. Loop through crtc index to
502 * create crtc from the main path and then ext_path and finally the
503 * third path.
504 */
505 for (i = 0; i < MAX_CRTC; i++) {
506 for (j = 0; j < private->data->mmsys_dev_num; j++) {
507 priv_n = private->all_drm_private[j];
508
509 if (priv_n->data->max_width)
510 drm->mode_config.max_width = priv_n->data->max_width;
511
512 if (priv_n->data->min_width)
513 drm->mode_config.min_width = priv_n->data->min_width;
514
515 if (priv_n->data->min_height)
516 drm->mode_config.min_height = priv_n->data->min_height;
517
518 if (i == CRTC_MAIN && priv_n->data->main_len) {
519 ret = mtk_crtc_create(drm, priv_n->data->main_path,
520 priv_n->data->main_len, j,
521 priv_n->data->conn_routes,
522 priv_n->data->num_conn_routes);
523 if (ret)
524 goto err_component_unbind;
525
526 continue;
527 } else if (i == CRTC_EXT && priv_n->data->ext_len) {
528 ret = mtk_crtc_create(drm, priv_n->data->ext_path,
529 priv_n->data->ext_len, j, NULL, 0);
530 if (ret)
531 goto err_component_unbind;
532
533 continue;
534 } else if (i == CRTC_THIRD && priv_n->data->third_len) {
535 ret = mtk_crtc_create(drm, priv_n->data->third_path,
536 priv_n->data->third_len, j, NULL, 0);
537 if (ret)
538 goto err_component_unbind;
539
540 continue;
541 }
542 }
543 }
544
545 /* IGT will check if the cursor size is configured */
546 drm->mode_config.cursor_width = 512;
547 drm->mode_config.cursor_height = 512;
548
549 /* Use OVL device for all DMA memory allocations */
550 crtc = drm_crtc_from_index(drm, 0);
551 if (crtc)
552 dma_dev = mtk_crtc_dma_dev_get(crtc);
553 if (!dma_dev) {
554 ret = -ENODEV;
555 dev_err(drm->dev, "Need at least one OVL device\n");
556 goto err_component_unbind;
557 }
558
559 for (i = 0; i < private->data->mmsys_dev_num; i++)
560 private->all_drm_private[i]->dma_dev = dma_dev;
561
562 /*
563 * Configure the DMA segment size to make sure we get contiguous IOVA
564 * when importing PRIME buffers.
565 */
566 dma_set_max_seg_size(dma_dev, UINT_MAX);
567
568 ret = drm_vblank_init(drm, MAX_CRTC);
569 if (ret < 0)
570 goto err_component_unbind;
571
572 drm_kms_helper_poll_init(drm);
573 drm_mode_config_reset(drm);
574
575 return 0;
576
577err_component_unbind:
578 for (i = 0; i < private->data->mmsys_dev_num; i++)
579 component_unbind_all(private->all_drm_private[i]->dev, drm);
580put_mutex_dev:
581 for (i = 0; i < private->data->mmsys_dev_num; i++)
582 put_device(private->all_drm_private[i]->mutex_dev);
583
584 return ret;
585}
586
587static void mtk_drm_kms_deinit(struct drm_device *drm)
588{
589 drm_kms_helper_poll_fini(drm);
590 drm_atomic_helper_shutdown(drm);
591
592 component_unbind_all(drm->dev, drm);
593}
594
595DEFINE_DRM_GEM_FOPS(mtk_drm_fops);
596
597/*
598 * We need to override this because the device used to import the memory is
599 * not dev->dev, as drm_gem_prime_import() expects.
600 */
601static struct drm_gem_object *mtk_gem_prime_import(struct drm_device *dev,
602 struct dma_buf *dma_buf)
603{
604 struct mtk_drm_private *private = dev->dev_private;
605
606 return drm_gem_prime_import_dev(dev, dma_buf, private->dma_dev);
607}
608
609static const struct drm_driver mtk_drm_driver = {
610 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC,
611
612 .dumb_create = mtk_gem_dumb_create,
613 DRM_FBDEV_DMA_DRIVER_OPS,
614
615 .gem_prime_import = mtk_gem_prime_import,
616 .gem_prime_import_sg_table = mtk_gem_prime_import_sg_table,
617 .fops = &mtk_drm_fops,
618
619 .name = DRIVER_NAME,
620 .desc = DRIVER_DESC,
621 .date = DRIVER_DATE,
622 .major = DRIVER_MAJOR,
623 .minor = DRIVER_MINOR,
624};
625
626static int compare_dev(struct device *dev, void *data)
627{
628 return dev == (struct device *)data;
629}
630
631static int mtk_drm_bind(struct device *dev)
632{
633 struct mtk_drm_private *private = dev_get_drvdata(dev);
634 struct platform_device *pdev;
635 struct drm_device *drm;
636 int ret, i;
637
638 pdev = of_find_device_by_node(private->mutex_node);
639 if (!pdev) {
640 dev_err(dev, "Waiting for disp-mutex device %pOF\n",
641 private->mutex_node);
642 of_node_put(private->mutex_node);
643 return -EPROBE_DEFER;
644 }
645
646 private->mutex_dev = &pdev->dev;
647 private->mtk_drm_bound = true;
648 private->dev = dev;
649
650 if (!mtk_drm_get_all_drm_priv(dev))
651 return 0;
652
653 drm = drm_dev_alloc(&mtk_drm_driver, dev);
654 if (IS_ERR(drm))
655 return PTR_ERR(drm);
656
657 private->drm_master = true;
658 drm->dev_private = private;
659 for (i = 0; i < private->data->mmsys_dev_num; i++)
660 private->all_drm_private[i]->drm = drm;
661
662 ret = mtk_drm_kms_init(drm);
663 if (ret < 0)
664 goto err_free;
665
666 ret = drm_dev_register(drm, 0);
667 if (ret < 0)
668 goto err_deinit;
669
670 drm_client_setup(drm, NULL);
671
672 return 0;
673
674err_deinit:
675 mtk_drm_kms_deinit(drm);
676err_free:
677 private->drm = NULL;
678 drm_dev_put(drm);
679 for (i = 0; i < private->data->mmsys_dev_num; i++)
680 private->all_drm_private[i]->drm = NULL;
681 return ret;
682}
683
684static void mtk_drm_unbind(struct device *dev)
685{
686 struct mtk_drm_private *private = dev_get_drvdata(dev);
687
688 /* for multi mmsys dev, unregister drm dev in mmsys master */
689 if (private->drm_master) {
690 drm_dev_unregister(private->drm);
691 mtk_drm_kms_deinit(private->drm);
692 drm_dev_put(private->drm);
693 }
694 private->mtk_drm_bound = false;
695 private->drm_master = false;
696 private->drm = NULL;
697}
698
699static const struct component_master_ops mtk_drm_ops = {
700 .bind = mtk_drm_bind,
701 .unbind = mtk_drm_unbind,
702};
703
704static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
705 { .compatible = "mediatek,mt8167-disp-aal",
706 .data = (void *)MTK_DISP_AAL},
707 { .compatible = "mediatek,mt8173-disp-aal",
708 .data = (void *)MTK_DISP_AAL},
709 { .compatible = "mediatek,mt8183-disp-aal",
710 .data = (void *)MTK_DISP_AAL},
711 { .compatible = "mediatek,mt8192-disp-aal",
712 .data = (void *)MTK_DISP_AAL},
713 { .compatible = "mediatek,mt8167-disp-ccorr",
714 .data = (void *)MTK_DISP_CCORR },
715 { .compatible = "mediatek,mt8183-disp-ccorr",
716 .data = (void *)MTK_DISP_CCORR },
717 { .compatible = "mediatek,mt8192-disp-ccorr",
718 .data = (void *)MTK_DISP_CCORR },
719 { .compatible = "mediatek,mt2701-disp-color",
720 .data = (void *)MTK_DISP_COLOR },
721 { .compatible = "mediatek,mt8167-disp-color",
722 .data = (void *)MTK_DISP_COLOR },
723 { .compatible = "mediatek,mt8173-disp-color",
724 .data = (void *)MTK_DISP_COLOR },
725 { .compatible = "mediatek,mt8167-disp-dither",
726 .data = (void *)MTK_DISP_DITHER },
727 { .compatible = "mediatek,mt8183-disp-dither",
728 .data = (void *)MTK_DISP_DITHER },
729 { .compatible = "mediatek,mt8195-disp-dsc",
730 .data = (void *)MTK_DISP_DSC },
731 { .compatible = "mediatek,mt8167-disp-gamma",
732 .data = (void *)MTK_DISP_GAMMA, },
733 { .compatible = "mediatek,mt8173-disp-gamma",
734 .data = (void *)MTK_DISP_GAMMA, },
735 { .compatible = "mediatek,mt8183-disp-gamma",
736 .data = (void *)MTK_DISP_GAMMA, },
737 { .compatible = "mediatek,mt8195-disp-gamma",
738 .data = (void *)MTK_DISP_GAMMA, },
739 { .compatible = "mediatek,mt8195-disp-merge",
740 .data = (void *)MTK_DISP_MERGE },
741 { .compatible = "mediatek,mt2701-disp-mutex",
742 .data = (void *)MTK_DISP_MUTEX },
743 { .compatible = "mediatek,mt2712-disp-mutex",
744 .data = (void *)MTK_DISP_MUTEX },
745 { .compatible = "mediatek,mt8167-disp-mutex",
746 .data = (void *)MTK_DISP_MUTEX },
747 { .compatible = "mediatek,mt8173-disp-mutex",
748 .data = (void *)MTK_DISP_MUTEX },
749 { .compatible = "mediatek,mt8183-disp-mutex",
750 .data = (void *)MTK_DISP_MUTEX },
751 { .compatible = "mediatek,mt8186-disp-mutex",
752 .data = (void *)MTK_DISP_MUTEX },
753 { .compatible = "mediatek,mt8188-disp-mutex",
754 .data = (void *)MTK_DISP_MUTEX },
755 { .compatible = "mediatek,mt8192-disp-mutex",
756 .data = (void *)MTK_DISP_MUTEX },
757 { .compatible = "mediatek,mt8195-disp-mutex",
758 .data = (void *)MTK_DISP_MUTEX },
759 { .compatible = "mediatek,mt8173-disp-od",
760 .data = (void *)MTK_DISP_OD },
761 { .compatible = "mediatek,mt2701-disp-ovl",
762 .data = (void *)MTK_DISP_OVL },
763 { .compatible = "mediatek,mt8167-disp-ovl",
764 .data = (void *)MTK_DISP_OVL },
765 { .compatible = "mediatek,mt8173-disp-ovl",
766 .data = (void *)MTK_DISP_OVL },
767 { .compatible = "mediatek,mt8183-disp-ovl",
768 .data = (void *)MTK_DISP_OVL },
769 { .compatible = "mediatek,mt8192-disp-ovl",
770 .data = (void *)MTK_DISP_OVL },
771 { .compatible = "mediatek,mt8195-disp-ovl",
772 .data = (void *)MTK_DISP_OVL },
773 { .compatible = "mediatek,mt8183-disp-ovl-2l",
774 .data = (void *)MTK_DISP_OVL_2L },
775 { .compatible = "mediatek,mt8192-disp-ovl-2l",
776 .data = (void *)MTK_DISP_OVL_2L },
777 { .compatible = "mediatek,mt8192-disp-postmask",
778 .data = (void *)MTK_DISP_POSTMASK },
779 { .compatible = "mediatek,mt2701-disp-pwm",
780 .data = (void *)MTK_DISP_BLS },
781 { .compatible = "mediatek,mt8167-disp-pwm",
782 .data = (void *)MTK_DISP_PWM },
783 { .compatible = "mediatek,mt8173-disp-pwm",
784 .data = (void *)MTK_DISP_PWM },
785 { .compatible = "mediatek,mt2701-disp-rdma",
786 .data = (void *)MTK_DISP_RDMA },
787 { .compatible = "mediatek,mt8167-disp-rdma",
788 .data = (void *)MTK_DISP_RDMA },
789 { .compatible = "mediatek,mt8173-disp-rdma",
790 .data = (void *)MTK_DISP_RDMA },
791 { .compatible = "mediatek,mt8183-disp-rdma",
792 .data = (void *)MTK_DISP_RDMA },
793 { .compatible = "mediatek,mt8195-disp-rdma",
794 .data = (void *)MTK_DISP_RDMA },
795 { .compatible = "mediatek,mt8173-disp-ufoe",
796 .data = (void *)MTK_DISP_UFOE },
797 { .compatible = "mediatek,mt8173-disp-wdma",
798 .data = (void *)MTK_DISP_WDMA },
799 { .compatible = "mediatek,mt2701-dpi",
800 .data = (void *)MTK_DPI },
801 { .compatible = "mediatek,mt8167-dsi",
802 .data = (void *)MTK_DSI },
803 { .compatible = "mediatek,mt8173-dpi",
804 .data = (void *)MTK_DPI },
805 { .compatible = "mediatek,mt8183-dpi",
806 .data = (void *)MTK_DPI },
807 { .compatible = "mediatek,mt8186-dpi",
808 .data = (void *)MTK_DPI },
809 { .compatible = "mediatek,mt8188-dp-intf",
810 .data = (void *)MTK_DP_INTF },
811 { .compatible = "mediatek,mt8192-dpi",
812 .data = (void *)MTK_DPI },
813 { .compatible = "mediatek,mt8195-dp-intf",
814 .data = (void *)MTK_DP_INTF },
815 { .compatible = "mediatek,mt2701-dsi",
816 .data = (void *)MTK_DSI },
817 { .compatible = "mediatek,mt8173-dsi",
818 .data = (void *)MTK_DSI },
819 { .compatible = "mediatek,mt8183-dsi",
820 .data = (void *)MTK_DSI },
821 { .compatible = "mediatek,mt8186-dsi",
822 .data = (void *)MTK_DSI },
823 { .compatible = "mediatek,mt8188-dsi",
824 .data = (void *)MTK_DSI },
825 { }
826};
827
828static int mtk_drm_of_get_ddp_comp_type(struct device_node *node, enum mtk_ddp_comp_type *ctype)
829{
830 const struct of_device_id *of_id = of_match_node(mtk_ddp_comp_dt_ids, node);
831
832 if (!of_id)
833 return -EINVAL;
834
835 *ctype = (enum mtk_ddp_comp_type)((uintptr_t)of_id->data);
836
837 return 0;
838}
839
840static int mtk_drm_of_get_ddp_ep_cid(struct device_node *node,
841 int output_port, enum mtk_crtc_path crtc_path,
842 struct device_node **next, unsigned int *cid)
843{
844 struct device_node *ep_dev_node, *ep_out;
845 enum mtk_ddp_comp_type comp_type;
846 int ret;
847
848 ep_out = of_graph_get_endpoint_by_regs(node, output_port, crtc_path);
849 if (!ep_out)
850 return -ENOENT;
851
852 ep_dev_node = of_graph_get_remote_port_parent(ep_out);
853 of_node_put(ep_out);
854 if (!ep_dev_node)
855 return -EINVAL;
856
857 /*
858 * Pass the next node pointer regardless of failures in the later code
859 * so that if this function is called in a loop it will walk through all
860 * of the subsequent endpoints anyway.
861 */
862 *next = ep_dev_node;
863
864 if (!of_device_is_available(ep_dev_node))
865 return -ENODEV;
866
867 ret = mtk_drm_of_get_ddp_comp_type(ep_dev_node, &comp_type);
868 if (ret) {
869 if (mtk_ovl_adaptor_is_comp_present(ep_dev_node)) {
870 *cid = (unsigned int)DDP_COMPONENT_DRM_OVL_ADAPTOR;
871 return 0;
872 }
873 return ret;
874 }
875
876 ret = mtk_ddp_comp_get_id(ep_dev_node, comp_type);
877 if (ret < 0)
878 return ret;
879
880 /* All ok! Pass the Component ID to the caller. */
881 *cid = (unsigned int)ret;
882
883 return 0;
884}
885
886/**
887 * mtk_drm_of_ddp_path_build_one - Build a Display HW Pipeline for a CRTC Path
888 * @dev: The mediatek-drm device
889 * @cpath: CRTC Path relative to a VDO or MMSYS
890 * @out_path: Pointer to an array that will contain the new pipeline
891 * @out_path_len: Number of entries in the pipeline array
892 *
893 * MediaTek SoCs can use different DDP hardware pipelines (or paths) depending
894 * on the board-specific desired display configuration; this function walks
895 * through all of the output endpoints starting from a VDO or MMSYS hardware
896 * instance and builds the right pipeline as specified in device trees.
897 *
898 * Return:
899 * * %0 - Display HW Pipeline successfully built and validated
900 * * %-ENOENT - Display pipeline was not specified in device tree
901 * * %-EINVAL - Display pipeline built but validation failed
902 * * %-ENOMEM - Failure to allocate pipeline array to pass to the caller
903 */
904static int mtk_drm_of_ddp_path_build_one(struct device *dev, enum mtk_crtc_path cpath,
905 const unsigned int **out_path,
906 unsigned int *out_path_len)
907{
908 struct device_node *next = NULL, *prev, *vdo = dev->parent->of_node;
909 unsigned int temp_path[DDP_COMPONENT_DRM_ID_MAX] = { 0 };
910 unsigned int *final_ddp_path;
911 unsigned short int idx = 0;
912 bool ovl_adaptor_comp_added = false;
913 int ret;
914
915 /* Get the first entry for the temp_path array */
916 ret = mtk_drm_of_get_ddp_ep_cid(vdo, 0, cpath, &next, &temp_path[idx]);
917 if (ret) {
918 if (next && temp_path[idx] == DDP_COMPONENT_DRM_OVL_ADAPTOR) {
919 dev_dbg(dev, "Adding OVL Adaptor for %pOF\n", next);
920 ovl_adaptor_comp_added = true;
921 } else {
922 if (next)
923 dev_err(dev, "Invalid component %pOF\n", next);
924 else
925 dev_err(dev, "Cannot find first endpoint for path %d\n", cpath);
926
927 return ret;
928 }
929 }
930 idx++;
931
932 /*
933 * Walk through port outputs until we reach the last valid mediatek-drm component.
934 * To be valid, this must end with an "invalid" component that is a display node.
935 */
936 do {
937 prev = next;
938 ret = mtk_drm_of_get_ddp_ep_cid(next, 1, cpath, &next, &temp_path[idx]);
939 of_node_put(prev);
940 if (ret) {
941 of_node_put(next);
942 break;
943 }
944
945 /*
946 * If this is an OVL adaptor exclusive component and one of those
947 * was already added, don't add another instance of the generic
948 * DDP_COMPONENT_OVL_ADAPTOR, as this is used only to decide whether
949 * to probe that component master driver of which only one instance
950 * is needed and possible.
951 */
952 if (temp_path[idx] == DDP_COMPONENT_DRM_OVL_ADAPTOR) {
953 if (!ovl_adaptor_comp_added)
954 ovl_adaptor_comp_added = true;
955 else
956 idx--;
957 }
958 } while (++idx < DDP_COMPONENT_DRM_ID_MAX);
959
960 /*
961 * The device component might not be enabled: in that case, don't
962 * check the last entry and just report that the device is missing.
963 */
964 if (ret == -ENODEV)
965 return ret;
966
967 /* If the last entry is not a final display output, the configuration is wrong */
968 switch (temp_path[idx - 1]) {
969 case DDP_COMPONENT_DP_INTF0:
970 case DDP_COMPONENT_DP_INTF1:
971 case DDP_COMPONENT_DPI0:
972 case DDP_COMPONENT_DPI1:
973 case DDP_COMPONENT_DSI0:
974 case DDP_COMPONENT_DSI1:
975 case DDP_COMPONENT_DSI2:
976 case DDP_COMPONENT_DSI3:
977 break;
978 default:
979 dev_err(dev, "Invalid display hw pipeline. Last component: %d (ret=%d)\n",
980 temp_path[idx - 1], ret);
981 return -EINVAL;
982 }
983
984 final_ddp_path = devm_kmemdup(dev, temp_path, idx * sizeof(temp_path[0]), GFP_KERNEL);
985 if (!final_ddp_path)
986 return -ENOMEM;
987
988 dev_dbg(dev, "Display HW Pipeline built with %d components.\n", idx);
989
990 /* Pipeline built! */
991 *out_path = final_ddp_path;
992 *out_path_len = idx;
993
994 return 0;
995}
996
997static int mtk_drm_of_ddp_path_build(struct device *dev, struct device_node *node,
998 struct mtk_mmsys_driver_data *data)
999{
1000 struct device_node *ep_node;
1001 struct of_endpoint of_ep;
1002 bool output_present[MAX_CRTC] = { false };
1003 int ret;
1004
1005 for_each_endpoint_of_node(node, ep_node) {
1006 ret = of_graph_parse_endpoint(ep_node, &of_ep);
1007 if (ret) {
1008 dev_err_probe(dev, ret, "Cannot parse endpoint\n");
1009 break;
1010 }
1011
1012 if (of_ep.id >= MAX_CRTC) {
1013 ret = dev_err_probe(dev, -EINVAL,
1014 "Invalid endpoint%u number\n", of_ep.port);
1015 break;
1016 }
1017
1018 output_present[of_ep.id] = true;
1019 }
1020
1021 if (ret) {
1022 of_node_put(ep_node);
1023 return ret;
1024 }
1025
1026 if (output_present[CRTC_MAIN]) {
1027 ret = mtk_drm_of_ddp_path_build_one(dev, CRTC_MAIN,
1028 &data->main_path, &data->main_len);
1029 if (ret && ret != -ENODEV)
1030 return ret;
1031 }
1032
1033 if (output_present[CRTC_EXT]) {
1034 ret = mtk_drm_of_ddp_path_build_one(dev, CRTC_EXT,
1035 &data->ext_path, &data->ext_len);
1036 if (ret && ret != -ENODEV)
1037 return ret;
1038 }
1039
1040 if (output_present[CRTC_THIRD]) {
1041 ret = mtk_drm_of_ddp_path_build_one(dev, CRTC_THIRD,
1042 &data->third_path, &data->third_len);
1043 if (ret && ret != -ENODEV)
1044 return ret;
1045 }
1046
1047 return 0;
1048}
1049
1050static int mtk_drm_probe(struct platform_device *pdev)
1051{
1052 struct device *dev = &pdev->dev;
1053 struct device_node *phandle = dev->parent->of_node;
1054 const struct of_device_id *of_id;
1055 struct mtk_drm_private *private;
1056 struct mtk_mmsys_driver_data *mtk_drm_data;
1057 struct device_node *node;
1058 struct component_match *match = NULL;
1059 struct platform_device *ovl_adaptor;
1060 int ret;
1061 int i;
1062
1063 private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL);
1064 if (!private)
1065 return -ENOMEM;
1066
1067 private->mmsys_dev = dev->parent;
1068 if (!private->mmsys_dev) {
1069 dev_err(dev, "Failed to get MMSYS device\n");
1070 return -ENODEV;
1071 }
1072
1073 of_id = of_match_node(mtk_drm_of_ids, phandle);
1074 if (!of_id)
1075 return -ENODEV;
1076
1077 mtk_drm_data = (struct mtk_mmsys_driver_data *)of_id->data;
1078 if (!mtk_drm_data)
1079 return -EINVAL;
1080
1081 /* Try to build the display pipeline from devicetree graphs */
1082 if (of_graph_is_present(phandle)) {
1083 dev_dbg(dev, "Building display pipeline for MMSYS %u\n",
1084 mtk_drm_data->mmsys_id);
1085 private->data = devm_kmemdup(dev, mtk_drm_data,
1086 sizeof(*mtk_drm_data), GFP_KERNEL);
1087 if (!private->data)
1088 return -ENOMEM;
1089
1090 ret = mtk_drm_of_ddp_path_build(dev, phandle, private->data);
1091 if (ret)
1092 return ret;
1093 } else {
1094 /* No devicetree graphs support: go with hardcoded paths if present */
1095 dev_dbg(dev, "Using hardcoded paths for MMSYS %u\n", mtk_drm_data->mmsys_id);
1096 private->data = mtk_drm_data;
1097 }
1098
1099 private->all_drm_private = devm_kmalloc_array(dev, private->data->mmsys_dev_num,
1100 sizeof(*private->all_drm_private),
1101 GFP_KERNEL);
1102 if (!private->all_drm_private)
1103 return -ENOMEM;
1104
1105 /* Bringup ovl_adaptor */
1106 if (mtk_drm_find_mmsys_comp(private, DDP_COMPONENT_DRM_OVL_ADAPTOR)) {
1107 ovl_adaptor = platform_device_register_data(dev, "mediatek-disp-ovl-adaptor",
1108 PLATFORM_DEVID_AUTO,
1109 (void *)private->mmsys_dev,
1110 sizeof(*private->mmsys_dev));
1111 private->ddp_comp[DDP_COMPONENT_DRM_OVL_ADAPTOR].dev = &ovl_adaptor->dev;
1112 mtk_ddp_comp_init(NULL, &private->ddp_comp[DDP_COMPONENT_DRM_OVL_ADAPTOR],
1113 DDP_COMPONENT_DRM_OVL_ADAPTOR);
1114 component_match_add(dev, &match, compare_dev, &ovl_adaptor->dev);
1115 }
1116
1117 /* Iterate over sibling DISP function blocks */
1118 for_each_child_of_node(phandle->parent, node) {
1119 enum mtk_ddp_comp_type comp_type;
1120 int comp_id;
1121
1122 ret = mtk_drm_of_get_ddp_comp_type(node, &comp_type);
1123 if (ret)
1124 continue;
1125
1126 if (!of_device_is_available(node)) {
1127 dev_dbg(dev, "Skipping disabled component %pOF\n",
1128 node);
1129 continue;
1130 }
1131
1132 if (comp_type == MTK_DISP_MUTEX) {
1133 int id;
1134
1135 id = of_alias_get_id(node, "mutex");
1136 if (id < 0 || id == private->data->mmsys_id) {
1137 private->mutex_node = of_node_get(node);
1138 dev_dbg(dev, "get mutex for mmsys %d", private->data->mmsys_id);
1139 }
1140 continue;
1141 }
1142
1143 comp_id = mtk_ddp_comp_get_id(node, comp_type);
1144 if (comp_id < 0) {
1145 dev_warn(dev, "Skipping unknown component %pOF\n",
1146 node);
1147 continue;
1148 }
1149
1150 if (!mtk_drm_find_mmsys_comp(private, comp_id))
1151 continue;
1152
1153 private->comp_node[comp_id] = of_node_get(node);
1154
1155 /*
1156 * Currently only the AAL, CCORR, COLOR, GAMMA, MERGE, OVL, RDMA, DSI, and DPI
1157 * blocks have separate component platform drivers and initialize their own
1158 * DDP component structure. The others are initialized here.
1159 */
1160 if (comp_type == MTK_DISP_AAL ||
1161 comp_type == MTK_DISP_CCORR ||
1162 comp_type == MTK_DISP_COLOR ||
1163 comp_type == MTK_DISP_GAMMA ||
1164 comp_type == MTK_DISP_MERGE ||
1165 comp_type == MTK_DISP_OVL ||
1166 comp_type == MTK_DISP_OVL_2L ||
1167 comp_type == MTK_DISP_OVL_ADAPTOR ||
1168 comp_type == MTK_DISP_RDMA ||
1169 comp_type == MTK_DP_INTF ||
1170 comp_type == MTK_DPI ||
1171 comp_type == MTK_DSI) {
1172 dev_info(dev, "Adding component match for %pOF\n",
1173 node);
1174 drm_of_component_match_add(dev, &match, component_compare_of,
1175 node);
1176 }
1177
1178 ret = mtk_ddp_comp_init(node, &private->ddp_comp[comp_id], comp_id);
1179 if (ret) {
1180 of_node_put(node);
1181 goto err_node;
1182 }
1183 }
1184
1185 if (!private->mutex_node) {
1186 dev_err(dev, "Failed to find disp-mutex node\n");
1187 ret = -ENODEV;
1188 goto err_node;
1189 }
1190
1191 pm_runtime_enable(dev);
1192
1193 platform_set_drvdata(pdev, private);
1194
1195 ret = component_master_add_with_match(dev, &mtk_drm_ops, match);
1196 if (ret)
1197 goto err_pm;
1198
1199 return 0;
1200
1201err_pm:
1202 pm_runtime_disable(dev);
1203err_node:
1204 of_node_put(private->mutex_node);
1205 for (i = 0; i < DDP_COMPONENT_DRM_ID_MAX; i++)
1206 of_node_put(private->comp_node[i]);
1207 return ret;
1208}
1209
1210static void mtk_drm_remove(struct platform_device *pdev)
1211{
1212 struct mtk_drm_private *private = platform_get_drvdata(pdev);
1213 int i;
1214
1215 component_master_del(&pdev->dev, &mtk_drm_ops);
1216 pm_runtime_disable(&pdev->dev);
1217 of_node_put(private->mutex_node);
1218 for (i = 0; i < DDP_COMPONENT_DRM_ID_MAX; i++)
1219 of_node_put(private->comp_node[i]);
1220}
1221
1222static void mtk_drm_shutdown(struct platform_device *pdev)
1223{
1224 struct mtk_drm_private *private = platform_get_drvdata(pdev);
1225
1226 drm_atomic_helper_shutdown(private->drm);
1227}
1228
1229static int mtk_drm_sys_prepare(struct device *dev)
1230{
1231 struct mtk_drm_private *private = dev_get_drvdata(dev);
1232 struct drm_device *drm = private->drm;
1233
1234 if (private->drm_master)
1235 return drm_mode_config_helper_suspend(drm);
1236 else
1237 return 0;
1238}
1239
1240static void mtk_drm_sys_complete(struct device *dev)
1241{
1242 struct mtk_drm_private *private = dev_get_drvdata(dev);
1243 struct drm_device *drm = private->drm;
1244 int ret = 0;
1245
1246 if (private->drm_master)
1247 ret = drm_mode_config_helper_resume(drm);
1248 if (ret)
1249 dev_err(dev, "Failed to resume\n");
1250}
1251
1252static const struct dev_pm_ops mtk_drm_pm_ops = {
1253 .prepare = mtk_drm_sys_prepare,
1254 .complete = mtk_drm_sys_complete,
1255};
1256
1257static struct platform_driver mtk_drm_platform_driver = {
1258 .probe = mtk_drm_probe,
1259 .remove = mtk_drm_remove,
1260 .shutdown = mtk_drm_shutdown,
1261 .driver = {
1262 .name = "mediatek-drm",
1263 .pm = &mtk_drm_pm_ops,
1264 },
1265};
1266
1267static struct platform_driver * const mtk_drm_drivers[] = {
1268 &mtk_disp_aal_driver,
1269 &mtk_disp_ccorr_driver,
1270 &mtk_disp_color_driver,
1271 &mtk_disp_gamma_driver,
1272 &mtk_disp_merge_driver,
1273 &mtk_disp_ovl_adaptor_driver,
1274 &mtk_disp_ovl_driver,
1275 &mtk_disp_rdma_driver,
1276 &mtk_dpi_driver,
1277 &mtk_drm_platform_driver,
1278 &mtk_dsi_driver,
1279 &mtk_ethdr_driver,
1280 &mtk_mdp_rdma_driver,
1281 &mtk_padding_driver,
1282};
1283
1284static int __init mtk_drm_init(void)
1285{
1286 return platform_register_drivers(mtk_drm_drivers,
1287 ARRAY_SIZE(mtk_drm_drivers));
1288}
1289
1290static void __exit mtk_drm_exit(void)
1291{
1292 platform_unregister_drivers(mtk_drm_drivers,
1293 ARRAY_SIZE(mtk_drm_drivers));
1294}
1295
1296module_init(mtk_drm_init);
1297module_exit(mtk_drm_exit);
1298
1299MODULE_AUTHOR("YT SHEN <yt.shen@mediatek.com>");
1300MODULE_DESCRIPTION("Mediatek SoC DRM driver");
1301MODULE_LICENSE("GPL v2");