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1/* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
2 * All Rights Reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
14 * of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef _I915_REG_H_
26#define _I915_REG_H_
27
28typedef struct {
29 uint32_t reg;
30} i915_reg_t;
31
32#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
33
34#define INVALID_MMIO_REG _MMIO(0)
35
36static inline uint32_t i915_mmio_reg_offset(i915_reg_t reg)
37{
38 return reg.reg;
39}
40
41static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b)
42{
43 return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b);
44}
45
46static inline bool i915_mmio_reg_valid(i915_reg_t reg)
47{
48 return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG);
49}
50
51#define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
52#define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b))
53#define _PLANE(plane, a, b) _PIPE(plane, a, b)
54#define _MMIO_PLANE(plane, a, b) _MMIO_PIPE(plane, a, b)
55#define _TRANS(tran, a, b) ((a) + (tran)*((b)-(a)))
56#define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b))
57#define _PORT(port, a, b) ((a) + (port)*((b)-(a)))
58#define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b))
59#define _PIPE3(pipe, a, b, c) ((pipe) == PIPE_A ? (a) : \
60 (pipe) == PIPE_B ? (b) : (c))
61#define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PIPE3(pipe, a, b, c))
62#define _PORT3(port, a, b, c) ((port) == PORT_A ? (a) : \
63 (port) == PORT_B ? (b) : (c))
64#define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PORT3(pipe, a, b, c))
65
66#define _MASKED_FIELD(mask, value) ({ \
67 if (__builtin_constant_p(mask)) \
68 BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \
69 if (__builtin_constant_p(value)) \
70 BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \
71 if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \
72 BUILD_BUG_ON_MSG((value) & ~(mask), \
73 "Incorrect value for mask"); \
74 (mask) << 16 | (value); })
75#define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
76#define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0))
77
78
79
80/* PCI config space */
81
82#define HPLLCC 0xc0 /* 85x only */
83#define GC_CLOCK_CONTROL_MASK (0x7 << 0)
84#define GC_CLOCK_133_200 (0 << 0)
85#define GC_CLOCK_100_200 (1 << 0)
86#define GC_CLOCK_100_133 (2 << 0)
87#define GC_CLOCK_133_266 (3 << 0)
88#define GC_CLOCK_133_200_2 (4 << 0)
89#define GC_CLOCK_133_266_2 (5 << 0)
90#define GC_CLOCK_166_266 (6 << 0)
91#define GC_CLOCK_166_250 (7 << 0)
92
93#define GCFGC2 0xda
94#define GCFGC 0xf0 /* 915+ only */
95#define GC_LOW_FREQUENCY_ENABLE (1 << 7)
96#define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
97#define GC_DISPLAY_CLOCK_333_MHZ (4 << 4)
98#define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4)
99#define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4)
100#define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4)
101#define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4)
102#define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4)
103#define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4)
104#define GC_DISPLAY_CLOCK_MASK (7 << 4)
105#define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
106#define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
107#define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
108#define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
109#define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
110#define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
111#define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
112#define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
113#define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
114#define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
115#define I945_GC_RENDER_CLOCK_MASK (7 << 0)
116#define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
117#define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
118#define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
119#define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
120#define I915_GC_RENDER_CLOCK_MASK (7 << 0)
121#define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
122#define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
123#define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
124#define GCDGMBUS 0xcc
125#define PCI_LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */
126
127
128/* Graphics reset regs */
129#define I915_GDRST 0xc0 /* PCI config register */
130#define GRDOM_FULL (0<<2)
131#define GRDOM_RENDER (1<<2)
132#define GRDOM_MEDIA (3<<2)
133#define GRDOM_MASK (3<<2)
134#define GRDOM_RESET_STATUS (1<<1)
135#define GRDOM_RESET_ENABLE (1<<0)
136
137#define ILK_GDSR _MMIO(MCHBAR_MIRROR_BASE + 0x2ca4)
138#define ILK_GRDOM_FULL (0<<1)
139#define ILK_GRDOM_RENDER (1<<1)
140#define ILK_GRDOM_MEDIA (3<<1)
141#define ILK_GRDOM_MASK (3<<1)
142#define ILK_GRDOM_RESET_ENABLE (1<<0)
143
144#define GEN6_MBCUNIT_SNPCR _MMIO(0x900c) /* for LLC config */
145#define GEN6_MBC_SNPCR_SHIFT 21
146#define GEN6_MBC_SNPCR_MASK (3<<21)
147#define GEN6_MBC_SNPCR_MAX (0<<21)
148#define GEN6_MBC_SNPCR_MED (1<<21)
149#define GEN6_MBC_SNPCR_LOW (2<<21)
150#define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */
151
152#define VLV_G3DCTL _MMIO(0x9024)
153#define VLV_GSCKGCTL _MMIO(0x9028)
154
155#define GEN6_MBCTL _MMIO(0x0907c)
156#define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4)
157#define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3)
158#define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2)
159#define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1)
160#define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0)
161
162#define GEN6_GDRST _MMIO(0x941c)
163#define GEN6_GRDOM_FULL (1 << 0)
164#define GEN6_GRDOM_RENDER (1 << 1)
165#define GEN6_GRDOM_MEDIA (1 << 2)
166#define GEN6_GRDOM_BLT (1 << 3)
167
168#define RING_PP_DIR_BASE(ring) _MMIO((ring)->mmio_base+0x228)
169#define RING_PP_DIR_BASE_READ(ring) _MMIO((ring)->mmio_base+0x518)
170#define RING_PP_DIR_DCLV(ring) _MMIO((ring)->mmio_base+0x220)
171#define PP_DIR_DCLV_2G 0xffffffff
172
173#define GEN8_RING_PDP_UDW(ring, n) _MMIO((ring)->mmio_base+0x270 + (n) * 8 + 4)
174#define GEN8_RING_PDP_LDW(ring, n) _MMIO((ring)->mmio_base+0x270 + (n) * 8)
175
176#define GEN8_R_PWR_CLK_STATE _MMIO(0x20C8)
177#define GEN8_RPCS_ENABLE (1 << 31)
178#define GEN8_RPCS_S_CNT_ENABLE (1 << 18)
179#define GEN8_RPCS_S_CNT_SHIFT 15
180#define GEN8_RPCS_S_CNT_MASK (0x7 << GEN8_RPCS_S_CNT_SHIFT)
181#define GEN8_RPCS_SS_CNT_ENABLE (1 << 11)
182#define GEN8_RPCS_SS_CNT_SHIFT 8
183#define GEN8_RPCS_SS_CNT_MASK (0x7 << GEN8_RPCS_SS_CNT_SHIFT)
184#define GEN8_RPCS_EU_MAX_SHIFT 4
185#define GEN8_RPCS_EU_MAX_MASK (0xf << GEN8_RPCS_EU_MAX_SHIFT)
186#define GEN8_RPCS_EU_MIN_SHIFT 0
187#define GEN8_RPCS_EU_MIN_MASK (0xf << GEN8_RPCS_EU_MIN_SHIFT)
188
189#define GAM_ECOCHK _MMIO(0x4090)
190#define BDW_DISABLE_HDC_INVALIDATION (1<<25)
191#define ECOCHK_SNB_BIT (1<<10)
192#define ECOCHK_DIS_TLB (1<<8)
193#define HSW_ECOCHK_ARB_PRIO_SOL (1<<6)
194#define ECOCHK_PPGTT_CACHE64B (0x3<<3)
195#define ECOCHK_PPGTT_CACHE4B (0x0<<3)
196#define ECOCHK_PPGTT_GFDT_IVB (0x1<<4)
197#define ECOCHK_PPGTT_LLC_IVB (0x1<<3)
198#define ECOCHK_PPGTT_UC_HSW (0x1<<3)
199#define ECOCHK_PPGTT_WT_HSW (0x2<<3)
200#define ECOCHK_PPGTT_WB_HSW (0x3<<3)
201
202#define GAC_ECO_BITS _MMIO(0x14090)
203#define ECOBITS_SNB_BIT (1<<13)
204#define ECOBITS_PPGTT_CACHE64B (3<<8)
205#define ECOBITS_PPGTT_CACHE4B (0<<8)
206
207#define GAB_CTL _MMIO(0x24000)
208#define GAB_CTL_CONT_AFTER_PAGEFAULT (1<<8)
209
210#define GEN6_STOLEN_RESERVED _MMIO(0x1082C0)
211#define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20)
212#define GEN7_STOLEN_RESERVED_ADDR_MASK (0x3FFF << 18)
213#define GEN6_STOLEN_RESERVED_SIZE_MASK (3 << 4)
214#define GEN6_STOLEN_RESERVED_1M (0 << 4)
215#define GEN6_STOLEN_RESERVED_512K (1 << 4)
216#define GEN6_STOLEN_RESERVED_256K (2 << 4)
217#define GEN6_STOLEN_RESERVED_128K (3 << 4)
218#define GEN7_STOLEN_RESERVED_SIZE_MASK (1 << 5)
219#define GEN7_STOLEN_RESERVED_1M (0 << 5)
220#define GEN7_STOLEN_RESERVED_256K (1 << 5)
221#define GEN8_STOLEN_RESERVED_SIZE_MASK (3 << 7)
222#define GEN8_STOLEN_RESERVED_1M (0 << 7)
223#define GEN8_STOLEN_RESERVED_2M (1 << 7)
224#define GEN8_STOLEN_RESERVED_4M (2 << 7)
225#define GEN8_STOLEN_RESERVED_8M (3 << 7)
226
227/* VGA stuff */
228
229#define VGA_ST01_MDA 0x3ba
230#define VGA_ST01_CGA 0x3da
231
232#define _VGA_MSR_WRITE _MMIO(0x3c2)
233#define VGA_MSR_WRITE 0x3c2
234#define VGA_MSR_READ 0x3cc
235#define VGA_MSR_MEM_EN (1<<1)
236#define VGA_MSR_CGA_MODE (1<<0)
237
238#define VGA_SR_INDEX 0x3c4
239#define SR01 1
240#define VGA_SR_DATA 0x3c5
241
242#define VGA_AR_INDEX 0x3c0
243#define VGA_AR_VID_EN (1<<5)
244#define VGA_AR_DATA_WRITE 0x3c0
245#define VGA_AR_DATA_READ 0x3c1
246
247#define VGA_GR_INDEX 0x3ce
248#define VGA_GR_DATA 0x3cf
249/* GR05 */
250#define VGA_GR_MEM_READ_MODE_SHIFT 3
251#define VGA_GR_MEM_READ_MODE_PLANE 1
252/* GR06 */
253#define VGA_GR_MEM_MODE_MASK 0xc
254#define VGA_GR_MEM_MODE_SHIFT 2
255#define VGA_GR_MEM_A0000_AFFFF 0
256#define VGA_GR_MEM_A0000_BFFFF 1
257#define VGA_GR_MEM_B0000_B7FFF 2
258#define VGA_GR_MEM_B0000_BFFFF 3
259
260#define VGA_DACMASK 0x3c6
261#define VGA_DACRX 0x3c7
262#define VGA_DACWX 0x3c8
263#define VGA_DACDATA 0x3c9
264
265#define VGA_CR_INDEX_MDA 0x3b4
266#define VGA_CR_DATA_MDA 0x3b5
267#define VGA_CR_INDEX_CGA 0x3d4
268#define VGA_CR_DATA_CGA 0x3d5
269
270/*
271 * Instruction field definitions used by the command parser
272 */
273#define INSTR_CLIENT_SHIFT 29
274#define INSTR_CLIENT_MASK 0xE0000000
275#define INSTR_MI_CLIENT 0x0
276#define INSTR_BC_CLIENT 0x2
277#define INSTR_RC_CLIENT 0x3
278#define INSTR_SUBCLIENT_SHIFT 27
279#define INSTR_SUBCLIENT_MASK 0x18000000
280#define INSTR_MEDIA_SUBCLIENT 0x2
281#define INSTR_26_TO_24_MASK 0x7000000
282#define INSTR_26_TO_24_SHIFT 24
283
284/*
285 * Memory interface instructions used by the kernel
286 */
287#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
288/* Many MI commands use bit 22 of the header dword for GGTT vs PPGTT */
289#define MI_GLOBAL_GTT (1<<22)
290
291#define MI_NOOP MI_INSTR(0, 0)
292#define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
293#define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
294#define MI_WAIT_FOR_OVERLAY_FLIP (1<<16)
295#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
296#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
297#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
298#define MI_FLUSH MI_INSTR(0x04, 0)
299#define MI_READ_FLUSH (1 << 0)
300#define MI_EXE_FLUSH (1 << 1)
301#define MI_NO_WRITE_FLUSH (1 << 2)
302#define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
303#define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
304#define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */
305#define MI_REPORT_HEAD MI_INSTR(0x07, 0)
306#define MI_ARB_ON_OFF MI_INSTR(0x08, 0)
307#define MI_ARB_ENABLE (1<<0)
308#define MI_ARB_DISABLE (0<<0)
309#define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
310#define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0)
311#define MI_SUSPEND_FLUSH_EN (1<<0)
312#define MI_SET_APPID MI_INSTR(0x0e, 0)
313#define MI_OVERLAY_FLIP MI_INSTR(0x11, 0)
314#define MI_OVERLAY_CONTINUE (0x0<<21)
315#define MI_OVERLAY_ON (0x1<<21)
316#define MI_OVERLAY_OFF (0x2<<21)
317#define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
318#define MI_DISPLAY_FLIP MI_INSTR(0x14, 2)
319#define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1)
320#define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
321/* IVB has funny definitions for which plane to flip. */
322#define MI_DISPLAY_FLIP_IVB_PLANE_A (0 << 19)
323#define MI_DISPLAY_FLIP_IVB_PLANE_B (1 << 19)
324#define MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19)
325#define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)
326#define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19)
327#define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)
328/* SKL ones */
329#define MI_DISPLAY_FLIP_SKL_PLANE_1_A (0 << 8)
330#define MI_DISPLAY_FLIP_SKL_PLANE_1_B (1 << 8)
331#define MI_DISPLAY_FLIP_SKL_PLANE_1_C (2 << 8)
332#define MI_DISPLAY_FLIP_SKL_PLANE_2_A (4 << 8)
333#define MI_DISPLAY_FLIP_SKL_PLANE_2_B (5 << 8)
334#define MI_DISPLAY_FLIP_SKL_PLANE_2_C (6 << 8)
335#define MI_DISPLAY_FLIP_SKL_PLANE_3_A (7 << 8)
336#define MI_DISPLAY_FLIP_SKL_PLANE_3_B (8 << 8)
337#define MI_DISPLAY_FLIP_SKL_PLANE_3_C (9 << 8)
338#define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6, gen7 */
339#define MI_SEMAPHORE_GLOBAL_GTT (1<<22)
340#define MI_SEMAPHORE_UPDATE (1<<21)
341#define MI_SEMAPHORE_COMPARE (1<<20)
342#define MI_SEMAPHORE_REGISTER (1<<18)
343#define MI_SEMAPHORE_SYNC_VR (0<<16) /* RCS wait for VCS (RVSYNC) */
344#define MI_SEMAPHORE_SYNC_VER (1<<16) /* RCS wait for VECS (RVESYNC) */
345#define MI_SEMAPHORE_SYNC_BR (2<<16) /* RCS wait for BCS (RBSYNC) */
346#define MI_SEMAPHORE_SYNC_BV (0<<16) /* VCS wait for BCS (VBSYNC) */
347#define MI_SEMAPHORE_SYNC_VEV (1<<16) /* VCS wait for VECS (VVESYNC) */
348#define MI_SEMAPHORE_SYNC_RV (2<<16) /* VCS wait for RCS (VRSYNC) */
349#define MI_SEMAPHORE_SYNC_RB (0<<16) /* BCS wait for RCS (BRSYNC) */
350#define MI_SEMAPHORE_SYNC_VEB (1<<16) /* BCS wait for VECS (BVESYNC) */
351#define MI_SEMAPHORE_SYNC_VB (2<<16) /* BCS wait for VCS (BVSYNC) */
352#define MI_SEMAPHORE_SYNC_BVE (0<<16) /* VECS wait for BCS (VEBSYNC) */
353#define MI_SEMAPHORE_SYNC_VVE (1<<16) /* VECS wait for VCS (VEVSYNC) */
354#define MI_SEMAPHORE_SYNC_RVE (2<<16) /* VECS wait for RCS (VERSYNC) */
355#define MI_SEMAPHORE_SYNC_INVALID (3<<16)
356#define MI_SEMAPHORE_SYNC_MASK (3<<16)
357#define MI_SET_CONTEXT MI_INSTR(0x18, 0)
358#define MI_MM_SPACE_GTT (1<<8)
359#define MI_MM_SPACE_PHYSICAL (0<<8)
360#define MI_SAVE_EXT_STATE_EN (1<<3)
361#define MI_RESTORE_EXT_STATE_EN (1<<2)
362#define MI_FORCE_RESTORE (1<<1)
363#define MI_RESTORE_INHIBIT (1<<0)
364#define HSW_MI_RS_SAVE_STATE_EN (1<<3)
365#define HSW_MI_RS_RESTORE_STATE_EN (1<<2)
366#define MI_SEMAPHORE_SIGNAL MI_INSTR(0x1b, 0) /* GEN8+ */
367#define MI_SEMAPHORE_TARGET(engine) ((engine)<<15)
368#define MI_SEMAPHORE_WAIT MI_INSTR(0x1c, 2) /* GEN8+ */
369#define MI_SEMAPHORE_POLL (1<<15)
370#define MI_SEMAPHORE_SAD_GTE_SDD (1<<12)
371#define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
372#define MI_STORE_DWORD_IMM_GEN4 MI_INSTR(0x20, 2)
373#define MI_MEM_VIRTUAL (1 << 22) /* 945,g33,965 */
374#define MI_USE_GGTT (1 << 22) /* g4x+ */
375#define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
376#define MI_STORE_DWORD_INDEX_SHIFT 2
377/* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
378 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
379 * simply ignores the register load under certain conditions.
380 * - One can actually load arbitrary many arbitrary registers: Simply issue x
381 * address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
382 */
383#define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1)
384#define MI_LRI_FORCE_POSTED (1<<12)
385#define MI_STORE_REGISTER_MEM MI_INSTR(0x24, 1)
386#define MI_STORE_REGISTER_MEM_GEN8 MI_INSTR(0x24, 2)
387#define MI_SRM_LRM_GLOBAL_GTT (1<<22)
388#define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */
389#define MI_FLUSH_DW_STORE_INDEX (1<<21)
390#define MI_INVALIDATE_TLB (1<<18)
391#define MI_FLUSH_DW_OP_STOREDW (1<<14)
392#define MI_FLUSH_DW_OP_MASK (3<<14)
393#define MI_FLUSH_DW_NOTIFY (1<<8)
394#define MI_INVALIDATE_BSD (1<<7)
395#define MI_FLUSH_DW_USE_GTT (1<<2)
396#define MI_FLUSH_DW_USE_PPGTT (0<<2)
397#define MI_LOAD_REGISTER_MEM MI_INSTR(0x29, 1)
398#define MI_LOAD_REGISTER_MEM_GEN8 MI_INSTR(0x29, 2)
399#define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
400#define MI_BATCH_NON_SECURE (1)
401/* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */
402#define MI_BATCH_NON_SECURE_I965 (1<<8)
403#define MI_BATCH_PPGTT_HSW (1<<8)
404#define MI_BATCH_NON_SECURE_HSW (1<<13)
405#define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
406#define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */
407#define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1)
408#define MI_BATCH_RESOURCE_STREAMER (1<<10)
409
410#define MI_PREDICATE_SRC0 _MMIO(0x2400)
411#define MI_PREDICATE_SRC0_UDW _MMIO(0x2400 + 4)
412#define MI_PREDICATE_SRC1 _MMIO(0x2408)
413#define MI_PREDICATE_SRC1_UDW _MMIO(0x2408 + 4)
414
415#define MI_PREDICATE_RESULT_2 _MMIO(0x2214)
416#define LOWER_SLICE_ENABLED (1<<0)
417#define LOWER_SLICE_DISABLED (0<<0)
418
419/*
420 * 3D instructions used by the kernel
421 */
422#define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
423
424#define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
425#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
426#define SC_UPDATE_SCISSOR (0x1<<1)
427#define SC_ENABLE_MASK (0x1<<0)
428#define SC_ENABLE (0x1<<0)
429#define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
430#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
431#define SCI_YMIN_MASK (0xffff<<16)
432#define SCI_XMIN_MASK (0xffff<<0)
433#define SCI_YMAX_MASK (0xffff<<16)
434#define SCI_XMAX_MASK (0xffff<<0)
435#define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
436#define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
437#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
438#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
439#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
440#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
441#define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
442#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
443#define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
444
445#define COLOR_BLT_CMD (2<<29 | 0x40<<22 | (5-2))
446#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
447#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
448#define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)
449#define BLT_WRITE_A (2<<20)
450#define BLT_WRITE_RGB (1<<20)
451#define BLT_WRITE_RGBA (BLT_WRITE_RGB | BLT_WRITE_A)
452#define BLT_DEPTH_8 (0<<24)
453#define BLT_DEPTH_16_565 (1<<24)
454#define BLT_DEPTH_16_1555 (2<<24)
455#define BLT_DEPTH_32 (3<<24)
456#define BLT_ROP_SRC_COPY (0xcc<<16)
457#define BLT_ROP_COLOR_COPY (0xf0<<16)
458#define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */
459#define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */
460#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
461#define ASYNC_FLIP (1<<22)
462#define DISPLAY_PLANE_A (0<<20)
463#define DISPLAY_PLANE_B (1<<20)
464#define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2))
465#define PIPE_CONTROL_FLUSH_L3 (1<<27)
466#define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */
467#define PIPE_CONTROL_MMIO_WRITE (1<<23)
468#define PIPE_CONTROL_STORE_DATA_INDEX (1<<21)
469#define PIPE_CONTROL_CS_STALL (1<<20)
470#define PIPE_CONTROL_TLB_INVALIDATE (1<<18)
471#define PIPE_CONTROL_MEDIA_STATE_CLEAR (1<<16)
472#define PIPE_CONTROL_QW_WRITE (1<<14)
473#define PIPE_CONTROL_POST_SYNC_OP_MASK (3<<14)
474#define PIPE_CONTROL_DEPTH_STALL (1<<13)
475#define PIPE_CONTROL_WRITE_FLUSH (1<<12)
476#define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */
477#define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */
478#define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */
479#define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9)
480#define PIPE_CONTROL_NOTIFY (1<<8)
481#define PIPE_CONTROL_FLUSH_ENABLE (1<<7) /* gen7+ */
482#define PIPE_CONTROL_DC_FLUSH_ENABLE (1<<5)
483#define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4)
484#define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3)
485#define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2)
486#define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1)
487#define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0)
488#define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
489
490/*
491 * Commands used only by the command parser
492 */
493#define MI_SET_PREDICATE MI_INSTR(0x01, 0)
494#define MI_ARB_CHECK MI_INSTR(0x05, 0)
495#define MI_RS_CONTROL MI_INSTR(0x06, 0)
496#define MI_URB_ATOMIC_ALLOC MI_INSTR(0x09, 0)
497#define MI_PREDICATE MI_INSTR(0x0C, 0)
498#define MI_RS_CONTEXT MI_INSTR(0x0F, 0)
499#define MI_TOPOLOGY_FILTER MI_INSTR(0x0D, 0)
500#define MI_LOAD_SCAN_LINES_EXCL MI_INSTR(0x13, 0)
501#define MI_URB_CLEAR MI_INSTR(0x19, 0)
502#define MI_UPDATE_GTT MI_INSTR(0x23, 0)
503#define MI_CLFLUSH MI_INSTR(0x27, 0)
504#define MI_REPORT_PERF_COUNT MI_INSTR(0x28, 0)
505#define MI_REPORT_PERF_COUNT_GGTT (1<<0)
506#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 0)
507#define MI_RS_STORE_DATA_IMM MI_INSTR(0x2B, 0)
508#define MI_LOAD_URB_MEM MI_INSTR(0x2C, 0)
509#define MI_STORE_URB_MEM MI_INSTR(0x2D, 0)
510#define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0)
511
512#define PIPELINE_SELECT ((0x3<<29)|(0x1<<27)|(0x1<<24)|(0x4<<16))
513#define GFX_OP_3DSTATE_VF_STATISTICS ((0x3<<29)|(0x1<<27)|(0x0<<24)|(0xB<<16))
514#define MEDIA_VFE_STATE ((0x3<<29)|(0x2<<27)|(0x0<<24)|(0x0<<16))
515#define MEDIA_VFE_STATE_MMIO_ACCESS_MASK (0x18)
516#define GPGPU_OBJECT ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x4<<16))
517#define GPGPU_WALKER ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x5<<16))
518#define GFX_OP_3DSTATE_DX9_CONSTANTF_VS \
519 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x39<<16))
520#define GFX_OP_3DSTATE_DX9_CONSTANTF_PS \
521 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x3A<<16))
522#define GFX_OP_3DSTATE_SO_DECL_LIST \
523 ((0x3<<29)|(0x3<<27)|(0x1<<24)|(0x17<<16))
524
525#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS \
526 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x43<<16))
527#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS \
528 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x44<<16))
529#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS \
530 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x45<<16))
531#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS \
532 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x46<<16))
533#define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS \
534 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x47<<16))
535
536#define MFX_WAIT ((0x3<<29)|(0x1<<27)|(0x0<<16))
537
538#define COLOR_BLT ((0x2<<29)|(0x40<<22))
539#define SRC_COPY_BLT ((0x2<<29)|(0x43<<22))
540
541/*
542 * Registers used only by the command parser
543 */
544#define BCS_SWCTRL _MMIO(0x22200)
545
546#define GPGPU_THREADS_DISPATCHED _MMIO(0x2290)
547#define GPGPU_THREADS_DISPATCHED_UDW _MMIO(0x2290 + 4)
548#define HS_INVOCATION_COUNT _MMIO(0x2300)
549#define HS_INVOCATION_COUNT_UDW _MMIO(0x2300 + 4)
550#define DS_INVOCATION_COUNT _MMIO(0x2308)
551#define DS_INVOCATION_COUNT_UDW _MMIO(0x2308 + 4)
552#define IA_VERTICES_COUNT _MMIO(0x2310)
553#define IA_VERTICES_COUNT_UDW _MMIO(0x2310 + 4)
554#define IA_PRIMITIVES_COUNT _MMIO(0x2318)
555#define IA_PRIMITIVES_COUNT_UDW _MMIO(0x2318 + 4)
556#define VS_INVOCATION_COUNT _MMIO(0x2320)
557#define VS_INVOCATION_COUNT_UDW _MMIO(0x2320 + 4)
558#define GS_INVOCATION_COUNT _MMIO(0x2328)
559#define GS_INVOCATION_COUNT_UDW _MMIO(0x2328 + 4)
560#define GS_PRIMITIVES_COUNT _MMIO(0x2330)
561#define GS_PRIMITIVES_COUNT_UDW _MMIO(0x2330 + 4)
562#define CL_INVOCATION_COUNT _MMIO(0x2338)
563#define CL_INVOCATION_COUNT_UDW _MMIO(0x2338 + 4)
564#define CL_PRIMITIVES_COUNT _MMIO(0x2340)
565#define CL_PRIMITIVES_COUNT_UDW _MMIO(0x2340 + 4)
566#define PS_INVOCATION_COUNT _MMIO(0x2348)
567#define PS_INVOCATION_COUNT_UDW _MMIO(0x2348 + 4)
568#define PS_DEPTH_COUNT _MMIO(0x2350)
569#define PS_DEPTH_COUNT_UDW _MMIO(0x2350 + 4)
570
571/* There are the 4 64-bit counter registers, one for each stream output */
572#define GEN7_SO_NUM_PRIMS_WRITTEN(n) _MMIO(0x5200 + (n) * 8)
573#define GEN7_SO_NUM_PRIMS_WRITTEN_UDW(n) _MMIO(0x5200 + (n) * 8 + 4)
574
575#define GEN7_SO_PRIM_STORAGE_NEEDED(n) _MMIO(0x5240 + (n) * 8)
576#define GEN7_SO_PRIM_STORAGE_NEEDED_UDW(n) _MMIO(0x5240 + (n) * 8 + 4)
577
578#define GEN7_3DPRIM_END_OFFSET _MMIO(0x2420)
579#define GEN7_3DPRIM_START_VERTEX _MMIO(0x2430)
580#define GEN7_3DPRIM_VERTEX_COUNT _MMIO(0x2434)
581#define GEN7_3DPRIM_INSTANCE_COUNT _MMIO(0x2438)
582#define GEN7_3DPRIM_START_INSTANCE _MMIO(0x243C)
583#define GEN7_3DPRIM_BASE_VERTEX _MMIO(0x2440)
584
585#define GEN7_GPGPU_DISPATCHDIMX _MMIO(0x2500)
586#define GEN7_GPGPU_DISPATCHDIMY _MMIO(0x2504)
587#define GEN7_GPGPU_DISPATCHDIMZ _MMIO(0x2508)
588
589#define OACONTROL _MMIO(0x2360)
590
591#define _GEN7_PIPEA_DE_LOAD_SL 0x70068
592#define _GEN7_PIPEB_DE_LOAD_SL 0x71068
593#define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL)
594
595/*
596 * Reset registers
597 */
598#define DEBUG_RESET_I830 _MMIO(0x6070)
599#define DEBUG_RESET_FULL (1<<7)
600#define DEBUG_RESET_RENDER (1<<8)
601#define DEBUG_RESET_DISPLAY (1<<9)
602
603/*
604 * IOSF sideband
605 */
606#define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100)
607#define IOSF_DEVFN_SHIFT 24
608#define IOSF_OPCODE_SHIFT 16
609#define IOSF_PORT_SHIFT 8
610#define IOSF_BYTE_ENABLES_SHIFT 4
611#define IOSF_BAR_SHIFT 1
612#define IOSF_SB_BUSY (1<<0)
613#define IOSF_PORT_BUNIT 0x03
614#define IOSF_PORT_PUNIT 0x04
615#define IOSF_PORT_NC 0x11
616#define IOSF_PORT_DPIO 0x12
617#define IOSF_PORT_GPIO_NC 0x13
618#define IOSF_PORT_CCK 0x14
619#define IOSF_PORT_DPIO_2 0x1a
620#define IOSF_PORT_FLISDSI 0x1b
621#define IOSF_PORT_GPIO_SC 0x48
622#define IOSF_PORT_GPIO_SUS 0xa8
623#define IOSF_PORT_CCU 0xa9
624#define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104)
625#define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108)
626
627/* See configdb bunit SB addr map */
628#define BUNIT_REG_BISOC 0x11
629
630#define PUNIT_REG_DSPFREQ 0x36
631#define DSPFREQSTAT_SHIFT_CHV 24
632#define DSPFREQSTAT_MASK_CHV (0x1f << DSPFREQSTAT_SHIFT_CHV)
633#define DSPFREQGUAR_SHIFT_CHV 8
634#define DSPFREQGUAR_MASK_CHV (0x1f << DSPFREQGUAR_SHIFT_CHV)
635#define DSPFREQSTAT_SHIFT 30
636#define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT)
637#define DSPFREQGUAR_SHIFT 14
638#define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT)
639#define DSP_MAXFIFO_PM5_STATUS (1 << 22) /* chv */
640#define DSP_AUTO_CDCLK_GATE_DISABLE (1 << 7) /* chv */
641#define DSP_MAXFIFO_PM5_ENABLE (1 << 6) /* chv */
642#define _DP_SSC(val, pipe) ((val) << (2 * (pipe)))
643#define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe))
644#define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe))
645#define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe))
646#define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe))
647#define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe))
648#define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16))
649#define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe))
650#define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe))
651#define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe))
652#define DP_SSS_RESET(pipe) _DP_SSS(0x2, (pipe))
653#define DP_SSS_PWR_GATE(pipe) _DP_SSS(0x3, (pipe))
654
655/* See the PUNIT HAS v0.8 for the below bits */
656enum punit_power_well {
657 /* These numbers are fixed and must match the position of the pw bits */
658 PUNIT_POWER_WELL_RENDER = 0,
659 PUNIT_POWER_WELL_MEDIA = 1,
660 PUNIT_POWER_WELL_DISP2D = 3,
661 PUNIT_POWER_WELL_DPIO_CMN_BC = 5,
662 PUNIT_POWER_WELL_DPIO_TX_B_LANES_01 = 6,
663 PUNIT_POWER_WELL_DPIO_TX_B_LANES_23 = 7,
664 PUNIT_POWER_WELL_DPIO_TX_C_LANES_01 = 8,
665 PUNIT_POWER_WELL_DPIO_TX_C_LANES_23 = 9,
666 PUNIT_POWER_WELL_DPIO_RX0 = 10,
667 PUNIT_POWER_WELL_DPIO_RX1 = 11,
668 PUNIT_POWER_WELL_DPIO_CMN_D = 12,
669
670 /* Not actual bit groups. Used as IDs for lookup_power_well() */
671 PUNIT_POWER_WELL_ALWAYS_ON,
672};
673
674enum skl_disp_power_wells {
675 /* These numbers are fixed and must match the position of the pw bits */
676 SKL_DISP_PW_MISC_IO,
677 SKL_DISP_PW_DDI_A_E,
678 SKL_DISP_PW_DDI_B,
679 SKL_DISP_PW_DDI_C,
680 SKL_DISP_PW_DDI_D,
681 SKL_DISP_PW_1 = 14,
682 SKL_DISP_PW_2,
683
684 /* Not actual bit groups. Used as IDs for lookup_power_well() */
685 SKL_DISP_PW_ALWAYS_ON,
686 SKL_DISP_PW_DC_OFF,
687};
688
689#define SKL_POWER_WELL_STATE(pw) (1 << ((pw) * 2))
690#define SKL_POWER_WELL_REQ(pw) (1 << (((pw) * 2) + 1))
691
692#define PUNIT_REG_PWRGT_CTRL 0x60
693#define PUNIT_REG_PWRGT_STATUS 0x61
694#define PUNIT_PWRGT_MASK(power_well) (3 << ((power_well) * 2))
695#define PUNIT_PWRGT_PWR_ON(power_well) (0 << ((power_well) * 2))
696#define PUNIT_PWRGT_CLK_GATE(power_well) (1 << ((power_well) * 2))
697#define PUNIT_PWRGT_RESET(power_well) (2 << ((power_well) * 2))
698#define PUNIT_PWRGT_PWR_GATE(power_well) (3 << ((power_well) * 2))
699
700#define PUNIT_REG_GPU_LFM 0xd3
701#define PUNIT_REG_GPU_FREQ_REQ 0xd4
702#define PUNIT_REG_GPU_FREQ_STS 0xd8
703#define GPLLENABLE (1<<4)
704#define GENFREQSTATUS (1<<0)
705#define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc
706#define PUNIT_REG_CZ_TIMESTAMP 0xce
707
708#define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
709#define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */
710
711#define FB_GFX_FMAX_AT_VMAX_FUSE 0x136
712#define FB_GFX_FREQ_FUSE_MASK 0xff
713#define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT 24
714#define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT 16
715#define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT 8
716
717#define FB_GFX_FMIN_AT_VMIN_FUSE 0x137
718#define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8
719
720#define PUNIT_REG_DDR_SETUP2 0x139
721#define FORCE_DDR_FREQ_REQ_ACK (1 << 8)
722#define FORCE_DDR_LOW_FREQ (1 << 1)
723#define FORCE_DDR_HIGH_FREQ (1 << 0)
724
725#define PUNIT_GPU_STATUS_REG 0xdb
726#define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16
727#define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff
728#define PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT 8
729#define PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK 0xff
730
731#define PUNIT_GPU_DUTYCYCLE_REG 0xdf
732#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT 8
733#define PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK 0xff
734
735#define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
736#define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
737#define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8
738#define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11
739#define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800
740#define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34
741#define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007
742#define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30
743#define FB_FMAX_VMIN_FREQ_LO_SHIFT 27
744#define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000
745
746#define VLV_TURBO_SOC_OVERRIDE 0x04
747#define VLV_OVERRIDE_EN 1
748#define VLV_SOC_TDP_EN (1 << 1)
749#define VLV_BIAS_CPU_125_SOC_875 (6 << 2)
750#define CHV_BIAS_CPU_50_SOC_50 (3 << 2)
751
752#define VLV_CZ_CLOCK_TO_MILLI_SEC 100000
753
754/* vlv2 north clock has */
755#define CCK_FUSE_REG 0x8
756#define CCK_FUSE_HPLL_FREQ_MASK 0x3
757#define CCK_REG_DSI_PLL_FUSE 0x44
758#define CCK_REG_DSI_PLL_CONTROL 0x48
759#define DSI_PLL_VCO_EN (1 << 31)
760#define DSI_PLL_LDO_GATE (1 << 30)
761#define DSI_PLL_P1_POST_DIV_SHIFT 17
762#define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17)
763#define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13)
764#define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12)
765#define DSI_PLL_MUX_MASK (3 << 9)
766#define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10)
767#define DSI_PLL_MUX_DSI0_CCK (1 << 10)
768#define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9)
769#define DSI_PLL_MUX_DSI1_CCK (1 << 9)
770#define DSI_PLL_CLK_GATE_MASK (0xf << 5)
771#define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8)
772#define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7)
773#define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6)
774#define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5)
775#define DSI_PLL_LOCK (1 << 0)
776#define CCK_REG_DSI_PLL_DIVIDER 0x4c
777#define DSI_PLL_LFSR (1 << 31)
778#define DSI_PLL_FRACTION_EN (1 << 30)
779#define DSI_PLL_FRAC_COUNTER_SHIFT 27
780#define DSI_PLL_FRAC_COUNTER_MASK (7 << 27)
781#define DSI_PLL_USYNC_CNT_SHIFT 18
782#define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18)
783#define DSI_PLL_N1_DIV_SHIFT 16
784#define DSI_PLL_N1_DIV_MASK (3 << 16)
785#define DSI_PLL_M1_DIV_SHIFT 0
786#define DSI_PLL_M1_DIV_MASK (0x1ff << 0)
787#define CCK_CZ_CLOCK_CONTROL 0x62
788#define CCK_DISPLAY_CLOCK_CONTROL 0x6b
789#define CCK_TRUNK_FORCE_ON (1 << 17)
790#define CCK_TRUNK_FORCE_OFF (1 << 16)
791#define CCK_FREQUENCY_STATUS (0x1f << 8)
792#define CCK_FREQUENCY_STATUS_SHIFT 8
793#define CCK_FREQUENCY_VALUES (0x1f << 0)
794
795/**
796 * DOC: DPIO
797 *
798 * VLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI
799 * ports. DPIO is the name given to such a display PHY. These PHYs
800 * don't follow the standard programming model using direct MMIO
801 * registers, and instead their registers must be accessed trough IOSF
802 * sideband. VLV has one such PHY for driving ports B and C, and CHV
803 * adds another PHY for driving port D. Each PHY responds to specific
804 * IOSF-SB port.
805 *
806 * Each display PHY is made up of one or two channels. Each channel
807 * houses a common lane part which contains the PLL and other common
808 * logic. CH0 common lane also contains the IOSF-SB logic for the
809 * Common Register Interface (CRI) ie. the DPIO registers. CRI clock
810 * must be running when any DPIO registers are accessed.
811 *
812 * In addition to having their own registers, the PHYs are also
813 * controlled through some dedicated signals from the display
814 * controller. These include PLL reference clock enable, PLL enable,
815 * and CRI clock selection, for example.
816 *
817 * Eeach channel also has two splines (also called data lanes), and
818 * each spline is made up of one Physical Access Coding Sub-Layer
819 * (PCS) block and two TX lanes. So each channel has two PCS blocks
820 * and four TX lanes. The TX lanes are used as DP lanes or TMDS
821 * data/clock pairs depending on the output type.
822 *
823 * Additionally the PHY also contains an AUX lane with AUX blocks
824 * for each channel. This is used for DP AUX communication, but
825 * this fact isn't really relevant for the driver since AUX is
826 * controlled from the display controller side. No DPIO registers
827 * need to be accessed during AUX communication,
828 *
829 * Generally on VLV/CHV the common lane corresponds to the pipe and
830 * the spline (PCS/TX) corresponds to the port.
831 *
832 * For dual channel PHY (VLV/CHV):
833 *
834 * pipe A == CMN/PLL/REF CH0
835 *
836 * pipe B == CMN/PLL/REF CH1
837 *
838 * port B == PCS/TX CH0
839 *
840 * port C == PCS/TX CH1
841 *
842 * This is especially important when we cross the streams
843 * ie. drive port B with pipe B, or port C with pipe A.
844 *
845 * For single channel PHY (CHV):
846 *
847 * pipe C == CMN/PLL/REF CH0
848 *
849 * port D == PCS/TX CH0
850 *
851 * On BXT the entire PHY channel corresponds to the port. That means
852 * the PLL is also now associated with the port rather than the pipe,
853 * and so the clock needs to be routed to the appropriate transcoder.
854 * Port A PLL is directly connected to transcoder EDP and port B/C
855 * PLLs can be routed to any transcoder A/B/C.
856 *
857 * Note: DDI0 is digital port B, DD1 is digital port C, and DDI2 is
858 * digital port D (CHV) or port A (BXT).
859 *
860 *
861 * Dual channel PHY (VLV/CHV/BXT)
862 * ---------------------------------
863 * | CH0 | CH1 |
864 * | CMN/PLL/REF | CMN/PLL/REF |
865 * |---------------|---------------| Display PHY
866 * | PCS01 | PCS23 | PCS01 | PCS23 |
867 * |-------|-------|-------|-------|
868 * |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3|
869 * ---------------------------------
870 * | DDI0 | DDI1 | DP/HDMI ports
871 * ---------------------------------
872 *
873 * Single channel PHY (CHV/BXT)
874 * -----------------
875 * | CH0 |
876 * | CMN/PLL/REF |
877 * |---------------| Display PHY
878 * | PCS01 | PCS23 |
879 * |-------|-------|
880 * |TX0|TX1|TX2|TX3|
881 * -----------------
882 * | DDI2 | DP/HDMI port
883 * -----------------
884 */
885#define DPIO_DEVFN 0
886
887#define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110)
888#define DPIO_MODSEL1 (1<<3) /* if ref clk b == 27 */
889#define DPIO_MODSEL0 (1<<2) /* if ref clk a == 27 */
890#define DPIO_SFR_BYPASS (1<<1)
891#define DPIO_CMNRST (1<<0)
892
893#define DPIO_PHY(pipe) ((pipe) >> 1)
894#define DPIO_PHY_IOSF_PORT(phy) (dev_priv->dpio_phy_iosf_port[phy])
895
896/*
897 * Per pipe/PLL DPIO regs
898 */
899#define _VLV_PLL_DW3_CH0 0x800c
900#define DPIO_POST_DIV_SHIFT (28) /* 3 bits */
901#define DPIO_POST_DIV_DAC 0
902#define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */
903#define DPIO_POST_DIV_LVDS1 2
904#define DPIO_POST_DIV_LVDS2 3
905#define DPIO_K_SHIFT (24) /* 4 bits */
906#define DPIO_P1_SHIFT (21) /* 3 bits */
907#define DPIO_P2_SHIFT (16) /* 5 bits */
908#define DPIO_N_SHIFT (12) /* 4 bits */
909#define DPIO_ENABLE_CALIBRATION (1<<11)
910#define DPIO_M1DIV_SHIFT (8) /* 3 bits */
911#define DPIO_M2DIV_MASK 0xff
912#define _VLV_PLL_DW3_CH1 0x802c
913#define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1)
914
915#define _VLV_PLL_DW5_CH0 0x8014
916#define DPIO_REFSEL_OVERRIDE 27
917#define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */
918#define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */
919#define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */
920#define DPIO_PLL_REFCLK_SEL_MASK 3
921#define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */
922#define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */
923#define _VLV_PLL_DW5_CH1 0x8034
924#define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1)
925
926#define _VLV_PLL_DW7_CH0 0x801c
927#define _VLV_PLL_DW7_CH1 0x803c
928#define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)
929
930#define _VLV_PLL_DW8_CH0 0x8040
931#define _VLV_PLL_DW8_CH1 0x8060
932#define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)
933
934#define VLV_PLL_DW9_BCAST 0xc044
935#define _VLV_PLL_DW9_CH0 0x8044
936#define _VLV_PLL_DW9_CH1 0x8064
937#define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)
938
939#define _VLV_PLL_DW10_CH0 0x8048
940#define _VLV_PLL_DW10_CH1 0x8068
941#define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1)
942
943#define _VLV_PLL_DW11_CH0 0x804c
944#define _VLV_PLL_DW11_CH1 0x806c
945#define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)
946
947/* Spec for ref block start counts at DW10 */
948#define VLV_REF_DW13 0x80ac
949
950#define VLV_CMN_DW0 0x8100
951
952/*
953 * Per DDI channel DPIO regs
954 */
955
956#define _VLV_PCS_DW0_CH0 0x8200
957#define _VLV_PCS_DW0_CH1 0x8400
958#define DPIO_PCS_TX_LANE2_RESET (1<<16)
959#define DPIO_PCS_TX_LANE1_RESET (1<<7)
960#define DPIO_LEFT_TXFIFO_RST_MASTER2 (1<<4)
961#define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1<<3)
962#define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
963
964#define _VLV_PCS01_DW0_CH0 0x200
965#define _VLV_PCS23_DW0_CH0 0x400
966#define _VLV_PCS01_DW0_CH1 0x2600
967#define _VLV_PCS23_DW0_CH1 0x2800
968#define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
969#define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
970
971#define _VLV_PCS_DW1_CH0 0x8204
972#define _VLV_PCS_DW1_CH1 0x8404
973#define CHV_PCS_REQ_SOFTRESET_EN (1<<23)
974#define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1<<22)
975#define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1<<21)
976#define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6)
977#define DPIO_PCS_CLK_SOFT_RESET (1<<5)
978#define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
979
980#define _VLV_PCS01_DW1_CH0 0x204
981#define _VLV_PCS23_DW1_CH0 0x404
982#define _VLV_PCS01_DW1_CH1 0x2604
983#define _VLV_PCS23_DW1_CH1 0x2804
984#define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)
985#define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)
986
987#define _VLV_PCS_DW8_CH0 0x8220
988#define _VLV_PCS_DW8_CH1 0x8420
989#define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20)
990#define CHV_PCS_USEDCLKCHANNEL (1 << 21)
991#define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
992
993#define _VLV_PCS01_DW8_CH0 0x0220
994#define _VLV_PCS23_DW8_CH0 0x0420
995#define _VLV_PCS01_DW8_CH1 0x2620
996#define _VLV_PCS23_DW8_CH1 0x2820
997#define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)
998#define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)
999
1000#define _VLV_PCS_DW9_CH0 0x8224
1001#define _VLV_PCS_DW9_CH1 0x8424
1002#define DPIO_PCS_TX2MARGIN_MASK (0x7<<13)
1003#define DPIO_PCS_TX2MARGIN_000 (0<<13)
1004#define DPIO_PCS_TX2MARGIN_101 (1<<13)
1005#define DPIO_PCS_TX1MARGIN_MASK (0x7<<10)
1006#define DPIO_PCS_TX1MARGIN_000 (0<<10)
1007#define DPIO_PCS_TX1MARGIN_101 (1<<10)
1008#define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
1009
1010#define _VLV_PCS01_DW9_CH0 0x224
1011#define _VLV_PCS23_DW9_CH0 0x424
1012#define _VLV_PCS01_DW9_CH1 0x2624
1013#define _VLV_PCS23_DW9_CH1 0x2824
1014#define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1)
1015#define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1)
1016
1017#define _CHV_PCS_DW10_CH0 0x8228
1018#define _CHV_PCS_DW10_CH1 0x8428
1019#define DPIO_PCS_SWING_CALC_TX0_TX2 (1<<30)
1020#define DPIO_PCS_SWING_CALC_TX1_TX3 (1<<31)
1021#define DPIO_PCS_TX2DEEMP_MASK (0xf<<24)
1022#define DPIO_PCS_TX2DEEMP_9P5 (0<<24)
1023#define DPIO_PCS_TX2DEEMP_6P0 (2<<24)
1024#define DPIO_PCS_TX1DEEMP_MASK (0xf<<16)
1025#define DPIO_PCS_TX1DEEMP_9P5 (0<<16)
1026#define DPIO_PCS_TX1DEEMP_6P0 (2<<16)
1027#define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)
1028
1029#define _VLV_PCS01_DW10_CH0 0x0228
1030#define _VLV_PCS23_DW10_CH0 0x0428
1031#define _VLV_PCS01_DW10_CH1 0x2628
1032#define _VLV_PCS23_DW10_CH1 0x2828
1033#define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1)
1034#define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1)
1035
1036#define _VLV_PCS_DW11_CH0 0x822c
1037#define _VLV_PCS_DW11_CH1 0x842c
1038#define DPIO_TX2_STAGGER_MASK(x) ((x)<<24)
1039#define DPIO_LANEDESKEW_STRAP_OVRD (1<<3)
1040#define DPIO_LEFT_TXFIFO_RST_MASTER (1<<1)
1041#define DPIO_RIGHT_TXFIFO_RST_MASTER (1<<0)
1042#define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
1043
1044#define _VLV_PCS01_DW11_CH0 0x022c
1045#define _VLV_PCS23_DW11_CH0 0x042c
1046#define _VLV_PCS01_DW11_CH1 0x262c
1047#define _VLV_PCS23_DW11_CH1 0x282c
1048#define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1)
1049#define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1)
1050
1051#define _VLV_PCS01_DW12_CH0 0x0230
1052#define _VLV_PCS23_DW12_CH0 0x0430
1053#define _VLV_PCS01_DW12_CH1 0x2630
1054#define _VLV_PCS23_DW12_CH1 0x2830
1055#define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1)
1056#define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1)
1057
1058#define _VLV_PCS_DW12_CH0 0x8230
1059#define _VLV_PCS_DW12_CH1 0x8430
1060#define DPIO_TX2_STAGGER_MULT(x) ((x)<<20)
1061#define DPIO_TX1_STAGGER_MULT(x) ((x)<<16)
1062#define DPIO_TX1_STAGGER_MASK(x) ((x)<<8)
1063#define DPIO_LANESTAGGER_STRAP_OVRD (1<<6)
1064#define DPIO_LANESTAGGER_STRAP(x) ((x)<<0)
1065#define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
1066
1067#define _VLV_PCS_DW14_CH0 0x8238
1068#define _VLV_PCS_DW14_CH1 0x8438
1069#define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)
1070
1071#define _VLV_PCS_DW23_CH0 0x825c
1072#define _VLV_PCS_DW23_CH1 0x845c
1073#define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)
1074
1075#define _VLV_TX_DW2_CH0 0x8288
1076#define _VLV_TX_DW2_CH1 0x8488
1077#define DPIO_SWING_MARGIN000_SHIFT 16
1078#define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT)
1079#define DPIO_UNIQ_TRANS_SCALE_SHIFT 8
1080#define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
1081
1082#define _VLV_TX_DW3_CH0 0x828c
1083#define _VLV_TX_DW3_CH1 0x848c
1084/* The following bit for CHV phy */
1085#define DPIO_TX_UNIQ_TRANS_SCALE_EN (1<<27)
1086#define DPIO_SWING_MARGIN101_SHIFT 16
1087#define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT)
1088#define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
1089
1090#define _VLV_TX_DW4_CH0 0x8290
1091#define _VLV_TX_DW4_CH1 0x8490
1092#define DPIO_SWING_DEEMPH9P5_SHIFT 24
1093#define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
1094#define DPIO_SWING_DEEMPH6P0_SHIFT 16
1095#define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
1096#define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
1097
1098#define _VLV_TX3_DW4_CH0 0x690
1099#define _VLV_TX3_DW4_CH1 0x2a90
1100#define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1)
1101
1102#define _VLV_TX_DW5_CH0 0x8294
1103#define _VLV_TX_DW5_CH1 0x8494
1104#define DPIO_TX_OCALINIT_EN (1<<31)
1105#define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1)
1106
1107#define _VLV_TX_DW11_CH0 0x82ac
1108#define _VLV_TX_DW11_CH1 0x84ac
1109#define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1)
1110
1111#define _VLV_TX_DW14_CH0 0x82b8
1112#define _VLV_TX_DW14_CH1 0x84b8
1113#define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)
1114
1115/* CHV dpPhy registers */
1116#define _CHV_PLL_DW0_CH0 0x8000
1117#define _CHV_PLL_DW0_CH1 0x8180
1118#define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1)
1119
1120#define _CHV_PLL_DW1_CH0 0x8004
1121#define _CHV_PLL_DW1_CH1 0x8184
1122#define DPIO_CHV_N_DIV_SHIFT 8
1123#define DPIO_CHV_M1_DIV_BY_2 (0 << 0)
1124#define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1)
1125
1126#define _CHV_PLL_DW2_CH0 0x8008
1127#define _CHV_PLL_DW2_CH1 0x8188
1128#define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1)
1129
1130#define _CHV_PLL_DW3_CH0 0x800c
1131#define _CHV_PLL_DW3_CH1 0x818c
1132#define DPIO_CHV_FRAC_DIV_EN (1 << 16)
1133#define DPIO_CHV_FIRST_MOD (0 << 8)
1134#define DPIO_CHV_SECOND_MOD (1 << 8)
1135#define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0
1136#define DPIO_CHV_FEEDFWD_GAIN_MASK (0xF << 0)
1137#define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
1138
1139#define _CHV_PLL_DW6_CH0 0x8018
1140#define _CHV_PLL_DW6_CH1 0x8198
1141#define DPIO_CHV_GAIN_CTRL_SHIFT 16
1142#define DPIO_CHV_INT_COEFF_SHIFT 8
1143#define DPIO_CHV_PROP_COEFF_SHIFT 0
1144#define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
1145
1146#define _CHV_PLL_DW8_CH0 0x8020
1147#define _CHV_PLL_DW8_CH1 0x81A0
1148#define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
1149#define DPIO_CHV_TDC_TARGET_CNT_MASK (0x3FF << 0)
1150#define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
1151
1152#define _CHV_PLL_DW9_CH0 0x8024
1153#define _CHV_PLL_DW9_CH1 0x81A4
1154#define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */
1155#define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 << 1)
1156#define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 : fine */
1157#define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
1158
1159#define _CHV_CMN_DW0_CH0 0x8100
1160#define DPIO_ALLDL_POWERDOWN_SHIFT_CH0 19
1161#define DPIO_ANYDL_POWERDOWN_SHIFT_CH0 18
1162#define DPIO_ALLDL_POWERDOWN (1 << 1)
1163#define DPIO_ANYDL_POWERDOWN (1 << 0)
1164
1165#define _CHV_CMN_DW5_CH0 0x8114
1166#define CHV_BUFRIGHTENA1_DISABLE (0 << 20)
1167#define CHV_BUFRIGHTENA1_NORMAL (1 << 20)
1168#define CHV_BUFRIGHTENA1_FORCE (3 << 20)
1169#define CHV_BUFRIGHTENA1_MASK (3 << 20)
1170#define CHV_BUFLEFTENA1_DISABLE (0 << 22)
1171#define CHV_BUFLEFTENA1_NORMAL (1 << 22)
1172#define CHV_BUFLEFTENA1_FORCE (3 << 22)
1173#define CHV_BUFLEFTENA1_MASK (3 << 22)
1174
1175#define _CHV_CMN_DW13_CH0 0x8134
1176#define _CHV_CMN_DW0_CH1 0x8080
1177#define DPIO_CHV_S1_DIV_SHIFT 21
1178#define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */
1179#define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */
1180#define DPIO_CHV_K_DIV_SHIFT 4
1181#define DPIO_PLL_FREQLOCK (1 << 1)
1182#define DPIO_PLL_LOCK (1 << 0)
1183#define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1)
1184
1185#define _CHV_CMN_DW14_CH0 0x8138
1186#define _CHV_CMN_DW1_CH1 0x8084
1187#define DPIO_AFC_RECAL (1 << 14)
1188#define DPIO_DCLKP_EN (1 << 13)
1189#define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */
1190#define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */
1191#define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */
1192#define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */
1193#define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */
1194#define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */
1195#define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */
1196#define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */
1197#define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)
1198
1199#define _CHV_CMN_DW19_CH0 0x814c
1200#define _CHV_CMN_DW6_CH1 0x8098
1201#define DPIO_ALLDL_POWERDOWN_SHIFT_CH1 30 /* CL2 DW6 only */
1202#define DPIO_ANYDL_POWERDOWN_SHIFT_CH1 29 /* CL2 DW6 only */
1203#define DPIO_DYNPWRDOWNEN_CH1 (1 << 28) /* CL2 DW6 only */
1204#define CHV_CMN_USEDCLKCHANNEL (1 << 13)
1205
1206#define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1)
1207
1208#define CHV_CMN_DW28 0x8170
1209#define DPIO_CL1POWERDOWNEN (1 << 23)
1210#define DPIO_DYNPWRDOWNEN_CH0 (1 << 22)
1211#define DPIO_SUS_CLK_CONFIG_ON (0 << 0)
1212#define DPIO_SUS_CLK_CONFIG_CLKREQ (1 << 0)
1213#define DPIO_SUS_CLK_CONFIG_GATE (2 << 0)
1214#define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ (3 << 0)
1215
1216#define CHV_CMN_DW30 0x8178
1217#define DPIO_CL2_LDOFUSE_PWRENB (1 << 6)
1218#define DPIO_LRC_BYPASS (1 << 3)
1219
1220#define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \
1221 (lane) * 0x200 + (offset))
1222
1223#define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80)
1224#define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84)
1225#define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88)
1226#define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c)
1227#define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90)
1228#define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94)
1229#define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98)
1230#define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c)
1231#define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0)
1232#define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4)
1233#define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8)
1234#define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac)
1235#define DPIO_FRC_LATENCY_SHFIT 8
1236#define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
1237#define DPIO_UPAR_SHIFT 30
1238
1239/* BXT PHY registers */
1240#define _BXT_PHY(phy, a, b) _MMIO_PIPE((phy), (a), (b))
1241
1242#define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090)
1243#define GT_DISPLAY_POWER_ON(phy) (1 << (phy))
1244
1245#define _PHY_CTL_FAMILY_EDP 0x64C80
1246#define _PHY_CTL_FAMILY_DDI 0x64C90
1247#define COMMON_RESET_DIS (1 << 31)
1248#define BXT_PHY_CTL_FAMILY(phy) _BXT_PHY((phy), _PHY_CTL_FAMILY_DDI, \
1249 _PHY_CTL_FAMILY_EDP)
1250
1251/* BXT PHY PLL registers */
1252#define _PORT_PLL_A 0x46074
1253#define _PORT_PLL_B 0x46078
1254#define _PORT_PLL_C 0x4607c
1255#define PORT_PLL_ENABLE (1 << 31)
1256#define PORT_PLL_LOCK (1 << 30)
1257#define PORT_PLL_REF_SEL (1 << 27)
1258#define BXT_PORT_PLL_ENABLE(port) _MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B)
1259
1260#define _PORT_PLL_EBB_0_A 0x162034
1261#define _PORT_PLL_EBB_0_B 0x6C034
1262#define _PORT_PLL_EBB_0_C 0x6C340
1263#define PORT_PLL_P1_SHIFT 13
1264#define PORT_PLL_P1_MASK (0x07 << PORT_PLL_P1_SHIFT)
1265#define PORT_PLL_P1(x) ((x) << PORT_PLL_P1_SHIFT)
1266#define PORT_PLL_P2_SHIFT 8
1267#define PORT_PLL_P2_MASK (0x1f << PORT_PLL_P2_SHIFT)
1268#define PORT_PLL_P2(x) ((x) << PORT_PLL_P2_SHIFT)
1269#define BXT_PORT_PLL_EBB_0(port) _MMIO_PORT3(port, _PORT_PLL_EBB_0_A, \
1270 _PORT_PLL_EBB_0_B, \
1271 _PORT_PLL_EBB_0_C)
1272
1273#define _PORT_PLL_EBB_4_A 0x162038
1274#define _PORT_PLL_EBB_4_B 0x6C038
1275#define _PORT_PLL_EBB_4_C 0x6C344
1276#define PORT_PLL_10BIT_CLK_ENABLE (1 << 13)
1277#define PORT_PLL_RECALIBRATE (1 << 14)
1278#define BXT_PORT_PLL_EBB_4(port) _MMIO_PORT3(port, _PORT_PLL_EBB_4_A, \
1279 _PORT_PLL_EBB_4_B, \
1280 _PORT_PLL_EBB_4_C)
1281
1282#define _PORT_PLL_0_A 0x162100
1283#define _PORT_PLL_0_B 0x6C100
1284#define _PORT_PLL_0_C 0x6C380
1285/* PORT_PLL_0_A */
1286#define PORT_PLL_M2_MASK 0xFF
1287/* PORT_PLL_1_A */
1288#define PORT_PLL_N_SHIFT 8
1289#define PORT_PLL_N_MASK (0x0F << PORT_PLL_N_SHIFT)
1290#define PORT_PLL_N(x) ((x) << PORT_PLL_N_SHIFT)
1291/* PORT_PLL_2_A */
1292#define PORT_PLL_M2_FRAC_MASK 0x3FFFFF
1293/* PORT_PLL_3_A */
1294#define PORT_PLL_M2_FRAC_ENABLE (1 << 16)
1295/* PORT_PLL_6_A */
1296#define PORT_PLL_PROP_COEFF_MASK 0xF
1297#define PORT_PLL_INT_COEFF_MASK (0x1F << 8)
1298#define PORT_PLL_INT_COEFF(x) ((x) << 8)
1299#define PORT_PLL_GAIN_CTL_MASK (0x07 << 16)
1300#define PORT_PLL_GAIN_CTL(x) ((x) << 16)
1301/* PORT_PLL_8_A */
1302#define PORT_PLL_TARGET_CNT_MASK 0x3FF
1303/* PORT_PLL_9_A */
1304#define PORT_PLL_LOCK_THRESHOLD_SHIFT 1
1305#define PORT_PLL_LOCK_THRESHOLD_MASK (0x7 << PORT_PLL_LOCK_THRESHOLD_SHIFT)
1306/* PORT_PLL_10_A */
1307#define PORT_PLL_DCO_AMP_OVR_EN_H (1<<27)
1308#define PORT_PLL_DCO_AMP_DEFAULT 15
1309#define PORT_PLL_DCO_AMP_MASK 0x3c00
1310#define PORT_PLL_DCO_AMP(x) ((x)<<10)
1311#define _PORT_PLL_BASE(port) _PORT3(port, _PORT_PLL_0_A, \
1312 _PORT_PLL_0_B, \
1313 _PORT_PLL_0_C)
1314#define BXT_PORT_PLL(port, idx) _MMIO(_PORT_PLL_BASE(port) + (idx) * 4)
1315
1316/* BXT PHY common lane registers */
1317#define _PORT_CL1CM_DW0_A 0x162000
1318#define _PORT_CL1CM_DW0_BC 0x6C000
1319#define PHY_POWER_GOOD (1 << 16)
1320#define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC, \
1321 _PORT_CL1CM_DW0_A)
1322
1323#define _PORT_CL1CM_DW9_A 0x162024
1324#define _PORT_CL1CM_DW9_BC 0x6C024
1325#define IREF0RC_OFFSET_SHIFT 8
1326#define IREF0RC_OFFSET_MASK (0xFF << IREF0RC_OFFSET_SHIFT)
1327#define BXT_PORT_CL1CM_DW9(phy) _BXT_PHY((phy), _PORT_CL1CM_DW9_BC, \
1328 _PORT_CL1CM_DW9_A)
1329
1330#define _PORT_CL1CM_DW10_A 0x162028
1331#define _PORT_CL1CM_DW10_BC 0x6C028
1332#define IREF1RC_OFFSET_SHIFT 8
1333#define IREF1RC_OFFSET_MASK (0xFF << IREF1RC_OFFSET_SHIFT)
1334#define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC, \
1335 _PORT_CL1CM_DW10_A)
1336
1337#define _PORT_CL1CM_DW28_A 0x162070
1338#define _PORT_CL1CM_DW28_BC 0x6C070
1339#define OCL1_POWER_DOWN_EN (1 << 23)
1340#define DW28_OLDO_DYN_PWR_DOWN_EN (1 << 22)
1341#define SUS_CLK_CONFIG 0x3
1342#define BXT_PORT_CL1CM_DW28(phy) _BXT_PHY((phy), _PORT_CL1CM_DW28_BC, \
1343 _PORT_CL1CM_DW28_A)
1344
1345#define _PORT_CL1CM_DW30_A 0x162078
1346#define _PORT_CL1CM_DW30_BC 0x6C078
1347#define OCL2_LDOFUSE_PWR_DIS (1 << 6)
1348#define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC, \
1349 _PORT_CL1CM_DW30_A)
1350
1351/* Defined for PHY0 only */
1352#define BXT_PORT_CL2CM_DW6_BC _MMIO(0x6C358)
1353#define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
1354
1355/* BXT PHY Ref registers */
1356#define _PORT_REF_DW3_A 0x16218C
1357#define _PORT_REF_DW3_BC 0x6C18C
1358#define GRC_DONE (1 << 22)
1359#define BXT_PORT_REF_DW3(phy) _BXT_PHY((phy), _PORT_REF_DW3_BC, \
1360 _PORT_REF_DW3_A)
1361
1362#define _PORT_REF_DW6_A 0x162198
1363#define _PORT_REF_DW6_BC 0x6C198
1364/*
1365 * FIXME: BSpec/CHV ConfigDB disagrees on the following two fields, fix them
1366 * after testing.
1367 */
1368#define GRC_CODE_SHIFT 23
1369#define GRC_CODE_MASK (0x1FF << GRC_CODE_SHIFT)
1370#define GRC_CODE_FAST_SHIFT 16
1371#define GRC_CODE_FAST_MASK (0x7F << GRC_CODE_FAST_SHIFT)
1372#define GRC_CODE_SLOW_SHIFT 8
1373#define GRC_CODE_SLOW_MASK (0xFF << GRC_CODE_SLOW_SHIFT)
1374#define GRC_CODE_NOM_MASK 0xFF
1375#define BXT_PORT_REF_DW6(phy) _BXT_PHY((phy), _PORT_REF_DW6_BC, \
1376 _PORT_REF_DW6_A)
1377
1378#define _PORT_REF_DW8_A 0x1621A0
1379#define _PORT_REF_DW8_BC 0x6C1A0
1380#define GRC_DIS (1 << 15)
1381#define GRC_RDY_OVRD (1 << 1)
1382#define BXT_PORT_REF_DW8(phy) _BXT_PHY((phy), _PORT_REF_DW8_BC, \
1383 _PORT_REF_DW8_A)
1384
1385/* BXT PHY PCS registers */
1386#define _PORT_PCS_DW10_LN01_A 0x162428
1387#define _PORT_PCS_DW10_LN01_B 0x6C428
1388#define _PORT_PCS_DW10_LN01_C 0x6C828
1389#define _PORT_PCS_DW10_GRP_A 0x162C28
1390#define _PORT_PCS_DW10_GRP_B 0x6CC28
1391#define _PORT_PCS_DW10_GRP_C 0x6CE28
1392#define BXT_PORT_PCS_DW10_LN01(port) _MMIO_PORT3(port, _PORT_PCS_DW10_LN01_A, \
1393 _PORT_PCS_DW10_LN01_B, \
1394 _PORT_PCS_DW10_LN01_C)
1395#define BXT_PORT_PCS_DW10_GRP(port) _MMIO_PORT3(port, _PORT_PCS_DW10_GRP_A, \
1396 _PORT_PCS_DW10_GRP_B, \
1397 _PORT_PCS_DW10_GRP_C)
1398#define TX2_SWING_CALC_INIT (1 << 31)
1399#define TX1_SWING_CALC_INIT (1 << 30)
1400
1401#define _PORT_PCS_DW12_LN01_A 0x162430
1402#define _PORT_PCS_DW12_LN01_B 0x6C430
1403#define _PORT_PCS_DW12_LN01_C 0x6C830
1404#define _PORT_PCS_DW12_LN23_A 0x162630
1405#define _PORT_PCS_DW12_LN23_B 0x6C630
1406#define _PORT_PCS_DW12_LN23_C 0x6CA30
1407#define _PORT_PCS_DW12_GRP_A 0x162c30
1408#define _PORT_PCS_DW12_GRP_B 0x6CC30
1409#define _PORT_PCS_DW12_GRP_C 0x6CE30
1410#define LANESTAGGER_STRAP_OVRD (1 << 6)
1411#define LANE_STAGGER_MASK 0x1F
1412#define BXT_PORT_PCS_DW12_LN01(port) _MMIO_PORT3(port, _PORT_PCS_DW12_LN01_A, \
1413 _PORT_PCS_DW12_LN01_B, \
1414 _PORT_PCS_DW12_LN01_C)
1415#define BXT_PORT_PCS_DW12_LN23(port) _MMIO_PORT3(port, _PORT_PCS_DW12_LN23_A, \
1416 _PORT_PCS_DW12_LN23_B, \
1417 _PORT_PCS_DW12_LN23_C)
1418#define BXT_PORT_PCS_DW12_GRP(port) _MMIO_PORT3(port, _PORT_PCS_DW12_GRP_A, \
1419 _PORT_PCS_DW12_GRP_B, \
1420 _PORT_PCS_DW12_GRP_C)
1421
1422/* BXT PHY TX registers */
1423#define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \
1424 ((lane) & 1) * 0x80)
1425
1426#define _PORT_TX_DW2_LN0_A 0x162508
1427#define _PORT_TX_DW2_LN0_B 0x6C508
1428#define _PORT_TX_DW2_LN0_C 0x6C908
1429#define _PORT_TX_DW2_GRP_A 0x162D08
1430#define _PORT_TX_DW2_GRP_B 0x6CD08
1431#define _PORT_TX_DW2_GRP_C 0x6CF08
1432#define BXT_PORT_TX_DW2_GRP(port) _MMIO_PORT3(port, _PORT_TX_DW2_GRP_A, \
1433 _PORT_TX_DW2_GRP_B, \
1434 _PORT_TX_DW2_GRP_C)
1435#define BXT_PORT_TX_DW2_LN0(port) _MMIO_PORT3(port, _PORT_TX_DW2_LN0_A, \
1436 _PORT_TX_DW2_LN0_B, \
1437 _PORT_TX_DW2_LN0_C)
1438#define MARGIN_000_SHIFT 16
1439#define MARGIN_000 (0xFF << MARGIN_000_SHIFT)
1440#define UNIQ_TRANS_SCALE_SHIFT 8
1441#define UNIQ_TRANS_SCALE (0xFF << UNIQ_TRANS_SCALE_SHIFT)
1442
1443#define _PORT_TX_DW3_LN0_A 0x16250C
1444#define _PORT_TX_DW3_LN0_B 0x6C50C
1445#define _PORT_TX_DW3_LN0_C 0x6C90C
1446#define _PORT_TX_DW3_GRP_A 0x162D0C
1447#define _PORT_TX_DW3_GRP_B 0x6CD0C
1448#define _PORT_TX_DW3_GRP_C 0x6CF0C
1449#define BXT_PORT_TX_DW3_GRP(port) _MMIO_PORT3(port, _PORT_TX_DW3_GRP_A, \
1450 _PORT_TX_DW3_GRP_B, \
1451 _PORT_TX_DW3_GRP_C)
1452#define BXT_PORT_TX_DW3_LN0(port) _MMIO_PORT3(port, _PORT_TX_DW3_LN0_A, \
1453 _PORT_TX_DW3_LN0_B, \
1454 _PORT_TX_DW3_LN0_C)
1455#define SCALE_DCOMP_METHOD (1 << 26)
1456#define UNIQUE_TRANGE_EN_METHOD (1 << 27)
1457
1458#define _PORT_TX_DW4_LN0_A 0x162510
1459#define _PORT_TX_DW4_LN0_B 0x6C510
1460#define _PORT_TX_DW4_LN0_C 0x6C910
1461#define _PORT_TX_DW4_GRP_A 0x162D10
1462#define _PORT_TX_DW4_GRP_B 0x6CD10
1463#define _PORT_TX_DW4_GRP_C 0x6CF10
1464#define BXT_PORT_TX_DW4_LN0(port) _MMIO_PORT3(port, _PORT_TX_DW4_LN0_A, \
1465 _PORT_TX_DW4_LN0_B, \
1466 _PORT_TX_DW4_LN0_C)
1467#define BXT_PORT_TX_DW4_GRP(port) _MMIO_PORT3(port, _PORT_TX_DW4_GRP_A, \
1468 _PORT_TX_DW4_GRP_B, \
1469 _PORT_TX_DW4_GRP_C)
1470#define DEEMPH_SHIFT 24
1471#define DE_EMPHASIS (0xFF << DEEMPH_SHIFT)
1472
1473#define _PORT_TX_DW14_LN0_A 0x162538
1474#define _PORT_TX_DW14_LN0_B 0x6C538
1475#define _PORT_TX_DW14_LN0_C 0x6C938
1476#define LATENCY_OPTIM_SHIFT 30
1477#define LATENCY_OPTIM (1 << LATENCY_OPTIM_SHIFT)
1478#define BXT_PORT_TX_DW14_LN(port, lane) _MMIO(_PORT3((port), _PORT_TX_DW14_LN0_A, \
1479 _PORT_TX_DW14_LN0_B, \
1480 _PORT_TX_DW14_LN0_C) + \
1481 _BXT_LANE_OFFSET(lane))
1482
1483/* UAIMI scratch pad register 1 */
1484#define UAIMI_SPR1 _MMIO(0x4F074)
1485/* SKL VccIO mask */
1486#define SKL_VCCIO_MASK 0x1
1487/* SKL balance leg register */
1488#define DISPIO_CR_TX_BMU_CR0 _MMIO(0x6C00C)
1489/* I_boost values */
1490#define BALANCE_LEG_SHIFT(port) (8+3*(port))
1491#define BALANCE_LEG_MASK(port) (7<<(8+3*(port)))
1492/* Balance leg disable bits */
1493#define BALANCE_LEG_DISABLE_SHIFT 23
1494
1495/*
1496 * Fence registers
1497 * [0-7] @ 0x2000 gen2,gen3
1498 * [8-15] @ 0x3000 945,g33,pnv
1499 *
1500 * [0-15] @ 0x3000 gen4,gen5
1501 *
1502 * [0-15] @ 0x100000 gen6,vlv,chv
1503 * [0-31] @ 0x100000 gen7+
1504 */
1505#define FENCE_REG(i) _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4)
1506#define I830_FENCE_START_MASK 0x07f80000
1507#define I830_FENCE_TILING_Y_SHIFT 12
1508#define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
1509#define I830_FENCE_PITCH_SHIFT 4
1510#define I830_FENCE_REG_VALID (1<<0)
1511#define I915_FENCE_MAX_PITCH_VAL 4
1512#define I830_FENCE_MAX_PITCH_VAL 6
1513#define I830_FENCE_MAX_SIZE_VAL (1<<8)
1514
1515#define I915_FENCE_START_MASK 0x0ff00000
1516#define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
1517
1518#define FENCE_REG_965_LO(i) _MMIO(0x03000 + (i) * 8)
1519#define FENCE_REG_965_HI(i) _MMIO(0x03000 + (i) * 8 + 4)
1520#define I965_FENCE_PITCH_SHIFT 2
1521#define I965_FENCE_TILING_Y_SHIFT 1
1522#define I965_FENCE_REG_VALID (1<<0)
1523#define I965_FENCE_MAX_PITCH_VAL 0x0400
1524
1525#define FENCE_REG_GEN6_LO(i) _MMIO(0x100000 + (i) * 8)
1526#define FENCE_REG_GEN6_HI(i) _MMIO(0x100000 + (i) * 8 + 4)
1527#define GEN6_FENCE_PITCH_SHIFT 32
1528#define GEN7_FENCE_MAX_PITCH_VAL 0x0800
1529
1530
1531/* control register for cpu gtt access */
1532#define TILECTL _MMIO(0x101000)
1533#define TILECTL_SWZCTL (1 << 0)
1534#define TILECTL_TLBPF (1 << 1)
1535#define TILECTL_TLB_PREFETCH_DIS (1 << 2)
1536#define TILECTL_BACKSNOOP_DIS (1 << 3)
1537
1538/*
1539 * Instruction and interrupt control regs
1540 */
1541#define PGTBL_CTL _MMIO(0x02020)
1542#define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */
1543#define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */
1544#define PGTBL_ER _MMIO(0x02024)
1545#define PRB0_BASE (0x2030-0x30)
1546#define PRB1_BASE (0x2040-0x30) /* 830,gen3 */
1547#define PRB2_BASE (0x2050-0x30) /* gen3 */
1548#define SRB0_BASE (0x2100-0x30) /* gen2 */
1549#define SRB1_BASE (0x2110-0x30) /* gen2 */
1550#define SRB2_BASE (0x2120-0x30) /* 830 */
1551#define SRB3_BASE (0x2130-0x30) /* 830 */
1552#define RENDER_RING_BASE 0x02000
1553#define BSD_RING_BASE 0x04000
1554#define GEN6_BSD_RING_BASE 0x12000
1555#define GEN8_BSD2_RING_BASE 0x1c000
1556#define VEBOX_RING_BASE 0x1a000
1557#define BLT_RING_BASE 0x22000
1558#define RING_TAIL(base) _MMIO((base)+0x30)
1559#define RING_HEAD(base) _MMIO((base)+0x34)
1560#define RING_START(base) _MMIO((base)+0x38)
1561#define RING_CTL(base) _MMIO((base)+0x3c)
1562#define RING_SYNC_0(base) _MMIO((base)+0x40)
1563#define RING_SYNC_1(base) _MMIO((base)+0x44)
1564#define RING_SYNC_2(base) _MMIO((base)+0x48)
1565#define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
1566#define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
1567#define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE))
1568#define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
1569#define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
1570#define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE))
1571#define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
1572#define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
1573#define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE))
1574#define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE))
1575#define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE))
1576#define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE))
1577#define GEN6_NOSYNC INVALID_MMIO_REG
1578#define RING_PSMI_CTL(base) _MMIO((base)+0x50)
1579#define RING_MAX_IDLE(base) _MMIO((base)+0x54)
1580#define RING_HWS_PGA(base) _MMIO((base)+0x80)
1581#define RING_HWS_PGA_GEN6(base) _MMIO((base)+0x2080)
1582#define RING_RESET_CTL(base) _MMIO((base)+0xd0)
1583#define RESET_CTL_REQUEST_RESET (1 << 0)
1584#define RESET_CTL_READY_TO_RESET (1 << 1)
1585
1586#define HSW_GTT_CACHE_EN _MMIO(0x4024)
1587#define GTT_CACHE_EN_ALL 0xF0007FFF
1588#define GEN7_WR_WATERMARK _MMIO(0x4028)
1589#define GEN7_GFX_PRIO_CTRL _MMIO(0x402C)
1590#define ARB_MODE _MMIO(0x4030)
1591#define ARB_MODE_SWIZZLE_SNB (1<<4)
1592#define ARB_MODE_SWIZZLE_IVB (1<<5)
1593#define GEN7_GFX_PEND_TLB0 _MMIO(0x4034)
1594#define GEN7_GFX_PEND_TLB1 _MMIO(0x4038)
1595/* L3, CVS, ZTLB, RCC, CASC LRA min, max values */
1596#define GEN7_LRA_LIMITS(i) _MMIO(0x403C + (i) * 4)
1597#define GEN7_LRA_LIMITS_REG_NUM 13
1598#define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070)
1599#define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074)
1600
1601#define GAMTARBMODE _MMIO(0x04a08)
1602#define ARB_MODE_BWGTLB_DISABLE (1<<9)
1603#define ARB_MODE_SWIZZLE_BDW (1<<1)
1604#define RENDER_HWS_PGA_GEN7 _MMIO(0x04080)
1605#define RING_FAULT_REG(ring) _MMIO(0x4094 + 0x100*(ring)->id)
1606#define RING_FAULT_GTTSEL_MASK (1<<11)
1607#define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff)
1608#define RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3)
1609#define RING_FAULT_VALID (1<<0)
1610#define DONE_REG _MMIO(0x40b0)
1611#define GEN8_PRIVATE_PAT_LO _MMIO(0x40e0)
1612#define GEN8_PRIVATE_PAT_HI _MMIO(0x40e0 + 4)
1613#define BSD_HWS_PGA_GEN7 _MMIO(0x04180)
1614#define BLT_HWS_PGA_GEN7 _MMIO(0x04280)
1615#define VEBOX_HWS_PGA_GEN7 _MMIO(0x04380)
1616#define RING_ACTHD(base) _MMIO((base)+0x74)
1617#define RING_ACTHD_UDW(base) _MMIO((base)+0x5c)
1618#define RING_NOPID(base) _MMIO((base)+0x94)
1619#define RING_IMR(base) _MMIO((base)+0xa8)
1620#define RING_HWSTAM(base) _MMIO((base)+0x98)
1621#define RING_TIMESTAMP(base) _MMIO((base)+0x358)
1622#define RING_TIMESTAMP_UDW(base) _MMIO((base)+0x358 + 4)
1623#define TAIL_ADDR 0x001FFFF8
1624#define HEAD_WRAP_COUNT 0xFFE00000
1625#define HEAD_WRAP_ONE 0x00200000
1626#define HEAD_ADDR 0x001FFFFC
1627#define RING_NR_PAGES 0x001FF000
1628#define RING_REPORT_MASK 0x00000006
1629#define RING_REPORT_64K 0x00000002
1630#define RING_REPORT_128K 0x00000004
1631#define RING_NO_REPORT 0x00000000
1632#define RING_VALID_MASK 0x00000001
1633#define RING_VALID 0x00000001
1634#define RING_INVALID 0x00000000
1635#define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */
1636#define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */
1637#define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */
1638
1639#define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base)+0x4D0) + (i)*4)
1640#define RING_MAX_NONPRIV_SLOTS 12
1641
1642#define GEN7_TLB_RD_ADDR _MMIO(0x4700)
1643
1644#if 0
1645#define PRB0_TAIL _MMIO(0x2030)
1646#define PRB0_HEAD _MMIO(0x2034)
1647#define PRB0_START _MMIO(0x2038)
1648#define PRB0_CTL _MMIO(0x203c)
1649#define PRB1_TAIL _MMIO(0x2040) /* 915+ only */
1650#define PRB1_HEAD _MMIO(0x2044) /* 915+ only */
1651#define PRB1_START _MMIO(0x2048) /* 915+ only */
1652#define PRB1_CTL _MMIO(0x204c) /* 915+ only */
1653#endif
1654#define IPEIR_I965 _MMIO(0x2064)
1655#define IPEHR_I965 _MMIO(0x2068)
1656#define GEN7_SC_INSTDONE _MMIO(0x7100)
1657#define GEN7_SAMPLER_INSTDONE _MMIO(0xe160)
1658#define GEN7_ROW_INSTDONE _MMIO(0xe164)
1659#define I915_NUM_INSTDONE_REG 4
1660#define RING_IPEIR(base) _MMIO((base)+0x64)
1661#define RING_IPEHR(base) _MMIO((base)+0x68)
1662/*
1663 * On GEN4, only the render ring INSTDONE exists and has a different
1664 * layout than the GEN7+ version.
1665 * The GEN2 counterpart of this register is GEN2_INSTDONE.
1666 */
1667#define RING_INSTDONE(base) _MMIO((base)+0x6c)
1668#define RING_INSTPS(base) _MMIO((base)+0x70)
1669#define RING_DMA_FADD(base) _MMIO((base)+0x78)
1670#define RING_DMA_FADD_UDW(base) _MMIO((base)+0x60) /* gen8+ */
1671#define RING_INSTPM(base) _MMIO((base)+0xc0)
1672#define RING_MI_MODE(base) _MMIO((base)+0x9c)
1673#define INSTPS _MMIO(0x2070) /* 965+ only */
1674#define GEN4_INSTDONE1 _MMIO(0x207c) /* 965+ only, aka INSTDONE_2 on SNB */
1675#define ACTHD_I965 _MMIO(0x2074)
1676#define HWS_PGA _MMIO(0x2080)
1677#define HWS_ADDRESS_MASK 0xfffff000
1678#define HWS_START_ADDRESS_SHIFT 4
1679#define PWRCTXA _MMIO(0x2088) /* 965GM+ only */
1680#define PWRCTX_EN (1<<0)
1681#define IPEIR _MMIO(0x2088)
1682#define IPEHR _MMIO(0x208c)
1683#define GEN2_INSTDONE _MMIO(0x2090)
1684#define NOPID _MMIO(0x2094)
1685#define HWSTAM _MMIO(0x2098)
1686#define DMA_FADD_I8XX _MMIO(0x20d0)
1687#define RING_BBSTATE(base) _MMIO((base)+0x110)
1688#define RING_BB_PPGTT (1 << 5)
1689#define RING_SBBADDR(base) _MMIO((base)+0x114) /* hsw+ */
1690#define RING_SBBSTATE(base) _MMIO((base)+0x118) /* hsw+ */
1691#define RING_SBBADDR_UDW(base) _MMIO((base)+0x11c) /* gen8+ */
1692#define RING_BBADDR(base) _MMIO((base)+0x140)
1693#define RING_BBADDR_UDW(base) _MMIO((base)+0x168) /* gen8+ */
1694#define RING_BB_PER_CTX_PTR(base) _MMIO((base)+0x1c0) /* gen8+ */
1695#define RING_INDIRECT_CTX(base) _MMIO((base)+0x1c4) /* gen8+ */
1696#define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base)+0x1c8) /* gen8+ */
1697#define RING_CTX_TIMESTAMP(base) _MMIO((base)+0x3a8) /* gen8+ */
1698
1699#define ERROR_GEN6 _MMIO(0x40a0)
1700#define GEN7_ERR_INT _MMIO(0x44040)
1701#define ERR_INT_POISON (1<<31)
1702#define ERR_INT_MMIO_UNCLAIMED (1<<13)
1703#define ERR_INT_PIPE_CRC_DONE_C (1<<8)
1704#define ERR_INT_FIFO_UNDERRUN_C (1<<6)
1705#define ERR_INT_PIPE_CRC_DONE_B (1<<5)
1706#define ERR_INT_FIFO_UNDERRUN_B (1<<3)
1707#define ERR_INT_PIPE_CRC_DONE_A (1<<2)
1708#define ERR_INT_PIPE_CRC_DONE(pipe) (1<<(2 + (pipe)*3))
1709#define ERR_INT_FIFO_UNDERRUN_A (1<<0)
1710#define ERR_INT_FIFO_UNDERRUN(pipe) (1<<((pipe)*3))
1711
1712#define GEN8_FAULT_TLB_DATA0 _MMIO(0x4b10)
1713#define GEN8_FAULT_TLB_DATA1 _MMIO(0x4b14)
1714
1715#define FPGA_DBG _MMIO(0x42300)
1716#define FPGA_DBG_RM_NOCLAIM (1<<31)
1717
1718#define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028)
1719#define CLAIM_ER_CLR (1 << 31)
1720#define CLAIM_ER_OVERFLOW (1 << 16)
1721#define CLAIM_ER_CTR_MASK 0xffff
1722
1723#define DERRMR _MMIO(0x44050)
1724/* Note that HBLANK events are reserved on bdw+ */
1725#define DERRMR_PIPEA_SCANLINE (1<<0)
1726#define DERRMR_PIPEA_PRI_FLIP_DONE (1<<1)
1727#define DERRMR_PIPEA_SPR_FLIP_DONE (1<<2)
1728#define DERRMR_PIPEA_VBLANK (1<<3)
1729#define DERRMR_PIPEA_HBLANK (1<<5)
1730#define DERRMR_PIPEB_SCANLINE (1<<8)
1731#define DERRMR_PIPEB_PRI_FLIP_DONE (1<<9)
1732#define DERRMR_PIPEB_SPR_FLIP_DONE (1<<10)
1733#define DERRMR_PIPEB_VBLANK (1<<11)
1734#define DERRMR_PIPEB_HBLANK (1<<13)
1735/* Note that PIPEC is not a simple translation of PIPEA/PIPEB */
1736#define DERRMR_PIPEC_SCANLINE (1<<14)
1737#define DERRMR_PIPEC_PRI_FLIP_DONE (1<<15)
1738#define DERRMR_PIPEC_SPR_FLIP_DONE (1<<20)
1739#define DERRMR_PIPEC_VBLANK (1<<21)
1740#define DERRMR_PIPEC_HBLANK (1<<22)
1741
1742
1743/* GM45+ chicken bits -- debug workaround bits that may be required
1744 * for various sorts of correct behavior. The top 16 bits of each are
1745 * the enables for writing to the corresponding low bit.
1746 */
1747#define _3D_CHICKEN _MMIO(0x2084)
1748#define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10)
1749#define _3D_CHICKEN2 _MMIO(0x208c)
1750/* Disables pipelining of read flushes past the SF-WIZ interface.
1751 * Required on all Ironlake steppings according to the B-Spec, but the
1752 * particular danger of not doing so is not specified.
1753 */
1754# define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14)
1755#define _3D_CHICKEN3 _MMIO(0x2090)
1756#define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10)
1757#define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5)
1758#define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x)<<1) /* gen8+ */
1759#define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1) /* gen6 */
1760
1761#define MI_MODE _MMIO(0x209c)
1762# define VS_TIMER_DISPATCH (1 << 6)
1763# define MI_FLUSH_ENABLE (1 << 12)
1764# define ASYNC_FLIP_PERF_DISABLE (1 << 14)
1765# define MODE_IDLE (1 << 9)
1766# define STOP_RING (1 << 8)
1767
1768#define GEN6_GT_MODE _MMIO(0x20d0)
1769#define GEN7_GT_MODE _MMIO(0x7008)
1770#define GEN6_WIZ_HASHING(hi, lo) (((hi) << 9) | ((lo) << 7))
1771#define GEN6_WIZ_HASHING_8x8 GEN6_WIZ_HASHING(0, 0)
1772#define GEN6_WIZ_HASHING_8x4 GEN6_WIZ_HASHING(0, 1)
1773#define GEN6_WIZ_HASHING_16x4 GEN6_WIZ_HASHING(1, 0)
1774#define GEN6_WIZ_HASHING_MASK GEN6_WIZ_HASHING(1, 1)
1775#define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5)
1776#define GEN9_IZ_HASHING_MASK(slice) (0x3 << ((slice) * 2))
1777#define GEN9_IZ_HASHING(slice, val) ((val) << ((slice) * 2))
1778
1779#define GFX_MODE _MMIO(0x2520)
1780#define GFX_MODE_GEN7 _MMIO(0x229c)
1781#define RING_MODE_GEN7(ring) _MMIO((ring)->mmio_base+0x29c)
1782#define GFX_RUN_LIST_ENABLE (1<<15)
1783#define GFX_INTERRUPT_STEERING (1<<14)
1784#define GFX_TLB_INVALIDATE_EXPLICIT (1<<13)
1785#define GFX_SURFACE_FAULT_ENABLE (1<<12)
1786#define GFX_REPLAY_MODE (1<<11)
1787#define GFX_PSMI_GRANULARITY (1<<10)
1788#define GFX_PPGTT_ENABLE (1<<9)
1789#define GEN8_GFX_PPGTT_48B (1<<7)
1790
1791#define GFX_FORWARD_VBLANK_MASK (3<<5)
1792#define GFX_FORWARD_VBLANK_NEVER (0<<5)
1793#define GFX_FORWARD_VBLANK_ALWAYS (1<<5)
1794#define GFX_FORWARD_VBLANK_COND (2<<5)
1795
1796#define VLV_DISPLAY_BASE 0x180000
1797#define VLV_MIPI_BASE VLV_DISPLAY_BASE
1798
1799#define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030)
1800#define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034)
1801#define SCPD0 _MMIO(0x209c) /* 915+ only */
1802#define IER _MMIO(0x20a0)
1803#define IIR _MMIO(0x20a4)
1804#define IMR _MMIO(0x20a8)
1805#define ISR _MMIO(0x20ac)
1806#define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060)
1807#define GINT_DIS (1<<22)
1808#define GCFG_DIS (1<<8)
1809#define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064)
1810#define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084)
1811#define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0)
1812#define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4)
1813#define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8)
1814#define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac)
1815#define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120)
1816#define VLV_PCBR_ADDR_SHIFT 12
1817
1818#define DISPLAY_PLANE_FLIP_PENDING(plane) (1<<(11-(plane))) /* A and B only */
1819#define EIR _MMIO(0x20b0)
1820#define EMR _MMIO(0x20b4)
1821#define ESR _MMIO(0x20b8)
1822#define GM45_ERROR_PAGE_TABLE (1<<5)
1823#define GM45_ERROR_MEM_PRIV (1<<4)
1824#define I915_ERROR_PAGE_TABLE (1<<4)
1825#define GM45_ERROR_CP_PRIV (1<<3)
1826#define I915_ERROR_MEMORY_REFRESH (1<<1)
1827#define I915_ERROR_INSTRUCTION (1<<0)
1828#define INSTPM _MMIO(0x20c0)
1829#define INSTPM_SELF_EN (1<<12) /* 915GM only */
1830#define INSTPM_AGPBUSY_INT_EN (1<<11) /* gen3: when disabled, pending interrupts
1831 will not assert AGPBUSY# and will only
1832 be delivered when out of C3. */
1833#define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */
1834#define INSTPM_TLB_INVALIDATE (1<<9)
1835#define INSTPM_SYNC_FLUSH (1<<5)
1836#define ACTHD _MMIO(0x20c8)
1837#define MEM_MODE _MMIO(0x20cc)
1838#define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1<<3) /* 830 only */
1839#define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1<<2) /* 830/845 only */
1840#define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1<<2) /* 85x only */
1841#define FW_BLC _MMIO(0x20d8)
1842#define FW_BLC2 _MMIO(0x20dc)
1843#define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */
1844#define FW_BLC_SELF_EN_MASK (1<<31)
1845#define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */
1846#define FW_BLC_SELF_EN (1<<15) /* 945 only */
1847#define MM_BURST_LENGTH 0x00700000
1848#define MM_FIFO_WATERMARK 0x0001F000
1849#define LM_BURST_LENGTH 0x00000700
1850#define LM_FIFO_WATERMARK 0x0000001F
1851#define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */
1852
1853/* Make render/texture TLB fetches lower priorty than associated data
1854 * fetches. This is not turned on by default
1855 */
1856#define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15)
1857
1858/* Isoch request wait on GTT enable (Display A/B/C streams).
1859 * Make isoch requests stall on the TLB update. May cause
1860 * display underruns (test mode only)
1861 */
1862#define MI_ARB_ISOCH_WAIT_GTT (1 << 14)
1863
1864/* Block grant count for isoch requests when block count is
1865 * set to a finite value.
1866 */
1867#define MI_ARB_BLOCK_GRANT_MASK (3 << 12)
1868#define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */
1869#define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */
1870#define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */
1871#define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */
1872
1873/* Enable render writes to complete in C2/C3/C4 power states.
1874 * If this isn't enabled, render writes are prevented in low
1875 * power states. That seems bad to me.
1876 */
1877#define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11)
1878
1879/* This acknowledges an async flip immediately instead
1880 * of waiting for 2TLB fetches.
1881 */
1882#define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10)
1883
1884/* Enables non-sequential data reads through arbiter
1885 */
1886#define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9)
1887
1888/* Disable FSB snooping of cacheable write cycles from binner/render
1889 * command stream
1890 */
1891#define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8)
1892
1893/* Arbiter time slice for non-isoch streams */
1894#define MI_ARB_TIME_SLICE_MASK (7 << 5)
1895#define MI_ARB_TIME_SLICE_1 (0 << 5)
1896#define MI_ARB_TIME_SLICE_2 (1 << 5)
1897#define MI_ARB_TIME_SLICE_4 (2 << 5)
1898#define MI_ARB_TIME_SLICE_6 (3 << 5)
1899#define MI_ARB_TIME_SLICE_8 (4 << 5)
1900#define MI_ARB_TIME_SLICE_10 (5 << 5)
1901#define MI_ARB_TIME_SLICE_14 (6 << 5)
1902#define MI_ARB_TIME_SLICE_16 (7 << 5)
1903
1904/* Low priority grace period page size */
1905#define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
1906#define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
1907
1908/* Disable display A/B trickle feed */
1909#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
1910
1911/* Set display plane priority */
1912#define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
1913#define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
1914
1915#define MI_STATE _MMIO(0x20e4) /* gen2 only */
1916#define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */
1917#define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */
1918
1919#define CACHE_MODE_0 _MMIO(0x2120) /* 915+ only */
1920#define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8)
1921#define CM0_IZ_OPT_DISABLE (1<<6)
1922#define CM0_ZR_OPT_DISABLE (1<<5)
1923#define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5)
1924#define CM0_DEPTH_EVICT_DISABLE (1<<4)
1925#define CM0_COLOR_EVICT_DISABLE (1<<3)
1926#define CM0_DEPTH_WRITE_DISABLE (1<<1)
1927#define CM0_RC_OP_FLUSH_DISABLE (1<<0)
1928#define GFX_FLSH_CNTL _MMIO(0x2170) /* 915+ only */
1929#define GFX_FLSH_CNTL_GEN6 _MMIO(0x101008)
1930#define GFX_FLSH_CNTL_EN (1<<0)
1931#define ECOSKPD _MMIO(0x21d0)
1932#define ECO_GATING_CX_ONLY (1<<3)
1933#define ECO_FLIP_DONE (1<<0)
1934
1935#define CACHE_MODE_0_GEN7 _MMIO(0x7000) /* IVB+ */
1936#define RC_OP_FLUSH_ENABLE (1<<0)
1937#define HIZ_RAW_STALL_OPT_DISABLE (1<<2)
1938#define CACHE_MODE_1 _MMIO(0x7004) /* IVB+ */
1939#define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6)
1940#define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1<<6)
1941#define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1<<1)
1942
1943#define GEN6_BLITTER_ECOSKPD _MMIO(0x221d0)
1944#define GEN6_BLITTER_LOCK_SHIFT 16
1945#define GEN6_BLITTER_FBC_NOTIFY (1<<3)
1946
1947#define GEN6_RC_SLEEP_PSMI_CONTROL _MMIO(0x2050)
1948#define GEN6_PSMI_SLEEP_MSG_DISABLE (1 << 0)
1949#define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12)
1950#define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1<<10)
1951
1952/* Fuse readout registers for GT */
1953#define CHV_FUSE_GT _MMIO(VLV_DISPLAY_BASE + 0x2168)
1954#define CHV_FGT_DISABLE_SS0 (1 << 10)
1955#define CHV_FGT_DISABLE_SS1 (1 << 11)
1956#define CHV_FGT_EU_DIS_SS0_R0_SHIFT 16
1957#define CHV_FGT_EU_DIS_SS0_R0_MASK (0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT)
1958#define CHV_FGT_EU_DIS_SS0_R1_SHIFT 20
1959#define CHV_FGT_EU_DIS_SS0_R1_MASK (0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT)
1960#define CHV_FGT_EU_DIS_SS1_R0_SHIFT 24
1961#define CHV_FGT_EU_DIS_SS1_R0_MASK (0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT)
1962#define CHV_FGT_EU_DIS_SS1_R1_SHIFT 28
1963#define CHV_FGT_EU_DIS_SS1_R1_MASK (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT)
1964
1965#define GEN8_FUSE2 _MMIO(0x9120)
1966#define GEN8_F2_SS_DIS_SHIFT 21
1967#define GEN8_F2_SS_DIS_MASK (0x7 << GEN8_F2_SS_DIS_SHIFT)
1968#define GEN8_F2_S_ENA_SHIFT 25
1969#define GEN8_F2_S_ENA_MASK (0x7 << GEN8_F2_S_ENA_SHIFT)
1970
1971#define GEN9_F2_SS_DIS_SHIFT 20
1972#define GEN9_F2_SS_DIS_MASK (0xf << GEN9_F2_SS_DIS_SHIFT)
1973
1974#define GEN8_EU_DISABLE0 _MMIO(0x9134)
1975#define GEN8_EU_DIS0_S0_MASK 0xffffff
1976#define GEN8_EU_DIS0_S1_SHIFT 24
1977#define GEN8_EU_DIS0_S1_MASK (0xff << GEN8_EU_DIS0_S1_SHIFT)
1978
1979#define GEN8_EU_DISABLE1 _MMIO(0x9138)
1980#define GEN8_EU_DIS1_S1_MASK 0xffff
1981#define GEN8_EU_DIS1_S2_SHIFT 16
1982#define GEN8_EU_DIS1_S2_MASK (0xffff << GEN8_EU_DIS1_S2_SHIFT)
1983
1984#define GEN8_EU_DISABLE2 _MMIO(0x913c)
1985#define GEN8_EU_DIS2_S2_MASK 0xff
1986
1987#define GEN9_EU_DISABLE(slice) _MMIO(0x9134 + (slice)*0x4)
1988
1989#define GEN6_BSD_SLEEP_PSMI_CONTROL _MMIO(0x12050)
1990#define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
1991#define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
1992#define GEN6_BSD_SLEEP_INDICATOR (1 << 3)
1993#define GEN6_BSD_GO_INDICATOR (1 << 4)
1994
1995/* On modern GEN architectures interrupt control consists of two sets
1996 * of registers. The first set pertains to the ring generating the
1997 * interrupt. The second control is for the functional block generating the
1998 * interrupt. These are PM, GT, DE, etc.
1999 *
2000 * Luckily *knocks on wood* all the ring interrupt bits match up with the
2001 * GT interrupt bits, so we don't need to duplicate the defines.
2002 *
2003 * These defines should cover us well from SNB->HSW with minor exceptions
2004 * it can also work on ILK.
2005 */
2006#define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26)
2007#define GT_BLT_CS_ERROR_INTERRUPT (1 << 25)
2008#define GT_BLT_USER_INTERRUPT (1 << 22)
2009#define GT_BSD_CS_ERROR_INTERRUPT (1 << 15)
2010#define GT_BSD_USER_INTERRUPT (1 << 12)
2011#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */
2012#define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8)
2013#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */
2014#define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4)
2015#define GT_RENDER_CS_MASTER_ERROR_INTERRUPT (1 << 3)
2016#define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2)
2017#define GT_RENDER_DEBUG_INTERRUPT (1 << 1)
2018#define GT_RENDER_USER_INTERRUPT (1 << 0)
2019
2020#define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */
2021#define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */
2022
2023#define GT_PARITY_ERROR(dev) \
2024 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \
2025 (IS_HASWELL(dev) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
2026
2027/* These are all the "old" interrupts */
2028#define ILK_BSD_USER_INTERRUPT (1<<5)
2029
2030#define I915_PM_INTERRUPT (1<<31)
2031#define I915_ISP_INTERRUPT (1<<22)
2032#define I915_LPE_PIPE_B_INTERRUPT (1<<21)
2033#define I915_LPE_PIPE_A_INTERRUPT (1<<20)
2034#define I915_MIPIC_INTERRUPT (1<<19)
2035#define I915_MIPIA_INTERRUPT (1<<18)
2036#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
2037#define I915_DISPLAY_PORT_INTERRUPT (1<<17)
2038#define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1<<16)
2039#define I915_MASTER_ERROR_INTERRUPT (1<<15)
2040#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
2041#define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1<<14)
2042#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */
2043#define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1<<13)
2044#define I915_HWB_OOM_INTERRUPT (1<<13)
2045#define I915_LPE_PIPE_C_INTERRUPT (1<<12)
2046#define I915_SYNC_STATUS_INTERRUPT (1<<12)
2047#define I915_MISC_INTERRUPT (1<<11)
2048#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
2049#define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1<<10)
2050#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
2051#define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1<<9)
2052#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
2053#define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1<<8)
2054#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
2055#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
2056#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
2057#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
2058#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
2059#define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1<<3)
2060#define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1<<2)
2061#define I915_DEBUG_INTERRUPT (1<<2)
2062#define I915_WINVALID_INTERRUPT (1<<1)
2063#define I915_USER_INTERRUPT (1<<1)
2064#define I915_ASLE_INTERRUPT (1<<0)
2065#define I915_BSD_USER_INTERRUPT (1<<25)
2066
2067#define GEN6_BSD_RNCID _MMIO(0x12198)
2068
2069#define GEN7_FF_THREAD_MODE _MMIO(0x20a0)
2070#define GEN7_FF_SCHED_MASK 0x0077070
2071#define GEN8_FF_DS_REF_CNT_FFME (1 << 19)
2072#define GEN7_FF_TS_SCHED_HS1 (0x5<<16)
2073#define GEN7_FF_TS_SCHED_HS0 (0x3<<16)
2074#define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1<<16)
2075#define GEN7_FF_TS_SCHED_HW (0x0<<16) /* Default */
2076#define GEN7_FF_VS_REF_CNT_FFME (1 << 15)
2077#define GEN7_FF_VS_SCHED_HS1 (0x5<<12)
2078#define GEN7_FF_VS_SCHED_HS0 (0x3<<12)
2079#define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1<<12) /* Default */
2080#define GEN7_FF_VS_SCHED_HW (0x0<<12)
2081#define GEN7_FF_DS_SCHED_HS1 (0x5<<4)
2082#define GEN7_FF_DS_SCHED_HS0 (0x3<<4)
2083#define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1<<4) /* Default */
2084#define GEN7_FF_DS_SCHED_HW (0x0<<4)
2085
2086/*
2087 * Framebuffer compression (915+ only)
2088 */
2089
2090#define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */
2091#define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */
2092#define FBC_CONTROL _MMIO(0x3208)
2093#define FBC_CTL_EN (1<<31)
2094#define FBC_CTL_PERIODIC (1<<30)
2095#define FBC_CTL_INTERVAL_SHIFT (16)
2096#define FBC_CTL_UNCOMPRESSIBLE (1<<14)
2097#define FBC_CTL_C3_IDLE (1<<13)
2098#define FBC_CTL_STRIDE_SHIFT (5)
2099#define FBC_CTL_FENCENO_SHIFT (0)
2100#define FBC_COMMAND _MMIO(0x320c)
2101#define FBC_CMD_COMPRESS (1<<0)
2102#define FBC_STATUS _MMIO(0x3210)
2103#define FBC_STAT_COMPRESSING (1<<31)
2104#define FBC_STAT_COMPRESSED (1<<30)
2105#define FBC_STAT_MODIFIED (1<<29)
2106#define FBC_STAT_CURRENT_LINE_SHIFT (0)
2107#define FBC_CONTROL2 _MMIO(0x3214)
2108#define FBC_CTL_FENCE_DBL (0<<4)
2109#define FBC_CTL_IDLE_IMM (0<<2)
2110#define FBC_CTL_IDLE_FULL (1<<2)
2111#define FBC_CTL_IDLE_LINE (2<<2)
2112#define FBC_CTL_IDLE_DEBUG (3<<2)
2113#define FBC_CTL_CPU_FENCE (1<<1)
2114#define FBC_CTL_PLANE(plane) ((plane)<<0)
2115#define FBC_FENCE_OFF _MMIO(0x3218) /* BSpec typo has 321Bh */
2116#define FBC_TAG(i) _MMIO(0x3300 + (i) * 4)
2117
2118#define FBC_STATUS2 _MMIO(0x43214)
2119#define FBC_COMPRESSION_MASK 0x7ff
2120
2121#define FBC_LL_SIZE (1536)
2122
2123/* Framebuffer compression for GM45+ */
2124#define DPFC_CB_BASE _MMIO(0x3200)
2125#define DPFC_CONTROL _MMIO(0x3208)
2126#define DPFC_CTL_EN (1<<31)
2127#define DPFC_CTL_PLANE(plane) ((plane)<<30)
2128#define IVB_DPFC_CTL_PLANE(plane) ((plane)<<29)
2129#define DPFC_CTL_FENCE_EN (1<<29)
2130#define IVB_DPFC_CTL_FENCE_EN (1<<28)
2131#define DPFC_CTL_PERSISTENT_MODE (1<<25)
2132#define DPFC_SR_EN (1<<10)
2133#define DPFC_CTL_LIMIT_1X (0<<6)
2134#define DPFC_CTL_LIMIT_2X (1<<6)
2135#define DPFC_CTL_LIMIT_4X (2<<6)
2136#define DPFC_RECOMP_CTL _MMIO(0x320c)
2137#define DPFC_RECOMP_STALL_EN (1<<27)
2138#define DPFC_RECOMP_STALL_WM_SHIFT (16)
2139#define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
2140#define DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
2141#define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
2142#define DPFC_STATUS _MMIO(0x3210)
2143#define DPFC_INVAL_SEG_SHIFT (16)
2144#define DPFC_INVAL_SEG_MASK (0x07ff0000)
2145#define DPFC_COMP_SEG_SHIFT (0)
2146#define DPFC_COMP_SEG_MASK (0x000003ff)
2147#define DPFC_STATUS2 _MMIO(0x3214)
2148#define DPFC_FENCE_YOFF _MMIO(0x3218)
2149#define DPFC_CHICKEN _MMIO(0x3224)
2150#define DPFC_HT_MODIFY (1<<31)
2151
2152/* Framebuffer compression for Ironlake */
2153#define ILK_DPFC_CB_BASE _MMIO(0x43200)
2154#define ILK_DPFC_CONTROL _MMIO(0x43208)
2155#define FBC_CTL_FALSE_COLOR (1<<10)
2156/* The bit 28-8 is reserved */
2157#define DPFC_RESERVED (0x1FFFFF00)
2158#define ILK_DPFC_RECOMP_CTL _MMIO(0x4320c)
2159#define ILK_DPFC_STATUS _MMIO(0x43210)
2160#define ILK_DPFC_FENCE_YOFF _MMIO(0x43218)
2161#define ILK_DPFC_CHICKEN _MMIO(0x43224)
2162#define ILK_FBC_RT_BASE _MMIO(0x2128)
2163#define ILK_FBC_RT_VALID (1<<0)
2164#define SNB_FBC_FRONT_BUFFER (1<<1)
2165
2166#define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000)
2167#define ILK_FBCQ_DIS (1<<22)
2168#define ILK_PABSTRETCH_DIS (1<<21)
2169
2170
2171/*
2172 * Framebuffer compression for Sandybridge
2173 *
2174 * The following two registers are of type GTTMMADR
2175 */
2176#define SNB_DPFC_CTL_SA _MMIO(0x100100)
2177#define SNB_CPU_FENCE_ENABLE (1<<29)
2178#define DPFC_CPU_FENCE_OFFSET _MMIO(0x100104)
2179
2180/* Framebuffer compression for Ivybridge */
2181#define IVB_FBC_RT_BASE _MMIO(0x7020)
2182
2183#define IPS_CTL _MMIO(0x43408)
2184#define IPS_ENABLE (1 << 31)
2185
2186#define MSG_FBC_REND_STATE _MMIO(0x50380)
2187#define FBC_REND_NUKE (1<<2)
2188#define FBC_REND_CACHE_CLEAN (1<<1)
2189
2190/*
2191 * GPIO regs
2192 */
2193#define GPIOA _MMIO(0x5010)
2194#define GPIOB _MMIO(0x5014)
2195#define GPIOC _MMIO(0x5018)
2196#define GPIOD _MMIO(0x501c)
2197#define GPIOE _MMIO(0x5020)
2198#define GPIOF _MMIO(0x5024)
2199#define GPIOG _MMIO(0x5028)
2200#define GPIOH _MMIO(0x502c)
2201# define GPIO_CLOCK_DIR_MASK (1 << 0)
2202# define GPIO_CLOCK_DIR_IN (0 << 1)
2203# define GPIO_CLOCK_DIR_OUT (1 << 1)
2204# define GPIO_CLOCK_VAL_MASK (1 << 2)
2205# define GPIO_CLOCK_VAL_OUT (1 << 3)
2206# define GPIO_CLOCK_VAL_IN (1 << 4)
2207# define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
2208# define GPIO_DATA_DIR_MASK (1 << 8)
2209# define GPIO_DATA_DIR_IN (0 << 9)
2210# define GPIO_DATA_DIR_OUT (1 << 9)
2211# define GPIO_DATA_VAL_MASK (1 << 10)
2212# define GPIO_DATA_VAL_OUT (1 << 11)
2213# define GPIO_DATA_VAL_IN (1 << 12)
2214# define GPIO_DATA_PULLUP_DISABLE (1 << 13)
2215
2216#define GMBUS0 _MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */
2217#define GMBUS_RATE_100KHZ (0<<8)
2218#define GMBUS_RATE_50KHZ (1<<8)
2219#define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */
2220#define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */
2221#define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */
2222#define GMBUS_PIN_DISABLED 0
2223#define GMBUS_PIN_SSC 1
2224#define GMBUS_PIN_VGADDC 2
2225#define GMBUS_PIN_PANEL 3
2226#define GMBUS_PIN_DPD_CHV 3 /* HDMID_CHV */
2227#define GMBUS_PIN_DPC 4 /* HDMIC */
2228#define GMBUS_PIN_DPB 5 /* SDVO, HDMIB */
2229#define GMBUS_PIN_DPD 6 /* HDMID */
2230#define GMBUS_PIN_RESERVED 7 /* 7 reserved */
2231#define GMBUS_PIN_1_BXT 1
2232#define GMBUS_PIN_2_BXT 2
2233#define GMBUS_PIN_3_BXT 3
2234#define GMBUS_NUM_PINS 7 /* including 0 */
2235#define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
2236#define GMBUS_SW_CLR_INT (1<<31)
2237#define GMBUS_SW_RDY (1<<30)
2238#define GMBUS_ENT (1<<29) /* enable timeout */
2239#define GMBUS_CYCLE_NONE (0<<25)
2240#define GMBUS_CYCLE_WAIT (1<<25)
2241#define GMBUS_CYCLE_INDEX (2<<25)
2242#define GMBUS_CYCLE_STOP (4<<25)
2243#define GMBUS_BYTE_COUNT_SHIFT 16
2244#define GMBUS_BYTE_COUNT_MAX 256U
2245#define GMBUS_SLAVE_INDEX_SHIFT 8
2246#define GMBUS_SLAVE_ADDR_SHIFT 1
2247#define GMBUS_SLAVE_READ (1<<0)
2248#define GMBUS_SLAVE_WRITE (0<<0)
2249#define GMBUS2 _MMIO(dev_priv->gpio_mmio_base + 0x5108) /* status */
2250#define GMBUS_INUSE (1<<15)
2251#define GMBUS_HW_WAIT_PHASE (1<<14)
2252#define GMBUS_STALL_TIMEOUT (1<<13)
2253#define GMBUS_INT (1<<12)
2254#define GMBUS_HW_RDY (1<<11)
2255#define GMBUS_SATOER (1<<10)
2256#define GMBUS_ACTIVE (1<<9)
2257#define GMBUS3 _MMIO(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */
2258#define GMBUS4 _MMIO(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */
2259#define GMBUS_SLAVE_TIMEOUT_EN (1<<4)
2260#define GMBUS_NAK_EN (1<<3)
2261#define GMBUS_IDLE_EN (1<<2)
2262#define GMBUS_HW_WAIT_EN (1<<1)
2263#define GMBUS_HW_RDY_EN (1<<0)
2264#define GMBUS5 _MMIO(dev_priv->gpio_mmio_base + 0x5120) /* byte index */
2265#define GMBUS_2BYTE_INDEX_EN (1<<31)
2266
2267/*
2268 * Clock control & power management
2269 */
2270#define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014)
2271#define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018)
2272#define _CHV_DPLL_C (dev_priv->info.display_mmio_offset + 0x6030)
2273#define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
2274
2275#define VGA0 _MMIO(0x6000)
2276#define VGA1 _MMIO(0x6004)
2277#define VGA_PD _MMIO(0x6010)
2278#define VGA0_PD_P2_DIV_4 (1 << 7)
2279#define VGA0_PD_P1_DIV_2 (1 << 5)
2280#define VGA0_PD_P1_SHIFT 0
2281#define VGA0_PD_P1_MASK (0x1f << 0)
2282#define VGA1_PD_P2_DIV_4 (1 << 15)
2283#define VGA1_PD_P1_DIV_2 (1 << 13)
2284#define VGA1_PD_P1_SHIFT 8
2285#define VGA1_PD_P1_MASK (0x1f << 8)
2286#define DPLL_VCO_ENABLE (1 << 31)
2287#define DPLL_SDVO_HIGH_SPEED (1 << 30)
2288#define DPLL_DVO_2X_MODE (1 << 30)
2289#define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30)
2290#define DPLL_SYNCLOCK_ENABLE (1 << 29)
2291#define DPLL_REF_CLK_ENABLE_VLV (1 << 29)
2292#define DPLL_VGA_MODE_DIS (1 << 28)
2293#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
2294#define DPLLB_MODE_LVDS (2 << 26) /* i915 */
2295#define DPLL_MODE_MASK (3 << 26)
2296#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
2297#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
2298#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
2299#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
2300#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
2301#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
2302#define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
2303#define DPLL_LOCK_VLV (1<<15)
2304#define DPLL_INTEGRATED_CRI_CLK_VLV (1<<14)
2305#define DPLL_INTEGRATED_REF_CLK_VLV (1<<13)
2306#define DPLL_SSC_REF_CLK_CHV (1<<13)
2307#define DPLL_PORTC_READY_MASK (0xf << 4)
2308#define DPLL_PORTB_READY_MASK (0xf)
2309
2310#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
2311
2312/* Additional CHV pll/phy registers */
2313#define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240)
2314#define DPLL_PORTD_READY_MASK (0xf)
2315#define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100)
2316#define PHY_CH_POWER_DOWN_OVRD_EN(phy, ch) (1 << (2*(phy)+(ch)+27))
2317#define PHY_LDO_DELAY_0NS 0x0
2318#define PHY_LDO_DELAY_200NS 0x1
2319#define PHY_LDO_DELAY_600NS 0x2
2320#define PHY_LDO_SEQ_DELAY(delay, phy) ((delay) << (2*(phy)+23))
2321#define PHY_CH_POWER_DOWN_OVRD(mask, phy, ch) ((mask) << (8*(phy)+4*(ch)+11))
2322#define PHY_CH_SU_PSR 0x1
2323#define PHY_CH_DEEP_PSR 0x7
2324#define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6*(phy)+3*(ch)+2))
2325#define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy))
2326#define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104)
2327#define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1<<31) : (1<<30))
2328#define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6-(6*(phy)+3*(ch))))
2329#define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8-(6*(phy)+3*(ch)+(spline))))
2330
2331/*
2332 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
2333 * this field (only one bit may be set).
2334 */
2335#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
2336#define DPLL_FPA01_P1_POST_DIV_SHIFT 16
2337#define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
2338/* i830, required in DVO non-gang */
2339#define PLL_P2_DIVIDE_BY_4 (1 << 23)
2340#define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
2341#define PLL_REF_INPUT_DREFCLK (0 << 13)
2342#define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
2343#define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
2344#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
2345#define PLL_REF_INPUT_MASK (3 << 13)
2346#define PLL_LOAD_PULSE_PHASE_SHIFT 9
2347/* Ironlake */
2348# define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
2349# define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
2350# define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9)
2351# define DPLL_FPA1_P1_POST_DIV_SHIFT 0
2352# define DPLL_FPA1_P1_POST_DIV_MASK 0xff
2353
2354/*
2355 * Parallel to Serial Load Pulse phase selection.
2356 * Selects the phase for the 10X DPLL clock for the PCIe
2357 * digital display port. The range is 4 to 13; 10 or more
2358 * is just a flip delay. The default is 6
2359 */
2360#define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
2361#define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
2362/*
2363 * SDVO multiplier for 945G/GM. Not used on 965.
2364 */
2365#define SDVO_MULTIPLIER_MASK 0x000000ff
2366#define SDVO_MULTIPLIER_SHIFT_HIRES 4
2367#define SDVO_MULTIPLIER_SHIFT_VGA 0
2368
2369#define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c)
2370#define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020)
2371#define _CHV_DPLL_C_MD (dev_priv->info.display_mmio_offset + 0x603c)
2372#define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
2373
2374/*
2375 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
2376 *
2377 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
2378 */
2379#define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
2380#define DPLL_MD_UDI_DIVIDER_SHIFT 24
2381/* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
2382#define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
2383#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
2384/*
2385 * SDVO/UDI pixel multiplier.
2386 *
2387 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
2388 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
2389 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
2390 * dummy bytes in the datastream at an increased clock rate, with both sides of
2391 * the link knowing how many bytes are fill.
2392 *
2393 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
2394 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
2395 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
2396 * through an SDVO command.
2397 *
2398 * This register field has values of multiplication factor minus 1, with
2399 * a maximum multiplier of 5 for SDVO.
2400 */
2401#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
2402#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
2403/*
2404 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
2405 * This best be set to the default value (3) or the CRT won't work. No,
2406 * I don't entirely understand what this does...
2407 */
2408#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
2409#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
2410
2411#define _FPA0 0x6040
2412#define _FPA1 0x6044
2413#define _FPB0 0x6048
2414#define _FPB1 0x604c
2415#define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0)
2416#define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1)
2417#define FP_N_DIV_MASK 0x003f0000
2418#define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
2419#define FP_N_DIV_SHIFT 16
2420#define FP_M1_DIV_MASK 0x00003f00
2421#define FP_M1_DIV_SHIFT 8
2422#define FP_M2_DIV_MASK 0x0000003f
2423#define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
2424#define FP_M2_DIV_SHIFT 0
2425#define DPLL_TEST _MMIO(0x606c)
2426#define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
2427#define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
2428#define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
2429#define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
2430#define DPLLB_TEST_N_BYPASS (1 << 19)
2431#define DPLLB_TEST_M_BYPASS (1 << 18)
2432#define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
2433#define DPLLA_TEST_N_BYPASS (1 << 3)
2434#define DPLLA_TEST_M_BYPASS (1 << 2)
2435#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
2436#define D_STATE _MMIO(0x6104)
2437#define DSTATE_GFX_RESET_I830 (1<<6)
2438#define DSTATE_PLL_D3_OFF (1<<3)
2439#define DSTATE_GFX_CLOCK_GATING (1<<1)
2440#define DSTATE_DOT_CLOCK_GATING (1<<0)
2441#define DSPCLK_GATE_D _MMIO(dev_priv->info.display_mmio_offset + 0x6200)
2442# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
2443# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
2444# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
2445# define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
2446# define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
2447# define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
2448# define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
2449# define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
2450# define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
2451# define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
2452# define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
2453# define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
2454# define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
2455# define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
2456# define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
2457# define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
2458# define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
2459# define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
2460# define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
2461# define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
2462# define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
2463# define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
2464# define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
2465# define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
2466# define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
2467# define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
2468# define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
2469# define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
2470/*
2471 * This bit must be set on the 830 to prevent hangs when turning off the
2472 * overlay scaler.
2473 */
2474# define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
2475# define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
2476# define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
2477# define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
2478# define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
2479
2480#define RENCLK_GATE_D1 _MMIO(0x6204)
2481# define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
2482# define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
2483# define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
2484# define PC_BE_CLOCK_GATE_DISABLE (1 << 10)
2485# define WINDOWER_CLOCK_GATE_DISABLE (1 << 9)
2486# define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8)
2487# define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7)
2488# define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6)
2489# define MAG_CLOCK_GATE_DISABLE (1 << 5)
2490/* This bit must be unset on 855,865 */
2491# define MECI_CLOCK_GATE_DISABLE (1 << 4)
2492# define DCMP_CLOCK_GATE_DISABLE (1 << 3)
2493# define MEC_CLOCK_GATE_DISABLE (1 << 2)
2494# define MECO_CLOCK_GATE_DISABLE (1 << 1)
2495/* This bit must be set on 855,865. */
2496# define SV_CLOCK_GATE_DISABLE (1 << 0)
2497# define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16)
2498# define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15)
2499# define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14)
2500# define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13)
2501# define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12)
2502# define I915_WM_CLOCK_GATE_DISABLE (1 << 11)
2503# define I915_IZ_CLOCK_GATE_DISABLE (1 << 10)
2504# define I915_PI_CLOCK_GATE_DISABLE (1 << 9)
2505# define I915_DI_CLOCK_GATE_DISABLE (1 << 8)
2506# define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7)
2507# define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6)
2508# define I915_SC_CLOCK_GATE_DISABLE (1 << 5)
2509# define I915_FL_CLOCK_GATE_DISABLE (1 << 4)
2510# define I915_DM_CLOCK_GATE_DISABLE (1 << 3)
2511# define I915_PS_CLOCK_GATE_DISABLE (1 << 2)
2512# define I915_CC_CLOCK_GATE_DISABLE (1 << 1)
2513# define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
2514
2515# define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30)
2516/* This bit must always be set on 965G/965GM */
2517# define I965_RCC_CLOCK_GATE_DISABLE (1 << 29)
2518# define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28)
2519# define I965_DAP_CLOCK_GATE_DISABLE (1 << 27)
2520# define I965_ROC_CLOCK_GATE_DISABLE (1 << 26)
2521# define I965_GW_CLOCK_GATE_DISABLE (1 << 25)
2522# define I965_TD_CLOCK_GATE_DISABLE (1 << 24)
2523/* This bit must always be set on 965G */
2524# define I965_ISC_CLOCK_GATE_DISABLE (1 << 23)
2525# define I965_IC_CLOCK_GATE_DISABLE (1 << 22)
2526# define I965_EU_CLOCK_GATE_DISABLE (1 << 21)
2527# define I965_IF_CLOCK_GATE_DISABLE (1 << 20)
2528# define I965_TC_CLOCK_GATE_DISABLE (1 << 19)
2529# define I965_SO_CLOCK_GATE_DISABLE (1 << 17)
2530# define I965_FBC_CLOCK_GATE_DISABLE (1 << 16)
2531# define I965_MARI_CLOCK_GATE_DISABLE (1 << 15)
2532# define I965_MASF_CLOCK_GATE_DISABLE (1 << 14)
2533# define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13)
2534# define I965_EM_CLOCK_GATE_DISABLE (1 << 12)
2535# define I965_UC_CLOCK_GATE_DISABLE (1 << 11)
2536# define I965_SI_CLOCK_GATE_DISABLE (1 << 6)
2537# define I965_MT_CLOCK_GATE_DISABLE (1 << 5)
2538# define I965_PL_CLOCK_GATE_DISABLE (1 << 4)
2539# define I965_DG_CLOCK_GATE_DISABLE (1 << 3)
2540# define I965_QC_CLOCK_GATE_DISABLE (1 << 2)
2541# define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
2542# define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
2543
2544#define RENCLK_GATE_D2 _MMIO(0x6208)
2545#define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
2546#define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
2547#define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
2548
2549#define VDECCLK_GATE_D _MMIO(0x620C) /* g4x only */
2550#define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4)
2551
2552#define RAMCLK_GATE_D _MMIO(0x6210) /* CRL only */
2553#define DEUC _MMIO(0x6214) /* CRL only */
2554
2555#define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500)
2556#define FW_CSPWRDWNEN (1<<15)
2557
2558#define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504)
2559
2560#define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508)
2561#define CDCLK_FREQ_SHIFT 4
2562#define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT)
2563#define CZCLK_FREQ_MASK 0xf
2564
2565#define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C)
2566#define PFI_CREDIT_63 (9 << 28) /* chv only */
2567#define PFI_CREDIT_31 (8 << 28) /* chv only */
2568#define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */
2569#define PFI_CREDIT_RESEND (1 << 27)
2570#define VGA_FAST_MODE_DISABLE (1 << 14)
2571
2572#define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510)
2573
2574/*
2575 * Palette regs
2576 */
2577#define PALETTE_A_OFFSET 0xa000
2578#define PALETTE_B_OFFSET 0xa800
2579#define CHV_PALETTE_C_OFFSET 0xc000
2580#define PALETTE(pipe, i) _MMIO(dev_priv->info.palette_offsets[pipe] + \
2581 dev_priv->info.display_mmio_offset + (i) * 4)
2582
2583/* MCH MMIO space */
2584
2585/*
2586 * MCHBAR mirror.
2587 *
2588 * This mirrors the MCHBAR MMIO space whose location is determined by
2589 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
2590 * every way. It is not accessible from the CP register read instructions.
2591 *
2592 * Starting from Haswell, you can't write registers using the MCHBAR mirror,
2593 * just read.
2594 */
2595#define MCHBAR_MIRROR_BASE 0x10000
2596
2597#define MCHBAR_MIRROR_BASE_SNB 0x140000
2598
2599#define CTG_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x34)
2600#define ELK_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x48)
2601#define G4X_STOLEN_RESERVED_ADDR1_MASK (0xFFFF << 16)
2602#define G4X_STOLEN_RESERVED_ADDR2_MASK (0xFFF << 4)
2603
2604/* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */
2605#define DCLK _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04)
2606
2607/* 915-945 and GM965 MCH register controlling DRAM channel access */
2608#define DCC _MMIO(MCHBAR_MIRROR_BASE + 0x200)
2609#define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
2610#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
2611#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
2612#define DCC_ADDRESSING_MODE_MASK (3 << 0)
2613#define DCC_CHANNEL_XOR_DISABLE (1 << 10)
2614#define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
2615#define DCC2 _MMIO(MCHBAR_MIRROR_BASE + 0x204)
2616#define DCC2_MODIFIED_ENHANCED_DISABLE (1 << 20)
2617
2618/* Pineview MCH register contains DDR3 setting */
2619#define CSHRDDR3CTL _MMIO(MCHBAR_MIRROR_BASE + 0x1a8)
2620#define CSHRDDR3CTL_DDR3 (1 << 2)
2621
2622/* 965 MCH register controlling DRAM channel configuration */
2623#define C0DRB3 _MMIO(MCHBAR_MIRROR_BASE + 0x206)
2624#define C1DRB3 _MMIO(MCHBAR_MIRROR_BASE + 0x606)
2625
2626/* snb MCH registers for reading the DRAM channel configuration */
2627#define MAD_DIMM_C0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004)
2628#define MAD_DIMM_C1 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008)
2629#define MAD_DIMM_C2 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
2630#define MAD_DIMM_ECC_MASK (0x3 << 24)
2631#define MAD_DIMM_ECC_OFF (0x0 << 24)
2632#define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24)
2633#define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24)
2634#define MAD_DIMM_ECC_ON (0x3 << 24)
2635#define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22)
2636#define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21)
2637#define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */
2638#define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */
2639#define MAD_DIMM_B_DUAL_RANK (0x1 << 18)
2640#define MAD_DIMM_A_DUAL_RANK (0x1 << 17)
2641#define MAD_DIMM_A_SELECT (0x1 << 16)
2642/* DIMM sizes are in multiples of 256mb. */
2643#define MAD_DIMM_B_SIZE_SHIFT 8
2644#define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT)
2645#define MAD_DIMM_A_SIZE_SHIFT 0
2646#define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT)
2647
2648/* snb MCH registers for priority tuning */
2649#define MCH_SSKPD _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10)
2650#define MCH_SSKPD_WM0_MASK 0x3f
2651#define MCH_SSKPD_WM0_VAL 0xc
2652
2653#define MCH_SECP_NRG_STTS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x592c)
2654
2655/* Clocking configuration register */
2656#define CLKCFG _MMIO(MCHBAR_MIRROR_BASE + 0xc00)
2657#define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */
2658#define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */
2659#define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */
2660#define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */
2661#define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */
2662#define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */
2663/* Note, below two are guess */
2664#define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */
2665#define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */
2666#define CLKCFG_FSB_MASK (7 << 0)
2667#define CLKCFG_MEM_533 (1 << 4)
2668#define CLKCFG_MEM_667 (2 << 4)
2669#define CLKCFG_MEM_800 (3 << 4)
2670#define CLKCFG_MEM_MASK (7 << 4)
2671
2672#define HPLLVCO _MMIO(MCHBAR_MIRROR_BASE + 0xc38)
2673#define HPLLVCO_MOBILE _MMIO(MCHBAR_MIRROR_BASE + 0xc0f)
2674
2675#define TSC1 _MMIO(0x11001)
2676#define TSE (1<<0)
2677#define TR1 _MMIO(0x11006)
2678#define TSFS _MMIO(0x11020)
2679#define TSFS_SLOPE_MASK 0x0000ff00
2680#define TSFS_SLOPE_SHIFT 8
2681#define TSFS_INTR_MASK 0x000000ff
2682
2683#define CRSTANDVID _MMIO(0x11100)
2684#define PXVFREQ(fstart) _MMIO(0x11110 + (fstart) * 4) /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
2685#define PXVFREQ_PX_MASK 0x7f000000
2686#define PXVFREQ_PX_SHIFT 24
2687#define VIDFREQ_BASE _MMIO(0x11110)
2688#define VIDFREQ1 _MMIO(0x11110) /* VIDFREQ1-4 (0x1111c) (Cantiga) */
2689#define VIDFREQ2 _MMIO(0x11114)
2690#define VIDFREQ3 _MMIO(0x11118)
2691#define VIDFREQ4 _MMIO(0x1111c)
2692#define VIDFREQ_P0_MASK 0x1f000000
2693#define VIDFREQ_P0_SHIFT 24
2694#define VIDFREQ_P0_CSCLK_MASK 0x00f00000
2695#define VIDFREQ_P0_CSCLK_SHIFT 20
2696#define VIDFREQ_P0_CRCLK_MASK 0x000f0000
2697#define VIDFREQ_P0_CRCLK_SHIFT 16
2698#define VIDFREQ_P1_MASK 0x00001f00
2699#define VIDFREQ_P1_SHIFT 8
2700#define VIDFREQ_P1_CSCLK_MASK 0x000000f0
2701#define VIDFREQ_P1_CSCLK_SHIFT 4
2702#define VIDFREQ_P1_CRCLK_MASK 0x0000000f
2703#define INTTOEXT_BASE_ILK _MMIO(0x11300)
2704#define INTTOEXT_BASE _MMIO(0x11120) /* INTTOEXT1-8 (0x1113c) */
2705#define INTTOEXT_MAP3_SHIFT 24
2706#define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT)
2707#define INTTOEXT_MAP2_SHIFT 16
2708#define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT)
2709#define INTTOEXT_MAP1_SHIFT 8
2710#define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT)
2711#define INTTOEXT_MAP0_SHIFT 0
2712#define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT)
2713#define MEMSWCTL _MMIO(0x11170) /* Ironlake only */
2714#define MEMCTL_CMD_MASK 0xe000
2715#define MEMCTL_CMD_SHIFT 13
2716#define MEMCTL_CMD_RCLK_OFF 0
2717#define MEMCTL_CMD_RCLK_ON 1
2718#define MEMCTL_CMD_CHFREQ 2
2719#define MEMCTL_CMD_CHVID 3
2720#define MEMCTL_CMD_VMMOFF 4
2721#define MEMCTL_CMD_VMMON 5
2722#define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears
2723 when command complete */
2724#define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */
2725#define MEMCTL_FREQ_SHIFT 8
2726#define MEMCTL_SFCAVM (1<<7)
2727#define MEMCTL_TGT_VID_MASK 0x007f
2728#define MEMIHYST _MMIO(0x1117c)
2729#define MEMINTREN _MMIO(0x11180) /* 16 bits */
2730#define MEMINT_RSEXIT_EN (1<<8)
2731#define MEMINT_CX_SUPR_EN (1<<7)
2732#define MEMINT_CONT_BUSY_EN (1<<6)
2733#define MEMINT_AVG_BUSY_EN (1<<5)
2734#define MEMINT_EVAL_CHG_EN (1<<4)
2735#define MEMINT_MON_IDLE_EN (1<<3)
2736#define MEMINT_UP_EVAL_EN (1<<2)
2737#define MEMINT_DOWN_EVAL_EN (1<<1)
2738#define MEMINT_SW_CMD_EN (1<<0)
2739#define MEMINTRSTR _MMIO(0x11182) /* 16 bits */
2740#define MEM_RSEXIT_MASK 0xc000
2741#define MEM_RSEXIT_SHIFT 14
2742#define MEM_CONT_BUSY_MASK 0x3000
2743#define MEM_CONT_BUSY_SHIFT 12
2744#define MEM_AVG_BUSY_MASK 0x0c00
2745#define MEM_AVG_BUSY_SHIFT 10
2746#define MEM_EVAL_CHG_MASK 0x0300
2747#define MEM_EVAL_BUSY_SHIFT 8
2748#define MEM_MON_IDLE_MASK 0x00c0
2749#define MEM_MON_IDLE_SHIFT 6
2750#define MEM_UP_EVAL_MASK 0x0030
2751#define MEM_UP_EVAL_SHIFT 4
2752#define MEM_DOWN_EVAL_MASK 0x000c
2753#define MEM_DOWN_EVAL_SHIFT 2
2754#define MEM_SW_CMD_MASK 0x0003
2755#define MEM_INT_STEER_GFX 0
2756#define MEM_INT_STEER_CMR 1
2757#define MEM_INT_STEER_SMI 2
2758#define MEM_INT_STEER_SCI 3
2759#define MEMINTRSTS _MMIO(0x11184)
2760#define MEMINT_RSEXIT (1<<7)
2761#define MEMINT_CONT_BUSY (1<<6)
2762#define MEMINT_AVG_BUSY (1<<5)
2763#define MEMINT_EVAL_CHG (1<<4)
2764#define MEMINT_MON_IDLE (1<<3)
2765#define MEMINT_UP_EVAL (1<<2)
2766#define MEMINT_DOWN_EVAL (1<<1)
2767#define MEMINT_SW_CMD (1<<0)
2768#define MEMMODECTL _MMIO(0x11190)
2769#define MEMMODE_BOOST_EN (1<<31)
2770#define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
2771#define MEMMODE_BOOST_FREQ_SHIFT 24
2772#define MEMMODE_IDLE_MODE_MASK 0x00030000
2773#define MEMMODE_IDLE_MODE_SHIFT 16
2774#define MEMMODE_IDLE_MODE_EVAL 0
2775#define MEMMODE_IDLE_MODE_CONT 1
2776#define MEMMODE_HWIDLE_EN (1<<15)
2777#define MEMMODE_SWMODE_EN (1<<14)
2778#define MEMMODE_RCLK_GATE (1<<13)
2779#define MEMMODE_HW_UPDATE (1<<12)
2780#define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */
2781#define MEMMODE_FSTART_SHIFT 8
2782#define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */
2783#define MEMMODE_FMAX_SHIFT 4
2784#define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */
2785#define RCBMAXAVG _MMIO(0x1119c)
2786#define MEMSWCTL2 _MMIO(0x1119e) /* Cantiga only */
2787#define SWMEMCMD_RENDER_OFF (0 << 13)
2788#define SWMEMCMD_RENDER_ON (1 << 13)
2789#define SWMEMCMD_SWFREQ (2 << 13)
2790#define SWMEMCMD_TARVID (3 << 13)
2791#define SWMEMCMD_VRM_OFF (4 << 13)
2792#define SWMEMCMD_VRM_ON (5 << 13)
2793#define CMDSTS (1<<12)
2794#define SFCAVM (1<<11)
2795#define SWFREQ_MASK 0x0380 /* P0-7 */
2796#define SWFREQ_SHIFT 7
2797#define TARVID_MASK 0x001f
2798#define MEMSTAT_CTG _MMIO(0x111a0)
2799#define RCBMINAVG _MMIO(0x111a0)
2800#define RCUPEI _MMIO(0x111b0)
2801#define RCDNEI _MMIO(0x111b4)
2802#define RSTDBYCTL _MMIO(0x111b8)
2803#define RS1EN (1<<31)
2804#define RS2EN (1<<30)
2805#define RS3EN (1<<29)
2806#define D3RS3EN (1<<28) /* Display D3 imlies RS3 */
2807#define SWPROMORSX (1<<27) /* RSx promotion timers ignored */
2808#define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */
2809#define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */
2810#define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */
2811#define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */
2812#define RSX_STATUS_MASK (7<<20)
2813#define RSX_STATUS_ON (0<<20)
2814#define RSX_STATUS_RC1 (1<<20)
2815#define RSX_STATUS_RC1E (2<<20)
2816#define RSX_STATUS_RS1 (3<<20)
2817#define RSX_STATUS_RS2 (4<<20) /* aka rc6 */
2818#define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */
2819#define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */
2820#define RSX_STATUS_RSVD2 (7<<20)
2821#define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */
2822#define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */
2823#define JRSC (1<<17) /* rsx coupled to cpu c-state */
2824#define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */
2825#define RS1CONTSAV_MASK (3<<14)
2826#define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */
2827#define RS1CONTSAV_RSVD (1<<14)
2828#define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */
2829#define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */
2830#define NORMSLEXLAT_MASK (3<<12)
2831#define SLOW_RS123 (0<<12)
2832#define SLOW_RS23 (1<<12)
2833#define SLOW_RS3 (2<<12)
2834#define NORMAL_RS123 (3<<12)
2835#define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */
2836#define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
2837#define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */
2838#define STATELOCK (1<<7) /* locked to rs_cstate if 0 */
2839#define RS_CSTATE_MASK (3<<4)
2840#define RS_CSTATE_C367_RS1 (0<<4)
2841#define RS_CSTATE_C36_RS1_C7_RS2 (1<<4)
2842#define RS_CSTATE_RSVD (2<<4)
2843#define RS_CSTATE_C367_RS2 (3<<4)
2844#define REDSAVES (1<<3) /* no context save if was idle during rs0 */
2845#define REDRESTORES (1<<2) /* no restore if was idle during rs0 */
2846#define VIDCTL _MMIO(0x111c0)
2847#define VIDSTS _MMIO(0x111c8)
2848#define VIDSTART _MMIO(0x111cc) /* 8 bits */
2849#define MEMSTAT_ILK _MMIO(0x111f8)
2850#define MEMSTAT_VID_MASK 0x7f00
2851#define MEMSTAT_VID_SHIFT 8
2852#define MEMSTAT_PSTATE_MASK 0x00f8
2853#define MEMSTAT_PSTATE_SHIFT 3
2854#define MEMSTAT_MON_ACTV (1<<2)
2855#define MEMSTAT_SRC_CTL_MASK 0x0003
2856#define MEMSTAT_SRC_CTL_CORE 0
2857#define MEMSTAT_SRC_CTL_TRB 1
2858#define MEMSTAT_SRC_CTL_THM 2
2859#define MEMSTAT_SRC_CTL_STDBY 3
2860#define RCPREVBSYTUPAVG _MMIO(0x113b8)
2861#define RCPREVBSYTDNAVG _MMIO(0x113bc)
2862#define PMMISC _MMIO(0x11214)
2863#define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */
2864#define SDEW _MMIO(0x1124c)
2865#define CSIEW0 _MMIO(0x11250)
2866#define CSIEW1 _MMIO(0x11254)
2867#define CSIEW2 _MMIO(0x11258)
2868#define PEW(i) _MMIO(0x1125c + (i) * 4) /* 5 registers */
2869#define DEW(i) _MMIO(0x11270 + (i) * 4) /* 3 registers */
2870#define MCHAFE _MMIO(0x112c0)
2871#define CSIEC _MMIO(0x112e0)
2872#define DMIEC _MMIO(0x112e4)
2873#define DDREC _MMIO(0x112e8)
2874#define PEG0EC _MMIO(0x112ec)
2875#define PEG1EC _MMIO(0x112f0)
2876#define GFXEC _MMIO(0x112f4)
2877#define RPPREVBSYTUPAVG _MMIO(0x113b8)
2878#define RPPREVBSYTDNAVG _MMIO(0x113bc)
2879#define ECR _MMIO(0x11600)
2880#define ECR_GPFE (1<<31)
2881#define ECR_IMONE (1<<30)
2882#define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */
2883#define OGW0 _MMIO(0x11608)
2884#define OGW1 _MMIO(0x1160c)
2885#define EG0 _MMIO(0x11610)
2886#define EG1 _MMIO(0x11614)
2887#define EG2 _MMIO(0x11618)
2888#define EG3 _MMIO(0x1161c)
2889#define EG4 _MMIO(0x11620)
2890#define EG5 _MMIO(0x11624)
2891#define EG6 _MMIO(0x11628)
2892#define EG7 _MMIO(0x1162c)
2893#define PXW(i) _MMIO(0x11664 + (i) * 4) /* 4 registers */
2894#define PXWL(i) _MMIO(0x11680 + (i) * 8) /* 8 registers */
2895#define LCFUSE02 _MMIO(0x116c0)
2896#define LCFUSE_HIV_MASK 0x000000ff
2897#define CSIPLL0 _MMIO(0x12c10)
2898#define DDRMPLL1 _MMIO(0X12c20)
2899#define PEG_BAND_GAP_DATA _MMIO(0x14d68)
2900
2901#define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c)
2902#define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
2903
2904#define GEN6_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5948)
2905#define BXT_GT_PERF_STATUS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7070)
2906#define GEN6_RP_STATE_LIMITS _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5994)
2907#define GEN6_RP_STATE_CAP _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5998)
2908#define BXT_RP_STATE_CAP _MMIO(0x138170)
2909
2910/*
2911 * Make these a multiple of magic 25 to avoid SNB (eg. Dell XPS
2912 * 8300) freezing up around GPU hangs. Looks as if even
2913 * scheduling/timer interrupts start misbehaving if the RPS
2914 * EI/thresholds are "bad", leading to a very sluggish or even
2915 * frozen machine.
2916 */
2917#define INTERVAL_1_28_US(us) roundup(((us) * 100) >> 7, 25)
2918#define INTERVAL_1_33_US(us) (((us) * 3) >> 2)
2919#define INTERVAL_0_833_US(us) (((us) * 6) / 5)
2920#define GT_INTERVAL_FROM_US(dev_priv, us) (IS_GEN9(dev_priv) ? \
2921 (IS_BROXTON(dev_priv) ? \
2922 INTERVAL_0_833_US(us) : \
2923 INTERVAL_1_33_US(us)) : \
2924 INTERVAL_1_28_US(us))
2925
2926/*
2927 * Logical Context regs
2928 */
2929#define CCID _MMIO(0x2180)
2930#define CCID_EN (1<<0)
2931/*
2932 * Notes on SNB/IVB/VLV context size:
2933 * - Power context is saved elsewhere (LLC or stolen)
2934 * - Ring/execlist context is saved on SNB, not on IVB
2935 * - Extended context size already includes render context size
2936 * - We always need to follow the extended context size.
2937 * SNB BSpec has comments indicating that we should use the
2938 * render context size instead if execlists are disabled, but
2939 * based on empirical testing that's just nonsense.
2940 * - Pipelined/VF state is saved on SNB/IVB respectively
2941 * - GT1 size just indicates how much of render context
2942 * doesn't need saving on GT1
2943 */
2944#define CXT_SIZE _MMIO(0x21a0)
2945#define GEN6_CXT_POWER_SIZE(cxt_reg) (((cxt_reg) >> 24) & 0x3f)
2946#define GEN6_CXT_RING_SIZE(cxt_reg) (((cxt_reg) >> 18) & 0x3f)
2947#define GEN6_CXT_RENDER_SIZE(cxt_reg) (((cxt_reg) >> 12) & 0x3f)
2948#define GEN6_CXT_EXTENDED_SIZE(cxt_reg) (((cxt_reg) >> 6) & 0x3f)
2949#define GEN6_CXT_PIPELINE_SIZE(cxt_reg) (((cxt_reg) >> 0) & 0x3f)
2950#define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \
2951 GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
2952 GEN6_CXT_PIPELINE_SIZE(cxt_reg))
2953#define GEN7_CXT_SIZE _MMIO(0x21a8)
2954#define GEN7_CXT_POWER_SIZE(ctx_reg) (((ctx_reg) >> 25) & 0x7f)
2955#define GEN7_CXT_RING_SIZE(ctx_reg) (((ctx_reg) >> 22) & 0x7)
2956#define GEN7_CXT_RENDER_SIZE(ctx_reg) (((ctx_reg) >> 16) & 0x3f)
2957#define GEN7_CXT_EXTENDED_SIZE(ctx_reg) (((ctx_reg) >> 9) & 0x7f)
2958#define GEN7_CXT_GT1_SIZE(ctx_reg) (((ctx_reg) >> 6) & 0x7)
2959#define GEN7_CXT_VFSTATE_SIZE(ctx_reg) (((ctx_reg) >> 0) & 0x3f)
2960#define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
2961 GEN7_CXT_VFSTATE_SIZE(ctx_reg))
2962/* Haswell does have the CXT_SIZE register however it does not appear to be
2963 * valid. Now, docs explain in dwords what is in the context object. The full
2964 * size is 70720 bytes, however, the power context and execlist context will
2965 * never be saved (power context is stored elsewhere, and execlists don't work
2966 * on HSW) - so the final size, including the extra state required for the
2967 * Resource Streamer, is 66944 bytes, which rounds to 17 pages.
2968 */
2969#define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE)
2970/* Same as Haswell, but 72064 bytes now. */
2971#define GEN8_CXT_TOTAL_SIZE (18 * PAGE_SIZE)
2972
2973#define CHV_CLK_CTL1 _MMIO(0x101100)
2974#define VLV_CLK_CTL2 _MMIO(0x101104)
2975#define CLK_CTL2_CZCOUNT_30NS_SHIFT 28
2976
2977/*
2978 * Overlay regs
2979 */
2980
2981#define OVADD _MMIO(0x30000)
2982#define DOVSTA _MMIO(0x30008)
2983#define OC_BUF (0x3<<20)
2984#define OGAMC5 _MMIO(0x30010)
2985#define OGAMC4 _MMIO(0x30014)
2986#define OGAMC3 _MMIO(0x30018)
2987#define OGAMC2 _MMIO(0x3001c)
2988#define OGAMC1 _MMIO(0x30020)
2989#define OGAMC0 _MMIO(0x30024)
2990
2991/*
2992 * GEN9 clock gating regs
2993 */
2994#define GEN9_CLKGATE_DIS_0 _MMIO(0x46530)
2995#define PWM2_GATING_DIS (1 << 14)
2996#define PWM1_GATING_DIS (1 << 13)
2997
2998/*
2999 * Display engine regs
3000 */
3001
3002/* Pipe A CRC regs */
3003#define _PIPE_CRC_CTL_A 0x60050
3004#define PIPE_CRC_ENABLE (1 << 31)
3005/* ivb+ source selection */
3006#define PIPE_CRC_SOURCE_PRIMARY_IVB (0 << 29)
3007#define PIPE_CRC_SOURCE_SPRITE_IVB (1 << 29)
3008#define PIPE_CRC_SOURCE_PF_IVB (2 << 29)
3009/* ilk+ source selection */
3010#define PIPE_CRC_SOURCE_PRIMARY_ILK (0 << 28)
3011#define PIPE_CRC_SOURCE_SPRITE_ILK (1 << 28)
3012#define PIPE_CRC_SOURCE_PIPE_ILK (2 << 28)
3013/* embedded DP port on the north display block, reserved on ivb */
3014#define PIPE_CRC_SOURCE_PORT_A_ILK (4 << 28)
3015#define PIPE_CRC_SOURCE_FDI_ILK (5 << 28) /* reserved on ivb */
3016/* vlv source selection */
3017#define PIPE_CRC_SOURCE_PIPE_VLV (0 << 27)
3018#define PIPE_CRC_SOURCE_HDMIB_VLV (1 << 27)
3019#define PIPE_CRC_SOURCE_HDMIC_VLV (2 << 27)
3020/* with DP port the pipe source is invalid */
3021#define PIPE_CRC_SOURCE_DP_D_VLV (3 << 27)
3022#define PIPE_CRC_SOURCE_DP_B_VLV (6 << 27)
3023#define PIPE_CRC_SOURCE_DP_C_VLV (7 << 27)
3024/* gen3+ source selection */
3025#define PIPE_CRC_SOURCE_PIPE_I9XX (0 << 28)
3026#define PIPE_CRC_SOURCE_SDVOB_I9XX (1 << 28)
3027#define PIPE_CRC_SOURCE_SDVOC_I9XX (2 << 28)
3028/* with DP/TV port the pipe source is invalid */
3029#define PIPE_CRC_SOURCE_DP_D_G4X (3 << 28)
3030#define PIPE_CRC_SOURCE_TV_PRE (4 << 28)
3031#define PIPE_CRC_SOURCE_TV_POST (5 << 28)
3032#define PIPE_CRC_SOURCE_DP_B_G4X (6 << 28)
3033#define PIPE_CRC_SOURCE_DP_C_G4X (7 << 28)
3034/* gen2 doesn't have source selection bits */
3035#define PIPE_CRC_INCLUDE_BORDER_I8XX (1 << 30)
3036
3037#define _PIPE_CRC_RES_1_A_IVB 0x60064
3038#define _PIPE_CRC_RES_2_A_IVB 0x60068
3039#define _PIPE_CRC_RES_3_A_IVB 0x6006c
3040#define _PIPE_CRC_RES_4_A_IVB 0x60070
3041#define _PIPE_CRC_RES_5_A_IVB 0x60074
3042
3043#define _PIPE_CRC_RES_RED_A 0x60060
3044#define _PIPE_CRC_RES_GREEN_A 0x60064
3045#define _PIPE_CRC_RES_BLUE_A 0x60068
3046#define _PIPE_CRC_RES_RES1_A_I915 0x6006c
3047#define _PIPE_CRC_RES_RES2_A_G4X 0x60080
3048
3049/* Pipe B CRC regs */
3050#define _PIPE_CRC_RES_1_B_IVB 0x61064
3051#define _PIPE_CRC_RES_2_B_IVB 0x61068
3052#define _PIPE_CRC_RES_3_B_IVB 0x6106c
3053#define _PIPE_CRC_RES_4_B_IVB 0x61070
3054#define _PIPE_CRC_RES_5_B_IVB 0x61074
3055
3056#define PIPE_CRC_CTL(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_CTL_A)
3057#define PIPE_CRC_RES_1_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_1_A_IVB)
3058#define PIPE_CRC_RES_2_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_2_A_IVB)
3059#define PIPE_CRC_RES_3_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_3_A_IVB)
3060#define PIPE_CRC_RES_4_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_4_A_IVB)
3061#define PIPE_CRC_RES_5_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_5_A_IVB)
3062
3063#define PIPE_CRC_RES_RED(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RED_A)
3064#define PIPE_CRC_RES_GREEN(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_GREEN_A)
3065#define PIPE_CRC_RES_BLUE(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_BLUE_A)
3066#define PIPE_CRC_RES_RES1_I915(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES1_A_I915)
3067#define PIPE_CRC_RES_RES2_G4X(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES2_A_G4X)
3068
3069/* Pipe A timing regs */
3070#define _HTOTAL_A 0x60000
3071#define _HBLANK_A 0x60004
3072#define _HSYNC_A 0x60008
3073#define _VTOTAL_A 0x6000c
3074#define _VBLANK_A 0x60010
3075#define _VSYNC_A 0x60014
3076#define _PIPEASRC 0x6001c
3077#define _BCLRPAT_A 0x60020
3078#define _VSYNCSHIFT_A 0x60028
3079#define _PIPE_MULT_A 0x6002c
3080
3081/* Pipe B timing regs */
3082#define _HTOTAL_B 0x61000
3083#define _HBLANK_B 0x61004
3084#define _HSYNC_B 0x61008
3085#define _VTOTAL_B 0x6100c
3086#define _VBLANK_B 0x61010
3087#define _VSYNC_B 0x61014
3088#define _PIPEBSRC 0x6101c
3089#define _BCLRPAT_B 0x61020
3090#define _VSYNCSHIFT_B 0x61028
3091#define _PIPE_MULT_B 0x6102c
3092
3093#define TRANSCODER_A_OFFSET 0x60000
3094#define TRANSCODER_B_OFFSET 0x61000
3095#define TRANSCODER_C_OFFSET 0x62000
3096#define CHV_TRANSCODER_C_OFFSET 0x63000
3097#define TRANSCODER_EDP_OFFSET 0x6f000
3098
3099#define _MMIO_TRANS2(pipe, reg) _MMIO(dev_priv->info.trans_offsets[(pipe)] - \
3100 dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \
3101 dev_priv->info.display_mmio_offset)
3102
3103#define HTOTAL(trans) _MMIO_TRANS2(trans, _HTOTAL_A)
3104#define HBLANK(trans) _MMIO_TRANS2(trans, _HBLANK_A)
3105#define HSYNC(trans) _MMIO_TRANS2(trans, _HSYNC_A)
3106#define VTOTAL(trans) _MMIO_TRANS2(trans, _VTOTAL_A)
3107#define VBLANK(trans) _MMIO_TRANS2(trans, _VBLANK_A)
3108#define VSYNC(trans) _MMIO_TRANS2(trans, _VSYNC_A)
3109#define BCLRPAT(trans) _MMIO_TRANS2(trans, _BCLRPAT_A)
3110#define VSYNCSHIFT(trans) _MMIO_TRANS2(trans, _VSYNCSHIFT_A)
3111#define PIPESRC(trans) _MMIO_TRANS2(trans, _PIPEASRC)
3112#define PIPE_MULT(trans) _MMIO_TRANS2(trans, _PIPE_MULT_A)
3113
3114/* VLV eDP PSR registers */
3115#define _PSRCTLA (VLV_DISPLAY_BASE + 0x60090)
3116#define _PSRCTLB (VLV_DISPLAY_BASE + 0x61090)
3117#define VLV_EDP_PSR_ENABLE (1<<0)
3118#define VLV_EDP_PSR_RESET (1<<1)
3119#define VLV_EDP_PSR_MODE_MASK (7<<2)
3120#define VLV_EDP_PSR_MODE_HW_TIMER (1<<3)
3121#define VLV_EDP_PSR_MODE_SW_TIMER (1<<2)
3122#define VLV_EDP_PSR_SINGLE_FRAME_UPDATE (1<<7)
3123#define VLV_EDP_PSR_ACTIVE_ENTRY (1<<8)
3124#define VLV_EDP_PSR_SRC_TRANSMITTER_STATE (1<<9)
3125#define VLV_EDP_PSR_DBL_FRAME (1<<10)
3126#define VLV_EDP_PSR_FRAME_COUNT_MASK (0xff<<16)
3127#define VLV_EDP_PSR_IDLE_FRAME_SHIFT 16
3128#define VLV_PSRCTL(pipe) _MMIO_PIPE(pipe, _PSRCTLA, _PSRCTLB)
3129
3130#define _VSCSDPA (VLV_DISPLAY_BASE + 0x600a0)
3131#define _VSCSDPB (VLV_DISPLAY_BASE + 0x610a0)
3132#define VLV_EDP_PSR_SDP_FREQ_MASK (3<<30)
3133#define VLV_EDP_PSR_SDP_FREQ_ONCE (1<<31)
3134#define VLV_EDP_PSR_SDP_FREQ_EVFRAME (1<<30)
3135#define VLV_VSCSDP(pipe) _MMIO_PIPE(pipe, _VSCSDPA, _VSCSDPB)
3136
3137#define _PSRSTATA (VLV_DISPLAY_BASE + 0x60094)
3138#define _PSRSTATB (VLV_DISPLAY_BASE + 0x61094)
3139#define VLV_EDP_PSR_LAST_STATE_MASK (7<<3)
3140#define VLV_EDP_PSR_CURR_STATE_MASK 7
3141#define VLV_EDP_PSR_DISABLED (0<<0)
3142#define VLV_EDP_PSR_INACTIVE (1<<0)
3143#define VLV_EDP_PSR_IN_TRANS_TO_ACTIVE (2<<0)
3144#define VLV_EDP_PSR_ACTIVE_NORFB_UP (3<<0)
3145#define VLV_EDP_PSR_ACTIVE_SF_UPDATE (4<<0)
3146#define VLV_EDP_PSR_EXIT (5<<0)
3147#define VLV_EDP_PSR_IN_TRANS (1<<7)
3148#define VLV_PSRSTAT(pipe) _MMIO_PIPE(pipe, _PSRSTATA, _PSRSTATB)
3149
3150/* HSW+ eDP PSR registers */
3151#define HSW_EDP_PSR_BASE 0x64800
3152#define BDW_EDP_PSR_BASE 0x6f800
3153#define EDP_PSR_CTL _MMIO(dev_priv->psr_mmio_base + 0)
3154#define EDP_PSR_ENABLE (1<<31)
3155#define BDW_PSR_SINGLE_FRAME (1<<30)
3156#define EDP_PSR_LINK_STANDBY (1<<27)
3157#define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25)
3158#define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0<<25)
3159#define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1<<25)
3160#define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2<<25)
3161#define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3<<25)
3162#define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20
3163#define EDP_PSR_SKIP_AUX_EXIT (1<<12)
3164#define EDP_PSR_TP1_TP2_SEL (0<<11)
3165#define EDP_PSR_TP1_TP3_SEL (1<<11)
3166#define EDP_PSR_TP2_TP3_TIME_500us (0<<8)
3167#define EDP_PSR_TP2_TP3_TIME_100us (1<<8)
3168#define EDP_PSR_TP2_TP3_TIME_2500us (2<<8)
3169#define EDP_PSR_TP2_TP3_TIME_0us (3<<8)
3170#define EDP_PSR_TP1_TIME_500us (0<<4)
3171#define EDP_PSR_TP1_TIME_100us (1<<4)
3172#define EDP_PSR_TP1_TIME_2500us (2<<4)
3173#define EDP_PSR_TP1_TIME_0us (3<<4)
3174#define EDP_PSR_IDLE_FRAME_SHIFT 0
3175
3176#define EDP_PSR_AUX_CTL _MMIO(dev_priv->psr_mmio_base + 0x10)
3177#define EDP_PSR_AUX_DATA(i) _MMIO(dev_priv->psr_mmio_base + 0x14 + (i) * 4) /* 5 registers */
3178
3179#define EDP_PSR_STATUS_CTL _MMIO(dev_priv->psr_mmio_base + 0x40)
3180#define EDP_PSR_STATUS_STATE_MASK (7<<29)
3181#define EDP_PSR_STATUS_STATE_IDLE (0<<29)
3182#define EDP_PSR_STATUS_STATE_SRDONACK (1<<29)
3183#define EDP_PSR_STATUS_STATE_SRDENT (2<<29)
3184#define EDP_PSR_STATUS_STATE_BUFOFF (3<<29)
3185#define EDP_PSR_STATUS_STATE_BUFON (4<<29)
3186#define EDP_PSR_STATUS_STATE_AUXACK (5<<29)
3187#define EDP_PSR_STATUS_STATE_SRDOFFACK (6<<29)
3188#define EDP_PSR_STATUS_LINK_MASK (3<<26)
3189#define EDP_PSR_STATUS_LINK_FULL_OFF (0<<26)
3190#define EDP_PSR_STATUS_LINK_FULL_ON (1<<26)
3191#define EDP_PSR_STATUS_LINK_STANDBY (2<<26)
3192#define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20
3193#define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f
3194#define EDP_PSR_STATUS_COUNT_SHIFT 16
3195#define EDP_PSR_STATUS_COUNT_MASK 0xf
3196#define EDP_PSR_STATUS_AUX_ERROR (1<<15)
3197#define EDP_PSR_STATUS_AUX_SENDING (1<<12)
3198#define EDP_PSR_STATUS_SENDING_IDLE (1<<9)
3199#define EDP_PSR_STATUS_SENDING_TP2_TP3 (1<<8)
3200#define EDP_PSR_STATUS_SENDING_TP1 (1<<4)
3201#define EDP_PSR_STATUS_IDLE_MASK 0xf
3202
3203#define EDP_PSR_PERF_CNT _MMIO(dev_priv->psr_mmio_base + 0x44)
3204#define EDP_PSR_PERF_CNT_MASK 0xffffff
3205
3206#define EDP_PSR_DEBUG_CTL _MMIO(dev_priv->psr_mmio_base + 0x60)
3207#define EDP_PSR_DEBUG_MASK_LPSP (1<<27)
3208#define EDP_PSR_DEBUG_MASK_MEMUP (1<<26)
3209#define EDP_PSR_DEBUG_MASK_HPD (1<<25)
3210
3211#define EDP_PSR2_CTL _MMIO(0x6f900)
3212#define EDP_PSR2_ENABLE (1<<31)
3213#define EDP_SU_TRACK_ENABLE (1<<30)
3214#define EDP_MAX_SU_DISABLE_TIME(t) ((t)<<20)
3215#define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f<<20)
3216#define EDP_PSR2_TP2_TIME_500 (0<<8)
3217#define EDP_PSR2_TP2_TIME_100 (1<<8)
3218#define EDP_PSR2_TP2_TIME_2500 (2<<8)
3219#define EDP_PSR2_TP2_TIME_50 (3<<8)
3220#define EDP_PSR2_TP2_TIME_MASK (3<<8)
3221#define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
3222#define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf<<4)
3223#define EDP_PSR2_IDLE_MASK 0xf
3224
3225/* VGA port control */
3226#define ADPA _MMIO(0x61100)
3227#define PCH_ADPA _MMIO(0xe1100)
3228#define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100)
3229
3230#define ADPA_DAC_ENABLE (1<<31)
3231#define ADPA_DAC_DISABLE 0
3232#define ADPA_PIPE_SELECT_MASK (1<<30)
3233#define ADPA_PIPE_A_SELECT 0
3234#define ADPA_PIPE_B_SELECT (1<<30)
3235#define ADPA_PIPE_SELECT(pipe) ((pipe) << 30)
3236/* CPT uses bits 29:30 for pch transcoder select */
3237#define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
3238#define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24)
3239#define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24)
3240#define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)
3241#define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24)
3242#define ADPA_CRT_HOTPLUG_ENABLE (1<<23)
3243#define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22)
3244#define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22)
3245#define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21)
3246#define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21)
3247#define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20)
3248#define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20)
3249#define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18)
3250#define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18)
3251#define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18)
3252#define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18)
3253#define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17)
3254#define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17)
3255#define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
3256#define ADPA_USE_VGA_HVPOLARITY (1<<15)
3257#define ADPA_SETS_HVPOLARITY 0
3258#define ADPA_VSYNC_CNTL_DISABLE (1<<10)
3259#define ADPA_VSYNC_CNTL_ENABLE 0
3260#define ADPA_HSYNC_CNTL_DISABLE (1<<11)
3261#define ADPA_HSYNC_CNTL_ENABLE 0
3262#define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
3263#define ADPA_VSYNC_ACTIVE_LOW 0
3264#define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
3265#define ADPA_HSYNC_ACTIVE_LOW 0
3266#define ADPA_DPMS_MASK (~(3<<10))
3267#define ADPA_DPMS_ON (0<<10)
3268#define ADPA_DPMS_SUSPEND (1<<10)
3269#define ADPA_DPMS_STANDBY (2<<10)
3270#define ADPA_DPMS_OFF (3<<10)
3271
3272
3273/* Hotplug control (945+ only) */
3274#define PORT_HOTPLUG_EN _MMIO(dev_priv->info.display_mmio_offset + 0x61110)
3275#define PORTB_HOTPLUG_INT_EN (1 << 29)
3276#define PORTC_HOTPLUG_INT_EN (1 << 28)
3277#define PORTD_HOTPLUG_INT_EN (1 << 27)
3278#define SDVOB_HOTPLUG_INT_EN (1 << 26)
3279#define SDVOC_HOTPLUG_INT_EN (1 << 25)
3280#define TV_HOTPLUG_INT_EN (1 << 18)
3281#define CRT_HOTPLUG_INT_EN (1 << 9)
3282#define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \
3283 PORTC_HOTPLUG_INT_EN | \
3284 PORTD_HOTPLUG_INT_EN | \
3285 SDVOC_HOTPLUG_INT_EN | \
3286 SDVOB_HOTPLUG_INT_EN | \
3287 CRT_HOTPLUG_INT_EN)
3288#define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
3289#define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
3290/* must use period 64 on GM45 according to docs */
3291#define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
3292#define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
3293#define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
3294#define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
3295#define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
3296#define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
3297#define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
3298#define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
3299#define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
3300#define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
3301#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
3302#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
3303
3304#define PORT_HOTPLUG_STAT _MMIO(dev_priv->info.display_mmio_offset + 0x61114)
3305/*
3306 * HDMI/DP bits are g4x+
3307 *
3308 * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused.
3309 * Please check the detailed lore in the commit message for for experimental
3310 * evidence.
3311 */
3312/* Bspec says GM45 should match G4X/VLV/CHV, but reality disagrees */
3313#define PORTD_HOTPLUG_LIVE_STATUS_GM45 (1 << 29)
3314#define PORTC_HOTPLUG_LIVE_STATUS_GM45 (1 << 28)
3315#define PORTB_HOTPLUG_LIVE_STATUS_GM45 (1 << 27)
3316/* G4X/VLV/CHV DP/HDMI bits again match Bspec */
3317#define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 27)
3318#define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28)
3319#define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 29)
3320#define PORTD_HOTPLUG_INT_STATUS (3 << 21)
3321#define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21)
3322#define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21)
3323#define PORTC_HOTPLUG_INT_STATUS (3 << 19)
3324#define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19)
3325#define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19)
3326#define PORTB_HOTPLUG_INT_STATUS (3 << 17)
3327#define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17)
3328#define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17)
3329/* CRT/TV common between gen3+ */
3330#define CRT_HOTPLUG_INT_STATUS (1 << 11)
3331#define TV_HOTPLUG_INT_STATUS (1 << 10)
3332#define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
3333#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
3334#define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
3335#define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
3336#define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6)
3337#define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5)
3338#define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4)
3339#define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4)
3340
3341/* SDVO is different across gen3/4 */
3342#define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3)
3343#define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2)
3344/*
3345 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm,
3346 * since reality corrobates that they're the same as on gen3. But keep these
3347 * bits here (and the comment!) to help any other lost wanderers back onto the
3348 * right tracks.
3349 */
3350#define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4)
3351#define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2)
3352#define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7)
3353#define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6)
3354#define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \
3355 SDVOB_HOTPLUG_INT_STATUS_G4X | \
3356 SDVOC_HOTPLUG_INT_STATUS_G4X | \
3357 PORTB_HOTPLUG_INT_STATUS | \
3358 PORTC_HOTPLUG_INT_STATUS | \
3359 PORTD_HOTPLUG_INT_STATUS)
3360
3361#define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \
3362 SDVOB_HOTPLUG_INT_STATUS_I915 | \
3363 SDVOC_HOTPLUG_INT_STATUS_I915 | \
3364 PORTB_HOTPLUG_INT_STATUS | \
3365 PORTC_HOTPLUG_INT_STATUS | \
3366 PORTD_HOTPLUG_INT_STATUS)
3367
3368/* SDVO and HDMI port control.
3369 * The same register may be used for SDVO or HDMI */
3370#define _GEN3_SDVOB 0x61140
3371#define _GEN3_SDVOC 0x61160
3372#define GEN3_SDVOB _MMIO(_GEN3_SDVOB)
3373#define GEN3_SDVOC _MMIO(_GEN3_SDVOC)
3374#define GEN4_HDMIB GEN3_SDVOB
3375#define GEN4_HDMIC GEN3_SDVOC
3376#define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140)
3377#define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160)
3378#define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C)
3379#define PCH_SDVOB _MMIO(0xe1140)
3380#define PCH_HDMIB PCH_SDVOB
3381#define PCH_HDMIC _MMIO(0xe1150)
3382#define PCH_HDMID _MMIO(0xe1160)
3383
3384#define PORT_DFT_I9XX _MMIO(0x61150)
3385#define DC_BALANCE_RESET (1 << 25)
3386#define PORT_DFT2_G4X _MMIO(dev_priv->info.display_mmio_offset + 0x61154)
3387#define DC_BALANCE_RESET_VLV (1 << 31)
3388#define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0))
3389#define PIPE_C_SCRAMBLE_RESET (1 << 14) /* chv */
3390#define PIPE_B_SCRAMBLE_RESET (1 << 1)
3391#define PIPE_A_SCRAMBLE_RESET (1 << 0)
3392
3393/* Gen 3 SDVO bits: */
3394#define SDVO_ENABLE (1 << 31)
3395#define SDVO_PIPE_SEL(pipe) ((pipe) << 30)
3396#define SDVO_PIPE_SEL_MASK (1 << 30)
3397#define SDVO_PIPE_B_SELECT (1 << 30)
3398#define SDVO_STALL_SELECT (1 << 29)
3399#define SDVO_INTERRUPT_ENABLE (1 << 26)
3400/*
3401 * 915G/GM SDVO pixel multiplier.
3402 * Programmed value is multiplier - 1, up to 5x.
3403 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
3404 */
3405#define SDVO_PORT_MULTIPLY_MASK (7 << 23)
3406#define SDVO_PORT_MULTIPLY_SHIFT 23
3407#define SDVO_PHASE_SELECT_MASK (15 << 19)
3408#define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
3409#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
3410#define SDVOC_GANG_MODE (1 << 16) /* Port C only */
3411#define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */
3412#define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */
3413#define SDVO_DETECTED (1 << 2)
3414/* Bits to be preserved when writing */
3415#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \
3416 SDVO_INTERRUPT_ENABLE)
3417#define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE)
3418
3419/* Gen 4 SDVO/HDMI bits: */
3420#define SDVO_COLOR_FORMAT_8bpc (0 << 26)
3421#define SDVO_COLOR_FORMAT_MASK (7 << 26)
3422#define SDVO_ENCODING_SDVO (0 << 10)
3423#define SDVO_ENCODING_HDMI (2 << 10)
3424#define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */
3425#define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */
3426#define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */
3427#define SDVO_AUDIO_ENABLE (1 << 6)
3428/* VSYNC/HSYNC bits new with 965, default is to be set */
3429#define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
3430#define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
3431
3432/* Gen 5 (IBX) SDVO/HDMI bits: */
3433#define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */
3434#define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */
3435
3436/* Gen 6 (CPT) SDVO/HDMI bits: */
3437#define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29)
3438#define SDVO_PIPE_SEL_MASK_CPT (3 << 29)
3439
3440/* CHV SDVO/HDMI bits: */
3441#define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24)
3442#define SDVO_PIPE_SEL_MASK_CHV (3 << 24)
3443
3444
3445/* DVO port control */
3446#define _DVOA 0x61120
3447#define DVOA _MMIO(_DVOA)
3448#define _DVOB 0x61140
3449#define DVOB _MMIO(_DVOB)
3450#define _DVOC 0x61160
3451#define DVOC _MMIO(_DVOC)
3452#define DVO_ENABLE (1 << 31)
3453#define DVO_PIPE_B_SELECT (1 << 30)
3454#define DVO_PIPE_STALL_UNUSED (0 << 28)
3455#define DVO_PIPE_STALL (1 << 28)
3456#define DVO_PIPE_STALL_TV (2 << 28)
3457#define DVO_PIPE_STALL_MASK (3 << 28)
3458#define DVO_USE_VGA_SYNC (1 << 15)
3459#define DVO_DATA_ORDER_I740 (0 << 14)
3460#define DVO_DATA_ORDER_FP (1 << 14)
3461#define DVO_VSYNC_DISABLE (1 << 11)
3462#define DVO_HSYNC_DISABLE (1 << 10)
3463#define DVO_VSYNC_TRISTATE (1 << 9)
3464#define DVO_HSYNC_TRISTATE (1 << 8)
3465#define DVO_BORDER_ENABLE (1 << 7)
3466#define DVO_DATA_ORDER_GBRG (1 << 6)
3467#define DVO_DATA_ORDER_RGGB (0 << 6)
3468#define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
3469#define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
3470#define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
3471#define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
3472#define DVO_BLANK_ACTIVE_HIGH (1 << 2)
3473#define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
3474#define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
3475#define DVO_PRESERVE_MASK (0x7<<24)
3476#define DVOA_SRCDIM _MMIO(0x61124)
3477#define DVOB_SRCDIM _MMIO(0x61144)
3478#define DVOC_SRCDIM _MMIO(0x61164)
3479#define DVO_SRCDIM_HORIZONTAL_SHIFT 12
3480#define DVO_SRCDIM_VERTICAL_SHIFT 0
3481
3482/* LVDS port control */
3483#define LVDS _MMIO(0x61180)
3484/*
3485 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
3486 * the DPLL semantics change when the LVDS is assigned to that pipe.
3487 */
3488#define LVDS_PORT_EN (1 << 31)
3489/* Selects pipe B for LVDS data. Must be set on pre-965. */
3490#define LVDS_PIPEB_SELECT (1 << 30)
3491#define LVDS_PIPE_MASK (1 << 30)
3492#define LVDS_PIPE(pipe) ((pipe) << 30)
3493/* LVDS dithering flag on 965/g4x platform */
3494#define LVDS_ENABLE_DITHER (1 << 25)
3495/* LVDS sync polarity flags. Set to invert (i.e. negative) */
3496#define LVDS_VSYNC_POLARITY (1 << 21)
3497#define LVDS_HSYNC_POLARITY (1 << 20)
3498
3499/* Enable border for unscaled (or aspect-scaled) display */
3500#define LVDS_BORDER_ENABLE (1 << 15)
3501/*
3502 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
3503 * pixel.
3504 */
3505#define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
3506#define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
3507#define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
3508/*
3509 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
3510 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
3511 * on.
3512 */
3513#define LVDS_A3_POWER_MASK (3 << 6)
3514#define LVDS_A3_POWER_DOWN (0 << 6)
3515#define LVDS_A3_POWER_UP (3 << 6)
3516/*
3517 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
3518 * is set.
3519 */
3520#define LVDS_CLKB_POWER_MASK (3 << 4)
3521#define LVDS_CLKB_POWER_DOWN (0 << 4)
3522#define LVDS_CLKB_POWER_UP (3 << 4)
3523/*
3524 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
3525 * setting for whether we are in dual-channel mode. The B3 pair will
3526 * additionally only be powered up when LVDS_A3_POWER_UP is set.
3527 */
3528#define LVDS_B0B3_POWER_MASK (3 << 2)
3529#define LVDS_B0B3_POWER_DOWN (0 << 2)
3530#define LVDS_B0B3_POWER_UP (3 << 2)
3531
3532/* Video Data Island Packet control */
3533#define VIDEO_DIP_DATA _MMIO(0x61178)
3534/* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC
3535 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
3536 * of the infoframe structure specified by CEA-861. */
3537#define VIDEO_DIP_DATA_SIZE 32
3538#define VIDEO_DIP_VSC_DATA_SIZE 36
3539#define VIDEO_DIP_CTL _MMIO(0x61170)
3540/* Pre HSW: */
3541#define VIDEO_DIP_ENABLE (1 << 31)
3542#define VIDEO_DIP_PORT(port) ((port) << 29)
3543#define VIDEO_DIP_PORT_MASK (3 << 29)
3544#define VIDEO_DIP_ENABLE_GCP (1 << 25)
3545#define VIDEO_DIP_ENABLE_AVI (1 << 21)
3546#define VIDEO_DIP_ENABLE_VENDOR (2 << 21)
3547#define VIDEO_DIP_ENABLE_GAMUT (4 << 21)
3548#define VIDEO_DIP_ENABLE_SPD (8 << 21)
3549#define VIDEO_DIP_SELECT_AVI (0 << 19)
3550#define VIDEO_DIP_SELECT_VENDOR (1 << 19)
3551#define VIDEO_DIP_SELECT_SPD (3 << 19)
3552#define VIDEO_DIP_SELECT_MASK (3 << 19)
3553#define VIDEO_DIP_FREQ_ONCE (0 << 16)
3554#define VIDEO_DIP_FREQ_VSYNC (1 << 16)
3555#define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
3556#define VIDEO_DIP_FREQ_MASK (3 << 16)
3557/* HSW and later: */
3558#define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20)
3559#define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16)
3560#define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12)
3561#define VIDEO_DIP_ENABLE_VS_HSW (1 << 8)
3562#define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
3563#define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
3564
3565/* Panel power sequencing */
3566#define PP_STATUS _MMIO(0x61200)
3567#define PP_ON (1 << 31)
3568/*
3569 * Indicates that all dependencies of the panel are on:
3570 *
3571 * - PLL enabled
3572 * - pipe enabled
3573 * - LVDS/DVOB/DVOC on
3574 */
3575#define PP_READY (1 << 30)
3576#define PP_SEQUENCE_NONE (0 << 28)
3577#define PP_SEQUENCE_POWER_UP (1 << 28)
3578#define PP_SEQUENCE_POWER_DOWN (2 << 28)
3579#define PP_SEQUENCE_MASK (3 << 28)
3580#define PP_SEQUENCE_SHIFT 28
3581#define PP_CYCLE_DELAY_ACTIVE (1 << 27)
3582#define PP_SEQUENCE_STATE_MASK 0x0000000f
3583#define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0)
3584#define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0)
3585#define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0)
3586#define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0)
3587#define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0)
3588#define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0)
3589#define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0)
3590#define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0)
3591#define PP_SEQUENCE_STATE_RESET (0xf << 0)
3592#define PP_CONTROL _MMIO(0x61204)
3593#define POWER_TARGET_ON (1 << 0)
3594#define PP_ON_DELAYS _MMIO(0x61208)
3595#define PP_OFF_DELAYS _MMIO(0x6120c)
3596#define PP_DIVISOR _MMIO(0x61210)
3597
3598/* Panel fitting */
3599#define PFIT_CONTROL _MMIO(dev_priv->info.display_mmio_offset + 0x61230)
3600#define PFIT_ENABLE (1 << 31)
3601#define PFIT_PIPE_MASK (3 << 29)
3602#define PFIT_PIPE_SHIFT 29
3603#define VERT_INTERP_DISABLE (0 << 10)
3604#define VERT_INTERP_BILINEAR (1 << 10)
3605#define VERT_INTERP_MASK (3 << 10)
3606#define VERT_AUTO_SCALE (1 << 9)
3607#define HORIZ_INTERP_DISABLE (0 << 6)
3608#define HORIZ_INTERP_BILINEAR (1 << 6)
3609#define HORIZ_INTERP_MASK (3 << 6)
3610#define HORIZ_AUTO_SCALE (1 << 5)
3611#define PANEL_8TO6_DITHER_ENABLE (1 << 3)
3612#define PFIT_FILTER_FUZZY (0 << 24)
3613#define PFIT_SCALING_AUTO (0 << 26)
3614#define PFIT_SCALING_PROGRAMMED (1 << 26)
3615#define PFIT_SCALING_PILLAR (2 << 26)
3616#define PFIT_SCALING_LETTER (3 << 26)
3617#define PFIT_PGM_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61234)
3618/* Pre-965 */
3619#define PFIT_VERT_SCALE_SHIFT 20
3620#define PFIT_VERT_SCALE_MASK 0xfff00000
3621#define PFIT_HORIZ_SCALE_SHIFT 4
3622#define PFIT_HORIZ_SCALE_MASK 0x0000fff0
3623/* 965+ */
3624#define PFIT_VERT_SCALE_SHIFT_965 16
3625#define PFIT_VERT_SCALE_MASK_965 0x1fff0000
3626#define PFIT_HORIZ_SCALE_SHIFT_965 0
3627#define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
3628
3629#define PFIT_AUTO_RATIOS _MMIO(dev_priv->info.display_mmio_offset + 0x61238)
3630
3631#define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250)
3632#define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350)
3633#define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
3634 _VLV_BLC_PWM_CTL2_B)
3635
3636#define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254)
3637#define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354)
3638#define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
3639 _VLV_BLC_PWM_CTL_B)
3640
3641#define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260)
3642#define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360)
3643#define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
3644 _VLV_BLC_HIST_CTL_B)
3645
3646/* Backlight control */
3647#define BLC_PWM_CTL2 _MMIO(dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */
3648#define BLM_PWM_ENABLE (1 << 31)
3649#define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */
3650#define BLM_PIPE_SELECT (1 << 29)
3651#define BLM_PIPE_SELECT_IVB (3 << 29)
3652#define BLM_PIPE_A (0 << 29)
3653#define BLM_PIPE_B (1 << 29)
3654#define BLM_PIPE_C (2 << 29) /* ivb + */
3655#define BLM_TRANSCODER_A BLM_PIPE_A /* hsw */
3656#define BLM_TRANSCODER_B BLM_PIPE_B
3657#define BLM_TRANSCODER_C BLM_PIPE_C
3658#define BLM_TRANSCODER_EDP (3 << 29)
3659#define BLM_PIPE(pipe) ((pipe) << 29)
3660#define BLM_POLARITY_I965 (1 << 28) /* gen4 only */
3661#define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26)
3662#define BLM_PHASE_IN_ENABLE (1 << 25)
3663#define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24)
3664#define BLM_PHASE_IN_TIME_BASE_SHIFT (16)
3665#define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16)
3666#define BLM_PHASE_IN_COUNT_SHIFT (8)
3667#define BLM_PHASE_IN_COUNT_MASK (0xff << 8)
3668#define BLM_PHASE_IN_INCR_SHIFT (0)
3669#define BLM_PHASE_IN_INCR_MASK (0xff << 0)
3670#define BLC_PWM_CTL _MMIO(dev_priv->info.display_mmio_offset + 0x61254)
3671/*
3672 * This is the most significant 15 bits of the number of backlight cycles in a
3673 * complete cycle of the modulated backlight control.
3674 *
3675 * The actual value is this field multiplied by two.
3676 */
3677#define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
3678#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
3679#define BLM_LEGACY_MODE (1 << 16) /* gen2 only */
3680/*
3681 * This is the number of cycles out of the backlight modulation cycle for which
3682 * the backlight is on.
3683 *
3684 * This field must be no greater than the number of cycles in the complete
3685 * backlight modulation cycle.
3686 */
3687#define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
3688#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
3689#define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe)
3690#define BLM_POLARITY_PNV (1 << 0) /* pnv only */
3691
3692#define BLC_HIST_CTL _MMIO(dev_priv->info.display_mmio_offset + 0x61260)
3693#define BLM_HISTOGRAM_ENABLE (1 << 31)
3694
3695/* New registers for PCH-split platforms. Safe where new bits show up, the
3696 * register layout machtes with gen4 BLC_PWM_CTL[12]. */
3697#define BLC_PWM_CPU_CTL2 _MMIO(0x48250)
3698#define BLC_PWM_CPU_CTL _MMIO(0x48254)
3699
3700#define HSW_BLC_PWM2_CTL _MMIO(0x48350)
3701
3702/* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
3703 * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
3704#define BLC_PWM_PCH_CTL1 _MMIO(0xc8250)
3705#define BLM_PCH_PWM_ENABLE (1 << 31)
3706#define BLM_PCH_OVERRIDE_ENABLE (1 << 30)
3707#define BLM_PCH_POLARITY (1 << 29)
3708#define BLC_PWM_PCH_CTL2 _MMIO(0xc8254)
3709
3710#define UTIL_PIN_CTL _MMIO(0x48400)
3711#define UTIL_PIN_ENABLE (1 << 31)
3712
3713#define UTIL_PIN_PIPE(x) ((x) << 29)
3714#define UTIL_PIN_PIPE_MASK (3 << 29)
3715#define UTIL_PIN_MODE_PWM (1 << 24)
3716#define UTIL_PIN_MODE_MASK (0xf << 24)
3717#define UTIL_PIN_POLARITY (1 << 22)
3718
3719/* BXT backlight register definition. */
3720#define _BXT_BLC_PWM_CTL1 0xC8250
3721#define BXT_BLC_PWM_ENABLE (1 << 31)
3722#define BXT_BLC_PWM_POLARITY (1 << 29)
3723#define _BXT_BLC_PWM_FREQ1 0xC8254
3724#define _BXT_BLC_PWM_DUTY1 0xC8258
3725
3726#define _BXT_BLC_PWM_CTL2 0xC8350
3727#define _BXT_BLC_PWM_FREQ2 0xC8354
3728#define _BXT_BLC_PWM_DUTY2 0xC8358
3729
3730#define BXT_BLC_PWM_CTL(controller) _MMIO_PIPE(controller, \
3731 _BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2)
3732#define BXT_BLC_PWM_FREQ(controller) _MMIO_PIPE(controller, \
3733 _BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2)
3734#define BXT_BLC_PWM_DUTY(controller) _MMIO_PIPE(controller, \
3735 _BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2)
3736
3737#define PCH_GTC_CTL _MMIO(0xe7000)
3738#define PCH_GTC_ENABLE (1 << 31)
3739
3740/* TV port control */
3741#define TV_CTL _MMIO(0x68000)
3742/* Enables the TV encoder */
3743# define TV_ENC_ENABLE (1 << 31)
3744/* Sources the TV encoder input from pipe B instead of A. */
3745# define TV_ENC_PIPEB_SELECT (1 << 30)
3746/* Outputs composite video (DAC A only) */
3747# define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
3748/* Outputs SVideo video (DAC B/C) */
3749# define TV_ENC_OUTPUT_SVIDEO (1 << 28)
3750/* Outputs Component video (DAC A/B/C) */
3751# define TV_ENC_OUTPUT_COMPONENT (2 << 28)
3752/* Outputs Composite and SVideo (DAC A/B/C) */
3753# define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
3754# define TV_TRILEVEL_SYNC (1 << 21)
3755/* Enables slow sync generation (945GM only) */
3756# define TV_SLOW_SYNC (1 << 20)
3757/* Selects 4x oversampling for 480i and 576p */
3758# define TV_OVERSAMPLE_4X (0 << 18)
3759/* Selects 2x oversampling for 720p and 1080i */
3760# define TV_OVERSAMPLE_2X (1 << 18)
3761/* Selects no oversampling for 1080p */
3762# define TV_OVERSAMPLE_NONE (2 << 18)
3763/* Selects 8x oversampling */
3764# define TV_OVERSAMPLE_8X (3 << 18)
3765/* Selects progressive mode rather than interlaced */
3766# define TV_PROGRESSIVE (1 << 17)
3767/* Sets the colorburst to PAL mode. Required for non-M PAL modes. */
3768# define TV_PAL_BURST (1 << 16)
3769/* Field for setting delay of Y compared to C */
3770# define TV_YC_SKEW_MASK (7 << 12)
3771/* Enables a fix for 480p/576p standard definition modes on the 915GM only */
3772# define TV_ENC_SDP_FIX (1 << 11)
3773/*
3774 * Enables a fix for the 915GM only.
3775 *
3776 * Not sure what it does.
3777 */
3778# define TV_ENC_C0_FIX (1 << 10)
3779/* Bits that must be preserved by software */
3780# define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
3781# define TV_FUSE_STATE_MASK (3 << 4)
3782/* Read-only state that reports all features enabled */
3783# define TV_FUSE_STATE_ENABLED (0 << 4)
3784/* Read-only state that reports that Macrovision is disabled in hardware*/
3785# define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
3786/* Read-only state that reports that TV-out is disabled in hardware. */
3787# define TV_FUSE_STATE_DISABLED (2 << 4)
3788/* Normal operation */
3789# define TV_TEST_MODE_NORMAL (0 << 0)
3790/* Encoder test pattern 1 - combo pattern */
3791# define TV_TEST_MODE_PATTERN_1 (1 << 0)
3792/* Encoder test pattern 2 - full screen vertical 75% color bars */
3793# define TV_TEST_MODE_PATTERN_2 (2 << 0)
3794/* Encoder test pattern 3 - full screen horizontal 75% color bars */
3795# define TV_TEST_MODE_PATTERN_3 (3 << 0)
3796/* Encoder test pattern 4 - random noise */
3797# define TV_TEST_MODE_PATTERN_4 (4 << 0)
3798/* Encoder test pattern 5 - linear color ramps */
3799# define TV_TEST_MODE_PATTERN_5 (5 << 0)
3800/*
3801 * This test mode forces the DACs to 50% of full output.
3802 *
3803 * This is used for load detection in combination with TVDAC_SENSE_MASK
3804 */
3805# define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
3806# define TV_TEST_MODE_MASK (7 << 0)
3807
3808#define TV_DAC _MMIO(0x68004)
3809# define TV_DAC_SAVE 0x00ffff00
3810/*
3811 * Reports that DAC state change logic has reported change (RO).
3812 *
3813 * This gets cleared when TV_DAC_STATE_EN is cleared
3814*/
3815# define TVDAC_STATE_CHG (1 << 31)
3816# define TVDAC_SENSE_MASK (7 << 28)
3817/* Reports that DAC A voltage is above the detect threshold */
3818# define TVDAC_A_SENSE (1 << 30)
3819/* Reports that DAC B voltage is above the detect threshold */
3820# define TVDAC_B_SENSE (1 << 29)
3821/* Reports that DAC C voltage is above the detect threshold */
3822# define TVDAC_C_SENSE (1 << 28)
3823/*
3824 * Enables DAC state detection logic, for load-based TV detection.
3825 *
3826 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
3827 * to off, for load detection to work.
3828 */
3829# define TVDAC_STATE_CHG_EN (1 << 27)
3830/* Sets the DAC A sense value to high */
3831# define TVDAC_A_SENSE_CTL (1 << 26)
3832/* Sets the DAC B sense value to high */
3833# define TVDAC_B_SENSE_CTL (1 << 25)
3834/* Sets the DAC C sense value to high */
3835# define TVDAC_C_SENSE_CTL (1 << 24)
3836/* Overrides the ENC_ENABLE and DAC voltage levels */
3837# define DAC_CTL_OVERRIDE (1 << 7)
3838/* Sets the slew rate. Must be preserved in software */
3839# define ENC_TVDAC_SLEW_FAST (1 << 6)
3840# define DAC_A_1_3_V (0 << 4)
3841# define DAC_A_1_1_V (1 << 4)
3842# define DAC_A_0_7_V (2 << 4)
3843# define DAC_A_MASK (3 << 4)
3844# define DAC_B_1_3_V (0 << 2)
3845# define DAC_B_1_1_V (1 << 2)
3846# define DAC_B_0_7_V (2 << 2)
3847# define DAC_B_MASK (3 << 2)
3848# define DAC_C_1_3_V (0 << 0)
3849# define DAC_C_1_1_V (1 << 0)
3850# define DAC_C_0_7_V (2 << 0)
3851# define DAC_C_MASK (3 << 0)
3852
3853/*
3854 * CSC coefficients are stored in a floating point format with 9 bits of
3855 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
3856 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
3857 * -1 (0x3) being the only legal negative value.
3858 */
3859#define TV_CSC_Y _MMIO(0x68010)
3860# define TV_RY_MASK 0x07ff0000
3861# define TV_RY_SHIFT 16
3862# define TV_GY_MASK 0x00000fff
3863# define TV_GY_SHIFT 0
3864
3865#define TV_CSC_Y2 _MMIO(0x68014)
3866# define TV_BY_MASK 0x07ff0000
3867# define TV_BY_SHIFT 16
3868/*
3869 * Y attenuation for component video.
3870 *
3871 * Stored in 1.9 fixed point.
3872 */
3873# define TV_AY_MASK 0x000003ff
3874# define TV_AY_SHIFT 0
3875
3876#define TV_CSC_U _MMIO(0x68018)
3877# define TV_RU_MASK 0x07ff0000
3878# define TV_RU_SHIFT 16
3879# define TV_GU_MASK 0x000007ff
3880# define TV_GU_SHIFT 0
3881
3882#define TV_CSC_U2 _MMIO(0x6801c)
3883# define TV_BU_MASK 0x07ff0000
3884# define TV_BU_SHIFT 16
3885/*
3886 * U attenuation for component video.
3887 *
3888 * Stored in 1.9 fixed point.
3889 */
3890# define TV_AU_MASK 0x000003ff
3891# define TV_AU_SHIFT 0
3892
3893#define TV_CSC_V _MMIO(0x68020)
3894# define TV_RV_MASK 0x0fff0000
3895# define TV_RV_SHIFT 16
3896# define TV_GV_MASK 0x000007ff
3897# define TV_GV_SHIFT 0
3898
3899#define TV_CSC_V2 _MMIO(0x68024)
3900# define TV_BV_MASK 0x07ff0000
3901# define TV_BV_SHIFT 16
3902/*
3903 * V attenuation for component video.
3904 *
3905 * Stored in 1.9 fixed point.
3906 */
3907# define TV_AV_MASK 0x000007ff
3908# define TV_AV_SHIFT 0
3909
3910#define TV_CLR_KNOBS _MMIO(0x68028)
3911/* 2s-complement brightness adjustment */
3912# define TV_BRIGHTNESS_MASK 0xff000000
3913# define TV_BRIGHTNESS_SHIFT 24
3914/* Contrast adjustment, as a 2.6 unsigned floating point number */
3915# define TV_CONTRAST_MASK 0x00ff0000
3916# define TV_CONTRAST_SHIFT 16
3917/* Saturation adjustment, as a 2.6 unsigned floating point number */
3918# define TV_SATURATION_MASK 0x0000ff00
3919# define TV_SATURATION_SHIFT 8
3920/* Hue adjustment, as an integer phase angle in degrees */
3921# define TV_HUE_MASK 0x000000ff
3922# define TV_HUE_SHIFT 0
3923
3924#define TV_CLR_LEVEL _MMIO(0x6802c)
3925/* Controls the DAC level for black */
3926# define TV_BLACK_LEVEL_MASK 0x01ff0000
3927# define TV_BLACK_LEVEL_SHIFT 16
3928/* Controls the DAC level for blanking */
3929# define TV_BLANK_LEVEL_MASK 0x000001ff
3930# define TV_BLANK_LEVEL_SHIFT 0
3931
3932#define TV_H_CTL_1 _MMIO(0x68030)
3933/* Number of pixels in the hsync. */
3934# define TV_HSYNC_END_MASK 0x1fff0000
3935# define TV_HSYNC_END_SHIFT 16
3936/* Total number of pixels minus one in the line (display and blanking). */
3937# define TV_HTOTAL_MASK 0x00001fff
3938# define TV_HTOTAL_SHIFT 0
3939
3940#define TV_H_CTL_2 _MMIO(0x68034)
3941/* Enables the colorburst (needed for non-component color) */
3942# define TV_BURST_ENA (1 << 31)
3943/* Offset of the colorburst from the start of hsync, in pixels minus one. */
3944# define TV_HBURST_START_SHIFT 16
3945# define TV_HBURST_START_MASK 0x1fff0000
3946/* Length of the colorburst */
3947# define TV_HBURST_LEN_SHIFT 0
3948# define TV_HBURST_LEN_MASK 0x0001fff
3949
3950#define TV_H_CTL_3 _MMIO(0x68038)
3951/* End of hblank, measured in pixels minus one from start of hsync */
3952# define TV_HBLANK_END_SHIFT 16
3953# define TV_HBLANK_END_MASK 0x1fff0000
3954/* Start of hblank, measured in pixels minus one from start of hsync */
3955# define TV_HBLANK_START_SHIFT 0
3956# define TV_HBLANK_START_MASK 0x0001fff
3957
3958#define TV_V_CTL_1 _MMIO(0x6803c)
3959/* XXX */
3960# define TV_NBR_END_SHIFT 16
3961# define TV_NBR_END_MASK 0x07ff0000
3962/* XXX */
3963# define TV_VI_END_F1_SHIFT 8
3964# define TV_VI_END_F1_MASK 0x00003f00
3965/* XXX */
3966# define TV_VI_END_F2_SHIFT 0
3967# define TV_VI_END_F2_MASK 0x0000003f
3968
3969#define TV_V_CTL_2 _MMIO(0x68040)
3970/* Length of vsync, in half lines */
3971# define TV_VSYNC_LEN_MASK 0x07ff0000
3972# define TV_VSYNC_LEN_SHIFT 16
3973/* Offset of the start of vsync in field 1, measured in one less than the
3974 * number of half lines.
3975 */
3976# define TV_VSYNC_START_F1_MASK 0x00007f00
3977# define TV_VSYNC_START_F1_SHIFT 8
3978/*
3979 * Offset of the start of vsync in field 2, measured in one less than the
3980 * number of half lines.
3981 */
3982# define TV_VSYNC_START_F2_MASK 0x0000007f
3983# define TV_VSYNC_START_F2_SHIFT 0
3984
3985#define TV_V_CTL_3 _MMIO(0x68044)
3986/* Enables generation of the equalization signal */
3987# define TV_EQUAL_ENA (1 << 31)
3988/* Length of vsync, in half lines */
3989# define TV_VEQ_LEN_MASK 0x007f0000
3990# define TV_VEQ_LEN_SHIFT 16
3991/* Offset of the start of equalization in field 1, measured in one less than
3992 * the number of half lines.
3993 */
3994# define TV_VEQ_START_F1_MASK 0x0007f00
3995# define TV_VEQ_START_F1_SHIFT 8
3996/*
3997 * Offset of the start of equalization in field 2, measured in one less than
3998 * the number of half lines.
3999 */
4000# define TV_VEQ_START_F2_MASK 0x000007f
4001# define TV_VEQ_START_F2_SHIFT 0
4002
4003#define TV_V_CTL_4 _MMIO(0x68048)
4004/*
4005 * Offset to start of vertical colorburst, measured in one less than the
4006 * number of lines from vertical start.
4007 */
4008# define TV_VBURST_START_F1_MASK 0x003f0000
4009# define TV_VBURST_START_F1_SHIFT 16
4010/*
4011 * Offset to the end of vertical colorburst, measured in one less than the
4012 * number of lines from the start of NBR.
4013 */
4014# define TV_VBURST_END_F1_MASK 0x000000ff
4015# define TV_VBURST_END_F1_SHIFT 0
4016
4017#define TV_V_CTL_5 _MMIO(0x6804c)
4018/*
4019 * Offset to start of vertical colorburst, measured in one less than the
4020 * number of lines from vertical start.
4021 */
4022# define TV_VBURST_START_F2_MASK 0x003f0000
4023# define TV_VBURST_START_F2_SHIFT 16
4024/*
4025 * Offset to the end of vertical colorburst, measured in one less than the
4026 * number of lines from the start of NBR.
4027 */
4028# define TV_VBURST_END_F2_MASK 0x000000ff
4029# define TV_VBURST_END_F2_SHIFT 0
4030
4031#define TV_V_CTL_6 _MMIO(0x68050)
4032/*
4033 * Offset to start of vertical colorburst, measured in one less than the
4034 * number of lines from vertical start.
4035 */
4036# define TV_VBURST_START_F3_MASK 0x003f0000
4037# define TV_VBURST_START_F3_SHIFT 16
4038/*
4039 * Offset to the end of vertical colorburst, measured in one less than the
4040 * number of lines from the start of NBR.
4041 */
4042# define TV_VBURST_END_F3_MASK 0x000000ff
4043# define TV_VBURST_END_F3_SHIFT 0
4044
4045#define TV_V_CTL_7 _MMIO(0x68054)
4046/*
4047 * Offset to start of vertical colorburst, measured in one less than the
4048 * number of lines from vertical start.
4049 */
4050# define TV_VBURST_START_F4_MASK 0x003f0000
4051# define TV_VBURST_START_F4_SHIFT 16
4052/*
4053 * Offset to the end of vertical colorburst, measured in one less than the
4054 * number of lines from the start of NBR.
4055 */
4056# define TV_VBURST_END_F4_MASK 0x000000ff
4057# define TV_VBURST_END_F4_SHIFT 0
4058
4059#define TV_SC_CTL_1 _MMIO(0x68060)
4060/* Turns on the first subcarrier phase generation DDA */
4061# define TV_SC_DDA1_EN (1 << 31)
4062/* Turns on the first subcarrier phase generation DDA */
4063# define TV_SC_DDA2_EN (1 << 30)
4064/* Turns on the first subcarrier phase generation DDA */
4065# define TV_SC_DDA3_EN (1 << 29)
4066/* Sets the subcarrier DDA to reset frequency every other field */
4067# define TV_SC_RESET_EVERY_2 (0 << 24)
4068/* Sets the subcarrier DDA to reset frequency every fourth field */
4069# define TV_SC_RESET_EVERY_4 (1 << 24)
4070/* Sets the subcarrier DDA to reset frequency every eighth field */
4071# define TV_SC_RESET_EVERY_8 (2 << 24)
4072/* Sets the subcarrier DDA to never reset the frequency */
4073# define TV_SC_RESET_NEVER (3 << 24)
4074/* Sets the peak amplitude of the colorburst.*/
4075# define TV_BURST_LEVEL_MASK 0x00ff0000
4076# define TV_BURST_LEVEL_SHIFT 16
4077/* Sets the increment of the first subcarrier phase generation DDA */
4078# define TV_SCDDA1_INC_MASK 0x00000fff
4079# define TV_SCDDA1_INC_SHIFT 0
4080
4081#define TV_SC_CTL_2 _MMIO(0x68064)
4082/* Sets the rollover for the second subcarrier phase generation DDA */
4083# define TV_SCDDA2_SIZE_MASK 0x7fff0000
4084# define TV_SCDDA2_SIZE_SHIFT 16
4085/* Sets the increent of the second subcarrier phase generation DDA */
4086# define TV_SCDDA2_INC_MASK 0x00007fff
4087# define TV_SCDDA2_INC_SHIFT 0
4088
4089#define TV_SC_CTL_3 _MMIO(0x68068)
4090/* Sets the rollover for the third subcarrier phase generation DDA */
4091# define TV_SCDDA3_SIZE_MASK 0x7fff0000
4092# define TV_SCDDA3_SIZE_SHIFT 16
4093/* Sets the increent of the third subcarrier phase generation DDA */
4094# define TV_SCDDA3_INC_MASK 0x00007fff
4095# define TV_SCDDA3_INC_SHIFT 0
4096
4097#define TV_WIN_POS _MMIO(0x68070)
4098/* X coordinate of the display from the start of horizontal active */
4099# define TV_XPOS_MASK 0x1fff0000
4100# define TV_XPOS_SHIFT 16
4101/* Y coordinate of the display from the start of vertical active (NBR) */
4102# define TV_YPOS_MASK 0x00000fff
4103# define TV_YPOS_SHIFT 0
4104
4105#define TV_WIN_SIZE _MMIO(0x68074)
4106/* Horizontal size of the display window, measured in pixels*/
4107# define TV_XSIZE_MASK 0x1fff0000
4108# define TV_XSIZE_SHIFT 16
4109/*
4110 * Vertical size of the display window, measured in pixels.
4111 *
4112 * Must be even for interlaced modes.
4113 */
4114# define TV_YSIZE_MASK 0x00000fff
4115# define TV_YSIZE_SHIFT 0
4116
4117#define TV_FILTER_CTL_1 _MMIO(0x68080)
4118/*
4119 * Enables automatic scaling calculation.
4120 *
4121 * If set, the rest of the registers are ignored, and the calculated values can
4122 * be read back from the register.
4123 */
4124# define TV_AUTO_SCALE (1 << 31)
4125/*
4126 * Disables the vertical filter.
4127 *
4128 * This is required on modes more than 1024 pixels wide */
4129# define TV_V_FILTER_BYPASS (1 << 29)
4130/* Enables adaptive vertical filtering */
4131# define TV_VADAPT (1 << 28)
4132# define TV_VADAPT_MODE_MASK (3 << 26)
4133/* Selects the least adaptive vertical filtering mode */
4134# define TV_VADAPT_MODE_LEAST (0 << 26)
4135/* Selects the moderately adaptive vertical filtering mode */
4136# define TV_VADAPT_MODE_MODERATE (1 << 26)
4137/* Selects the most adaptive vertical filtering mode */
4138# define TV_VADAPT_MODE_MOST (3 << 26)
4139/*
4140 * Sets the horizontal scaling factor.
4141 *
4142 * This should be the fractional part of the horizontal scaling factor divided
4143 * by the oversampling rate. TV_HSCALE should be less than 1, and set to:
4144 *
4145 * (src width - 1) / ((oversample * dest width) - 1)
4146 */
4147# define TV_HSCALE_FRAC_MASK 0x00003fff
4148# define TV_HSCALE_FRAC_SHIFT 0
4149
4150#define TV_FILTER_CTL_2 _MMIO(0x68084)
4151/*
4152 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
4153 *
4154 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
4155 */
4156# define TV_VSCALE_INT_MASK 0x00038000
4157# define TV_VSCALE_INT_SHIFT 15
4158/*
4159 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
4160 *
4161 * \sa TV_VSCALE_INT_MASK
4162 */
4163# define TV_VSCALE_FRAC_MASK 0x00007fff
4164# define TV_VSCALE_FRAC_SHIFT 0
4165
4166#define TV_FILTER_CTL_3 _MMIO(0x68088)
4167/*
4168 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
4169 *
4170 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
4171 *
4172 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
4173 */
4174# define TV_VSCALE_IP_INT_MASK 0x00038000
4175# define TV_VSCALE_IP_INT_SHIFT 15
4176/*
4177 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
4178 *
4179 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
4180 *
4181 * \sa TV_VSCALE_IP_INT_MASK
4182 */
4183# define TV_VSCALE_IP_FRAC_MASK 0x00007fff
4184# define TV_VSCALE_IP_FRAC_SHIFT 0
4185
4186#define TV_CC_CONTROL _MMIO(0x68090)
4187# define TV_CC_ENABLE (1 << 31)
4188/*
4189 * Specifies which field to send the CC data in.
4190 *
4191 * CC data is usually sent in field 0.
4192 */
4193# define TV_CC_FID_MASK (1 << 27)
4194# define TV_CC_FID_SHIFT 27
4195/* Sets the horizontal position of the CC data. Usually 135. */
4196# define TV_CC_HOFF_MASK 0x03ff0000
4197# define TV_CC_HOFF_SHIFT 16
4198/* Sets the vertical position of the CC data. Usually 21 */
4199# define TV_CC_LINE_MASK 0x0000003f
4200# define TV_CC_LINE_SHIFT 0
4201
4202#define TV_CC_DATA _MMIO(0x68094)
4203# define TV_CC_RDY (1 << 31)
4204/* Second word of CC data to be transmitted. */
4205# define TV_CC_DATA_2_MASK 0x007f0000
4206# define TV_CC_DATA_2_SHIFT 16
4207/* First word of CC data to be transmitted. */
4208# define TV_CC_DATA_1_MASK 0x0000007f
4209# define TV_CC_DATA_1_SHIFT 0
4210
4211#define TV_H_LUMA(i) _MMIO(0x68100 + (i) * 4) /* 60 registers */
4212#define TV_H_CHROMA(i) _MMIO(0x68200 + (i) * 4) /* 60 registers */
4213#define TV_V_LUMA(i) _MMIO(0x68300 + (i) * 4) /* 43 registers */
4214#define TV_V_CHROMA(i) _MMIO(0x68400 + (i) * 4) /* 43 registers */
4215
4216/* Display Port */
4217#define DP_A _MMIO(0x64000) /* eDP */
4218#define DP_B _MMIO(0x64100)
4219#define DP_C _MMIO(0x64200)
4220#define DP_D _MMIO(0x64300)
4221
4222#define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100)
4223#define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200)
4224#define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300)
4225
4226#define DP_PORT_EN (1 << 31)
4227#define DP_PIPEB_SELECT (1 << 30)
4228#define DP_PIPE_MASK (1 << 30)
4229#define DP_PIPE_SELECT_CHV(pipe) ((pipe) << 16)
4230#define DP_PIPE_MASK_CHV (3 << 16)
4231
4232/* Link training mode - select a suitable mode for each stage */
4233#define DP_LINK_TRAIN_PAT_1 (0 << 28)
4234#define DP_LINK_TRAIN_PAT_2 (1 << 28)
4235#define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
4236#define DP_LINK_TRAIN_OFF (3 << 28)
4237#define DP_LINK_TRAIN_MASK (3 << 28)
4238#define DP_LINK_TRAIN_SHIFT 28
4239#define DP_LINK_TRAIN_PAT_3_CHV (1 << 14)
4240#define DP_LINK_TRAIN_MASK_CHV ((3 << 28)|(1<<14))
4241
4242/* CPT Link training mode */
4243#define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
4244#define DP_LINK_TRAIN_PAT_2_CPT (1 << 8)
4245#define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8)
4246#define DP_LINK_TRAIN_OFF_CPT (3 << 8)
4247#define DP_LINK_TRAIN_MASK_CPT (7 << 8)
4248#define DP_LINK_TRAIN_SHIFT_CPT 8
4249
4250/* Signal voltages. These are mostly controlled by the other end */
4251#define DP_VOLTAGE_0_4 (0 << 25)
4252#define DP_VOLTAGE_0_6 (1 << 25)
4253#define DP_VOLTAGE_0_8 (2 << 25)
4254#define DP_VOLTAGE_1_2 (3 << 25)
4255#define DP_VOLTAGE_MASK (7 << 25)
4256#define DP_VOLTAGE_SHIFT 25
4257
4258/* Signal pre-emphasis levels, like voltages, the other end tells us what
4259 * they want
4260 */
4261#define DP_PRE_EMPHASIS_0 (0 << 22)
4262#define DP_PRE_EMPHASIS_3_5 (1 << 22)
4263#define DP_PRE_EMPHASIS_6 (2 << 22)
4264#define DP_PRE_EMPHASIS_9_5 (3 << 22)
4265#define DP_PRE_EMPHASIS_MASK (7 << 22)
4266#define DP_PRE_EMPHASIS_SHIFT 22
4267
4268/* How many wires to use. I guess 3 was too hard */
4269#define DP_PORT_WIDTH(width) (((width) - 1) << 19)
4270#define DP_PORT_WIDTH_MASK (7 << 19)
4271#define DP_PORT_WIDTH_SHIFT 19
4272
4273/* Mystic DPCD version 1.1 special mode */
4274#define DP_ENHANCED_FRAMING (1 << 18)
4275
4276/* eDP */
4277#define DP_PLL_FREQ_270MHZ (0 << 16)
4278#define DP_PLL_FREQ_162MHZ (1 << 16)
4279#define DP_PLL_FREQ_MASK (3 << 16)
4280
4281/* locked once port is enabled */
4282#define DP_PORT_REVERSAL (1 << 15)
4283
4284/* eDP */
4285#define DP_PLL_ENABLE (1 << 14)
4286
4287/* sends the clock on lane 15 of the PEG for debug */
4288#define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
4289
4290#define DP_SCRAMBLING_DISABLE (1 << 12)
4291#define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
4292
4293/* limit RGB values to avoid confusing TVs */
4294#define DP_COLOR_RANGE_16_235 (1 << 8)
4295
4296/* Turn on the audio link */
4297#define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
4298
4299/* vs and hs sync polarity */
4300#define DP_SYNC_VS_HIGH (1 << 4)
4301#define DP_SYNC_HS_HIGH (1 << 3)
4302
4303/* A fantasy */
4304#define DP_DETECTED (1 << 2)
4305
4306/* The aux channel provides a way to talk to the
4307 * signal sink for DDC etc. Max packet size supported
4308 * is 20 bytes in each direction, hence the 5 fixed
4309 * data registers
4310 */
4311#define _DPA_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64010)
4312#define _DPA_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64014)
4313#define _DPA_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64018)
4314#define _DPA_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6401c)
4315#define _DPA_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64020)
4316#define _DPA_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64024)
4317
4318#define _DPB_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64110)
4319#define _DPB_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64114)
4320#define _DPB_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64118)
4321#define _DPB_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6411c)
4322#define _DPB_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64120)
4323#define _DPB_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64124)
4324
4325#define _DPC_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64210)
4326#define _DPC_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64214)
4327#define _DPC_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64218)
4328#define _DPC_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6421c)
4329#define _DPC_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64220)
4330#define _DPC_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64224)
4331
4332#define _DPD_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64310)
4333#define _DPD_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64314)
4334#define _DPD_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64318)
4335#define _DPD_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6431c)
4336#define _DPD_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64320)
4337#define _DPD_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64324)
4338
4339#define DP_AUX_CH_CTL(port) _MMIO_PORT(port, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
4340#define DP_AUX_CH_DATA(port, i) _MMIO(_PORT(port, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
4341
4342#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
4343#define DP_AUX_CH_CTL_DONE (1 << 30)
4344#define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
4345#define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
4346#define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
4347#define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
4348#define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
4349#define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26)
4350#define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
4351#define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
4352#define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
4353#define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
4354#define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
4355#define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
4356#define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
4357#define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)
4358#define DP_AUX_CH_CTL_SYNC_TEST (1 << 13)
4359#define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)
4360#define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
4361#define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
4362#define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
4363#define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL (1 << 14)
4364#define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL (1 << 13)
4365#define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL (1 << 12)
4366#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (0x1f << 5)
4367#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
4368#define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1)
4369
4370/*
4371 * Computing GMCH M and N values for the Display Port link
4372 *
4373 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
4374 *
4375 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
4376 *
4377 * The GMCH value is used internally
4378 *
4379 * bytes_per_pixel is the number of bytes coming out of the plane,
4380 * which is after the LUTs, so we want the bytes for our color format.
4381 * For our current usage, this is always 3, one byte for R, G and B.
4382 */
4383#define _PIPEA_DATA_M_G4X 0x70050
4384#define _PIPEB_DATA_M_G4X 0x71050
4385
4386/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
4387#define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */
4388#define TU_SIZE_SHIFT 25
4389#define TU_SIZE_MASK (0x3f << 25)
4390
4391#define DATA_LINK_M_N_MASK (0xffffff)
4392#define DATA_LINK_N_MAX (0x800000)
4393
4394#define _PIPEA_DATA_N_G4X 0x70054
4395#define _PIPEB_DATA_N_G4X 0x71054
4396#define PIPE_GMCH_DATA_N_MASK (0xffffff)
4397
4398/*
4399 * Computing Link M and N values for the Display Port link
4400 *
4401 * Link M / N = pixel_clock / ls_clk
4402 *
4403 * (the DP spec calls pixel_clock the 'strm_clk')
4404 *
4405 * The Link value is transmitted in the Main Stream
4406 * Attributes and VB-ID.
4407 */
4408
4409#define _PIPEA_LINK_M_G4X 0x70060
4410#define _PIPEB_LINK_M_G4X 0x71060
4411#define PIPEA_DP_LINK_M_MASK (0xffffff)
4412
4413#define _PIPEA_LINK_N_G4X 0x70064
4414#define _PIPEB_LINK_N_G4X 0x71064
4415#define PIPEA_DP_LINK_N_MASK (0xffffff)
4416
4417#define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
4418#define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
4419#define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)
4420#define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)
4421
4422/* Display & cursor control */
4423
4424/* Pipe A */
4425#define _PIPEADSL 0x70000
4426#define DSL_LINEMASK_GEN2 0x00000fff
4427#define DSL_LINEMASK_GEN3 0x00001fff
4428#define _PIPEACONF 0x70008
4429#define PIPECONF_ENABLE (1<<31)
4430#define PIPECONF_DISABLE 0
4431#define PIPECONF_DOUBLE_WIDE (1<<30)
4432#define I965_PIPECONF_ACTIVE (1<<30)
4433#define PIPECONF_DSI_PLL_LOCKED (1<<29) /* vlv & pipe A only */
4434#define PIPECONF_FRAME_START_DELAY_MASK (3<<27)
4435#define PIPECONF_SINGLE_WIDE 0
4436#define PIPECONF_PIPE_UNLOCKED 0
4437#define PIPECONF_PIPE_LOCKED (1<<25)
4438#define PIPECONF_PALETTE 0
4439#define PIPECONF_GAMMA (1<<24)
4440#define PIPECONF_FORCE_BORDER (1<<25)
4441#define PIPECONF_INTERLACE_MASK (7 << 21)
4442#define PIPECONF_INTERLACE_MASK_HSW (3 << 21)
4443/* Note that pre-gen3 does not support interlaced display directly. Panel
4444 * fitting must be disabled on pre-ilk for interlaced. */
4445#define PIPECONF_PROGRESSIVE (0 << 21)
4446#define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */
4447#define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */
4448#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
4449#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */
4450/* Ironlake and later have a complete new set of values for interlaced. PFIT
4451 * means panel fitter required, PF means progressive fetch, DBL means power
4452 * saving pixel doubling. */
4453#define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21)
4454#define PIPECONF_INTERLACED_ILK (3 << 21)
4455#define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */
4456#define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */
4457#define PIPECONF_INTERLACE_MODE_MASK (7 << 21)
4458#define PIPECONF_EDP_RR_MODE_SWITCH (1 << 20)
4459#define PIPECONF_CXSR_DOWNCLOCK (1<<16)
4460#define PIPECONF_EDP_RR_MODE_SWITCH_VLV (1 << 14)
4461#define PIPECONF_COLOR_RANGE_SELECT (1 << 13)
4462#define PIPECONF_BPC_MASK (0x7 << 5)
4463#define PIPECONF_8BPC (0<<5)
4464#define PIPECONF_10BPC (1<<5)
4465#define PIPECONF_6BPC (2<<5)
4466#define PIPECONF_12BPC (3<<5)
4467#define PIPECONF_DITHER_EN (1<<4)
4468#define PIPECONF_DITHER_TYPE_MASK (0x0000000c)
4469#define PIPECONF_DITHER_TYPE_SP (0<<2)
4470#define PIPECONF_DITHER_TYPE_ST1 (1<<2)
4471#define PIPECONF_DITHER_TYPE_ST2 (2<<2)
4472#define PIPECONF_DITHER_TYPE_TEMP (3<<2)
4473#define _PIPEASTAT 0x70024
4474#define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)
4475#define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL<<30)
4476#define PIPE_CRC_ERROR_ENABLE (1UL<<29)
4477#define PIPE_CRC_DONE_ENABLE (1UL<<28)
4478#define PERF_COUNTER2_INTERRUPT_EN (1UL<<27)
4479#define PIPE_GMBUS_EVENT_ENABLE (1UL<<27)
4480#define PLANE_FLIP_DONE_INT_EN_VLV (1UL<<26)
4481#define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26)
4482#define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25)
4483#define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
4484#define PIPE_DPST_EVENT_ENABLE (1UL<<23)
4485#define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL<<22)
4486#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
4487#define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
4488#define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
4489#define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL<<19)
4490#define PERF_COUNTER_INTERRUPT_EN (1UL<<19)
4491#define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */
4492#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
4493#define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL<<17)
4494#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17)
4495#define PIPEA_HBLANK_INT_EN_VLV (1UL<<16)
4496#define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16)
4497#define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL<<15)
4498#define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL<<14)
4499#define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
4500#define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
4501#define PERF_COUNTER2_INTERRUPT_STATUS (1UL<<11)
4502#define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11)
4503#define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL<<10)
4504#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10)
4505#define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9)
4506#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
4507#define PIPE_DPST_EVENT_STATUS (1UL<<7)
4508#define PIPE_A_PSR_STATUS_VLV (1UL<<6)
4509#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6)
4510#define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
4511#define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
4512#define PIPE_B_PSR_STATUS_VLV (1UL<<3)
4513#define PERF_COUNTER_INTERRUPT_STATUS (1UL<<3)
4514#define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */
4515#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
4516#define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL<<1)
4517#define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1)
4518#define PIPE_HBLANK_INT_STATUS (1UL<<0)
4519#define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0)
4520
4521#define PIPESTAT_INT_ENABLE_MASK 0x7fff0000
4522#define PIPESTAT_INT_STATUS_MASK 0x0000ffff
4523
4524#define PIPE_A_OFFSET 0x70000
4525#define PIPE_B_OFFSET 0x71000
4526#define PIPE_C_OFFSET 0x72000
4527#define CHV_PIPE_C_OFFSET 0x74000
4528/*
4529 * There's actually no pipe EDP. Some pipe registers have
4530 * simply shifted from the pipe to the transcoder, while
4531 * keeping their original offset. Thus we need PIPE_EDP_OFFSET
4532 * to access such registers in transcoder EDP.
4533 */
4534#define PIPE_EDP_OFFSET 0x7f000
4535
4536#define _MMIO_PIPE2(pipe, reg) _MMIO(dev_priv->info.pipe_offsets[pipe] - \
4537 dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
4538 dev_priv->info.display_mmio_offset)
4539
4540#define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF)
4541#define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL)
4542#define PIPEFRAME(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH)
4543#define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEPIXEL)
4544#define PIPESTAT(pipe) _MMIO_PIPE2(pipe, _PIPEASTAT)
4545
4546#define _PIPE_MISC_A 0x70030
4547#define _PIPE_MISC_B 0x71030
4548#define PIPEMISC_DITHER_BPC_MASK (7<<5)
4549#define PIPEMISC_DITHER_8_BPC (0<<5)
4550#define PIPEMISC_DITHER_10_BPC (1<<5)
4551#define PIPEMISC_DITHER_6_BPC (2<<5)
4552#define PIPEMISC_DITHER_12_BPC (3<<5)
4553#define PIPEMISC_DITHER_ENABLE (1<<4)
4554#define PIPEMISC_DITHER_TYPE_MASK (3<<2)
4555#define PIPEMISC_DITHER_TYPE_SP (0<<2)
4556#define PIPEMISC(pipe) _MMIO_PIPE2(pipe, _PIPE_MISC_A)
4557
4558#define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028)
4559#define PIPEB_LINE_COMPARE_INT_EN (1<<29)
4560#define PIPEB_HLINE_INT_EN (1<<28)
4561#define PIPEB_VBLANK_INT_EN (1<<27)
4562#define SPRITED_FLIP_DONE_INT_EN (1<<26)
4563#define SPRITEC_FLIP_DONE_INT_EN (1<<25)
4564#define PLANEB_FLIP_DONE_INT_EN (1<<24)
4565#define PIPE_PSR_INT_EN (1<<22)
4566#define PIPEA_LINE_COMPARE_INT_EN (1<<21)
4567#define PIPEA_HLINE_INT_EN (1<<20)
4568#define PIPEA_VBLANK_INT_EN (1<<19)
4569#define SPRITEB_FLIP_DONE_INT_EN (1<<18)
4570#define SPRITEA_FLIP_DONE_INT_EN (1<<17)
4571#define PLANEA_FLIPDONE_INT_EN (1<<16)
4572#define PIPEC_LINE_COMPARE_INT_EN (1<<13)
4573#define PIPEC_HLINE_INT_EN (1<<12)
4574#define PIPEC_VBLANK_INT_EN (1<<11)
4575#define SPRITEF_FLIPDONE_INT_EN (1<<10)
4576#define SPRITEE_FLIPDONE_INT_EN (1<<9)
4577#define PLANEC_FLIPDONE_INT_EN (1<<8)
4578
4579#define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
4580#define SPRITEF_INVALID_GTT_INT_EN (1<<27)
4581#define SPRITEE_INVALID_GTT_INT_EN (1<<26)
4582#define PLANEC_INVALID_GTT_INT_EN (1<<25)
4583#define CURSORC_INVALID_GTT_INT_EN (1<<24)
4584#define CURSORB_INVALID_GTT_INT_EN (1<<23)
4585#define CURSORA_INVALID_GTT_INT_EN (1<<22)
4586#define SPRITED_INVALID_GTT_INT_EN (1<<21)
4587#define SPRITEC_INVALID_GTT_INT_EN (1<<20)
4588#define PLANEB_INVALID_GTT_INT_EN (1<<19)
4589#define SPRITEB_INVALID_GTT_INT_EN (1<<18)
4590#define SPRITEA_INVALID_GTT_INT_EN (1<<17)
4591#define PLANEA_INVALID_GTT_INT_EN (1<<16)
4592#define DPINVGTT_EN_MASK 0xff0000
4593#define DPINVGTT_EN_MASK_CHV 0xfff0000
4594#define SPRITEF_INVALID_GTT_STATUS (1<<11)
4595#define SPRITEE_INVALID_GTT_STATUS (1<<10)
4596#define PLANEC_INVALID_GTT_STATUS (1<<9)
4597#define CURSORC_INVALID_GTT_STATUS (1<<8)
4598#define CURSORB_INVALID_GTT_STATUS (1<<7)
4599#define CURSORA_INVALID_GTT_STATUS (1<<6)
4600#define SPRITED_INVALID_GTT_STATUS (1<<5)
4601#define SPRITEC_INVALID_GTT_STATUS (1<<4)
4602#define PLANEB_INVALID_GTT_STATUS (1<<3)
4603#define SPRITEB_INVALID_GTT_STATUS (1<<2)
4604#define SPRITEA_INVALID_GTT_STATUS (1<<1)
4605#define PLANEA_INVALID_GTT_STATUS (1<<0)
4606#define DPINVGTT_STATUS_MASK 0xff
4607#define DPINVGTT_STATUS_MASK_CHV 0xfff
4608
4609#define DSPARB _MMIO(dev_priv->info.display_mmio_offset + 0x70030)
4610#define DSPARB_CSTART_MASK (0x7f << 7)
4611#define DSPARB_CSTART_SHIFT 7
4612#define DSPARB_BSTART_MASK (0x7f)
4613#define DSPARB_BSTART_SHIFT 0
4614#define DSPARB_BEND_SHIFT 9 /* on 855 */
4615#define DSPARB_AEND_SHIFT 0
4616#define DSPARB_SPRITEA_SHIFT_VLV 0
4617#define DSPARB_SPRITEA_MASK_VLV (0xff << 0)
4618#define DSPARB_SPRITEB_SHIFT_VLV 8
4619#define DSPARB_SPRITEB_MASK_VLV (0xff << 8)
4620#define DSPARB_SPRITEC_SHIFT_VLV 16
4621#define DSPARB_SPRITEC_MASK_VLV (0xff << 16)
4622#define DSPARB_SPRITED_SHIFT_VLV 24
4623#define DSPARB_SPRITED_MASK_VLV (0xff << 24)
4624#define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */
4625#define DSPARB_SPRITEA_HI_SHIFT_VLV 0
4626#define DSPARB_SPRITEA_HI_MASK_VLV (0x1 << 0)
4627#define DSPARB_SPRITEB_HI_SHIFT_VLV 4
4628#define DSPARB_SPRITEB_HI_MASK_VLV (0x1 << 4)
4629#define DSPARB_SPRITEC_HI_SHIFT_VLV 8
4630#define DSPARB_SPRITEC_HI_MASK_VLV (0x1 << 8)
4631#define DSPARB_SPRITED_HI_SHIFT_VLV 12
4632#define DSPARB_SPRITED_HI_MASK_VLV (0x1 << 12)
4633#define DSPARB_SPRITEE_HI_SHIFT_VLV 16
4634#define DSPARB_SPRITEE_HI_MASK_VLV (0x1 << 16)
4635#define DSPARB_SPRITEF_HI_SHIFT_VLV 20
4636#define DSPARB_SPRITEF_HI_MASK_VLV (0x1 << 20)
4637#define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */
4638#define DSPARB_SPRITEE_SHIFT_VLV 0
4639#define DSPARB_SPRITEE_MASK_VLV (0xff << 0)
4640#define DSPARB_SPRITEF_SHIFT_VLV 8
4641#define DSPARB_SPRITEF_MASK_VLV (0xff << 8)
4642
4643/* pnv/gen4/g4x/vlv/chv */
4644#define DSPFW1 _MMIO(dev_priv->info.display_mmio_offset + 0x70034)
4645#define DSPFW_SR_SHIFT 23
4646#define DSPFW_SR_MASK (0x1ff<<23)
4647#define DSPFW_CURSORB_SHIFT 16
4648#define DSPFW_CURSORB_MASK (0x3f<<16)
4649#define DSPFW_PLANEB_SHIFT 8
4650#define DSPFW_PLANEB_MASK (0x7f<<8)
4651#define DSPFW_PLANEB_MASK_VLV (0xff<<8) /* vlv/chv */
4652#define DSPFW_PLANEA_SHIFT 0
4653#define DSPFW_PLANEA_MASK (0x7f<<0)
4654#define DSPFW_PLANEA_MASK_VLV (0xff<<0) /* vlv/chv */
4655#define DSPFW2 _MMIO(dev_priv->info.display_mmio_offset + 0x70038)
4656#define DSPFW_FBC_SR_EN (1<<31) /* g4x */
4657#define DSPFW_FBC_SR_SHIFT 28
4658#define DSPFW_FBC_SR_MASK (0x7<<28) /* g4x */
4659#define DSPFW_FBC_HPLL_SR_SHIFT 24
4660#define DSPFW_FBC_HPLL_SR_MASK (0xf<<24) /* g4x */
4661#define DSPFW_SPRITEB_SHIFT (16)
4662#define DSPFW_SPRITEB_MASK (0x7f<<16) /* g4x */
4663#define DSPFW_SPRITEB_MASK_VLV (0xff<<16) /* vlv/chv */
4664#define DSPFW_CURSORA_SHIFT 8
4665#define DSPFW_CURSORA_MASK (0x3f<<8)
4666#define DSPFW_PLANEC_OLD_SHIFT 0
4667#define DSPFW_PLANEC_OLD_MASK (0x7f<<0) /* pre-gen4 sprite C */
4668#define DSPFW_SPRITEA_SHIFT 0
4669#define DSPFW_SPRITEA_MASK (0x7f<<0) /* g4x */
4670#define DSPFW_SPRITEA_MASK_VLV (0xff<<0) /* vlv/chv */
4671#define DSPFW3 _MMIO(dev_priv->info.display_mmio_offset + 0x7003c)
4672#define DSPFW_HPLL_SR_EN (1<<31)
4673#define PINEVIEW_SELF_REFRESH_EN (1<<30)
4674#define DSPFW_CURSOR_SR_SHIFT 24
4675#define DSPFW_CURSOR_SR_MASK (0x3f<<24)
4676#define DSPFW_HPLL_CURSOR_SHIFT 16
4677#define DSPFW_HPLL_CURSOR_MASK (0x3f<<16)
4678#define DSPFW_HPLL_SR_SHIFT 0
4679#define DSPFW_HPLL_SR_MASK (0x1ff<<0)
4680
4681/* vlv/chv */
4682#define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070)
4683#define DSPFW_SPRITEB_WM1_SHIFT 16
4684#define DSPFW_SPRITEB_WM1_MASK (0xff<<16)
4685#define DSPFW_CURSORA_WM1_SHIFT 8
4686#define DSPFW_CURSORA_WM1_MASK (0x3f<<8)
4687#define DSPFW_SPRITEA_WM1_SHIFT 0
4688#define DSPFW_SPRITEA_WM1_MASK (0xff<<0)
4689#define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074)
4690#define DSPFW_PLANEB_WM1_SHIFT 24
4691#define DSPFW_PLANEB_WM1_MASK (0xff<<24)
4692#define DSPFW_PLANEA_WM1_SHIFT 16
4693#define DSPFW_PLANEA_WM1_MASK (0xff<<16)
4694#define DSPFW_CURSORB_WM1_SHIFT 8
4695#define DSPFW_CURSORB_WM1_MASK (0x3f<<8)
4696#define DSPFW_CURSOR_SR_WM1_SHIFT 0
4697#define DSPFW_CURSOR_SR_WM1_MASK (0x3f<<0)
4698#define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078)
4699#define DSPFW_SR_WM1_SHIFT 0
4700#define DSPFW_SR_WM1_MASK (0x1ff<<0)
4701#define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c)
4702#define DSPFW7_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
4703#define DSPFW_SPRITED_WM1_SHIFT 24
4704#define DSPFW_SPRITED_WM1_MASK (0xff<<24)
4705#define DSPFW_SPRITED_SHIFT 16
4706#define DSPFW_SPRITED_MASK_VLV (0xff<<16)
4707#define DSPFW_SPRITEC_WM1_SHIFT 8
4708#define DSPFW_SPRITEC_WM1_MASK (0xff<<8)
4709#define DSPFW_SPRITEC_SHIFT 0
4710#define DSPFW_SPRITEC_MASK_VLV (0xff<<0)
4711#define DSPFW8_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b8)
4712#define DSPFW_SPRITEF_WM1_SHIFT 24
4713#define DSPFW_SPRITEF_WM1_MASK (0xff<<24)
4714#define DSPFW_SPRITEF_SHIFT 16
4715#define DSPFW_SPRITEF_MASK_VLV (0xff<<16)
4716#define DSPFW_SPRITEE_WM1_SHIFT 8
4717#define DSPFW_SPRITEE_WM1_MASK (0xff<<8)
4718#define DSPFW_SPRITEE_SHIFT 0
4719#define DSPFW_SPRITEE_MASK_VLV (0xff<<0)
4720#define DSPFW9_CHV _MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
4721#define DSPFW_PLANEC_WM1_SHIFT 24
4722#define DSPFW_PLANEC_WM1_MASK (0xff<<24)
4723#define DSPFW_PLANEC_SHIFT 16
4724#define DSPFW_PLANEC_MASK_VLV (0xff<<16)
4725#define DSPFW_CURSORC_WM1_SHIFT 8
4726#define DSPFW_CURSORC_WM1_MASK (0x3f<<16)
4727#define DSPFW_CURSORC_SHIFT 0
4728#define DSPFW_CURSORC_MASK (0x3f<<0)
4729
4730/* vlv/chv high order bits */
4731#define DSPHOWM _MMIO(VLV_DISPLAY_BASE + 0x70064)
4732#define DSPFW_SR_HI_SHIFT 24
4733#define DSPFW_SR_HI_MASK (3<<24) /* 2 bits for chv, 1 for vlv */
4734#define DSPFW_SPRITEF_HI_SHIFT 23
4735#define DSPFW_SPRITEF_HI_MASK (1<<23)
4736#define DSPFW_SPRITEE_HI_SHIFT 22
4737#define DSPFW_SPRITEE_HI_MASK (1<<22)
4738#define DSPFW_PLANEC_HI_SHIFT 21
4739#define DSPFW_PLANEC_HI_MASK (1<<21)
4740#define DSPFW_SPRITED_HI_SHIFT 20
4741#define DSPFW_SPRITED_HI_MASK (1<<20)
4742#define DSPFW_SPRITEC_HI_SHIFT 16
4743#define DSPFW_SPRITEC_HI_MASK (1<<16)
4744#define DSPFW_PLANEB_HI_SHIFT 12
4745#define DSPFW_PLANEB_HI_MASK (1<<12)
4746#define DSPFW_SPRITEB_HI_SHIFT 8
4747#define DSPFW_SPRITEB_HI_MASK (1<<8)
4748#define DSPFW_SPRITEA_HI_SHIFT 4
4749#define DSPFW_SPRITEA_HI_MASK (1<<4)
4750#define DSPFW_PLANEA_HI_SHIFT 0
4751#define DSPFW_PLANEA_HI_MASK (1<<0)
4752#define DSPHOWM1 _MMIO(VLV_DISPLAY_BASE + 0x70068)
4753#define DSPFW_SR_WM1_HI_SHIFT 24
4754#define DSPFW_SR_WM1_HI_MASK (3<<24) /* 2 bits for chv, 1 for vlv */
4755#define DSPFW_SPRITEF_WM1_HI_SHIFT 23
4756#define DSPFW_SPRITEF_WM1_HI_MASK (1<<23)
4757#define DSPFW_SPRITEE_WM1_HI_SHIFT 22
4758#define DSPFW_SPRITEE_WM1_HI_MASK (1<<22)
4759#define DSPFW_PLANEC_WM1_HI_SHIFT 21
4760#define DSPFW_PLANEC_WM1_HI_MASK (1<<21)
4761#define DSPFW_SPRITED_WM1_HI_SHIFT 20
4762#define DSPFW_SPRITED_WM1_HI_MASK (1<<20)
4763#define DSPFW_SPRITEC_WM1_HI_SHIFT 16
4764#define DSPFW_SPRITEC_WM1_HI_MASK (1<<16)
4765#define DSPFW_PLANEB_WM1_HI_SHIFT 12
4766#define DSPFW_PLANEB_WM1_HI_MASK (1<<12)
4767#define DSPFW_SPRITEB_WM1_HI_SHIFT 8
4768#define DSPFW_SPRITEB_WM1_HI_MASK (1<<8)
4769#define DSPFW_SPRITEA_WM1_HI_SHIFT 4
4770#define DSPFW_SPRITEA_WM1_HI_MASK (1<<4)
4771#define DSPFW_PLANEA_WM1_HI_SHIFT 0
4772#define DSPFW_PLANEA_WM1_HI_MASK (1<<0)
4773
4774/* drain latency register values*/
4775#define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
4776#define DDL_CURSOR_SHIFT 24
4777#define DDL_SPRITE_SHIFT(sprite) (8+8*(sprite))
4778#define DDL_PLANE_SHIFT 0
4779#define DDL_PRECISION_HIGH (1<<7)
4780#define DDL_PRECISION_LOW (0<<7)
4781#define DRAIN_LATENCY_MASK 0x7f
4782
4783#define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400)
4784#define CBR_PND_DEADLINE_DISABLE (1<<31)
4785#define CBR_PWM_CLOCK_MUX_SELECT (1<<30)
4786
4787/* FIFO watermark sizes etc */
4788#define G4X_FIFO_LINE_SIZE 64
4789#define I915_FIFO_LINE_SIZE 64
4790#define I830_FIFO_LINE_SIZE 32
4791
4792#define VALLEYVIEW_FIFO_SIZE 255
4793#define G4X_FIFO_SIZE 127
4794#define I965_FIFO_SIZE 512
4795#define I945_FIFO_SIZE 127
4796#define I915_FIFO_SIZE 95
4797#define I855GM_FIFO_SIZE 127 /* In cachelines */
4798#define I830_FIFO_SIZE 95
4799
4800#define VALLEYVIEW_MAX_WM 0xff
4801#define G4X_MAX_WM 0x3f
4802#define I915_MAX_WM 0x3f
4803
4804#define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */
4805#define PINEVIEW_FIFO_LINE_SIZE 64
4806#define PINEVIEW_MAX_WM 0x1ff
4807#define PINEVIEW_DFT_WM 0x3f
4808#define PINEVIEW_DFT_HPLLOFF_WM 0
4809#define PINEVIEW_GUARD_WM 10
4810#define PINEVIEW_CURSOR_FIFO 64
4811#define PINEVIEW_CURSOR_MAX_WM 0x3f
4812#define PINEVIEW_CURSOR_DFT_WM 0
4813#define PINEVIEW_CURSOR_GUARD_WM 5
4814
4815#define VALLEYVIEW_CURSOR_MAX_WM 64
4816#define I965_CURSOR_FIFO 64
4817#define I965_CURSOR_MAX_WM 32
4818#define I965_CURSOR_DFT_WM 8
4819
4820/* Watermark register definitions for SKL */
4821#define _CUR_WM_A_0 0x70140
4822#define _CUR_WM_B_0 0x71140
4823#define _PLANE_WM_1_A_0 0x70240
4824#define _PLANE_WM_1_B_0 0x71240
4825#define _PLANE_WM_2_A_0 0x70340
4826#define _PLANE_WM_2_B_0 0x71340
4827#define _PLANE_WM_TRANS_1_A_0 0x70268
4828#define _PLANE_WM_TRANS_1_B_0 0x71268
4829#define _PLANE_WM_TRANS_2_A_0 0x70368
4830#define _PLANE_WM_TRANS_2_B_0 0x71368
4831#define _CUR_WM_TRANS_A_0 0x70168
4832#define _CUR_WM_TRANS_B_0 0x71168
4833#define PLANE_WM_EN (1 << 31)
4834#define PLANE_WM_LINES_SHIFT 14
4835#define PLANE_WM_LINES_MASK 0x1f
4836#define PLANE_WM_BLOCKS_MASK 0x3ff
4837
4838#define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
4839#define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level)))
4840#define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A_0, _CUR_WM_TRANS_B_0)
4841
4842#define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0)
4843#define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
4844#define _PLANE_WM_BASE(pipe, plane) \
4845 _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
4846#define PLANE_WM(pipe, plane, level) \
4847 _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
4848#define _PLANE_WM_TRANS_1(pipe) \
4849 _PIPE(pipe, _PLANE_WM_TRANS_1_A_0, _PLANE_WM_TRANS_1_B_0)
4850#define _PLANE_WM_TRANS_2(pipe) \
4851 _PIPE(pipe, _PLANE_WM_TRANS_2_A_0, _PLANE_WM_TRANS_2_B_0)
4852#define PLANE_WM_TRANS(pipe, plane) \
4853 _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
4854
4855/* define the Watermark register on Ironlake */
4856#define WM0_PIPEA_ILK _MMIO(0x45100)
4857#define WM0_PIPE_PLANE_MASK (0xffff<<16)
4858#define WM0_PIPE_PLANE_SHIFT 16
4859#define WM0_PIPE_SPRITE_MASK (0xff<<8)
4860#define WM0_PIPE_SPRITE_SHIFT 8
4861#define WM0_PIPE_CURSOR_MASK (0xff)
4862
4863#define WM0_PIPEB_ILK _MMIO(0x45104)
4864#define WM0_PIPEC_IVB _MMIO(0x45200)
4865#define WM1_LP_ILK _MMIO(0x45108)
4866#define WM1_LP_SR_EN (1<<31)
4867#define WM1_LP_LATENCY_SHIFT 24
4868#define WM1_LP_LATENCY_MASK (0x7f<<24)
4869#define WM1_LP_FBC_MASK (0xf<<20)
4870#define WM1_LP_FBC_SHIFT 20
4871#define WM1_LP_FBC_SHIFT_BDW 19
4872#define WM1_LP_SR_MASK (0x7ff<<8)
4873#define WM1_LP_SR_SHIFT 8
4874#define WM1_LP_CURSOR_MASK (0xff)
4875#define WM2_LP_ILK _MMIO(0x4510c)
4876#define WM2_LP_EN (1<<31)
4877#define WM3_LP_ILK _MMIO(0x45110)
4878#define WM3_LP_EN (1<<31)
4879#define WM1S_LP_ILK _MMIO(0x45120)
4880#define WM2S_LP_IVB _MMIO(0x45124)
4881#define WM3S_LP_IVB _MMIO(0x45128)
4882#define WM1S_LP_EN (1<<31)
4883
4884#define HSW_WM_LP_VAL(lat, fbc, pri, cur) \
4885 (WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \
4886 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur))
4887
4888/* Memory latency timer register */
4889#define MLTR_ILK _MMIO(0x11222)
4890#define MLTR_WM1_SHIFT 0
4891#define MLTR_WM2_SHIFT 8
4892/* the unit of memory self-refresh latency time is 0.5us */
4893#define ILK_SRLT_MASK 0x3f
4894
4895
4896/* the address where we get all kinds of latency value */
4897#define SSKPD _MMIO(0x5d10)
4898#define SSKPD_WM_MASK 0x3f
4899#define SSKPD_WM0_SHIFT 0
4900#define SSKPD_WM1_SHIFT 8
4901#define SSKPD_WM2_SHIFT 16
4902#define SSKPD_WM3_SHIFT 24
4903
4904/*
4905 * The two pipe frame counter registers are not synchronized, so
4906 * reading a stable value is somewhat tricky. The following code
4907 * should work:
4908 *
4909 * do {
4910 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
4911 * PIPE_FRAME_HIGH_SHIFT;
4912 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
4913 * PIPE_FRAME_LOW_SHIFT);
4914 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
4915 * PIPE_FRAME_HIGH_SHIFT);
4916 * } while (high1 != high2);
4917 * frame = (high1 << 8) | low1;
4918 */
4919#define _PIPEAFRAMEHIGH 0x70040
4920#define PIPE_FRAME_HIGH_MASK 0x0000ffff
4921#define PIPE_FRAME_HIGH_SHIFT 0
4922#define _PIPEAFRAMEPIXEL 0x70044
4923#define PIPE_FRAME_LOW_MASK 0xff000000
4924#define PIPE_FRAME_LOW_SHIFT 24
4925#define PIPE_PIXEL_MASK 0x00ffffff
4926#define PIPE_PIXEL_SHIFT 0
4927/* GM45+ just has to be different */
4928#define _PIPEA_FRMCOUNT_G4X 0x70040
4929#define _PIPEA_FLIPCOUNT_G4X 0x70044
4930#define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FRMCOUNT_G4X)
4931#define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X)
4932
4933/* Cursor A & B regs */
4934#define _CURACNTR 0x70080
4935/* Old style CUR*CNTR flags (desktop 8xx) */
4936#define CURSOR_ENABLE 0x80000000
4937#define CURSOR_GAMMA_ENABLE 0x40000000
4938#define CURSOR_STRIDE_SHIFT 28
4939#define CURSOR_STRIDE(x) ((ffs(x)-9) << CURSOR_STRIDE_SHIFT) /* 256,512,1k,2k */
4940#define CURSOR_PIPE_CSC_ENABLE (1<<24)
4941#define CURSOR_FORMAT_SHIFT 24
4942#define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT)
4943#define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT)
4944#define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT)
4945#define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT)
4946#define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT)
4947#define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT)
4948/* New style CUR*CNTR flags */
4949#define CURSOR_MODE 0x27
4950#define CURSOR_MODE_DISABLE 0x00
4951#define CURSOR_MODE_128_32B_AX 0x02
4952#define CURSOR_MODE_256_32B_AX 0x03
4953#define CURSOR_MODE_64_32B_AX 0x07
4954#define CURSOR_MODE_128_ARGB_AX ((1 << 5) | CURSOR_MODE_128_32B_AX)
4955#define CURSOR_MODE_256_ARGB_AX ((1 << 5) | CURSOR_MODE_256_32B_AX)
4956#define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
4957#define MCURSOR_PIPE_SELECT (1 << 28)
4958#define MCURSOR_PIPE_A 0x00
4959#define MCURSOR_PIPE_B (1 << 28)
4960#define MCURSOR_GAMMA_ENABLE (1 << 26)
4961#define CURSOR_ROTATE_180 (1<<15)
4962#define CURSOR_TRICKLE_FEED_DISABLE (1 << 14)
4963#define _CURABASE 0x70084
4964#define _CURAPOS 0x70088
4965#define CURSOR_POS_MASK 0x007FF
4966#define CURSOR_POS_SIGN 0x8000
4967#define CURSOR_X_SHIFT 0
4968#define CURSOR_Y_SHIFT 16
4969#define CURSIZE _MMIO(0x700a0)
4970#define _CURBCNTR 0x700c0
4971#define _CURBBASE 0x700c4
4972#define _CURBPOS 0x700c8
4973
4974#define _CURBCNTR_IVB 0x71080
4975#define _CURBBASE_IVB 0x71084
4976#define _CURBPOS_IVB 0x71088
4977
4978#define _CURSOR2(pipe, reg) _MMIO(dev_priv->info.cursor_offsets[(pipe)] - \
4979 dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \
4980 dev_priv->info.display_mmio_offset)
4981
4982#define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR)
4983#define CURBASE(pipe) _CURSOR2(pipe, _CURABASE)
4984#define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS)
4985
4986#define CURSOR_A_OFFSET 0x70080
4987#define CURSOR_B_OFFSET 0x700c0
4988#define CHV_CURSOR_C_OFFSET 0x700e0
4989#define IVB_CURSOR_B_OFFSET 0x71080
4990#define IVB_CURSOR_C_OFFSET 0x72080
4991
4992/* Display A control */
4993#define _DSPACNTR 0x70180
4994#define DISPLAY_PLANE_ENABLE (1<<31)
4995#define DISPLAY_PLANE_DISABLE 0
4996#define DISPPLANE_GAMMA_ENABLE (1<<30)
4997#define DISPPLANE_GAMMA_DISABLE 0
4998#define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
4999#define DISPPLANE_YUV422 (0x0<<26)
5000#define DISPPLANE_8BPP (0x2<<26)
5001#define DISPPLANE_BGRA555 (0x3<<26)
5002#define DISPPLANE_BGRX555 (0x4<<26)
5003#define DISPPLANE_BGRX565 (0x5<<26)
5004#define DISPPLANE_BGRX888 (0x6<<26)
5005#define DISPPLANE_BGRA888 (0x7<<26)
5006#define DISPPLANE_RGBX101010 (0x8<<26)
5007#define DISPPLANE_RGBA101010 (0x9<<26)
5008#define DISPPLANE_BGRX101010 (0xa<<26)
5009#define DISPPLANE_RGBX161616 (0xc<<26)
5010#define DISPPLANE_RGBX888 (0xe<<26)
5011#define DISPPLANE_RGBA888 (0xf<<26)
5012#define DISPPLANE_STEREO_ENABLE (1<<25)
5013#define DISPPLANE_STEREO_DISABLE 0
5014#define DISPPLANE_PIPE_CSC_ENABLE (1<<24)
5015#define DISPPLANE_SEL_PIPE_SHIFT 24
5016#define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT)
5017#define DISPPLANE_SEL_PIPE_A 0
5018#define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT)
5019#define DISPPLANE_SRC_KEY_ENABLE (1<<22)
5020#define DISPPLANE_SRC_KEY_DISABLE 0
5021#define DISPPLANE_LINE_DOUBLE (1<<20)
5022#define DISPPLANE_NO_LINE_DOUBLE 0
5023#define DISPPLANE_STEREO_POLARITY_FIRST 0
5024#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
5025#define DISPPLANE_ALPHA_PREMULTIPLY (1<<16) /* CHV pipe B */
5026#define DISPPLANE_ROTATE_180 (1<<15)
5027#define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */
5028#define DISPPLANE_TILED (1<<10)
5029#define DISPPLANE_MIRROR (1<<8) /* CHV pipe B */
5030#define _DSPAADDR 0x70184
5031#define _DSPASTRIDE 0x70188
5032#define _DSPAPOS 0x7018C /* reserved */
5033#define _DSPASIZE 0x70190
5034#define _DSPASURF 0x7019C /* 965+ only */
5035#define _DSPATILEOFF 0x701A4 /* 965+ only */
5036#define _DSPAOFFSET 0x701A4 /* HSW */
5037#define _DSPASURFLIVE 0x701AC
5038
5039#define DSPCNTR(plane) _MMIO_PIPE2(plane, _DSPACNTR)
5040#define DSPADDR(plane) _MMIO_PIPE2(plane, _DSPAADDR)
5041#define DSPSTRIDE(plane) _MMIO_PIPE2(plane, _DSPASTRIDE)
5042#define DSPPOS(plane) _MMIO_PIPE2(plane, _DSPAPOS)
5043#define DSPSIZE(plane) _MMIO_PIPE2(plane, _DSPASIZE)
5044#define DSPSURF(plane) _MMIO_PIPE2(plane, _DSPASURF)
5045#define DSPTILEOFF(plane) _MMIO_PIPE2(plane, _DSPATILEOFF)
5046#define DSPLINOFF(plane) DSPADDR(plane)
5047#define DSPOFFSET(plane) _MMIO_PIPE2(plane, _DSPAOFFSET)
5048#define DSPSURFLIVE(plane) _MMIO_PIPE2(plane, _DSPASURFLIVE)
5049
5050/* CHV pipe B blender and primary plane */
5051#define _CHV_BLEND_A 0x60a00
5052#define CHV_BLEND_LEGACY (0<<30)
5053#define CHV_BLEND_ANDROID (1<<30)
5054#define CHV_BLEND_MPO (2<<30)
5055#define CHV_BLEND_MASK (3<<30)
5056#define _CHV_CANVAS_A 0x60a04
5057#define _PRIMPOS_A 0x60a08
5058#define _PRIMSIZE_A 0x60a0c
5059#define _PRIMCNSTALPHA_A 0x60a10
5060#define PRIM_CONST_ALPHA_ENABLE (1<<31)
5061
5062#define CHV_BLEND(pipe) _MMIO_TRANS2(pipe, _CHV_BLEND_A)
5063#define CHV_CANVAS(pipe) _MMIO_TRANS2(pipe, _CHV_CANVAS_A)
5064#define PRIMPOS(plane) _MMIO_TRANS2(plane, _PRIMPOS_A)
5065#define PRIMSIZE(plane) _MMIO_TRANS2(plane, _PRIMSIZE_A)
5066#define PRIMCNSTALPHA(plane) _MMIO_TRANS2(plane, _PRIMCNSTALPHA_A)
5067
5068/* Display/Sprite base address macros */
5069#define DISP_BASEADDR_MASK (0xfffff000)
5070#define I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK)
5071#define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK)
5072
5073/*
5074 * VBIOS flags
5075 * gen2:
5076 * [00:06] alm,mgm
5077 * [10:16] all
5078 * [30:32] alm,mgm
5079 * gen3+:
5080 * [00:0f] all
5081 * [10:1f] all
5082 * [30:32] all
5083 */
5084#define SWF0(i) _MMIO(dev_priv->info.display_mmio_offset + 0x70410 + (i) * 4)
5085#define SWF1(i) _MMIO(dev_priv->info.display_mmio_offset + 0x71410 + (i) * 4)
5086#define SWF3(i) _MMIO(dev_priv->info.display_mmio_offset + 0x72414 + (i) * 4)
5087#define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4)
5088
5089/* Pipe B */
5090#define _PIPEBDSL (dev_priv->info.display_mmio_offset + 0x71000)
5091#define _PIPEBCONF (dev_priv->info.display_mmio_offset + 0x71008)
5092#define _PIPEBSTAT (dev_priv->info.display_mmio_offset + 0x71024)
5093#define _PIPEBFRAMEHIGH 0x71040
5094#define _PIPEBFRAMEPIXEL 0x71044
5095#define _PIPEB_FRMCOUNT_G4X (dev_priv->info.display_mmio_offset + 0x71040)
5096#define _PIPEB_FLIPCOUNT_G4X (dev_priv->info.display_mmio_offset + 0x71044)
5097
5098
5099/* Display B control */
5100#define _DSPBCNTR (dev_priv->info.display_mmio_offset + 0x71180)
5101#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
5102#define DISPPLANE_ALPHA_TRANS_DISABLE 0
5103#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
5104#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
5105#define _DSPBADDR (dev_priv->info.display_mmio_offset + 0x71184)
5106#define _DSPBSTRIDE (dev_priv->info.display_mmio_offset + 0x71188)
5107#define _DSPBPOS (dev_priv->info.display_mmio_offset + 0x7118C)
5108#define _DSPBSIZE (dev_priv->info.display_mmio_offset + 0x71190)
5109#define _DSPBSURF (dev_priv->info.display_mmio_offset + 0x7119C)
5110#define _DSPBTILEOFF (dev_priv->info.display_mmio_offset + 0x711A4)
5111#define _DSPBOFFSET (dev_priv->info.display_mmio_offset + 0x711A4)
5112#define _DSPBSURFLIVE (dev_priv->info.display_mmio_offset + 0x711AC)
5113
5114/* Sprite A control */
5115#define _DVSACNTR 0x72180
5116#define DVS_ENABLE (1<<31)
5117#define DVS_GAMMA_ENABLE (1<<30)
5118#define DVS_PIXFORMAT_MASK (3<<25)
5119#define DVS_FORMAT_YUV422 (0<<25)
5120#define DVS_FORMAT_RGBX101010 (1<<25)
5121#define DVS_FORMAT_RGBX888 (2<<25)
5122#define DVS_FORMAT_RGBX161616 (3<<25)
5123#define DVS_PIPE_CSC_ENABLE (1<<24)
5124#define DVS_SOURCE_KEY (1<<22)
5125#define DVS_RGB_ORDER_XBGR (1<<20)
5126#define DVS_YUV_BYTE_ORDER_MASK (3<<16)
5127#define DVS_YUV_ORDER_YUYV (0<<16)
5128#define DVS_YUV_ORDER_UYVY (1<<16)
5129#define DVS_YUV_ORDER_YVYU (2<<16)
5130#define DVS_YUV_ORDER_VYUY (3<<16)
5131#define DVS_ROTATE_180 (1<<15)
5132#define DVS_DEST_KEY (1<<2)
5133#define DVS_TRICKLE_FEED_DISABLE (1<<14)
5134#define DVS_TILED (1<<10)
5135#define _DVSALINOFF 0x72184
5136#define _DVSASTRIDE 0x72188
5137#define _DVSAPOS 0x7218c
5138#define _DVSASIZE 0x72190
5139#define _DVSAKEYVAL 0x72194
5140#define _DVSAKEYMSK 0x72198
5141#define _DVSASURF 0x7219c
5142#define _DVSAKEYMAXVAL 0x721a0
5143#define _DVSATILEOFF 0x721a4
5144#define _DVSASURFLIVE 0x721ac
5145#define _DVSASCALE 0x72204
5146#define DVS_SCALE_ENABLE (1<<31)
5147#define DVS_FILTER_MASK (3<<29)
5148#define DVS_FILTER_MEDIUM (0<<29)
5149#define DVS_FILTER_ENHANCING (1<<29)
5150#define DVS_FILTER_SOFTENING (2<<29)
5151#define DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
5152#define DVS_VERTICAL_OFFSET_ENABLE (1<<27)
5153#define _DVSAGAMC 0x72300
5154
5155#define _DVSBCNTR 0x73180
5156#define _DVSBLINOFF 0x73184
5157#define _DVSBSTRIDE 0x73188
5158#define _DVSBPOS 0x7318c
5159#define _DVSBSIZE 0x73190
5160#define _DVSBKEYVAL 0x73194
5161#define _DVSBKEYMSK 0x73198
5162#define _DVSBSURF 0x7319c
5163#define _DVSBKEYMAXVAL 0x731a0
5164#define _DVSBTILEOFF 0x731a4
5165#define _DVSBSURFLIVE 0x731ac
5166#define _DVSBSCALE 0x73204
5167#define _DVSBGAMC 0x73300
5168
5169#define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR)
5170#define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
5171#define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
5172#define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS)
5173#define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF)
5174#define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
5175#define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE)
5176#define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE)
5177#define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
5178#define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
5179#define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
5180#define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
5181
5182#define _SPRA_CTL 0x70280
5183#define SPRITE_ENABLE (1<<31)
5184#define SPRITE_GAMMA_ENABLE (1<<30)
5185#define SPRITE_PIXFORMAT_MASK (7<<25)
5186#define SPRITE_FORMAT_YUV422 (0<<25)
5187#define SPRITE_FORMAT_RGBX101010 (1<<25)
5188#define SPRITE_FORMAT_RGBX888 (2<<25)
5189#define SPRITE_FORMAT_RGBX161616 (3<<25)
5190#define SPRITE_FORMAT_YUV444 (4<<25)
5191#define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */
5192#define SPRITE_PIPE_CSC_ENABLE (1<<24)
5193#define SPRITE_SOURCE_KEY (1<<22)
5194#define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */
5195#define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19)
5196#define SPRITE_YUV_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */
5197#define SPRITE_YUV_BYTE_ORDER_MASK (3<<16)
5198#define SPRITE_YUV_ORDER_YUYV (0<<16)
5199#define SPRITE_YUV_ORDER_UYVY (1<<16)
5200#define SPRITE_YUV_ORDER_YVYU (2<<16)
5201#define SPRITE_YUV_ORDER_VYUY (3<<16)
5202#define SPRITE_ROTATE_180 (1<<15)
5203#define SPRITE_TRICKLE_FEED_DISABLE (1<<14)
5204#define SPRITE_INT_GAMMA_ENABLE (1<<13)
5205#define SPRITE_TILED (1<<10)
5206#define SPRITE_DEST_KEY (1<<2)
5207#define _SPRA_LINOFF 0x70284
5208#define _SPRA_STRIDE 0x70288
5209#define _SPRA_POS 0x7028c
5210#define _SPRA_SIZE 0x70290
5211#define _SPRA_KEYVAL 0x70294
5212#define _SPRA_KEYMSK 0x70298
5213#define _SPRA_SURF 0x7029c
5214#define _SPRA_KEYMAX 0x702a0
5215#define _SPRA_TILEOFF 0x702a4
5216#define _SPRA_OFFSET 0x702a4
5217#define _SPRA_SURFLIVE 0x702ac
5218#define _SPRA_SCALE 0x70304
5219#define SPRITE_SCALE_ENABLE (1<<31)
5220#define SPRITE_FILTER_MASK (3<<29)
5221#define SPRITE_FILTER_MEDIUM (0<<29)
5222#define SPRITE_FILTER_ENHANCING (1<<29)
5223#define SPRITE_FILTER_SOFTENING (2<<29)
5224#define SPRITE_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
5225#define SPRITE_VERTICAL_OFFSET_ENABLE (1<<27)
5226#define _SPRA_GAMC 0x70400
5227
5228#define _SPRB_CTL 0x71280
5229#define _SPRB_LINOFF 0x71284
5230#define _SPRB_STRIDE 0x71288
5231#define _SPRB_POS 0x7128c
5232#define _SPRB_SIZE 0x71290
5233#define _SPRB_KEYVAL 0x71294
5234#define _SPRB_KEYMSK 0x71298
5235#define _SPRB_SURF 0x7129c
5236#define _SPRB_KEYMAX 0x712a0
5237#define _SPRB_TILEOFF 0x712a4
5238#define _SPRB_OFFSET 0x712a4
5239#define _SPRB_SURFLIVE 0x712ac
5240#define _SPRB_SCALE 0x71304
5241#define _SPRB_GAMC 0x71400
5242
5243#define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
5244#define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
5245#define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
5246#define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS)
5247#define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
5248#define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
5249#define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
5250#define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
5251#define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
5252#define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
5253#define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
5254#define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
5255#define SPRGAMC(pipe) _MMIO_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
5256#define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
5257
5258#define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)
5259#define SP_ENABLE (1<<31)
5260#define SP_GAMMA_ENABLE (1<<30)
5261#define SP_PIXFORMAT_MASK (0xf<<26)
5262#define SP_FORMAT_YUV422 (0<<26)
5263#define SP_FORMAT_BGR565 (5<<26)
5264#define SP_FORMAT_BGRX8888 (6<<26)
5265#define SP_FORMAT_BGRA8888 (7<<26)
5266#define SP_FORMAT_RGBX1010102 (8<<26)
5267#define SP_FORMAT_RGBA1010102 (9<<26)
5268#define SP_FORMAT_RGBX8888 (0xe<<26)
5269#define SP_FORMAT_RGBA8888 (0xf<<26)
5270#define SP_ALPHA_PREMULTIPLY (1<<23) /* CHV pipe B */
5271#define SP_SOURCE_KEY (1<<22)
5272#define SP_YUV_BYTE_ORDER_MASK (3<<16)
5273#define SP_YUV_ORDER_YUYV (0<<16)
5274#define SP_YUV_ORDER_UYVY (1<<16)
5275#define SP_YUV_ORDER_YVYU (2<<16)
5276#define SP_YUV_ORDER_VYUY (3<<16)
5277#define SP_ROTATE_180 (1<<15)
5278#define SP_TILED (1<<10)
5279#define SP_MIRROR (1<<8) /* CHV pipe B */
5280#define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)
5281#define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)
5282#define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c)
5283#define _SPASIZE (VLV_DISPLAY_BASE + 0x72190)
5284#define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194)
5285#define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198)
5286#define _SPASURF (VLV_DISPLAY_BASE + 0x7219c)
5287#define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0)
5288#define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4)
5289#define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8)
5290#define SP_CONST_ALPHA_ENABLE (1<<31)
5291#define _SPAGAMC (VLV_DISPLAY_BASE + 0x721f4)
5292
5293#define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)
5294#define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284)
5295#define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288)
5296#define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c)
5297#define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290)
5298#define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294)
5299#define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298)
5300#define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c)
5301#define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0)
5302#define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4)
5303#define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)
5304#define _SPBGAMC (VLV_DISPLAY_BASE + 0x722f4)
5305
5306#define SPCNTR(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPACNTR, _SPBCNTR)
5307#define SPLINOFF(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPALINOFF, _SPBLINOFF)
5308#define SPSTRIDE(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPASTRIDE, _SPBSTRIDE)
5309#define SPPOS(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAPOS, _SPBPOS)
5310#define SPSIZE(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPASIZE, _SPBSIZE)
5311#define SPKEYMINVAL(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAKEYMINVAL, _SPBKEYMINVAL)
5312#define SPKEYMSK(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAKEYMSK, _SPBKEYMSK)
5313#define SPSURF(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPASURF, _SPBSURF)
5314#define SPKEYMAXVAL(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
5315#define SPTILEOFF(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPATILEOFF, _SPBTILEOFF)
5316#define SPCONSTALPHA(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPACONSTALPHA, _SPBCONSTALPHA)
5317#define SPGAMC(pipe, plane) _MMIO_PIPE((pipe) * 2 + (plane), _SPAGAMC, _SPBGAMC)
5318
5319/*
5320 * CHV pipe B sprite CSC
5321 *
5322 * |cr| |c0 c1 c2| |cr + cr_ioff| |cr_ooff|
5323 * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff|
5324 * |cb| |c6 c7 c8| |cb + cr_ioff| |cb_ooff|
5325 */
5326#define SPCSCYGOFF(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d900 + (sprite) * 0x1000)
5327#define SPCSCCBOFF(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d904 + (sprite) * 0x1000)
5328#define SPCSCCROFF(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d908 + (sprite) * 0x1000)
5329#define SPCSC_OOFF(x) (((x) & 0x7ff) << 16) /* s11 */
5330#define SPCSC_IOFF(x) (((x) & 0x7ff) << 0) /* s11 */
5331
5332#define SPCSCC01(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d90c + (sprite) * 0x1000)
5333#define SPCSCC23(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d910 + (sprite) * 0x1000)
5334#define SPCSCC45(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d914 + (sprite) * 0x1000)
5335#define SPCSCC67(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d918 + (sprite) * 0x1000)
5336#define SPCSCC8(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d91c + (sprite) * 0x1000)
5337#define SPCSC_C1(x) (((x) & 0x7fff) << 16) /* s3.12 */
5338#define SPCSC_C0(x) (((x) & 0x7fff) << 0) /* s3.12 */
5339
5340#define SPCSCYGICLAMP(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d920 + (sprite) * 0x1000)
5341#define SPCSCCBICLAMP(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d924 + (sprite) * 0x1000)
5342#define SPCSCCRICLAMP(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d928 + (sprite) * 0x1000)
5343#define SPCSC_IMAX(x) (((x) & 0x7ff) << 16) /* s11 */
5344#define SPCSC_IMIN(x) (((x) & 0x7ff) << 0) /* s11 */
5345
5346#define SPCSCYGOCLAMP(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d92c + (sprite) * 0x1000)
5347#define SPCSCCBOCLAMP(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d930 + (sprite) * 0x1000)
5348#define SPCSCCROCLAMP(sprite) _MMIO(VLV_DISPLAY_BASE + 0x6d934 + (sprite) * 0x1000)
5349#define SPCSC_OMAX(x) ((x) << 16) /* u10 */
5350#define SPCSC_OMIN(x) ((x) << 0) /* u10 */
5351
5352/* Skylake plane registers */
5353
5354#define _PLANE_CTL_1_A 0x70180
5355#define _PLANE_CTL_2_A 0x70280
5356#define _PLANE_CTL_3_A 0x70380
5357#define PLANE_CTL_ENABLE (1 << 31)
5358#define PLANE_CTL_PIPE_GAMMA_ENABLE (1 << 30)
5359#define PLANE_CTL_FORMAT_MASK (0xf << 24)
5360#define PLANE_CTL_FORMAT_YUV422 ( 0 << 24)
5361#define PLANE_CTL_FORMAT_NV12 ( 1 << 24)
5362#define PLANE_CTL_FORMAT_XRGB_2101010 ( 2 << 24)
5363#define PLANE_CTL_FORMAT_XRGB_8888 ( 4 << 24)
5364#define PLANE_CTL_FORMAT_XRGB_16161616F ( 6 << 24)
5365#define PLANE_CTL_FORMAT_AYUV ( 8 << 24)
5366#define PLANE_CTL_FORMAT_INDEXED ( 12 << 24)
5367#define PLANE_CTL_FORMAT_RGB_565 ( 14 << 24)
5368#define PLANE_CTL_PIPE_CSC_ENABLE (1 << 23)
5369#define PLANE_CTL_KEY_ENABLE_MASK (0x3 << 21)
5370#define PLANE_CTL_KEY_ENABLE_SOURCE ( 1 << 21)
5371#define PLANE_CTL_KEY_ENABLE_DESTINATION ( 2 << 21)
5372#define PLANE_CTL_ORDER_BGRX (0 << 20)
5373#define PLANE_CTL_ORDER_RGBX (1 << 20)
5374#define PLANE_CTL_YUV422_ORDER_MASK (0x3 << 16)
5375#define PLANE_CTL_YUV422_YUYV ( 0 << 16)
5376#define PLANE_CTL_YUV422_UYVY ( 1 << 16)
5377#define PLANE_CTL_YUV422_YVYU ( 2 << 16)
5378#define PLANE_CTL_YUV422_VYUY ( 3 << 16)
5379#define PLANE_CTL_DECOMPRESSION_ENABLE (1 << 15)
5380#define PLANE_CTL_TRICKLE_FEED_DISABLE (1 << 14)
5381#define PLANE_CTL_PLANE_GAMMA_DISABLE (1 << 13)
5382#define PLANE_CTL_TILED_MASK (0x7 << 10)
5383#define PLANE_CTL_TILED_LINEAR ( 0 << 10)
5384#define PLANE_CTL_TILED_X ( 1 << 10)
5385#define PLANE_CTL_TILED_Y ( 4 << 10)
5386#define PLANE_CTL_TILED_YF ( 5 << 10)
5387#define PLANE_CTL_ALPHA_MASK (0x3 << 4)
5388#define PLANE_CTL_ALPHA_DISABLE ( 0 << 4)
5389#define PLANE_CTL_ALPHA_SW_PREMULTIPLY ( 2 << 4)
5390#define PLANE_CTL_ALPHA_HW_PREMULTIPLY ( 3 << 4)
5391#define PLANE_CTL_ROTATE_MASK 0x3
5392#define PLANE_CTL_ROTATE_0 0x0
5393#define PLANE_CTL_ROTATE_90 0x1
5394#define PLANE_CTL_ROTATE_180 0x2
5395#define PLANE_CTL_ROTATE_270 0x3
5396#define _PLANE_STRIDE_1_A 0x70188
5397#define _PLANE_STRIDE_2_A 0x70288
5398#define _PLANE_STRIDE_3_A 0x70388
5399#define _PLANE_POS_1_A 0x7018c
5400#define _PLANE_POS_2_A 0x7028c
5401#define _PLANE_POS_3_A 0x7038c
5402#define _PLANE_SIZE_1_A 0x70190
5403#define _PLANE_SIZE_2_A 0x70290
5404#define _PLANE_SIZE_3_A 0x70390
5405#define _PLANE_SURF_1_A 0x7019c
5406#define _PLANE_SURF_2_A 0x7029c
5407#define _PLANE_SURF_3_A 0x7039c
5408#define _PLANE_OFFSET_1_A 0x701a4
5409#define _PLANE_OFFSET_2_A 0x702a4
5410#define _PLANE_OFFSET_3_A 0x703a4
5411#define _PLANE_KEYVAL_1_A 0x70194
5412#define _PLANE_KEYVAL_2_A 0x70294
5413#define _PLANE_KEYMSK_1_A 0x70198
5414#define _PLANE_KEYMSK_2_A 0x70298
5415#define _PLANE_KEYMAX_1_A 0x701a0
5416#define _PLANE_KEYMAX_2_A 0x702a0
5417#define _PLANE_BUF_CFG_1_A 0x7027c
5418#define _PLANE_BUF_CFG_2_A 0x7037c
5419#define _PLANE_NV12_BUF_CFG_1_A 0x70278
5420#define _PLANE_NV12_BUF_CFG_2_A 0x70378
5421
5422#define _PLANE_CTL_1_B 0x71180
5423#define _PLANE_CTL_2_B 0x71280
5424#define _PLANE_CTL_3_B 0x71380
5425#define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B)
5426#define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)
5427#define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B)
5428#define PLANE_CTL(pipe, plane) \
5429 _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
5430
5431#define _PLANE_STRIDE_1_B 0x71188
5432#define _PLANE_STRIDE_2_B 0x71288
5433#define _PLANE_STRIDE_3_B 0x71388
5434#define _PLANE_STRIDE_1(pipe) \
5435 _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B)
5436#define _PLANE_STRIDE_2(pipe) \
5437 _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)
5438#define _PLANE_STRIDE_3(pipe) \
5439 _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
5440#define PLANE_STRIDE(pipe, plane) \
5441 _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
5442
5443#define _PLANE_POS_1_B 0x7118c
5444#define _PLANE_POS_2_B 0x7128c
5445#define _PLANE_POS_3_B 0x7138c
5446#define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B)
5447#define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B)
5448#define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B)
5449#define PLANE_POS(pipe, plane) \
5450 _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
5451
5452#define _PLANE_SIZE_1_B 0x71190
5453#define _PLANE_SIZE_2_B 0x71290
5454#define _PLANE_SIZE_3_B 0x71390
5455#define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B)
5456#define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
5457#define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B)
5458#define PLANE_SIZE(pipe, plane) \
5459 _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
5460
5461#define _PLANE_SURF_1_B 0x7119c
5462#define _PLANE_SURF_2_B 0x7129c
5463#define _PLANE_SURF_3_B 0x7139c
5464#define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B)
5465#define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B)
5466#define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
5467#define PLANE_SURF(pipe, plane) \
5468 _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
5469
5470#define _PLANE_OFFSET_1_B 0x711a4
5471#define _PLANE_OFFSET_2_B 0x712a4
5472#define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B)
5473#define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B)
5474#define PLANE_OFFSET(pipe, plane) \
5475 _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))
5476
5477#define _PLANE_KEYVAL_1_B 0x71194
5478#define _PLANE_KEYVAL_2_B 0x71294
5479#define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B)
5480#define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B)
5481#define PLANE_KEYVAL(pipe, plane) \
5482 _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))
5483
5484#define _PLANE_KEYMSK_1_B 0x71198
5485#define _PLANE_KEYMSK_2_B 0x71298
5486#define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B)
5487#define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B)
5488#define PLANE_KEYMSK(pipe, plane) \
5489 _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))
5490
5491#define _PLANE_KEYMAX_1_B 0x711a0
5492#define _PLANE_KEYMAX_2_B 0x712a0
5493#define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B)
5494#define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B)
5495#define PLANE_KEYMAX(pipe, plane) \
5496 _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))
5497
5498#define _PLANE_BUF_CFG_1_B 0x7127c
5499#define _PLANE_BUF_CFG_2_B 0x7137c
5500#define _PLANE_BUF_CFG_1(pipe) \
5501 _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
5502#define _PLANE_BUF_CFG_2(pipe) \
5503 _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
5504#define PLANE_BUF_CFG(pipe, plane) \
5505 _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe))
5506
5507#define _PLANE_NV12_BUF_CFG_1_B 0x71278
5508#define _PLANE_NV12_BUF_CFG_2_B 0x71378
5509#define _PLANE_NV12_BUF_CFG_1(pipe) \
5510 _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B)
5511#define _PLANE_NV12_BUF_CFG_2(pipe) \
5512 _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B)
5513#define PLANE_NV12_BUF_CFG(pipe, plane) \
5514 _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe))
5515
5516/* SKL new cursor registers */
5517#define _CUR_BUF_CFG_A 0x7017c
5518#define _CUR_BUF_CFG_B 0x7117c
5519#define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
5520
5521/* VBIOS regs */
5522#define VGACNTRL _MMIO(0x71400)
5523# define VGA_DISP_DISABLE (1 << 31)
5524# define VGA_2X_MODE (1 << 30)
5525# define VGA_PIPE_B_SELECT (1 << 29)
5526
5527#define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400)
5528
5529/* Ironlake */
5530
5531#define CPU_VGACNTRL _MMIO(0x41000)
5532
5533#define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030)
5534#define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
5535#define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */
5536#define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2) /* pre-HSW */
5537#define DIGITAL_PORTA_PULSE_DURATION_6ms (2 << 2) /* pre-HSW */
5538#define DIGITAL_PORTA_PULSE_DURATION_100ms (3 << 2) /* pre-HSW */
5539#define DIGITAL_PORTA_PULSE_DURATION_MASK (3 << 2) /* pre-HSW */
5540#define DIGITAL_PORTA_HOTPLUG_STATUS_MASK (3 << 0)
5541#define DIGITAL_PORTA_HOTPLUG_NO_DETECT (0 << 0)
5542#define DIGITAL_PORTA_HOTPLUG_SHORT_DETECT (1 << 0)
5543#define DIGITAL_PORTA_HOTPLUG_LONG_DETECT (2 << 0)
5544
5545/* refresh rate hardware control */
5546#define RR_HW_CTL _MMIO(0x45300)
5547#define RR_HW_LOW_POWER_FRAMES_MASK 0xff
5548#define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
5549
5550#define FDI_PLL_BIOS_0 _MMIO(0x46000)
5551#define FDI_PLL_FB_CLOCK_MASK 0xff
5552#define FDI_PLL_BIOS_1 _MMIO(0x46004)
5553#define FDI_PLL_BIOS_2 _MMIO(0x46008)
5554#define DISPLAY_PORT_PLL_BIOS_0 _MMIO(0x4600c)
5555#define DISPLAY_PORT_PLL_BIOS_1 _MMIO(0x46010)
5556#define DISPLAY_PORT_PLL_BIOS_2 _MMIO(0x46014)
5557
5558#define PCH_3DCGDIS0 _MMIO(0x46020)
5559# define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
5560# define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
5561
5562#define PCH_3DCGDIS1 _MMIO(0x46024)
5563# define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
5564
5565#define FDI_PLL_FREQ_CTL _MMIO(0x46030)
5566#define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24)
5567#define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
5568#define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
5569
5570
5571#define _PIPEA_DATA_M1 0x60030
5572#define PIPE_DATA_M1_OFFSET 0
5573#define _PIPEA_DATA_N1 0x60034
5574#define PIPE_DATA_N1_OFFSET 0
5575
5576#define _PIPEA_DATA_M2 0x60038
5577#define PIPE_DATA_M2_OFFSET 0
5578#define _PIPEA_DATA_N2 0x6003c
5579#define PIPE_DATA_N2_OFFSET 0
5580
5581#define _PIPEA_LINK_M1 0x60040
5582#define PIPE_LINK_M1_OFFSET 0
5583#define _PIPEA_LINK_N1 0x60044
5584#define PIPE_LINK_N1_OFFSET 0
5585
5586#define _PIPEA_LINK_M2 0x60048
5587#define PIPE_LINK_M2_OFFSET 0
5588#define _PIPEA_LINK_N2 0x6004c
5589#define PIPE_LINK_N2_OFFSET 0
5590
5591/* PIPEB timing regs are same start from 0x61000 */
5592
5593#define _PIPEB_DATA_M1 0x61030
5594#define _PIPEB_DATA_N1 0x61034
5595#define _PIPEB_DATA_M2 0x61038
5596#define _PIPEB_DATA_N2 0x6103c
5597#define _PIPEB_LINK_M1 0x61040
5598#define _PIPEB_LINK_N1 0x61044
5599#define _PIPEB_LINK_M2 0x61048
5600#define _PIPEB_LINK_N2 0x6104c
5601
5602#define PIPE_DATA_M1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M1)
5603#define PIPE_DATA_N1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N1)
5604#define PIPE_DATA_M2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M2)
5605#define PIPE_DATA_N2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N2)
5606#define PIPE_LINK_M1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M1)
5607#define PIPE_LINK_N1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N1)
5608#define PIPE_LINK_M2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M2)
5609#define PIPE_LINK_N2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N2)
5610
5611/* CPU panel fitter */
5612/* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
5613#define _PFA_CTL_1 0x68080
5614#define _PFB_CTL_1 0x68880
5615#define PF_ENABLE (1<<31)
5616#define PF_PIPE_SEL_MASK_IVB (3<<29)
5617#define PF_PIPE_SEL_IVB(pipe) ((pipe)<<29)
5618#define PF_FILTER_MASK (3<<23)
5619#define PF_FILTER_PROGRAMMED (0<<23)
5620#define PF_FILTER_MED_3x3 (1<<23)
5621#define PF_FILTER_EDGE_ENHANCE (2<<23)
5622#define PF_FILTER_EDGE_SOFTEN (3<<23)
5623#define _PFA_WIN_SZ 0x68074
5624#define _PFB_WIN_SZ 0x68874
5625#define _PFA_WIN_POS 0x68070
5626#define _PFB_WIN_POS 0x68870
5627#define _PFA_VSCALE 0x68084
5628#define _PFB_VSCALE 0x68884
5629#define _PFA_HSCALE 0x68090
5630#define _PFB_HSCALE 0x68890
5631
5632#define PF_CTL(pipe) _MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
5633#define PF_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
5634#define PF_WIN_POS(pipe) _MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
5635#define PF_VSCALE(pipe) _MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
5636#define PF_HSCALE(pipe) _MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
5637
5638#define _PSA_CTL 0x68180
5639#define _PSB_CTL 0x68980
5640#define PS_ENABLE (1<<31)
5641#define _PSA_WIN_SZ 0x68174
5642#define _PSB_WIN_SZ 0x68974
5643#define _PSA_WIN_POS 0x68170
5644#define _PSB_WIN_POS 0x68970
5645
5646#define PS_CTL(pipe) _MMIO_PIPE(pipe, _PSA_CTL, _PSB_CTL)
5647#define PS_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ)
5648#define PS_WIN_POS(pipe) _MMIO_PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS)
5649
5650/*
5651 * Skylake scalers
5652 */
5653#define _PS_1A_CTRL 0x68180
5654#define _PS_2A_CTRL 0x68280
5655#define _PS_1B_CTRL 0x68980
5656#define _PS_2B_CTRL 0x68A80
5657#define _PS_1C_CTRL 0x69180
5658#define PS_SCALER_EN (1 << 31)
5659#define PS_SCALER_MODE_MASK (3 << 28)
5660#define PS_SCALER_MODE_DYN (0 << 28)
5661#define PS_SCALER_MODE_HQ (1 << 28)
5662#define PS_PLANE_SEL_MASK (7 << 25)
5663#define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
5664#define PS_FILTER_MASK (3 << 23)
5665#define PS_FILTER_MEDIUM (0 << 23)
5666#define PS_FILTER_EDGE_ENHANCE (2 << 23)
5667#define PS_FILTER_BILINEAR (3 << 23)
5668#define PS_VERT3TAP (1 << 21)
5669#define PS_VERT_INT_INVERT_FIELD1 (0 << 20)
5670#define PS_VERT_INT_INVERT_FIELD0 (1 << 20)
5671#define PS_PWRUP_PROGRESS (1 << 17)
5672#define PS_V_FILTER_BYPASS (1 << 8)
5673#define PS_VADAPT_EN (1 << 7)
5674#define PS_VADAPT_MODE_MASK (3 << 5)
5675#define PS_VADAPT_MODE_LEAST_ADAPT (0 << 5)
5676#define PS_VADAPT_MODE_MOD_ADAPT (1 << 5)
5677#define PS_VADAPT_MODE_MOST_ADAPT (3 << 5)
5678
5679#define _PS_PWR_GATE_1A 0x68160
5680#define _PS_PWR_GATE_2A 0x68260
5681#define _PS_PWR_GATE_1B 0x68960
5682#define _PS_PWR_GATE_2B 0x68A60
5683#define _PS_PWR_GATE_1C 0x69160
5684#define PS_PWR_GATE_DIS_OVERRIDE (1 << 31)
5685#define PS_PWR_GATE_SETTLING_TIME_32 (0 << 3)
5686#define PS_PWR_GATE_SETTLING_TIME_64 (1 << 3)
5687#define PS_PWR_GATE_SETTLING_TIME_96 (2 << 3)
5688#define PS_PWR_GATE_SETTLING_TIME_128 (3 << 3)
5689#define PS_PWR_GATE_SLPEN_8 0
5690#define PS_PWR_GATE_SLPEN_16 1
5691#define PS_PWR_GATE_SLPEN_24 2
5692#define PS_PWR_GATE_SLPEN_32 3
5693
5694#define _PS_WIN_POS_1A 0x68170
5695#define _PS_WIN_POS_2A 0x68270
5696#define _PS_WIN_POS_1B 0x68970
5697#define _PS_WIN_POS_2B 0x68A70
5698#define _PS_WIN_POS_1C 0x69170
5699
5700#define _PS_WIN_SZ_1A 0x68174
5701#define _PS_WIN_SZ_2A 0x68274
5702#define _PS_WIN_SZ_1B 0x68974
5703#define _PS_WIN_SZ_2B 0x68A74
5704#define _PS_WIN_SZ_1C 0x69174
5705
5706#define _PS_VSCALE_1A 0x68184
5707#define _PS_VSCALE_2A 0x68284
5708#define _PS_VSCALE_1B 0x68984
5709#define _PS_VSCALE_2B 0x68A84
5710#define _PS_VSCALE_1C 0x69184
5711
5712#define _PS_HSCALE_1A 0x68190
5713#define _PS_HSCALE_2A 0x68290
5714#define _PS_HSCALE_1B 0x68990
5715#define _PS_HSCALE_2B 0x68A90
5716#define _PS_HSCALE_1C 0x69190
5717
5718#define _PS_VPHASE_1A 0x68188
5719#define _PS_VPHASE_2A 0x68288
5720#define _PS_VPHASE_1B 0x68988
5721#define _PS_VPHASE_2B 0x68A88
5722#define _PS_VPHASE_1C 0x69188
5723
5724#define _PS_HPHASE_1A 0x68194
5725#define _PS_HPHASE_2A 0x68294
5726#define _PS_HPHASE_1B 0x68994
5727#define _PS_HPHASE_2B 0x68A94
5728#define _PS_HPHASE_1C 0x69194
5729
5730#define _PS_ECC_STAT_1A 0x681D0
5731#define _PS_ECC_STAT_2A 0x682D0
5732#define _PS_ECC_STAT_1B 0x689D0
5733#define _PS_ECC_STAT_2B 0x68AD0
5734#define _PS_ECC_STAT_1C 0x691D0
5735
5736#define _ID(id, a, b) ((a) + (id)*((b)-(a)))
5737#define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \
5738 _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \
5739 _ID(id, _PS_1B_CTRL, _PS_2B_CTRL))
5740#define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe, \
5741 _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \
5742 _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B))
5743#define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe, \
5744 _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \
5745 _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B))
5746#define SKL_PS_WIN_SZ(pipe, id) _MMIO_PIPE(pipe, \
5747 _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \
5748 _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B))
5749#define SKL_PS_VSCALE(pipe, id) _MMIO_PIPE(pipe, \
5750 _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \
5751 _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B))
5752#define SKL_PS_HSCALE(pipe, id) _MMIO_PIPE(pipe, \
5753 _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \
5754 _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B))
5755#define SKL_PS_VPHASE(pipe, id) _MMIO_PIPE(pipe, \
5756 _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \
5757 _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B))
5758#define SKL_PS_HPHASE(pipe, id) _MMIO_PIPE(pipe, \
5759 _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \
5760 _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B))
5761#define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \
5762 _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \
5763 _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
5764
5765/* legacy palette */
5766#define _LGC_PALETTE_A 0x4a000
5767#define _LGC_PALETTE_B 0x4a800
5768#define LGC_PALETTE(pipe, i) _MMIO(_PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B) + (i) * 4)
5769
5770#define _GAMMA_MODE_A 0x4a480
5771#define _GAMMA_MODE_B 0x4ac80
5772#define GAMMA_MODE(pipe) _MMIO_PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
5773#define GAMMA_MODE_MODE_MASK (3 << 0)
5774#define GAMMA_MODE_MODE_8BIT (0 << 0)
5775#define GAMMA_MODE_MODE_10BIT (1 << 0)
5776#define GAMMA_MODE_MODE_12BIT (2 << 0)
5777#define GAMMA_MODE_MODE_SPLIT (3 << 0)
5778
5779/* DMC/CSR */
5780#define CSR_PROGRAM(i) _MMIO(0x80000 + (i) * 4)
5781#define CSR_SSP_BASE_ADDR_GEN9 0x00002FC0
5782#define CSR_HTP_ADDR_SKL 0x00500034
5783#define CSR_SSP_BASE _MMIO(0x8F074)
5784#define CSR_HTP_SKL _MMIO(0x8F004)
5785#define CSR_LAST_WRITE _MMIO(0x8F034)
5786#define CSR_LAST_WRITE_VALUE 0xc003b400
5787/* MMIO address range for CSR program (0x80000 - 0x82FFF) */
5788#define CSR_MMIO_START_RANGE 0x80000
5789#define CSR_MMIO_END_RANGE 0x8FFFF
5790#define SKL_CSR_DC3_DC5_COUNT _MMIO(0x80030)
5791#define SKL_CSR_DC5_DC6_COUNT _MMIO(0x8002C)
5792#define BXT_CSR_DC3_DC5_COUNT _MMIO(0x80038)
5793
5794/* interrupts */
5795#define DE_MASTER_IRQ_CONTROL (1 << 31)
5796#define DE_SPRITEB_FLIP_DONE (1 << 29)
5797#define DE_SPRITEA_FLIP_DONE (1 << 28)
5798#define DE_PLANEB_FLIP_DONE (1 << 27)
5799#define DE_PLANEA_FLIP_DONE (1 << 26)
5800#define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane)))
5801#define DE_PCU_EVENT (1 << 25)
5802#define DE_GTT_FAULT (1 << 24)
5803#define DE_POISON (1 << 23)
5804#define DE_PERFORM_COUNTER (1 << 22)
5805#define DE_PCH_EVENT (1 << 21)
5806#define DE_AUX_CHANNEL_A (1 << 20)
5807#define DE_DP_A_HOTPLUG (1 << 19)
5808#define DE_GSE (1 << 18)
5809#define DE_PIPEB_VBLANK (1 << 15)
5810#define DE_PIPEB_EVEN_FIELD (1 << 14)
5811#define DE_PIPEB_ODD_FIELD (1 << 13)
5812#define DE_PIPEB_LINE_COMPARE (1 << 12)
5813#define DE_PIPEB_VSYNC (1 << 11)
5814#define DE_PIPEB_CRC_DONE (1 << 10)
5815#define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
5816#define DE_PIPEA_VBLANK (1 << 7)
5817#define DE_PIPE_VBLANK(pipe) (1 << (7 + 8*(pipe)))
5818#define DE_PIPEA_EVEN_FIELD (1 << 6)
5819#define DE_PIPEA_ODD_FIELD (1 << 5)
5820#define DE_PIPEA_LINE_COMPARE (1 << 4)
5821#define DE_PIPEA_VSYNC (1 << 3)
5822#define DE_PIPEA_CRC_DONE (1 << 2)
5823#define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8*(pipe)))
5824#define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
5825#define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8*(pipe)))
5826
5827/* More Ivybridge lolz */
5828#define DE_ERR_INT_IVB (1<<30)
5829#define DE_GSE_IVB (1<<29)
5830#define DE_PCH_EVENT_IVB (1<<28)
5831#define DE_DP_A_HOTPLUG_IVB (1<<27)
5832#define DE_AUX_CHANNEL_A_IVB (1<<26)
5833#define DE_SPRITEC_FLIP_DONE_IVB (1<<14)
5834#define DE_PLANEC_FLIP_DONE_IVB (1<<13)
5835#define DE_PIPEC_VBLANK_IVB (1<<10)
5836#define DE_SPRITEB_FLIP_DONE_IVB (1<<9)
5837#define DE_PLANEB_FLIP_DONE_IVB (1<<8)
5838#define DE_PIPEB_VBLANK_IVB (1<<5)
5839#define DE_SPRITEA_FLIP_DONE_IVB (1<<4)
5840#define DE_PLANEA_FLIP_DONE_IVB (1<<3)
5841#define DE_PLANE_FLIP_DONE_IVB(plane) (1<< (3 + 5*(plane)))
5842#define DE_PIPEA_VBLANK_IVB (1<<0)
5843#define DE_PIPE_VBLANK_IVB(pipe) (1 << ((pipe) * 5))
5844
5845#define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */
5846#define MASTER_INTERRUPT_ENABLE (1<<31)
5847
5848#define DEISR _MMIO(0x44000)
5849#define DEIMR _MMIO(0x44004)
5850#define DEIIR _MMIO(0x44008)
5851#define DEIER _MMIO(0x4400c)
5852
5853#define GTISR _MMIO(0x44010)
5854#define GTIMR _MMIO(0x44014)
5855#define GTIIR _MMIO(0x44018)
5856#define GTIER _MMIO(0x4401c)
5857
5858#define GEN8_MASTER_IRQ _MMIO(0x44200)
5859#define GEN8_MASTER_IRQ_CONTROL (1<<31)
5860#define GEN8_PCU_IRQ (1<<30)
5861#define GEN8_DE_PCH_IRQ (1<<23)
5862#define GEN8_DE_MISC_IRQ (1<<22)
5863#define GEN8_DE_PORT_IRQ (1<<20)
5864#define GEN8_DE_PIPE_C_IRQ (1<<18)
5865#define GEN8_DE_PIPE_B_IRQ (1<<17)
5866#define GEN8_DE_PIPE_A_IRQ (1<<16)
5867#define GEN8_DE_PIPE_IRQ(pipe) (1<<(16+(pipe)))
5868#define GEN8_GT_VECS_IRQ (1<<6)
5869#define GEN8_GT_PM_IRQ (1<<4)
5870#define GEN8_GT_VCS2_IRQ (1<<3)
5871#define GEN8_GT_VCS1_IRQ (1<<2)
5872#define GEN8_GT_BCS_IRQ (1<<1)
5873#define GEN8_GT_RCS_IRQ (1<<0)
5874
5875#define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which)))
5876#define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which)))
5877#define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))
5878#define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which)))
5879
5880#define GEN8_RCS_IRQ_SHIFT 0
5881#define GEN8_BCS_IRQ_SHIFT 16
5882#define GEN8_VCS1_IRQ_SHIFT 0
5883#define GEN8_VCS2_IRQ_SHIFT 16
5884#define GEN8_VECS_IRQ_SHIFT 0
5885#define GEN8_WD_IRQ_SHIFT 16
5886
5887#define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe)))
5888#define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe)))
5889#define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe)))
5890#define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe)))
5891#define GEN8_PIPE_FIFO_UNDERRUN (1 << 31)
5892#define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29)
5893#define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28)
5894#define GEN8_PIPE_CURSOR_FAULT (1 << 10)
5895#define GEN8_PIPE_SPRITE_FAULT (1 << 9)
5896#define GEN8_PIPE_PRIMARY_FAULT (1 << 8)
5897#define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5)
5898#define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4)
5899#define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2)
5900#define GEN8_PIPE_VSYNC (1 << 1)
5901#define GEN8_PIPE_VBLANK (1 << 0)
5902#define GEN9_PIPE_CURSOR_FAULT (1 << 11)
5903#define GEN9_PIPE_PLANE4_FAULT (1 << 10)
5904#define GEN9_PIPE_PLANE3_FAULT (1 << 9)
5905#define GEN9_PIPE_PLANE2_FAULT (1 << 8)
5906#define GEN9_PIPE_PLANE1_FAULT (1 << 7)
5907#define GEN9_PIPE_PLANE4_FLIP_DONE (1 << 6)
5908#define GEN9_PIPE_PLANE3_FLIP_DONE (1 << 5)
5909#define GEN9_PIPE_PLANE2_FLIP_DONE (1 << 4)
5910#define GEN9_PIPE_PLANE1_FLIP_DONE (1 << 3)
5911#define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + (p)))
5912#define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \
5913 (GEN8_PIPE_CURSOR_FAULT | \
5914 GEN8_PIPE_SPRITE_FAULT | \
5915 GEN8_PIPE_PRIMARY_FAULT)
5916#define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \
5917 (GEN9_PIPE_CURSOR_FAULT | \
5918 GEN9_PIPE_PLANE4_FAULT | \
5919 GEN9_PIPE_PLANE3_FAULT | \
5920 GEN9_PIPE_PLANE2_FAULT | \
5921 GEN9_PIPE_PLANE1_FAULT)
5922
5923#define GEN8_DE_PORT_ISR _MMIO(0x44440)
5924#define GEN8_DE_PORT_IMR _MMIO(0x44444)
5925#define GEN8_DE_PORT_IIR _MMIO(0x44448)
5926#define GEN8_DE_PORT_IER _MMIO(0x4444c)
5927#define GEN9_AUX_CHANNEL_D (1 << 27)
5928#define GEN9_AUX_CHANNEL_C (1 << 26)
5929#define GEN9_AUX_CHANNEL_B (1 << 25)
5930#define BXT_DE_PORT_HP_DDIC (1 << 5)
5931#define BXT_DE_PORT_HP_DDIB (1 << 4)
5932#define BXT_DE_PORT_HP_DDIA (1 << 3)
5933#define BXT_DE_PORT_HOTPLUG_MASK (BXT_DE_PORT_HP_DDIA | \
5934 BXT_DE_PORT_HP_DDIB | \
5935 BXT_DE_PORT_HP_DDIC)
5936#define GEN8_PORT_DP_A_HOTPLUG (1 << 3)
5937#define BXT_DE_PORT_GMBUS (1 << 1)
5938#define GEN8_AUX_CHANNEL_A (1 << 0)
5939
5940#define GEN8_DE_MISC_ISR _MMIO(0x44460)
5941#define GEN8_DE_MISC_IMR _MMIO(0x44464)
5942#define GEN8_DE_MISC_IIR _MMIO(0x44468)
5943#define GEN8_DE_MISC_IER _MMIO(0x4446c)
5944#define GEN8_DE_MISC_GSE (1 << 27)
5945
5946#define GEN8_PCU_ISR _MMIO(0x444e0)
5947#define GEN8_PCU_IMR _MMIO(0x444e4)
5948#define GEN8_PCU_IIR _MMIO(0x444e8)
5949#define GEN8_PCU_IER _MMIO(0x444ec)
5950
5951#define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004)
5952/* Required on all Ironlake and Sandybridge according to the B-Spec. */
5953#define ILK_ELPIN_409_SELECT (1 << 25)
5954#define ILK_DPARB_GATE (1<<22)
5955#define ILK_VSDPFD_FULL (1<<21)
5956#define FUSE_STRAP _MMIO(0x42014)
5957#define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31)
5958#define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30)
5959#define ILK_DISPLAY_DEBUG_DISABLE (1 << 29)
5960#define IVB_PIPE_C_DISABLE (1 << 28)
5961#define ILK_HDCP_DISABLE (1 << 25)
5962#define ILK_eDP_A_DISABLE (1 << 24)
5963#define HSW_CDCLK_LIMIT (1 << 24)
5964#define ILK_DESKTOP (1 << 23)
5965
5966#define ILK_DSPCLK_GATE_D _MMIO(0x42020)
5967#define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28)
5968#define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9)
5969#define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8)
5970#define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7)
5971#define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5)
5972
5973#define IVB_CHICKEN3 _MMIO(0x4200c)
5974# define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5)
5975# define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2)
5976
5977#define CHICKEN_PAR1_1 _MMIO(0x42080)
5978#define DPA_MASK_VBLANK_SRD (1 << 15)
5979#define FORCE_ARB_IDLE_PLANES (1 << 14)
5980
5981#define _CHICKEN_PIPESL_1_A 0x420b0
5982#define _CHICKEN_PIPESL_1_B 0x420b4
5983#define HSW_FBCQ_DIS (1 << 22)
5984#define BDW_DPRS_MASK_VBLANK_SRD (1 << 0)
5985#define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
5986
5987#define DISP_ARB_CTL _MMIO(0x45000)
5988#define DISP_TILE_SURFACE_SWIZZLING (1<<13)
5989#define DISP_FBC_WM_DIS (1<<15)
5990#define DISP_ARB_CTL2 _MMIO(0x45004)
5991#define DISP_DATA_PARTITION_5_6 (1<<6)
5992#define DBUF_CTL _MMIO(0x45008)
5993#define DBUF_POWER_REQUEST (1<<31)
5994#define DBUF_POWER_STATE (1<<30)
5995#define GEN7_MSG_CTL _MMIO(0x45010)
5996#define WAIT_FOR_PCH_RESET_ACK (1<<1)
5997#define WAIT_FOR_PCH_FLR_ACK (1<<0)
5998#define HSW_NDE_RSTWRN_OPT _MMIO(0x46408)
5999#define RESET_PCH_HANDSHAKE_ENABLE (1<<4)
6000
6001#define SKL_DFSM _MMIO(0x51000)
6002#define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23)
6003#define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23)
6004#define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
6005#define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23)
6006#define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23)
6007#define SKL_DFSM_PIPE_A_DISABLE (1 << 30)
6008#define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
6009#define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
6010
6011#define GEN7_FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0)
6012#define GEN9_FFSC_PERCTX_PREEMPT_CTRL (1<<14)
6013
6014#define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4)
6015#define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8)
6016
6017#define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec)
6018#define GEN8_CS_CHICKEN1 _MMIO(0x2580)
6019
6020/* GEN7 chicken */
6021#define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010)
6022# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26))
6023# define GEN9_RHWO_OPTIMIZATION_DISABLE (1<<14)
6024#define COMMON_SLICE_CHICKEN2 _MMIO(0x7014)
6025# define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0)
6026
6027#define HIZ_CHICKEN _MMIO(0x7018)
6028# define CHV_HZ_8X8_MODE_IN_1X (1<<15)
6029# define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE (1<<3)
6030
6031#define GEN9_SLICE_COMMON_ECO_CHICKEN0 _MMIO(0x7308)
6032#define DISABLE_PIXEL_MASK_CAMMING (1<<14)
6033
6034#define GEN7_L3SQCREG1 _MMIO(0xB010)
6035#define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
6036
6037#define GEN8_L3SQCREG1 _MMIO(0xB100)
6038#define BDW_WA_L3SQCREG1_DEFAULT 0x784000
6039
6040#define GEN7_L3CNTLREG1 _MMIO(0xB01C)
6041#define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C
6042#define GEN7_L3AGDIS (1<<19)
6043#define GEN7_L3CNTLREG2 _MMIO(0xB020)
6044#define GEN7_L3CNTLREG3 _MMIO(0xB024)
6045
6046#define GEN7_L3_CHICKEN_MODE_REGISTER _MMIO(0xB030)
6047#define GEN7_WA_L3_CHICKEN_MODE 0x20000000
6048
6049#define GEN7_L3SQCREG4 _MMIO(0xb034)
6050#define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27)
6051
6052#define GEN8_L3SQCREG4 _MMIO(0xb118)
6053#define GEN8_LQSC_RO_PERF_DIS (1<<27)
6054#define GEN8_LQSC_FLUSH_COHERENT_LINES (1<<21)
6055
6056/* GEN8 chicken */
6057#define HDC_CHICKEN0 _MMIO(0x7300)
6058#define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1<<15)
6059#define HDC_FENCE_DEST_SLM_DISABLE (1<<14)
6060#define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11)
6061#define HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT (1<<5)
6062#define HDC_FORCE_NON_COHERENT (1<<4)
6063#define HDC_BARRIER_PERFORMANCE_DISABLE (1<<10)
6064
6065#define GEN8_HDC_CHICKEN1 _MMIO(0x7304)
6066
6067/* GEN9 chicken */
6068#define SLICE_ECO_CHICKEN0 _MMIO(0x7308)
6069#define PIXEL_MASK_CAMMING_DISABLE (1 << 14)
6070
6071/* WaCatErrorRejectionIssue */
6072#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG _MMIO(0x9030)
6073#define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11)
6074
6075#define HSW_SCRATCH1 _MMIO(0xb038)
6076#define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1<<27)
6077
6078#define BDW_SCRATCH1 _MMIO(0xb11c)
6079#define GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE (1<<2)
6080
6081/* PCH */
6082
6083/* south display engine interrupt: IBX */
6084#define SDE_AUDIO_POWER_D (1 << 27)
6085#define SDE_AUDIO_POWER_C (1 << 26)
6086#define SDE_AUDIO_POWER_B (1 << 25)
6087#define SDE_AUDIO_POWER_SHIFT (25)
6088#define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT)
6089#define SDE_GMBUS (1 << 24)
6090#define SDE_AUDIO_HDCP_TRANSB (1 << 23)
6091#define SDE_AUDIO_HDCP_TRANSA (1 << 22)
6092#define SDE_AUDIO_HDCP_MASK (3 << 22)
6093#define SDE_AUDIO_TRANSB (1 << 21)
6094#define SDE_AUDIO_TRANSA (1 << 20)
6095#define SDE_AUDIO_TRANS_MASK (3 << 20)
6096#define SDE_POISON (1 << 19)
6097/* 18 reserved */
6098#define SDE_FDI_RXB (1 << 17)
6099#define SDE_FDI_RXA (1 << 16)
6100#define SDE_FDI_MASK (3 << 16)
6101#define SDE_AUXD (1 << 15)
6102#define SDE_AUXC (1 << 14)
6103#define SDE_AUXB (1 << 13)
6104#define SDE_AUX_MASK (7 << 13)
6105/* 12 reserved */
6106#define SDE_CRT_HOTPLUG (1 << 11)
6107#define SDE_PORTD_HOTPLUG (1 << 10)
6108#define SDE_PORTC_HOTPLUG (1 << 9)
6109#define SDE_PORTB_HOTPLUG (1 << 8)
6110#define SDE_SDVOB_HOTPLUG (1 << 6)
6111#define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \
6112 SDE_SDVOB_HOTPLUG | \
6113 SDE_PORTB_HOTPLUG | \
6114 SDE_PORTC_HOTPLUG | \
6115 SDE_PORTD_HOTPLUG)
6116#define SDE_TRANSB_CRC_DONE (1 << 5)
6117#define SDE_TRANSB_CRC_ERR (1 << 4)
6118#define SDE_TRANSB_FIFO_UNDER (1 << 3)
6119#define SDE_TRANSA_CRC_DONE (1 << 2)
6120#define SDE_TRANSA_CRC_ERR (1 << 1)
6121#define SDE_TRANSA_FIFO_UNDER (1 << 0)
6122#define SDE_TRANS_MASK (0x3f)
6123
6124/* south display engine interrupt: CPT/PPT */
6125#define SDE_AUDIO_POWER_D_CPT (1 << 31)
6126#define SDE_AUDIO_POWER_C_CPT (1 << 30)
6127#define SDE_AUDIO_POWER_B_CPT (1 << 29)
6128#define SDE_AUDIO_POWER_SHIFT_CPT 29
6129#define SDE_AUDIO_POWER_MASK_CPT (7 << 29)
6130#define SDE_AUXD_CPT (1 << 27)
6131#define SDE_AUXC_CPT (1 << 26)
6132#define SDE_AUXB_CPT (1 << 25)
6133#define SDE_AUX_MASK_CPT (7 << 25)
6134#define SDE_PORTE_HOTPLUG_SPT (1 << 25)
6135#define SDE_PORTA_HOTPLUG_SPT (1 << 24)
6136#define SDE_PORTD_HOTPLUG_CPT (1 << 23)
6137#define SDE_PORTC_HOTPLUG_CPT (1 << 22)
6138#define SDE_PORTB_HOTPLUG_CPT (1 << 21)
6139#define SDE_CRT_HOTPLUG_CPT (1 << 19)
6140#define SDE_SDVOB_HOTPLUG_CPT (1 << 18)
6141#define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \
6142 SDE_SDVOB_HOTPLUG_CPT | \
6143 SDE_PORTD_HOTPLUG_CPT | \
6144 SDE_PORTC_HOTPLUG_CPT | \
6145 SDE_PORTB_HOTPLUG_CPT)
6146#define SDE_HOTPLUG_MASK_SPT (SDE_PORTE_HOTPLUG_SPT | \
6147 SDE_PORTD_HOTPLUG_CPT | \
6148 SDE_PORTC_HOTPLUG_CPT | \
6149 SDE_PORTB_HOTPLUG_CPT | \
6150 SDE_PORTA_HOTPLUG_SPT)
6151#define SDE_GMBUS_CPT (1 << 17)
6152#define SDE_ERROR_CPT (1 << 16)
6153#define SDE_AUDIO_CP_REQ_C_CPT (1 << 10)
6154#define SDE_AUDIO_CP_CHG_C_CPT (1 << 9)
6155#define SDE_FDI_RXC_CPT (1 << 8)
6156#define SDE_AUDIO_CP_REQ_B_CPT (1 << 6)
6157#define SDE_AUDIO_CP_CHG_B_CPT (1 << 5)
6158#define SDE_FDI_RXB_CPT (1 << 4)
6159#define SDE_AUDIO_CP_REQ_A_CPT (1 << 2)
6160#define SDE_AUDIO_CP_CHG_A_CPT (1 << 1)
6161#define SDE_FDI_RXA_CPT (1 << 0)
6162#define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \
6163 SDE_AUDIO_CP_REQ_B_CPT | \
6164 SDE_AUDIO_CP_REQ_A_CPT)
6165#define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \
6166 SDE_AUDIO_CP_CHG_B_CPT | \
6167 SDE_AUDIO_CP_CHG_A_CPT)
6168#define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \
6169 SDE_FDI_RXB_CPT | \
6170 SDE_FDI_RXA_CPT)
6171
6172#define SDEISR _MMIO(0xc4000)
6173#define SDEIMR _MMIO(0xc4004)
6174#define SDEIIR _MMIO(0xc4008)
6175#define SDEIER _MMIO(0xc400c)
6176
6177#define SERR_INT _MMIO(0xc4040)
6178#define SERR_INT_POISON (1<<31)
6179#define SERR_INT_TRANS_C_FIFO_UNDERRUN (1<<6)
6180#define SERR_INT_TRANS_B_FIFO_UNDERRUN (1<<3)
6181#define SERR_INT_TRANS_A_FIFO_UNDERRUN (1<<0)
6182#define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1<<((pipe)*3))
6183
6184/* digital port hotplug */
6185#define PCH_PORT_HOTPLUG _MMIO(0xc4030) /* SHOTPLUG_CTL */
6186#define PORTA_HOTPLUG_ENABLE (1 << 28) /* LPT:LP+ & BXT */
6187#define PORTA_HOTPLUG_STATUS_MASK (3 << 24) /* SPT+ & BXT */
6188#define PORTA_HOTPLUG_NO_DETECT (0 << 24) /* SPT+ & BXT */
6189#define PORTA_HOTPLUG_SHORT_DETECT (1 << 24) /* SPT+ & BXT */
6190#define PORTA_HOTPLUG_LONG_DETECT (2 << 24) /* SPT+ & BXT */
6191#define PORTD_HOTPLUG_ENABLE (1 << 20)
6192#define PORTD_PULSE_DURATION_2ms (0 << 18) /* pre-LPT */
6193#define PORTD_PULSE_DURATION_4_5ms (1 << 18) /* pre-LPT */
6194#define PORTD_PULSE_DURATION_6ms (2 << 18) /* pre-LPT */
6195#define PORTD_PULSE_DURATION_100ms (3 << 18) /* pre-LPT */
6196#define PORTD_PULSE_DURATION_MASK (3 << 18) /* pre-LPT */
6197#define PORTD_HOTPLUG_STATUS_MASK (3 << 16)
6198#define PORTD_HOTPLUG_NO_DETECT (0 << 16)
6199#define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
6200#define PORTD_HOTPLUG_LONG_DETECT (2 << 16)
6201#define PORTC_HOTPLUG_ENABLE (1 << 12)
6202#define PORTC_PULSE_DURATION_2ms (0 << 10) /* pre-LPT */
6203#define PORTC_PULSE_DURATION_4_5ms (1 << 10) /* pre-LPT */
6204#define PORTC_PULSE_DURATION_6ms (2 << 10) /* pre-LPT */
6205#define PORTC_PULSE_DURATION_100ms (3 << 10) /* pre-LPT */
6206#define PORTC_PULSE_DURATION_MASK (3 << 10) /* pre-LPT */
6207#define PORTC_HOTPLUG_STATUS_MASK (3 << 8)
6208#define PORTC_HOTPLUG_NO_DETECT (0 << 8)
6209#define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
6210#define PORTC_HOTPLUG_LONG_DETECT (2 << 8)
6211#define PORTB_HOTPLUG_ENABLE (1 << 4)
6212#define PORTB_PULSE_DURATION_2ms (0 << 2) /* pre-LPT */
6213#define PORTB_PULSE_DURATION_4_5ms (1 << 2) /* pre-LPT */
6214#define PORTB_PULSE_DURATION_6ms (2 << 2) /* pre-LPT */
6215#define PORTB_PULSE_DURATION_100ms (3 << 2) /* pre-LPT */
6216#define PORTB_PULSE_DURATION_MASK (3 << 2) /* pre-LPT */
6217#define PORTB_HOTPLUG_STATUS_MASK (3 << 0)
6218#define PORTB_HOTPLUG_NO_DETECT (0 << 0)
6219#define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
6220#define PORTB_HOTPLUG_LONG_DETECT (2 << 0)
6221
6222#define PCH_PORT_HOTPLUG2 _MMIO(0xc403C) /* SHOTPLUG_CTL2 SPT+ */
6223#define PORTE_HOTPLUG_ENABLE (1 << 4)
6224#define PORTE_HOTPLUG_STATUS_MASK (3 << 0)
6225#define PORTE_HOTPLUG_NO_DETECT (0 << 0)
6226#define PORTE_HOTPLUG_SHORT_DETECT (1 << 0)
6227#define PORTE_HOTPLUG_LONG_DETECT (2 << 0)
6228
6229#define PCH_GPIOA _MMIO(0xc5010)
6230#define PCH_GPIOB _MMIO(0xc5014)
6231#define PCH_GPIOC _MMIO(0xc5018)
6232#define PCH_GPIOD _MMIO(0xc501c)
6233#define PCH_GPIOE _MMIO(0xc5020)
6234#define PCH_GPIOF _MMIO(0xc5024)
6235
6236#define PCH_GMBUS0 _MMIO(0xc5100)
6237#define PCH_GMBUS1 _MMIO(0xc5104)
6238#define PCH_GMBUS2 _MMIO(0xc5108)
6239#define PCH_GMBUS3 _MMIO(0xc510c)
6240#define PCH_GMBUS4 _MMIO(0xc5110)
6241#define PCH_GMBUS5 _MMIO(0xc5120)
6242
6243#define _PCH_DPLL_A 0xc6014
6244#define _PCH_DPLL_B 0xc6018
6245#define PCH_DPLL(pll) _MMIO(pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
6246
6247#define _PCH_FPA0 0xc6040
6248#define FP_CB_TUNE (0x3<<22)
6249#define _PCH_FPA1 0xc6044
6250#define _PCH_FPB0 0xc6048
6251#define _PCH_FPB1 0xc604c
6252#define PCH_FP0(pll) _MMIO(pll == 0 ? _PCH_FPA0 : _PCH_FPB0)
6253#define PCH_FP1(pll) _MMIO(pll == 0 ? _PCH_FPA1 : _PCH_FPB1)
6254
6255#define PCH_DPLL_TEST _MMIO(0xc606c)
6256
6257#define PCH_DREF_CONTROL _MMIO(0xC6200)
6258#define DREF_CONTROL_MASK 0x7fc3
6259#define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13)
6260#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13)
6261#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13)
6262#define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13)
6263#define DREF_SSC_SOURCE_DISABLE (0<<11)
6264#define DREF_SSC_SOURCE_ENABLE (2<<11)
6265#define DREF_SSC_SOURCE_MASK (3<<11)
6266#define DREF_NONSPREAD_SOURCE_DISABLE (0<<9)
6267#define DREF_NONSPREAD_CK505_ENABLE (1<<9)
6268#define DREF_NONSPREAD_SOURCE_ENABLE (2<<9)
6269#define DREF_NONSPREAD_SOURCE_MASK (3<<9)
6270#define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7)
6271#define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7)
6272#define DREF_SUPERSPREAD_SOURCE_MASK (3<<7)
6273#define DREF_SSC4_DOWNSPREAD (0<<6)
6274#define DREF_SSC4_CENTERSPREAD (1<<6)
6275#define DREF_SSC1_DISABLE (0<<1)
6276#define DREF_SSC1_ENABLE (1<<1)
6277#define DREF_SSC4_DISABLE (0)
6278#define DREF_SSC4_ENABLE (1)
6279
6280#define PCH_RAWCLK_FREQ _MMIO(0xc6204)
6281#define FDL_TP1_TIMER_SHIFT 12
6282#define FDL_TP1_TIMER_MASK (3<<12)
6283#define FDL_TP2_TIMER_SHIFT 10
6284#define FDL_TP2_TIMER_MASK (3<<10)
6285#define RAWCLK_FREQ_MASK 0x3ff
6286
6287#define PCH_DPLL_TMR_CFG _MMIO(0xc6208)
6288
6289#define PCH_SSC4_PARMS _MMIO(0xc6210)
6290#define PCH_SSC4_AUX_PARMS _MMIO(0xc6214)
6291
6292#define PCH_DPLL_SEL _MMIO(0xc7000)
6293#define TRANS_DPLLB_SEL(pipe) (1 << ((pipe) * 4))
6294#define TRANS_DPLLA_SEL(pipe) 0
6295#define TRANS_DPLL_ENABLE(pipe) (1 << ((pipe) * 4 + 3))
6296
6297/* transcoder */
6298
6299#define _PCH_TRANS_HTOTAL_A 0xe0000
6300#define TRANS_HTOTAL_SHIFT 16
6301#define TRANS_HACTIVE_SHIFT 0
6302#define _PCH_TRANS_HBLANK_A 0xe0004
6303#define TRANS_HBLANK_END_SHIFT 16
6304#define TRANS_HBLANK_START_SHIFT 0
6305#define _PCH_TRANS_HSYNC_A 0xe0008
6306#define TRANS_HSYNC_END_SHIFT 16
6307#define TRANS_HSYNC_START_SHIFT 0
6308#define _PCH_TRANS_VTOTAL_A 0xe000c
6309#define TRANS_VTOTAL_SHIFT 16
6310#define TRANS_VACTIVE_SHIFT 0
6311#define _PCH_TRANS_VBLANK_A 0xe0010
6312#define TRANS_VBLANK_END_SHIFT 16
6313#define TRANS_VBLANK_START_SHIFT 0
6314#define _PCH_TRANS_VSYNC_A 0xe0014
6315#define TRANS_VSYNC_END_SHIFT 16
6316#define TRANS_VSYNC_START_SHIFT 0
6317#define _PCH_TRANS_VSYNCSHIFT_A 0xe0028
6318
6319#define _PCH_TRANSA_DATA_M1 0xe0030
6320#define _PCH_TRANSA_DATA_N1 0xe0034
6321#define _PCH_TRANSA_DATA_M2 0xe0038
6322#define _PCH_TRANSA_DATA_N2 0xe003c
6323#define _PCH_TRANSA_LINK_M1 0xe0040
6324#define _PCH_TRANSA_LINK_N1 0xe0044
6325#define _PCH_TRANSA_LINK_M2 0xe0048
6326#define _PCH_TRANSA_LINK_N2 0xe004c
6327
6328/* Per-transcoder DIP controls (PCH) */
6329#define _VIDEO_DIP_CTL_A 0xe0200
6330#define _VIDEO_DIP_DATA_A 0xe0208
6331#define _VIDEO_DIP_GCP_A 0xe0210
6332#define GCP_COLOR_INDICATION (1 << 2)
6333#define GCP_DEFAULT_PHASE_ENABLE (1 << 1)
6334#define GCP_AV_MUTE (1 << 0)
6335
6336#define _VIDEO_DIP_CTL_B 0xe1200
6337#define _VIDEO_DIP_DATA_B 0xe1208
6338#define _VIDEO_DIP_GCP_B 0xe1210
6339
6340#define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
6341#define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
6342#define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
6343
6344/* Per-transcoder DIP controls (VLV) */
6345#define _VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200)
6346#define _VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208)
6347#define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210)
6348
6349#define _VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170)
6350#define _VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174)
6351#define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178)
6352
6353#define _CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0)
6354#define _CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4)
6355#define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8)
6356
6357#define VLV_TVIDEO_DIP_CTL(pipe) \
6358 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_CTL_A, \
6359 _VLV_VIDEO_DIP_CTL_B, _CHV_VIDEO_DIP_CTL_C)
6360#define VLV_TVIDEO_DIP_DATA(pipe) \
6361 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_DATA_A, \
6362 _VLV_VIDEO_DIP_DATA_B, _CHV_VIDEO_DIP_DATA_C)
6363#define VLV_TVIDEO_DIP_GCP(pipe) \
6364 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \
6365 _VLV_VIDEO_DIP_GDCP_PAYLOAD_B, _CHV_VIDEO_DIP_GDCP_PAYLOAD_C)
6366
6367/* Haswell DIP controls */
6368
6369#define _HSW_VIDEO_DIP_CTL_A 0x60200
6370#define _HSW_VIDEO_DIP_AVI_DATA_A 0x60220
6371#define _HSW_VIDEO_DIP_VS_DATA_A 0x60260
6372#define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0
6373#define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0
6374#define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320
6375#define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240
6376#define _HSW_VIDEO_DIP_VS_ECC_A 0x60280
6377#define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0
6378#define _HSW_VIDEO_DIP_GMP_ECC_A 0x60300
6379#define _HSW_VIDEO_DIP_VSC_ECC_A 0x60344
6380#define _HSW_VIDEO_DIP_GCP_A 0x60210
6381
6382#define _HSW_VIDEO_DIP_CTL_B 0x61200
6383#define _HSW_VIDEO_DIP_AVI_DATA_B 0x61220
6384#define _HSW_VIDEO_DIP_VS_DATA_B 0x61260
6385#define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0
6386#define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0
6387#define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320
6388#define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240
6389#define _HSW_VIDEO_DIP_VS_ECC_B 0x61280
6390#define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0
6391#define _HSW_VIDEO_DIP_GMP_ECC_B 0x61300
6392#define _HSW_VIDEO_DIP_VSC_ECC_B 0x61344
6393#define _HSW_VIDEO_DIP_GCP_B 0x61210
6394
6395#define HSW_TVIDEO_DIP_CTL(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_CTL_A)
6396#define HSW_TVIDEO_DIP_AVI_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4)
6397#define HSW_TVIDEO_DIP_VS_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4)
6398#define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4)
6399#define HSW_TVIDEO_DIP_GCP(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GCP_A)
6400#define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4)
6401
6402#define _HSW_STEREO_3D_CTL_A 0x70020
6403#define S3D_ENABLE (1<<31)
6404#define _HSW_STEREO_3D_CTL_B 0x71020
6405
6406#define HSW_STEREO_3D_CTL(trans) _MMIO_PIPE2(trans, _HSW_STEREO_3D_CTL_A)
6407
6408#define _PCH_TRANS_HTOTAL_B 0xe1000
6409#define _PCH_TRANS_HBLANK_B 0xe1004
6410#define _PCH_TRANS_HSYNC_B 0xe1008
6411#define _PCH_TRANS_VTOTAL_B 0xe100c
6412#define _PCH_TRANS_VBLANK_B 0xe1010
6413#define _PCH_TRANS_VSYNC_B 0xe1014
6414#define _PCH_TRANS_VSYNCSHIFT_B 0xe1028
6415
6416#define PCH_TRANS_HTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
6417#define PCH_TRANS_HBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
6418#define PCH_TRANS_HSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
6419#define PCH_TRANS_VTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
6420#define PCH_TRANS_VBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
6421#define PCH_TRANS_VSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
6422#define PCH_TRANS_VSYNCSHIFT(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B)
6423
6424#define _PCH_TRANSB_DATA_M1 0xe1030
6425#define _PCH_TRANSB_DATA_N1 0xe1034
6426#define _PCH_TRANSB_DATA_M2 0xe1038
6427#define _PCH_TRANSB_DATA_N2 0xe103c
6428#define _PCH_TRANSB_LINK_M1 0xe1040
6429#define _PCH_TRANSB_LINK_N1 0xe1044
6430#define _PCH_TRANSB_LINK_M2 0xe1048
6431#define _PCH_TRANSB_LINK_N2 0xe104c
6432
6433#define PCH_TRANS_DATA_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
6434#define PCH_TRANS_DATA_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
6435#define PCH_TRANS_DATA_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
6436#define PCH_TRANS_DATA_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
6437#define PCH_TRANS_LINK_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
6438#define PCH_TRANS_LINK_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
6439#define PCH_TRANS_LINK_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
6440#define PCH_TRANS_LINK_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
6441
6442#define _PCH_TRANSACONF 0xf0008
6443#define _PCH_TRANSBCONF 0xf1008
6444#define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
6445#define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */
6446#define TRANS_DISABLE (0<<31)
6447#define TRANS_ENABLE (1<<31)
6448#define TRANS_STATE_MASK (1<<30)
6449#define TRANS_STATE_DISABLE (0<<30)
6450#define TRANS_STATE_ENABLE (1<<30)
6451#define TRANS_FSYNC_DELAY_HB1 (0<<27)
6452#define TRANS_FSYNC_DELAY_HB2 (1<<27)
6453#define TRANS_FSYNC_DELAY_HB3 (2<<27)
6454#define TRANS_FSYNC_DELAY_HB4 (3<<27)
6455#define TRANS_INTERLACE_MASK (7<<21)
6456#define TRANS_PROGRESSIVE (0<<21)
6457#define TRANS_INTERLACED (3<<21)
6458#define TRANS_LEGACY_INTERLACED_ILK (2<<21)
6459#define TRANS_8BPC (0<<5)
6460#define TRANS_10BPC (1<<5)
6461#define TRANS_6BPC (2<<5)
6462#define TRANS_12BPC (3<<5)
6463
6464#define _TRANSA_CHICKEN1 0xf0060
6465#define _TRANSB_CHICKEN1 0xf1060
6466#define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
6467#define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE (1<<10)
6468#define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1<<4)
6469#define _TRANSA_CHICKEN2 0xf0064
6470#define _TRANSB_CHICKEN2 0xf1064
6471#define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
6472#define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31)
6473#define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1<<29)
6474#define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3<<27)
6475#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1<<26)
6476#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1<<25)
6477
6478#define SOUTH_CHICKEN1 _MMIO(0xc2000)
6479#define FDIA_PHASE_SYNC_SHIFT_OVR 19
6480#define FDIA_PHASE_SYNC_SHIFT_EN 18
6481#define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
6482#define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
6483#define FDI_BC_BIFURCATION_SELECT (1 << 12)
6484#define SPT_PWM_GRANULARITY (1<<0)
6485#define SOUTH_CHICKEN2 _MMIO(0xc2004)
6486#define FDI_MPHY_IOSFSB_RESET_STATUS (1<<13)
6487#define FDI_MPHY_IOSFSB_RESET_CTL (1<<12)
6488#define LPT_PWM_GRANULARITY (1<<5)
6489#define DPLS_EDP_PPS_FIX_DIS (1<<0)
6490
6491#define _FDI_RXA_CHICKEN 0xc200c
6492#define _FDI_RXB_CHICKEN 0xc2010
6493#define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1)
6494#define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0)
6495#define FDI_RX_CHICKEN(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
6496
6497#define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020)
6498#define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30)
6499#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
6500#define PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14)
6501#define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12)
6502
6503/* CPU: FDI_TX */
6504#define _FDI_TXA_CTL 0x60100
6505#define _FDI_TXB_CTL 0x61100
6506#define FDI_TX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
6507#define FDI_TX_DISABLE (0<<31)
6508#define FDI_TX_ENABLE (1<<31)
6509#define FDI_LINK_TRAIN_PATTERN_1 (0<<28)
6510#define FDI_LINK_TRAIN_PATTERN_2 (1<<28)
6511#define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28)
6512#define FDI_LINK_TRAIN_NONE (3<<28)
6513#define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25)
6514#define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25)
6515#define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25)
6516#define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25)
6517#define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22)
6518#define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
6519#define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22)
6520#define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22)
6521/* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
6522 SNB has different settings. */
6523/* SNB A-stepping */
6524#define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
6525#define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
6526#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
6527#define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
6528/* SNB B-stepping */
6529#define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22)
6530#define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22)
6531#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22)
6532#define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22)
6533#define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22)
6534#define FDI_DP_PORT_WIDTH_SHIFT 19
6535#define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT)
6536#define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT)
6537#define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18)
6538/* Ironlake: hardwired to 1 */
6539#define FDI_TX_PLL_ENABLE (1<<14)
6540
6541/* Ivybridge has different bits for lolz */
6542#define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8)
6543#define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8)
6544#define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8)
6545#define FDI_LINK_TRAIN_NONE_IVB (3<<8)
6546
6547/* both Tx and Rx */
6548#define FDI_COMPOSITE_SYNC (1<<11)
6549#define FDI_LINK_TRAIN_AUTO (1<<10)
6550#define FDI_SCRAMBLING_ENABLE (0<<7)
6551#define FDI_SCRAMBLING_DISABLE (1<<7)
6552
6553/* FDI_RX, FDI_X is hard-wired to Transcoder_X */
6554#define _FDI_RXA_CTL 0xf000c
6555#define _FDI_RXB_CTL 0xf100c
6556#define FDI_RX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
6557#define FDI_RX_ENABLE (1<<31)
6558/* train, dp width same as FDI_TX */
6559#define FDI_FS_ERRC_ENABLE (1<<27)
6560#define FDI_FE_ERRC_ENABLE (1<<26)
6561#define FDI_RX_POLARITY_REVERSED_LPT (1<<16)
6562#define FDI_8BPC (0<<16)
6563#define FDI_10BPC (1<<16)
6564#define FDI_6BPC (2<<16)
6565#define FDI_12BPC (3<<16)
6566#define FDI_RX_LINK_REVERSAL_OVERRIDE (1<<15)
6567#define FDI_DMI_LINK_REVERSE_MASK (1<<14)
6568#define FDI_RX_PLL_ENABLE (1<<13)
6569#define FDI_FS_ERR_CORRECT_ENABLE (1<<11)
6570#define FDI_FE_ERR_CORRECT_ENABLE (1<<10)
6571#define FDI_FS_ERR_REPORT_ENABLE (1<<9)
6572#define FDI_FE_ERR_REPORT_ENABLE (1<<8)
6573#define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6)
6574#define FDI_PCDCLK (1<<4)
6575/* CPT */
6576#define FDI_AUTO_TRAINING (1<<10)
6577#define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8)
6578#define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8)
6579#define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8)
6580#define FDI_LINK_TRAIN_NORMAL_CPT (3<<8)
6581#define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8)
6582
6583#define _FDI_RXA_MISC 0xf0010
6584#define _FDI_RXB_MISC 0xf1010
6585#define FDI_RX_PWRDN_LANE1_MASK (3<<26)
6586#define FDI_RX_PWRDN_LANE1_VAL(x) ((x)<<26)
6587#define FDI_RX_PWRDN_LANE0_MASK (3<<24)
6588#define FDI_RX_PWRDN_LANE0_VAL(x) ((x)<<24)
6589#define FDI_RX_TP1_TO_TP2_48 (2<<20)
6590#define FDI_RX_TP1_TO_TP2_64 (3<<20)
6591#define FDI_RX_FDI_DELAY_90 (0x90<<0)
6592#define FDI_RX_MISC(pipe) _MMIO_PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
6593
6594#define _FDI_RXA_TUSIZE1 0xf0030
6595#define _FDI_RXA_TUSIZE2 0xf0038
6596#define _FDI_RXB_TUSIZE1 0xf1030
6597#define _FDI_RXB_TUSIZE2 0xf1038
6598#define FDI_RX_TUSIZE1(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
6599#define FDI_RX_TUSIZE2(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
6600
6601/* FDI_RX interrupt register format */
6602#define FDI_RX_INTER_LANE_ALIGN (1<<10)
6603#define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */
6604#define FDI_RX_BIT_LOCK (1<<8) /* train 1 */
6605#define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7)
6606#define FDI_RX_FS_CODE_ERR (1<<6)
6607#define FDI_RX_FE_CODE_ERR (1<<5)
6608#define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4)
6609#define FDI_RX_HDCP_LINK_FAIL (1<<3)
6610#define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2)
6611#define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1)
6612#define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0)
6613
6614#define _FDI_RXA_IIR 0xf0014
6615#define _FDI_RXA_IMR 0xf0018
6616#define _FDI_RXB_IIR 0xf1014
6617#define _FDI_RXB_IMR 0xf1018
6618#define FDI_RX_IIR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
6619#define FDI_RX_IMR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
6620
6621#define FDI_PLL_CTL_1 _MMIO(0xfe000)
6622#define FDI_PLL_CTL_2 _MMIO(0xfe004)
6623
6624#define PCH_LVDS _MMIO(0xe1180)
6625#define LVDS_DETECTED (1 << 1)
6626
6627/* vlv has 2 sets of panel control regs. */
6628#define _PIPEA_PP_STATUS (VLV_DISPLAY_BASE + 0x61200)
6629#define _PIPEA_PP_CONTROL (VLV_DISPLAY_BASE + 0x61204)
6630#define _PIPEA_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61208)
6631#define PANEL_PORT_SELECT_VLV(port) ((port) << 30)
6632#define _PIPEA_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6120c)
6633#define _PIPEA_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61210)
6634
6635#define _PIPEB_PP_STATUS (VLV_DISPLAY_BASE + 0x61300)
6636#define _PIPEB_PP_CONTROL (VLV_DISPLAY_BASE + 0x61304)
6637#define _PIPEB_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61308)
6638#define _PIPEB_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6130c)
6639#define _PIPEB_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61310)
6640
6641#define VLV_PIPE_PP_STATUS(pipe) _MMIO_PIPE(pipe, _PIPEA_PP_STATUS, _PIPEB_PP_STATUS)
6642#define VLV_PIPE_PP_CONTROL(pipe) _MMIO_PIPE(pipe, _PIPEA_PP_CONTROL, _PIPEB_PP_CONTROL)
6643#define VLV_PIPE_PP_ON_DELAYS(pipe) _MMIO_PIPE(pipe, _PIPEA_PP_ON_DELAYS, _PIPEB_PP_ON_DELAYS)
6644#define VLV_PIPE_PP_OFF_DELAYS(pipe) _MMIO_PIPE(pipe, _PIPEA_PP_OFF_DELAYS, _PIPEB_PP_OFF_DELAYS)
6645#define VLV_PIPE_PP_DIVISOR(pipe) _MMIO_PIPE(pipe, _PIPEA_PP_DIVISOR, _PIPEB_PP_DIVISOR)
6646
6647#define _PCH_PP_STATUS 0xc7200
6648#define _PCH_PP_CONTROL 0xc7204
6649#define PANEL_UNLOCK_REGS (0xabcd << 16)
6650#define PANEL_UNLOCK_MASK (0xffff << 16)
6651#define BXT_POWER_CYCLE_DELAY_MASK (0x1f0)
6652#define BXT_POWER_CYCLE_DELAY_SHIFT 4
6653#define EDP_FORCE_VDD (1 << 3)
6654#define EDP_BLC_ENABLE (1 << 2)
6655#define PANEL_POWER_RESET (1 << 1)
6656#define PANEL_POWER_OFF (0 << 0)
6657#define PANEL_POWER_ON (1 << 0)
6658#define _PCH_PP_ON_DELAYS 0xc7208
6659#define PANEL_PORT_SELECT_MASK (3 << 30)
6660#define PANEL_PORT_SELECT_LVDS (0 << 30)
6661#define PANEL_PORT_SELECT_DPA (1 << 30)
6662#define PANEL_PORT_SELECT_DPC (2 << 30)
6663#define PANEL_PORT_SELECT_DPD (3 << 30)
6664#define PANEL_POWER_UP_DELAY_MASK (0x1fff0000)
6665#define PANEL_POWER_UP_DELAY_SHIFT 16
6666#define PANEL_LIGHT_ON_DELAY_MASK (0x1fff)
6667#define PANEL_LIGHT_ON_DELAY_SHIFT 0
6668
6669#define _PCH_PP_OFF_DELAYS 0xc720c
6670#define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000)
6671#define PANEL_POWER_DOWN_DELAY_SHIFT 16
6672#define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff)
6673#define PANEL_LIGHT_OFF_DELAY_SHIFT 0
6674
6675#define _PCH_PP_DIVISOR 0xc7210
6676#define PP_REFERENCE_DIVIDER_MASK (0xffffff00)
6677#define PP_REFERENCE_DIVIDER_SHIFT 8
6678#define PANEL_POWER_CYCLE_DELAY_MASK (0x1f)
6679#define PANEL_POWER_CYCLE_DELAY_SHIFT 0
6680
6681#define PCH_PP_STATUS _MMIO(_PCH_PP_STATUS)
6682#define PCH_PP_CONTROL _MMIO(_PCH_PP_CONTROL)
6683#define PCH_PP_ON_DELAYS _MMIO(_PCH_PP_ON_DELAYS)
6684#define PCH_PP_OFF_DELAYS _MMIO(_PCH_PP_OFF_DELAYS)
6685#define PCH_PP_DIVISOR _MMIO(_PCH_PP_DIVISOR)
6686
6687/* BXT PPS changes - 2nd set of PPS registers */
6688#define _BXT_PP_STATUS2 0xc7300
6689#define _BXT_PP_CONTROL2 0xc7304
6690#define _BXT_PP_ON_DELAYS2 0xc7308
6691#define _BXT_PP_OFF_DELAYS2 0xc730c
6692
6693#define BXT_PP_STATUS(n) _MMIO_PIPE(n, _PCH_PP_STATUS, _BXT_PP_STATUS2)
6694#define BXT_PP_CONTROL(n) _MMIO_PIPE(n, _PCH_PP_CONTROL, _BXT_PP_CONTROL2)
6695#define BXT_PP_ON_DELAYS(n) _MMIO_PIPE(n, _PCH_PP_ON_DELAYS, _BXT_PP_ON_DELAYS2)
6696#define BXT_PP_OFF_DELAYS(n) _MMIO_PIPE(n, _PCH_PP_OFF_DELAYS, _BXT_PP_OFF_DELAYS2)
6697
6698#define _PCH_DP_B 0xe4100
6699#define PCH_DP_B _MMIO(_PCH_DP_B)
6700#define _PCH_DPB_AUX_CH_CTL 0xe4110
6701#define _PCH_DPB_AUX_CH_DATA1 0xe4114
6702#define _PCH_DPB_AUX_CH_DATA2 0xe4118
6703#define _PCH_DPB_AUX_CH_DATA3 0xe411c
6704#define _PCH_DPB_AUX_CH_DATA4 0xe4120
6705#define _PCH_DPB_AUX_CH_DATA5 0xe4124
6706
6707#define _PCH_DP_C 0xe4200
6708#define PCH_DP_C _MMIO(_PCH_DP_C)
6709#define _PCH_DPC_AUX_CH_CTL 0xe4210
6710#define _PCH_DPC_AUX_CH_DATA1 0xe4214
6711#define _PCH_DPC_AUX_CH_DATA2 0xe4218
6712#define _PCH_DPC_AUX_CH_DATA3 0xe421c
6713#define _PCH_DPC_AUX_CH_DATA4 0xe4220
6714#define _PCH_DPC_AUX_CH_DATA5 0xe4224
6715
6716#define _PCH_DP_D 0xe4300
6717#define PCH_DP_D _MMIO(_PCH_DP_D)
6718#define _PCH_DPD_AUX_CH_CTL 0xe4310
6719#define _PCH_DPD_AUX_CH_DATA1 0xe4314
6720#define _PCH_DPD_AUX_CH_DATA2 0xe4318
6721#define _PCH_DPD_AUX_CH_DATA3 0xe431c
6722#define _PCH_DPD_AUX_CH_DATA4 0xe4320
6723#define _PCH_DPD_AUX_CH_DATA5 0xe4324
6724
6725#define PCH_DP_AUX_CH_CTL(port) _MMIO_PORT((port) - PORT_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL)
6726#define PCH_DP_AUX_CH_DATA(port, i) _MMIO(_PORT((port) - PORT_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
6727
6728/* CPT */
6729#define PORT_TRANS_A_SEL_CPT 0
6730#define PORT_TRANS_B_SEL_CPT (1<<29)
6731#define PORT_TRANS_C_SEL_CPT (2<<29)
6732#define PORT_TRANS_SEL_MASK (3<<29)
6733#define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29)
6734#define PORT_TO_PIPE(val) (((val) & (1<<30)) >> 30)
6735#define PORT_TO_PIPE_CPT(val) (((val) & PORT_TRANS_SEL_MASK) >> 29)
6736#define SDVO_PORT_TO_PIPE_CHV(val) (((val) & (3<<24)) >> 24)
6737#define DP_PORT_TO_PIPE_CHV(val) (((val) & (3<<16)) >> 16)
6738
6739#define _TRANS_DP_CTL_A 0xe0300
6740#define _TRANS_DP_CTL_B 0xe1300
6741#define _TRANS_DP_CTL_C 0xe2300
6742#define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B)
6743#define TRANS_DP_OUTPUT_ENABLE (1<<31)
6744#define TRANS_DP_PORT_SEL_B (0<<29)
6745#define TRANS_DP_PORT_SEL_C (1<<29)
6746#define TRANS_DP_PORT_SEL_D (2<<29)
6747#define TRANS_DP_PORT_SEL_NONE (3<<29)
6748#define TRANS_DP_PORT_SEL_MASK (3<<29)
6749#define TRANS_DP_PIPE_TO_PORT(val) ((((val) & TRANS_DP_PORT_SEL_MASK) >> 29) + PORT_B)
6750#define TRANS_DP_AUDIO_ONLY (1<<26)
6751#define TRANS_DP_ENH_FRAMING (1<<18)
6752#define TRANS_DP_8BPC (0<<9)
6753#define TRANS_DP_10BPC (1<<9)
6754#define TRANS_DP_6BPC (2<<9)
6755#define TRANS_DP_12BPC (3<<9)
6756#define TRANS_DP_BPC_MASK (3<<9)
6757#define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4)
6758#define TRANS_DP_VSYNC_ACTIVE_LOW 0
6759#define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3)
6760#define TRANS_DP_HSYNC_ACTIVE_LOW 0
6761#define TRANS_DP_SYNC_MASK (3<<3)
6762
6763/* SNB eDP training params */
6764/* SNB A-stepping */
6765#define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
6766#define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
6767#define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
6768#define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
6769/* SNB B-stepping */
6770#define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22)
6771#define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22)
6772#define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22)
6773#define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22)
6774#define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22)
6775#define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22)
6776
6777/* IVB */
6778#define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 <<22)
6779#define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a <<22)
6780#define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f <<22)
6781#define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 <<22)
6782#define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 <<22)
6783#define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 <<22)
6784#define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e <<22)
6785
6786/* legacy values */
6787#define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 <<22)
6788#define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 <<22)
6789#define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 <<22)
6790#define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 <<22)
6791#define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 <<22)
6792
6793#define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22)
6794
6795#define VLV_PMWGICZ _MMIO(0x1300a4)
6796
6797#define RC6_LOCATION _MMIO(0xD40)
6798#define RC6_CTX_IN_DRAM (1 << 0)
6799#define RC6_CTX_BASE _MMIO(0xD48)
6800#define RC6_CTX_BASE_MASK 0xFFFFFFF0
6801#define PWRCTX_MAXCNT_RCSUNIT _MMIO(0x2054)
6802#define PWRCTX_MAXCNT_VCSUNIT0 _MMIO(0x12054)
6803#define PWRCTX_MAXCNT_BCSUNIT _MMIO(0x22054)
6804#define PWRCTX_MAXCNT_VECSUNIT _MMIO(0x1A054)
6805#define PWRCTX_MAXCNT_VCSUNIT1 _MMIO(0x1C054)
6806#define IDLE_TIME_MASK 0xFFFFF
6807#define FORCEWAKE _MMIO(0xA18C)
6808#define FORCEWAKE_VLV _MMIO(0x1300b0)
6809#define FORCEWAKE_ACK_VLV _MMIO(0x1300b4)
6810#define FORCEWAKE_MEDIA_VLV _MMIO(0x1300b8)
6811#define FORCEWAKE_ACK_MEDIA_VLV _MMIO(0x1300bc)
6812#define FORCEWAKE_ACK_HSW _MMIO(0x130044)
6813#define FORCEWAKE_ACK _MMIO(0x130090)
6814#define VLV_GTLC_WAKE_CTRL _MMIO(0x130090)
6815#define VLV_GTLC_RENDER_CTX_EXISTS (1 << 25)
6816#define VLV_GTLC_MEDIA_CTX_EXISTS (1 << 24)
6817#define VLV_GTLC_ALLOWWAKEREQ (1 << 0)
6818
6819#define VLV_GTLC_PW_STATUS _MMIO(0x130094)
6820#define VLV_GTLC_ALLOWWAKEACK (1 << 0)
6821#define VLV_GTLC_ALLOWWAKEERR (1 << 1)
6822#define VLV_GTLC_PW_MEDIA_STATUS_MASK (1 << 5)
6823#define VLV_GTLC_PW_RENDER_STATUS_MASK (1 << 7)
6824#define FORCEWAKE_MT _MMIO(0xa188) /* multi-threaded */
6825#define FORCEWAKE_MEDIA_GEN9 _MMIO(0xa270)
6826#define FORCEWAKE_RENDER_GEN9 _MMIO(0xa278)
6827#define FORCEWAKE_BLITTER_GEN9 _MMIO(0xa188)
6828#define FORCEWAKE_ACK_MEDIA_GEN9 _MMIO(0x0D88)
6829#define FORCEWAKE_ACK_RENDER_GEN9 _MMIO(0x0D84)
6830#define FORCEWAKE_ACK_BLITTER_GEN9 _MMIO(0x130044)
6831#define FORCEWAKE_KERNEL 0x1
6832#define FORCEWAKE_USER 0x2
6833#define FORCEWAKE_MT_ACK _MMIO(0x130040)
6834#define ECOBUS _MMIO(0xa180)
6835#define FORCEWAKE_MT_ENABLE (1<<5)
6836#define VLV_SPAREG2H _MMIO(0xA194)
6837
6838#define GTFIFODBG _MMIO(0x120000)
6839#define GT_FIFO_SBDROPERR (1<<6)
6840#define GT_FIFO_BLOBDROPERR (1<<5)
6841#define GT_FIFO_SB_READ_ABORTERR (1<<4)
6842#define GT_FIFO_DROPERR (1<<3)
6843#define GT_FIFO_OVFERR (1<<2)
6844#define GT_FIFO_IAWRERR (1<<1)
6845#define GT_FIFO_IARDERR (1<<0)
6846
6847#define GTFIFOCTL _MMIO(0x120008)
6848#define GT_FIFO_FREE_ENTRIES_MASK 0x7f
6849#define GT_FIFO_NUM_RESERVED_ENTRIES 20
6850#define GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL (1 << 12)
6851#define GT_FIFO_CTL_RC6_POLICY_STALL (1 << 11)
6852
6853#define HSW_IDICR _MMIO(0x9008)
6854#define IDIHASHMSK(x) (((x) & 0x3f) << 16)
6855#define HSW_EDRAM_PRESENT _MMIO(0x120010)
6856#define EDRAM_ENABLED 0x1
6857
6858#define GEN6_UCGCTL1 _MMIO(0x9400)
6859# define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE (1 << 16)
6860# define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5)
6861# define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7)
6862
6863#define GEN6_UCGCTL2 _MMIO(0x9404)
6864# define GEN6_VFUNIT_CLOCK_GATE_DISABLE (1 << 31)
6865# define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30)
6866# define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22)
6867# define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13)
6868# define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12)
6869# define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11)
6870
6871#define GEN6_UCGCTL3 _MMIO(0x9408)
6872
6873#define GEN7_UCGCTL4 _MMIO(0x940c)
6874#define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1<<25)
6875
6876#define GEN6_RCGCTL1 _MMIO(0x9410)
6877#define GEN6_RCGCTL2 _MMIO(0x9414)
6878#define GEN6_RSTCTL _MMIO(0x9420)
6879
6880#define GEN8_UCGCTL6 _MMIO(0x9430)
6881#define GEN8_GAPSUNIT_CLOCK_GATE_DISABLE (1<<24)
6882#define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1<<14)
6883#define GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1<<28)
6884
6885#define GEN6_GFXPAUSE _MMIO(0xA000)
6886#define GEN6_RPNSWREQ _MMIO(0xA008)
6887#define GEN6_TURBO_DISABLE (1<<31)
6888#define GEN6_FREQUENCY(x) ((x)<<25)
6889#define HSW_FREQUENCY(x) ((x)<<24)
6890#define GEN9_FREQUENCY(x) ((x)<<23)
6891#define GEN6_OFFSET(x) ((x)<<19)
6892#define GEN6_AGGRESSIVE_TURBO (0<<15)
6893#define GEN6_RC_VIDEO_FREQ _MMIO(0xA00C)
6894#define GEN6_RC_CONTROL _MMIO(0xA090)
6895#define GEN6_RC_CTL_RC6pp_ENABLE (1<<16)
6896#define GEN6_RC_CTL_RC6p_ENABLE (1<<17)
6897#define GEN6_RC_CTL_RC6_ENABLE (1<<18)
6898#define GEN6_RC_CTL_RC1e_ENABLE (1<<20)
6899#define GEN6_RC_CTL_RC7_ENABLE (1<<22)
6900#define VLV_RC_CTL_CTX_RST_PARALLEL (1<<24)
6901#define GEN7_RC_CTL_TO_MODE (1<<28)
6902#define GEN6_RC_CTL_EI_MODE(x) ((x)<<27)
6903#define GEN6_RC_CTL_HW_ENABLE (1<<31)
6904#define GEN6_RP_DOWN_TIMEOUT _MMIO(0xA010)
6905#define GEN6_RP_INTERRUPT_LIMITS _MMIO(0xA014)
6906#define GEN6_RPSTAT1 _MMIO(0xA01C)
6907#define GEN6_CAGF_SHIFT 8
6908#define HSW_CAGF_SHIFT 7
6909#define GEN9_CAGF_SHIFT 23
6910#define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT)
6911#define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT)
6912#define GEN9_CAGF_MASK (0x1ff << GEN9_CAGF_SHIFT)
6913#define GEN6_RP_CONTROL _MMIO(0xA024)
6914#define GEN6_RP_MEDIA_TURBO (1<<11)
6915#define GEN6_RP_MEDIA_MODE_MASK (3<<9)
6916#define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9)
6917#define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9)
6918#define GEN6_RP_MEDIA_HW_MODE (1<<9)
6919#define GEN6_RP_MEDIA_SW_MODE (0<<9)
6920#define GEN6_RP_MEDIA_IS_GFX (1<<8)
6921#define GEN6_RP_ENABLE (1<<7)
6922#define GEN6_RP_UP_IDLE_MIN (0x1<<3)
6923#define GEN6_RP_UP_BUSY_AVG (0x2<<3)
6924#define GEN6_RP_UP_BUSY_CONT (0x4<<3)
6925#define GEN6_RP_DOWN_IDLE_AVG (0x2<<0)
6926#define GEN6_RP_DOWN_IDLE_CONT (0x1<<0)
6927#define GEN6_RP_UP_THRESHOLD _MMIO(0xA02C)
6928#define GEN6_RP_DOWN_THRESHOLD _MMIO(0xA030)
6929#define GEN6_RP_CUR_UP_EI _MMIO(0xA050)
6930#define GEN6_CURICONT_MASK 0xffffff
6931#define GEN6_RP_CUR_UP _MMIO(0xA054)
6932#define GEN6_CURBSYTAVG_MASK 0xffffff
6933#define GEN6_RP_PREV_UP _MMIO(0xA058)
6934#define GEN6_RP_CUR_DOWN_EI _MMIO(0xA05C)
6935#define GEN6_CURIAVG_MASK 0xffffff
6936#define GEN6_RP_CUR_DOWN _MMIO(0xA060)
6937#define GEN6_RP_PREV_DOWN _MMIO(0xA064)
6938#define GEN6_RP_UP_EI _MMIO(0xA068)
6939#define GEN6_RP_DOWN_EI _MMIO(0xA06C)
6940#define GEN6_RP_IDLE_HYSTERSIS _MMIO(0xA070)
6941#define GEN6_RPDEUHWTC _MMIO(0xA080)
6942#define GEN6_RPDEUC _MMIO(0xA084)
6943#define GEN6_RPDEUCSW _MMIO(0xA088)
6944#define GEN6_RC_STATE _MMIO(0xA094)
6945#define RC6_STATE (1 << 18)
6946#define GEN6_RC1_WAKE_RATE_LIMIT _MMIO(0xA098)
6947#define GEN6_RC6_WAKE_RATE_LIMIT _MMIO(0xA09C)
6948#define GEN6_RC6pp_WAKE_RATE_LIMIT _MMIO(0xA0A0)
6949#define GEN6_RC_EVALUATION_INTERVAL _MMIO(0xA0A8)
6950#define GEN6_RC_IDLE_HYSTERSIS _MMIO(0xA0AC)
6951#define GEN6_RC_SLEEP _MMIO(0xA0B0)
6952#define GEN6_RCUBMABDTMR _MMIO(0xA0B0)
6953#define GEN6_RC1e_THRESHOLD _MMIO(0xA0B4)
6954#define GEN6_RC6_THRESHOLD _MMIO(0xA0B8)
6955#define GEN6_RC6p_THRESHOLD _MMIO(0xA0BC)
6956#define VLV_RCEDATA _MMIO(0xA0BC)
6957#define GEN6_RC6pp_THRESHOLD _MMIO(0xA0C0)
6958#define GEN6_PMINTRMSK _MMIO(0xA168)
6959#define GEN8_PMINTR_REDIRECT_TO_NON_DISP (1<<31)
6960#define VLV_PWRDWNUPCTL _MMIO(0xA294)
6961#define GEN9_MEDIA_PG_IDLE_HYSTERESIS _MMIO(0xA0C4)
6962#define GEN9_RENDER_PG_IDLE_HYSTERESIS _MMIO(0xA0C8)
6963#define GEN9_PG_ENABLE _MMIO(0xA210)
6964#define GEN9_RENDER_PG_ENABLE (1<<0)
6965#define GEN9_MEDIA_PG_ENABLE (1<<1)
6966
6967#define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C)
6968#define PIXEL_OVERLAP_CNT_MASK (3 << 30)
6969#define PIXEL_OVERLAP_CNT_SHIFT 30
6970
6971#define GEN6_PMISR _MMIO(0x44020)
6972#define GEN6_PMIMR _MMIO(0x44024) /* rps_lock */
6973#define GEN6_PMIIR _MMIO(0x44028)
6974#define GEN6_PMIER _MMIO(0x4402C)
6975#define GEN6_PM_MBOX_EVENT (1<<25)
6976#define GEN6_PM_THERMAL_EVENT (1<<24)
6977#define GEN6_PM_RP_DOWN_TIMEOUT (1<<6)
6978#define GEN6_PM_RP_UP_THRESHOLD (1<<5)
6979#define GEN6_PM_RP_DOWN_THRESHOLD (1<<4)
6980#define GEN6_PM_RP_UP_EI_EXPIRED (1<<2)
6981#define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1)
6982#define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \
6983 GEN6_PM_RP_DOWN_THRESHOLD | \
6984 GEN6_PM_RP_DOWN_TIMEOUT)
6985
6986#define GEN7_GT_SCRATCH(i) _MMIO(0x4F100 + (i) * 4)
6987#define GEN7_GT_SCRATCH_REG_NUM 8
6988
6989#define VLV_GTLC_SURVIVABILITY_REG _MMIO(0x130098)
6990#define VLV_GFX_CLK_STATUS_BIT (1<<3)
6991#define VLV_GFX_CLK_FORCE_ON_BIT (1<<2)
6992
6993#define GEN6_GT_GFX_RC6_LOCKED _MMIO(0x138104)
6994#define VLV_COUNTER_CONTROL _MMIO(0x138104)
6995#define VLV_COUNT_RANGE_HIGH (1<<15)
6996#define VLV_MEDIA_RC0_COUNT_EN (1<<5)
6997#define VLV_RENDER_RC0_COUNT_EN (1<<4)
6998#define VLV_MEDIA_RC6_COUNT_EN (1<<1)
6999#define VLV_RENDER_RC6_COUNT_EN (1<<0)
7000#define GEN6_GT_GFX_RC6 _MMIO(0x138108)
7001#define VLV_GT_RENDER_RC6 _MMIO(0x138108)
7002#define VLV_GT_MEDIA_RC6 _MMIO(0x13810C)
7003
7004#define GEN6_GT_GFX_RC6p _MMIO(0x13810C)
7005#define GEN6_GT_GFX_RC6pp _MMIO(0x138110)
7006#define VLV_RENDER_C0_COUNT _MMIO(0x138118)
7007#define VLV_MEDIA_C0_COUNT _MMIO(0x13811C)
7008
7009#define GEN6_PCODE_MAILBOX _MMIO(0x138124)
7010#define GEN6_PCODE_READY (1<<31)
7011#define GEN6_PCODE_WRITE_RC6VIDS 0x4
7012#define GEN6_PCODE_READ_RC6VIDS 0x5
7013#define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
7014#define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245)
7015#define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18
7016#define GEN9_PCODE_READ_MEM_LATENCY 0x6
7017#define GEN9_MEM_LATENCY_LEVEL_MASK 0xFF
7018#define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8
7019#define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16
7020#define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24
7021#define SKL_PCODE_CDCLK_CONTROL 0x7
7022#define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3
7023#define SKL_CDCLK_READY_FOR_CHANGE 0x1
7024#define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
7025#define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
7026#define GEN6_READ_OC_PARAMS 0xc
7027#define GEN6_PCODE_READ_D_COMP 0x10
7028#define GEN6_PCODE_WRITE_D_COMP 0x11
7029#define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
7030#define DISPLAY_IPS_CONTROL 0x19
7031#define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
7032#define GEN6_PCODE_DATA _MMIO(0x138128)
7033#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
7034#define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
7035#define GEN6_PCODE_DATA1 _MMIO(0x13812C)
7036
7037#define GEN6_GT_CORE_STATUS _MMIO(0x138060)
7038#define GEN6_CORE_CPD_STATE_MASK (7<<4)
7039#define GEN6_RCn_MASK 7
7040#define GEN6_RC0 0
7041#define GEN6_RC3 2
7042#define GEN6_RC6 3
7043#define GEN6_RC7 4
7044
7045#define GEN8_GT_SLICE_INFO _MMIO(0x138064)
7046#define GEN8_LSLICESTAT_MASK 0x7
7047
7048#define CHV_POWER_SS0_SIG1 _MMIO(0xa720)
7049#define CHV_POWER_SS1_SIG1 _MMIO(0xa728)
7050#define CHV_SS_PG_ENABLE (1<<1)
7051#define CHV_EU08_PG_ENABLE (1<<9)
7052#define CHV_EU19_PG_ENABLE (1<<17)
7053#define CHV_EU210_PG_ENABLE (1<<25)
7054
7055#define CHV_POWER_SS0_SIG2 _MMIO(0xa724)
7056#define CHV_POWER_SS1_SIG2 _MMIO(0xa72c)
7057#define CHV_EU311_PG_ENABLE (1<<1)
7058
7059#define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice)*0x4)
7060#define GEN9_PGCTL_SLICE_ACK (1 << 0)
7061#define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice)*2))
7062
7063#define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice)*0x8)
7064#define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice)*0x8)
7065#define GEN9_PGCTL_SSA_EU08_ACK (1 << 0)
7066#define GEN9_PGCTL_SSA_EU19_ACK (1 << 2)
7067#define GEN9_PGCTL_SSA_EU210_ACK (1 << 4)
7068#define GEN9_PGCTL_SSA_EU311_ACK (1 << 6)
7069#define GEN9_PGCTL_SSB_EU08_ACK (1 << 8)
7070#define GEN9_PGCTL_SSB_EU19_ACK (1 << 10)
7071#define GEN9_PGCTL_SSB_EU210_ACK (1 << 12)
7072#define GEN9_PGCTL_SSB_EU311_ACK (1 << 14)
7073
7074#define GEN7_MISCCPCTL _MMIO(0x9424)
7075#define GEN7_DOP_CLOCK_GATE_ENABLE (1<<0)
7076#define GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE (1<<2)
7077#define GEN8_DOP_CLOCK_GATE_GUC_ENABLE (1<<4)
7078#define GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE (1<<6)
7079
7080#define GEN8_GARBCNTL _MMIO(0xB004)
7081#define GEN9_GAPS_TSV_CREDIT_DISABLE (1<<7)
7082
7083/* IVYBRIDGE DPF */
7084#define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
7085#define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
7086#define GEN7_PARITY_ERROR_VALID (1<<13)
7087#define GEN7_L3CDERRST1_BANK_MASK (3<<11)
7088#define GEN7_L3CDERRST1_SUBBANK_MASK (7<<8)
7089#define GEN7_PARITY_ERROR_ROW(reg) \
7090 ((reg & GEN7_L3CDERRST1_ROW_MASK) >> 14)
7091#define GEN7_PARITY_ERROR_BANK(reg) \
7092 ((reg & GEN7_L3CDERRST1_BANK_MASK) >> 11)
7093#define GEN7_PARITY_ERROR_SUBBANK(reg) \
7094 ((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
7095#define GEN7_L3CDERRST1_ENABLE (1<<7)
7096
7097#define GEN7_L3LOG(slice, i) _MMIO(0xB070 + (slice) * 0x200 + (i) * 4)
7098#define GEN7_L3LOG_SIZE 0x80
7099
7100#define GEN7_HALF_SLICE_CHICKEN1 _MMIO(0xe100) /* IVB GT1 + VLV */
7101#define GEN7_HALF_SLICE_CHICKEN1_GT2 _MMIO(0xf100)
7102#define GEN7_MAX_PS_THREAD_DEP (8<<12)
7103#define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1<<10)
7104#define GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE (1<<4)
7105#define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3)
7106
7107#define GEN9_HALF_SLICE_CHICKEN5 _MMIO(0xe188)
7108#define GEN9_DG_MIRROR_FIX_ENABLE (1<<5)
7109#define GEN9_CCS_TLB_PREFETCH_ENABLE (1<<3)
7110
7111#define GEN8_ROW_CHICKEN _MMIO(0xe4f0)
7112#define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1<<8)
7113#define STALL_DOP_GATING_DISABLE (1<<5)
7114
7115#define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4)
7116#define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4)
7117#define DOP_CLOCK_GATING_DISABLE (1<<0)
7118
7119#define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
7120#define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
7121
7122#define HALF_SLICE_CHICKEN2 _MMIO(0xe180)
7123#define GEN8_ST_PO_DISABLE (1<<13)
7124
7125#define HALF_SLICE_CHICKEN3 _MMIO(0xe184)
7126#define HSW_SAMPLE_C_PERFORMANCE (1<<9)
7127#define GEN8_CENTROID_PIXEL_OPT_DIS (1<<8)
7128#define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1<<5)
7129#define GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1)
7130
7131#define GEN9_HALF_SLICE_CHICKEN7 _MMIO(0xe194)
7132#define GEN9_ENABLE_YV12_BUGFIX (1<<4)
7133
7134/* Audio */
7135#define G4X_AUD_VID_DID _MMIO(dev_priv->info.display_mmio_offset + 0x62020)
7136#define INTEL_AUDIO_DEVCL 0x808629FB
7137#define INTEL_AUDIO_DEVBLC 0x80862801
7138#define INTEL_AUDIO_DEVCTG 0x80862802
7139
7140#define G4X_AUD_CNTL_ST _MMIO(0x620B4)
7141#define G4X_ELDV_DEVCL_DEVBLC (1 << 13)
7142#define G4X_ELDV_DEVCTG (1 << 14)
7143#define G4X_ELD_ADDR_MASK (0xf << 5)
7144#define G4X_ELD_ACK (1 << 4)
7145#define G4X_HDMIW_HDMIEDID _MMIO(0x6210C)
7146
7147#define _IBX_HDMIW_HDMIEDID_A 0xE2050
7148#define _IBX_HDMIW_HDMIEDID_B 0xE2150
7149#define IBX_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _IBX_HDMIW_HDMIEDID_A, \
7150 _IBX_HDMIW_HDMIEDID_B)
7151#define _IBX_AUD_CNTL_ST_A 0xE20B4
7152#define _IBX_AUD_CNTL_ST_B 0xE21B4
7153#define IBX_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CNTL_ST_A, \
7154 _IBX_AUD_CNTL_ST_B)
7155#define IBX_ELD_BUFFER_SIZE_MASK (0x1f << 10)
7156#define IBX_ELD_ADDRESS_MASK (0x1f << 5)
7157#define IBX_ELD_ACK (1 << 4)
7158#define IBX_AUD_CNTL_ST2 _MMIO(0xE20C0)
7159#define IBX_CP_READY(port) ((1 << 1) << (((port) - 1) * 4))
7160#define IBX_ELD_VALID(port) ((1 << 0) << (((port) - 1) * 4))
7161
7162#define _CPT_HDMIW_HDMIEDID_A 0xE5050
7163#define _CPT_HDMIW_HDMIEDID_B 0xE5150
7164#define CPT_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _CPT_HDMIW_HDMIEDID_A, _CPT_HDMIW_HDMIEDID_B)
7165#define _CPT_AUD_CNTL_ST_A 0xE50B4
7166#define _CPT_AUD_CNTL_ST_B 0xE51B4
7167#define CPT_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CNTL_ST_A, _CPT_AUD_CNTL_ST_B)
7168#define CPT_AUD_CNTRL_ST2 _MMIO(0xE50C0)
7169
7170#define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050)
7171#define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150)
7172#define VLV_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _VLV_HDMIW_HDMIEDID_A, _VLV_HDMIW_HDMIEDID_B)
7173#define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4)
7174#define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4)
7175#define VLV_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CNTL_ST_A, _VLV_AUD_CNTL_ST_B)
7176#define VLV_AUD_CNTL_ST2 _MMIO(VLV_DISPLAY_BASE + 0x620C0)
7177
7178/* These are the 4 32-bit write offset registers for each stream
7179 * output buffer. It determines the offset from the
7180 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
7181 */
7182#define GEN7_SO_WRITE_OFFSET(n) _MMIO(0x5280 + (n) * 4)
7183
7184#define _IBX_AUD_CONFIG_A 0xe2000
7185#define _IBX_AUD_CONFIG_B 0xe2100
7186#define IBX_AUD_CFG(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CONFIG_A, _IBX_AUD_CONFIG_B)
7187#define _CPT_AUD_CONFIG_A 0xe5000
7188#define _CPT_AUD_CONFIG_B 0xe5100
7189#define CPT_AUD_CFG(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CONFIG_A, _CPT_AUD_CONFIG_B)
7190#define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000)
7191#define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100)
7192#define VLV_AUD_CFG(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CONFIG_A, _VLV_AUD_CONFIG_B)
7193
7194#define AUD_CONFIG_N_VALUE_INDEX (1 << 29)
7195#define AUD_CONFIG_N_PROG_ENABLE (1 << 28)
7196#define AUD_CONFIG_UPPER_N_SHIFT 20
7197#define AUD_CONFIG_UPPER_N_MASK (0xff << 20)
7198#define AUD_CONFIG_LOWER_N_SHIFT 4
7199#define AUD_CONFIG_LOWER_N_MASK (0xfff << 4)
7200#define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16
7201#define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16)
7202#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16)
7203#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16)
7204#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16)
7205#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16)
7206#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16)
7207#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16)
7208#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16)
7209#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16)
7210#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16)
7211#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16)
7212#define AUD_CONFIG_DISABLE_NCTS (1 << 3)
7213
7214/* HSW Audio */
7215#define _HSW_AUD_CONFIG_A 0x65000
7216#define _HSW_AUD_CONFIG_B 0x65100
7217#define HSW_AUD_CFG(pipe) _MMIO_PIPE(pipe, _HSW_AUD_CONFIG_A, _HSW_AUD_CONFIG_B)
7218
7219#define _HSW_AUD_MISC_CTRL_A 0x65010
7220#define _HSW_AUD_MISC_CTRL_B 0x65110
7221#define HSW_AUD_MISC_CTRL(pipe) _MMIO_PIPE(pipe, _HSW_AUD_MISC_CTRL_A, _HSW_AUD_MISC_CTRL_B)
7222
7223#define _HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4
7224#define _HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4
7225#define HSW_AUD_DIP_ELD_CTRL(pipe) _MMIO_PIPE(pipe, _HSW_AUD_DIP_ELD_CTRL_ST_A, _HSW_AUD_DIP_ELD_CTRL_ST_B)
7226
7227/* Audio Digital Converter */
7228#define _HSW_AUD_DIG_CNVT_1 0x65080
7229#define _HSW_AUD_DIG_CNVT_2 0x65180
7230#define AUD_DIG_CNVT(pipe) _MMIO_PIPE(pipe, _HSW_AUD_DIG_CNVT_1, _HSW_AUD_DIG_CNVT_2)
7231#define DIP_PORT_SEL_MASK 0x3
7232
7233#define _HSW_AUD_EDID_DATA_A 0x65050
7234#define _HSW_AUD_EDID_DATA_B 0x65150
7235#define HSW_AUD_EDID_DATA(pipe) _MMIO_PIPE(pipe, _HSW_AUD_EDID_DATA_A, _HSW_AUD_EDID_DATA_B)
7236
7237#define HSW_AUD_PIPE_CONV_CFG _MMIO(0x6507c)
7238#define HSW_AUD_PIN_ELD_CP_VLD _MMIO(0x650c0)
7239#define AUDIO_INACTIVE(trans) ((1 << 3) << ((trans) * 4))
7240#define AUDIO_OUTPUT_ENABLE(trans) ((1 << 2) << ((trans) * 4))
7241#define AUDIO_CP_READY(trans) ((1 << 1) << ((trans) * 4))
7242#define AUDIO_ELD_VALID(trans) ((1 << 0) << ((trans) * 4))
7243
7244#define HSW_AUD_CHICKENBIT _MMIO(0x65f10)
7245#define SKL_AUD_CODEC_WAKE_SIGNAL (1 << 15)
7246
7247/* HSW Power Wells */
7248#define HSW_PWR_WELL_BIOS _MMIO(0x45400) /* CTL1 */
7249#define HSW_PWR_WELL_DRIVER _MMIO(0x45404) /* CTL2 */
7250#define HSW_PWR_WELL_KVMR _MMIO(0x45408) /* CTL3 */
7251#define HSW_PWR_WELL_DEBUG _MMIO(0x4540C) /* CTL4 */
7252#define HSW_PWR_WELL_ENABLE_REQUEST (1<<31)
7253#define HSW_PWR_WELL_STATE_ENABLED (1<<30)
7254#define HSW_PWR_WELL_CTL5 _MMIO(0x45410)
7255#define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31)
7256#define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20)
7257#define HSW_PWR_WELL_FORCE_ON (1<<19)
7258#define HSW_PWR_WELL_CTL6 _MMIO(0x45414)
7259
7260/* SKL Fuse Status */
7261#define SKL_FUSE_STATUS _MMIO(0x42000)
7262#define SKL_FUSE_DOWNLOAD_STATUS (1<<31)
7263#define SKL_FUSE_PG0_DIST_STATUS (1<<27)
7264#define SKL_FUSE_PG1_DIST_STATUS (1<<26)
7265#define SKL_FUSE_PG2_DIST_STATUS (1<<25)
7266
7267/* Per-pipe DDI Function Control */
7268#define _TRANS_DDI_FUNC_CTL_A 0x60400
7269#define _TRANS_DDI_FUNC_CTL_B 0x61400
7270#define _TRANS_DDI_FUNC_CTL_C 0x62400
7271#define _TRANS_DDI_FUNC_CTL_EDP 0x6F400
7272#define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL_A)
7273
7274#define TRANS_DDI_FUNC_ENABLE (1<<31)
7275/* Those bits are ignored by pipe EDP since it can only connect to DDI A */
7276#define TRANS_DDI_PORT_MASK (7<<28)
7277#define TRANS_DDI_PORT_SHIFT 28
7278#define TRANS_DDI_SELECT_PORT(x) ((x)<<28)
7279#define TRANS_DDI_PORT_NONE (0<<28)
7280#define TRANS_DDI_MODE_SELECT_MASK (7<<24)
7281#define TRANS_DDI_MODE_SELECT_HDMI (0<<24)
7282#define TRANS_DDI_MODE_SELECT_DVI (1<<24)
7283#define TRANS_DDI_MODE_SELECT_DP_SST (2<<24)
7284#define TRANS_DDI_MODE_SELECT_DP_MST (3<<24)
7285#define TRANS_DDI_MODE_SELECT_FDI (4<<24)
7286#define TRANS_DDI_BPC_MASK (7<<20)
7287#define TRANS_DDI_BPC_8 (0<<20)
7288#define TRANS_DDI_BPC_10 (1<<20)
7289#define TRANS_DDI_BPC_6 (2<<20)
7290#define TRANS_DDI_BPC_12 (3<<20)
7291#define TRANS_DDI_PVSYNC (1<<17)
7292#define TRANS_DDI_PHSYNC (1<<16)
7293#define TRANS_DDI_EDP_INPUT_MASK (7<<12)
7294#define TRANS_DDI_EDP_INPUT_A_ON (0<<12)
7295#define TRANS_DDI_EDP_INPUT_A_ONOFF (4<<12)
7296#define TRANS_DDI_EDP_INPUT_B_ONOFF (5<<12)
7297#define TRANS_DDI_EDP_INPUT_C_ONOFF (6<<12)
7298#define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1<<8)
7299#define TRANS_DDI_BFI_ENABLE (1<<4)
7300
7301/* DisplayPort Transport Control */
7302#define _DP_TP_CTL_A 0x64040
7303#define _DP_TP_CTL_B 0x64140
7304#define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
7305#define DP_TP_CTL_ENABLE (1<<31)
7306#define DP_TP_CTL_MODE_SST (0<<27)
7307#define DP_TP_CTL_MODE_MST (1<<27)
7308#define DP_TP_CTL_FORCE_ACT (1<<25)
7309#define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18)
7310#define DP_TP_CTL_FDI_AUTOTRAIN (1<<15)
7311#define DP_TP_CTL_LINK_TRAIN_MASK (7<<8)
7312#define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8)
7313#define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8)
7314#define DP_TP_CTL_LINK_TRAIN_PAT3 (4<<8)
7315#define DP_TP_CTL_LINK_TRAIN_IDLE (2<<8)
7316#define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8)
7317#define DP_TP_CTL_SCRAMBLE_DISABLE (1<<7)
7318
7319/* DisplayPort Transport Status */
7320#define _DP_TP_STATUS_A 0x64044
7321#define _DP_TP_STATUS_B 0x64144
7322#define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)
7323#define DP_TP_STATUS_IDLE_DONE (1<<25)
7324#define DP_TP_STATUS_ACT_SENT (1<<24)
7325#define DP_TP_STATUS_MODE_STATUS_MST (1<<23)
7326#define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12)
7327#define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8)
7328#define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4)
7329#define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0)
7330
7331/* DDI Buffer Control */
7332#define _DDI_BUF_CTL_A 0x64000
7333#define _DDI_BUF_CTL_B 0x64100
7334#define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B)
7335#define DDI_BUF_CTL_ENABLE (1<<31)
7336#define DDI_BUF_TRANS_SELECT(n) ((n) << 24)
7337#define DDI_BUF_EMP_MASK (0xf<<24)
7338#define DDI_BUF_PORT_REVERSAL (1<<16)
7339#define DDI_BUF_IS_IDLE (1<<7)
7340#define DDI_A_4_LANES (1<<4)
7341#define DDI_PORT_WIDTH(width) (((width) - 1) << 1)
7342#define DDI_PORT_WIDTH_MASK (7 << 1)
7343#define DDI_PORT_WIDTH_SHIFT 1
7344#define DDI_INIT_DISPLAY_DETECTED (1<<0)
7345
7346/* DDI Buffer Translations */
7347#define _DDI_BUF_TRANS_A 0x64E00
7348#define _DDI_BUF_TRANS_B 0x64E60
7349#define DDI_BUF_TRANS_LO(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8)
7350#define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
7351
7352/* Sideband Interface (SBI) is programmed indirectly, via
7353 * SBI_ADDR, which contains the register offset; and SBI_DATA,
7354 * which contains the payload */
7355#define SBI_ADDR _MMIO(0xC6000)
7356#define SBI_DATA _MMIO(0xC6004)
7357#define SBI_CTL_STAT _MMIO(0xC6008)
7358#define SBI_CTL_DEST_ICLK (0x0<<16)
7359#define SBI_CTL_DEST_MPHY (0x1<<16)
7360#define SBI_CTL_OP_IORD (0x2<<8)
7361#define SBI_CTL_OP_IOWR (0x3<<8)
7362#define SBI_CTL_OP_CRRD (0x6<<8)
7363#define SBI_CTL_OP_CRWR (0x7<<8)
7364#define SBI_RESPONSE_FAIL (0x1<<1)
7365#define SBI_RESPONSE_SUCCESS (0x0<<1)
7366#define SBI_BUSY (0x1<<0)
7367#define SBI_READY (0x0<<0)
7368
7369/* SBI offsets */
7370#define SBI_SSCDIVINTPHASE 0x0200
7371#define SBI_SSCDIVINTPHASE6 0x0600
7372#define SBI_SSCDIVINTPHASE_DIVSEL_MASK ((0x7f)<<1)
7373#define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x)<<1)
7374#define SBI_SSCDIVINTPHASE_INCVAL_MASK ((0x7f)<<8)
7375#define SBI_SSCDIVINTPHASE_INCVAL(x) ((x)<<8)
7376#define SBI_SSCDIVINTPHASE_DIR(x) ((x)<<15)
7377#define SBI_SSCDIVINTPHASE_PROPAGATE (1<<0)
7378#define SBI_SSCDITHPHASE 0x0204
7379#define SBI_SSCCTL 0x020c
7380#define SBI_SSCCTL6 0x060C
7381#define SBI_SSCCTL_PATHALT (1<<3)
7382#define SBI_SSCCTL_DISABLE (1<<0)
7383#define SBI_SSCAUXDIV6 0x0610
7384#define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x)<<4)
7385#define SBI_DBUFF0 0x2a00
7386#define SBI_GEN0 0x1f00
7387#define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1<<0)
7388
7389/* LPT PIXCLK_GATE */
7390#define PIXCLK_GATE _MMIO(0xC6020)
7391#define PIXCLK_GATE_UNGATE (1<<0)
7392#define PIXCLK_GATE_GATE (0<<0)
7393
7394/* SPLL */
7395#define SPLL_CTL _MMIO(0x46020)
7396#define SPLL_PLL_ENABLE (1<<31)
7397#define SPLL_PLL_SSC (1<<28)
7398#define SPLL_PLL_NON_SSC (2<<28)
7399#define SPLL_PLL_LCPLL (3<<28)
7400#define SPLL_PLL_REF_MASK (3<<28)
7401#define SPLL_PLL_FREQ_810MHz (0<<26)
7402#define SPLL_PLL_FREQ_1350MHz (1<<26)
7403#define SPLL_PLL_FREQ_2700MHz (2<<26)
7404#define SPLL_PLL_FREQ_MASK (3<<26)
7405
7406/* WRPLL */
7407#define _WRPLL_CTL1 0x46040
7408#define _WRPLL_CTL2 0x46060
7409#define WRPLL_CTL(pll) _MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2)
7410#define WRPLL_PLL_ENABLE (1<<31)
7411#define WRPLL_PLL_SSC (1<<28)
7412#define WRPLL_PLL_NON_SSC (2<<28)
7413#define WRPLL_PLL_LCPLL (3<<28)
7414#define WRPLL_PLL_REF_MASK (3<<28)
7415/* WRPLL divider programming */
7416#define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0)
7417#define WRPLL_DIVIDER_REF_MASK (0xff)
7418#define WRPLL_DIVIDER_POST(x) ((x)<<8)
7419#define WRPLL_DIVIDER_POST_MASK (0x3f<<8)
7420#define WRPLL_DIVIDER_POST_SHIFT 8
7421#define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16)
7422#define WRPLL_DIVIDER_FB_SHIFT 16
7423#define WRPLL_DIVIDER_FB_MASK (0xff<<16)
7424
7425/* Port clock selection */
7426#define _PORT_CLK_SEL_A 0x46100
7427#define _PORT_CLK_SEL_B 0x46104
7428#define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B)
7429#define PORT_CLK_SEL_LCPLL_2700 (0<<29)
7430#define PORT_CLK_SEL_LCPLL_1350 (1<<29)
7431#define PORT_CLK_SEL_LCPLL_810 (2<<29)
7432#define PORT_CLK_SEL_SPLL (3<<29)
7433#define PORT_CLK_SEL_WRPLL(pll) (((pll)+4)<<29)
7434#define PORT_CLK_SEL_WRPLL1 (4<<29)
7435#define PORT_CLK_SEL_WRPLL2 (5<<29)
7436#define PORT_CLK_SEL_NONE (7<<29)
7437#define PORT_CLK_SEL_MASK (7<<29)
7438
7439/* Transcoder clock selection */
7440#define _TRANS_CLK_SEL_A 0x46140
7441#define _TRANS_CLK_SEL_B 0x46144
7442#define TRANS_CLK_SEL(tran) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B)
7443/* For each transcoder, we need to select the corresponding port clock */
7444#define TRANS_CLK_SEL_DISABLED (0x0<<29)
7445#define TRANS_CLK_SEL_PORT(x) (((x)+1)<<29)
7446
7447#define CDCLK_FREQ _MMIO(0x46200)
7448
7449#define _TRANSA_MSA_MISC 0x60410
7450#define _TRANSB_MSA_MISC 0x61410
7451#define _TRANSC_MSA_MISC 0x62410
7452#define _TRANS_EDP_MSA_MISC 0x6f410
7453#define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC)
7454
7455#define TRANS_MSA_SYNC_CLK (1<<0)
7456#define TRANS_MSA_6_BPC (0<<5)
7457#define TRANS_MSA_8_BPC (1<<5)
7458#define TRANS_MSA_10_BPC (2<<5)
7459#define TRANS_MSA_12_BPC (3<<5)
7460#define TRANS_MSA_16_BPC (4<<5)
7461
7462/* LCPLL Control */
7463#define LCPLL_CTL _MMIO(0x130040)
7464#define LCPLL_PLL_DISABLE (1<<31)
7465#define LCPLL_PLL_LOCK (1<<30)
7466#define LCPLL_CLK_FREQ_MASK (3<<26)
7467#define LCPLL_CLK_FREQ_450 (0<<26)
7468#define LCPLL_CLK_FREQ_54O_BDW (1<<26)
7469#define LCPLL_CLK_FREQ_337_5_BDW (2<<26)
7470#define LCPLL_CLK_FREQ_675_BDW (3<<26)
7471#define LCPLL_CD_CLOCK_DISABLE (1<<25)
7472#define LCPLL_ROOT_CD_CLOCK_DISABLE (1<<24)
7473#define LCPLL_CD2X_CLOCK_DISABLE (1<<23)
7474#define LCPLL_POWER_DOWN_ALLOW (1<<22)
7475#define LCPLL_CD_SOURCE_FCLK (1<<21)
7476#define LCPLL_CD_SOURCE_FCLK_DONE (1<<19)
7477
7478/*
7479 * SKL Clocks
7480 */
7481
7482/* CDCLK_CTL */
7483#define CDCLK_CTL _MMIO(0x46000)
7484#define CDCLK_FREQ_SEL_MASK (3<<26)
7485#define CDCLK_FREQ_450_432 (0<<26)
7486#define CDCLK_FREQ_540 (1<<26)
7487#define CDCLK_FREQ_337_308 (2<<26)
7488#define CDCLK_FREQ_675_617 (3<<26)
7489#define CDCLK_FREQ_DECIMAL_MASK (0x7ff)
7490
7491#define BXT_CDCLK_CD2X_DIV_SEL_MASK (3<<22)
7492#define BXT_CDCLK_CD2X_DIV_SEL_1 (0<<22)
7493#define BXT_CDCLK_CD2X_DIV_SEL_1_5 (1<<22)
7494#define BXT_CDCLK_CD2X_DIV_SEL_2 (2<<22)
7495#define BXT_CDCLK_CD2X_DIV_SEL_4 (3<<22)
7496#define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1<<16)
7497
7498/* LCPLL_CTL */
7499#define LCPLL1_CTL _MMIO(0x46010)
7500#define LCPLL2_CTL _MMIO(0x46014)
7501#define LCPLL_PLL_ENABLE (1<<31)
7502
7503/* DPLL control1 */
7504#define DPLL_CTRL1 _MMIO(0x6C058)
7505#define DPLL_CTRL1_HDMI_MODE(id) (1<<((id)*6+5))
7506#define DPLL_CTRL1_SSC(id) (1<<((id)*6+4))
7507#define DPLL_CTRL1_LINK_RATE_MASK(id) (7<<((id)*6+1))
7508#define DPLL_CTRL1_LINK_RATE_SHIFT(id) ((id)*6+1)
7509#define DPLL_CTRL1_LINK_RATE(linkrate, id) ((linkrate)<<((id)*6+1))
7510#define DPLL_CTRL1_OVERRIDE(id) (1<<((id)*6))
7511#define DPLL_CTRL1_LINK_RATE_2700 0
7512#define DPLL_CTRL1_LINK_RATE_1350 1
7513#define DPLL_CTRL1_LINK_RATE_810 2
7514#define DPLL_CTRL1_LINK_RATE_1620 3
7515#define DPLL_CTRL1_LINK_RATE_1080 4
7516#define DPLL_CTRL1_LINK_RATE_2160 5
7517
7518/* DPLL control2 */
7519#define DPLL_CTRL2 _MMIO(0x6C05C)
7520#define DPLL_CTRL2_DDI_CLK_OFF(port) (1<<((port)+15))
7521#define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3<<((port)*3+1))
7522#define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port)*3+1)
7523#define DPLL_CTRL2_DDI_CLK_SEL(clk, port) ((clk)<<((port)*3+1))
7524#define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1<<((port)*3))
7525
7526/* DPLL Status */
7527#define DPLL_STATUS _MMIO(0x6C060)
7528#define DPLL_LOCK(id) (1<<((id)*8))
7529
7530/* DPLL cfg */
7531#define _DPLL1_CFGCR1 0x6C040
7532#define _DPLL2_CFGCR1 0x6C048
7533#define _DPLL3_CFGCR1 0x6C050
7534#define DPLL_CFGCR1_FREQ_ENABLE (1<<31)
7535#define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff<<9)
7536#define DPLL_CFGCR1_DCO_FRACTION(x) ((x)<<9)
7537#define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff)
7538
7539#define _DPLL1_CFGCR2 0x6C044
7540#define _DPLL2_CFGCR2 0x6C04C
7541#define _DPLL3_CFGCR2 0x6C054
7542#define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff<<8)
7543#define DPLL_CFGCR2_QDIV_RATIO(x) ((x)<<8)
7544#define DPLL_CFGCR2_QDIV_MODE(x) ((x)<<7)
7545#define DPLL_CFGCR2_KDIV_MASK (3<<5)
7546#define DPLL_CFGCR2_KDIV(x) ((x)<<5)
7547#define DPLL_CFGCR2_KDIV_5 (0<<5)
7548#define DPLL_CFGCR2_KDIV_2 (1<<5)
7549#define DPLL_CFGCR2_KDIV_3 (2<<5)
7550#define DPLL_CFGCR2_KDIV_1 (3<<5)
7551#define DPLL_CFGCR2_PDIV_MASK (7<<2)
7552#define DPLL_CFGCR2_PDIV(x) ((x)<<2)
7553#define DPLL_CFGCR2_PDIV_1 (0<<2)
7554#define DPLL_CFGCR2_PDIV_2 (1<<2)
7555#define DPLL_CFGCR2_PDIV_3 (2<<2)
7556#define DPLL_CFGCR2_PDIV_7 (4<<2)
7557#define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3)
7558
7559#define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1)
7560#define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2)
7561
7562/* BXT display engine PLL */
7563#define BXT_DE_PLL_CTL _MMIO(0x6d000)
7564#define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */
7565#define BXT_DE_PLL_RATIO_MASK 0xff
7566
7567#define BXT_DE_PLL_ENABLE _MMIO(0x46070)
7568#define BXT_DE_PLL_PLL_ENABLE (1 << 31)
7569#define BXT_DE_PLL_LOCK (1 << 30)
7570
7571/* GEN9 DC */
7572#define DC_STATE_EN _MMIO(0x45504)
7573#define DC_STATE_DISABLE 0
7574#define DC_STATE_EN_UPTO_DC5 (1<<0)
7575#define DC_STATE_EN_DC9 (1<<3)
7576#define DC_STATE_EN_UPTO_DC6 (2<<0)
7577#define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3
7578
7579#define DC_STATE_DEBUG _MMIO(0x45520)
7580#define DC_STATE_DEBUG_MASK_CORES (1<<0)
7581#define DC_STATE_DEBUG_MASK_MEMORY_UP (1<<1)
7582
7583/* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
7584 * since on HSW we can't write to it using I915_WRITE. */
7585#define D_COMP_HSW _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
7586#define D_COMP_BDW _MMIO(0x138144)
7587#define D_COMP_RCOMP_IN_PROGRESS (1<<9)
7588#define D_COMP_COMP_FORCE (1<<8)
7589#define D_COMP_COMP_DISABLE (1<<0)
7590
7591/* Pipe WM_LINETIME - watermark line time */
7592#define _PIPE_WM_LINETIME_A 0x45270
7593#define _PIPE_WM_LINETIME_B 0x45274
7594#define PIPE_WM_LINETIME(pipe) _MMIO_PIPE(pipe, _PIPE_WM_LINETIME_A, _PIPE_WM_LINETIME_B)
7595#define PIPE_WM_LINETIME_MASK (0x1ff)
7596#define PIPE_WM_LINETIME_TIME(x) ((x))
7597#define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff<<16)
7598#define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x)<<16)
7599
7600/* SFUSE_STRAP */
7601#define SFUSE_STRAP _MMIO(0xc2014)
7602#define SFUSE_STRAP_FUSE_LOCK (1<<13)
7603#define SFUSE_STRAP_DISPLAY_DISABLED (1<<7)
7604#define SFUSE_STRAP_CRT_DISABLED (1<<6)
7605#define SFUSE_STRAP_DDIB_DETECTED (1<<2)
7606#define SFUSE_STRAP_DDIC_DETECTED (1<<1)
7607#define SFUSE_STRAP_DDID_DETECTED (1<<0)
7608
7609#define WM_MISC _MMIO(0x45260)
7610#define WM_MISC_DATA_PARTITION_5_6 (1 << 0)
7611
7612#define WM_DBG _MMIO(0x45280)
7613#define WM_DBG_DISALLOW_MULTIPLE_LP (1<<0)
7614#define WM_DBG_DISALLOW_MAXFIFO (1<<1)
7615#define WM_DBG_DISALLOW_SPRITE (1<<2)
7616
7617/* pipe CSC */
7618#define _PIPE_A_CSC_COEFF_RY_GY 0x49010
7619#define _PIPE_A_CSC_COEFF_BY 0x49014
7620#define _PIPE_A_CSC_COEFF_RU_GU 0x49018
7621#define _PIPE_A_CSC_COEFF_BU 0x4901c
7622#define _PIPE_A_CSC_COEFF_RV_GV 0x49020
7623#define _PIPE_A_CSC_COEFF_BV 0x49024
7624#define _PIPE_A_CSC_MODE 0x49028
7625#define CSC_BLACK_SCREEN_OFFSET (1 << 2)
7626#define CSC_POSITION_BEFORE_GAMMA (1 << 1)
7627#define CSC_MODE_YUV_TO_RGB (1 << 0)
7628#define _PIPE_A_CSC_PREOFF_HI 0x49030
7629#define _PIPE_A_CSC_PREOFF_ME 0x49034
7630#define _PIPE_A_CSC_PREOFF_LO 0x49038
7631#define _PIPE_A_CSC_POSTOFF_HI 0x49040
7632#define _PIPE_A_CSC_POSTOFF_ME 0x49044
7633#define _PIPE_A_CSC_POSTOFF_LO 0x49048
7634
7635#define _PIPE_B_CSC_COEFF_RY_GY 0x49110
7636#define _PIPE_B_CSC_COEFF_BY 0x49114
7637#define _PIPE_B_CSC_COEFF_RU_GU 0x49118
7638#define _PIPE_B_CSC_COEFF_BU 0x4911c
7639#define _PIPE_B_CSC_COEFF_RV_GV 0x49120
7640#define _PIPE_B_CSC_COEFF_BV 0x49124
7641#define _PIPE_B_CSC_MODE 0x49128
7642#define _PIPE_B_CSC_PREOFF_HI 0x49130
7643#define _PIPE_B_CSC_PREOFF_ME 0x49134
7644#define _PIPE_B_CSC_PREOFF_LO 0x49138
7645#define _PIPE_B_CSC_POSTOFF_HI 0x49140
7646#define _PIPE_B_CSC_POSTOFF_ME 0x49144
7647#define _PIPE_B_CSC_POSTOFF_LO 0x49148
7648
7649#define PIPE_CSC_COEFF_RY_GY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)
7650#define PIPE_CSC_COEFF_BY(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)
7651#define PIPE_CSC_COEFF_RU_GU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)
7652#define PIPE_CSC_COEFF_BU(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU)
7653#define PIPE_CSC_COEFF_RV_GV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV)
7654#define PIPE_CSC_COEFF_BV(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV)
7655#define PIPE_CSC_MODE(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE)
7656#define PIPE_CSC_PREOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI)
7657#define PIPE_CSC_PREOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME)
7658#define PIPE_CSC_PREOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO)
7659#define PIPE_CSC_POSTOFF_HI(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI)
7660#define PIPE_CSC_POSTOFF_ME(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
7661#define PIPE_CSC_POSTOFF_LO(pipe) _MMIO_PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
7662
7663/* MIPI DSI registers */
7664
7665#define _MIPI_PORT(port, a, c) _PORT3(port, a, 0, c) /* ports A and C only */
7666#define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c))
7667
7668/* BXT MIPI clock controls */
7669#define BXT_MAX_VAR_OUTPUT_KHZ 39500
7670
7671#define BXT_MIPI_CLOCK_CTL _MMIO(0x46090)
7672#define BXT_MIPI1_DIV_SHIFT 26
7673#define BXT_MIPI2_DIV_SHIFT 10
7674#define BXT_MIPI_DIV_SHIFT(port) \
7675 _MIPI_PORT(port, BXT_MIPI1_DIV_SHIFT, \
7676 BXT_MIPI2_DIV_SHIFT)
7677/* Var clock divider to generate TX source. Result must be < 39.5 M */
7678#define BXT_MIPI1_ESCLK_VAR_DIV_MASK (0x3F << 26)
7679#define BXT_MIPI2_ESCLK_VAR_DIV_MASK (0x3F << 10)
7680#define BXT_MIPI_ESCLK_VAR_DIV_MASK(port) \
7681 _MIPI_PORT(port, BXT_MIPI1_ESCLK_VAR_DIV_MASK, \
7682 BXT_MIPI2_ESCLK_VAR_DIV_MASK)
7683
7684#define BXT_MIPI_ESCLK_VAR_DIV(port, val) \
7685 (val << BXT_MIPI_DIV_SHIFT(port))
7686/* TX control divider to select actual TX clock output from (8x/var) */
7687#define BXT_MIPI1_TX_ESCLK_SHIFT 21
7688#define BXT_MIPI2_TX_ESCLK_SHIFT 5
7689#define BXT_MIPI_TX_ESCLK_SHIFT(port) \
7690 _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_SHIFT, \
7691 BXT_MIPI2_TX_ESCLK_SHIFT)
7692#define BXT_MIPI1_TX_ESCLK_FIXDIV_MASK (3 << 21)
7693#define BXT_MIPI2_TX_ESCLK_FIXDIV_MASK (3 << 5)
7694#define BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port) \
7695 _MIPI_PORT(port, BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, \
7696 BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)
7697#define BXT_MIPI_TX_ESCLK_8XDIV_BY2(port) \
7698 (0x0 << BXT_MIPI_TX_ESCLK_SHIFT(port))
7699#define BXT_MIPI_TX_ESCLK_8XDIV_BY4(port) \
7700 (0x1 << BXT_MIPI_TX_ESCLK_SHIFT(port))
7701#define BXT_MIPI_TX_ESCLK_8XDIV_BY8(port) \
7702 (0x2 << BXT_MIPI_TX_ESCLK_SHIFT(port))
7703/* RX control divider to select actual RX clock output from 8x*/
7704#define BXT_MIPI1_RX_ESCLK_SHIFT 19
7705#define BXT_MIPI2_RX_ESCLK_SHIFT 3
7706#define BXT_MIPI_RX_ESCLK_SHIFT(port) \
7707 _MIPI_PORT(port, BXT_MIPI1_RX_ESCLK_SHIFT, \
7708 BXT_MIPI2_RX_ESCLK_SHIFT)
7709#define BXT_MIPI1_RX_ESCLK_FIXDIV_MASK (3 << 19)
7710#define BXT_MIPI2_RX_ESCLK_FIXDIV_MASK (3 << 3)
7711#define BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port) \
7712 (3 << BXT_MIPI_RX_ESCLK_SHIFT(port))
7713#define BXT_MIPI_RX_ESCLK_8X_BY2(port) \
7714 (1 << BXT_MIPI_RX_ESCLK_SHIFT(port))
7715#define BXT_MIPI_RX_ESCLK_8X_BY3(port) \
7716 (2 << BXT_MIPI_RX_ESCLK_SHIFT(port))
7717#define BXT_MIPI_RX_ESCLK_8X_BY4(port) \
7718 (3 << BXT_MIPI_RX_ESCLK_SHIFT(port))
7719/* BXT-A WA: Always prog DPHY dividers to 00 */
7720#define BXT_MIPI1_DPHY_DIV_SHIFT 16
7721#define BXT_MIPI2_DPHY_DIV_SHIFT 0
7722#define BXT_MIPI_DPHY_DIV_SHIFT(port) \
7723 _MIPI_PORT(port, BXT_MIPI1_DPHY_DIV_SHIFT, \
7724 BXT_MIPI2_DPHY_DIV_SHIFT)
7725#define BXT_MIPI_1_DPHY_DIVIDER_MASK (3 << 16)
7726#define BXT_MIPI_2_DPHY_DIVIDER_MASK (3 << 0)
7727#define BXT_MIPI_DPHY_DIVIDER_MASK(port) \
7728 (3 << BXT_MIPI_DPHY_DIV_SHIFT(port))
7729
7730/* BXT MIPI mode configure */
7731#define _BXT_MIPIA_TRANS_HACTIVE 0x6B0F8
7732#define _BXT_MIPIC_TRANS_HACTIVE 0x6B8F8
7733#define BXT_MIPI_TRANS_HACTIVE(tc) _MMIO_MIPI(tc, \
7734 _BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE)
7735
7736#define _BXT_MIPIA_TRANS_VACTIVE 0x6B0FC
7737#define _BXT_MIPIC_TRANS_VACTIVE 0x6B8FC
7738#define BXT_MIPI_TRANS_VACTIVE(tc) _MMIO_MIPI(tc, \
7739 _BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE)
7740
7741#define _BXT_MIPIA_TRANS_VTOTAL 0x6B100
7742#define _BXT_MIPIC_TRANS_VTOTAL 0x6B900
7743#define BXT_MIPI_TRANS_VTOTAL(tc) _MMIO_MIPI(tc, \
7744 _BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL)
7745
7746#define BXT_DSI_PLL_CTL _MMIO(0x161000)
7747#define BXT_DSI_PLL_PVD_RATIO_SHIFT 16
7748#define BXT_DSI_PLL_PVD_RATIO_MASK (3 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
7749#define BXT_DSI_PLL_PVD_RATIO_1 (1 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
7750#define BXT_DSIC_16X_BY2 (1 << 10)
7751#define BXT_DSIC_16X_BY3 (2 << 10)
7752#define BXT_DSIC_16X_BY4 (3 << 10)
7753#define BXT_DSIA_16X_BY2 (1 << 8)
7754#define BXT_DSIA_16X_BY3 (2 << 8)
7755#define BXT_DSIA_16X_BY4 (3 << 8)
7756#define BXT_DSI_FREQ_SEL_SHIFT 8
7757#define BXT_DSI_FREQ_SEL_MASK (0xF << BXT_DSI_FREQ_SEL_SHIFT)
7758
7759#define BXT_DSI_PLL_RATIO_MAX 0x7D
7760#define BXT_DSI_PLL_RATIO_MIN 0x22
7761#define BXT_DSI_PLL_RATIO_MASK 0xFF
7762#define BXT_REF_CLOCK_KHZ 19200
7763
7764#define BXT_DSI_PLL_ENABLE _MMIO(0x46080)
7765#define BXT_DSI_PLL_DO_ENABLE (1 << 31)
7766#define BXT_DSI_PLL_LOCKED (1 << 30)
7767
7768#define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190)
7769#define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700)
7770#define MIPI_PORT_CTRL(port) _MMIO_MIPI(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL)
7771
7772 /* BXT port control */
7773#define _BXT_MIPIA_PORT_CTRL 0x6B0C0
7774#define _BXT_MIPIC_PORT_CTRL 0x6B8C0
7775#define BXT_MIPI_PORT_CTRL(tc) _MMIO_MIPI(tc, _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL)
7776
7777#define DPI_ENABLE (1 << 31) /* A + C */
7778#define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27
7779#define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27)
7780#define DUAL_LINK_MODE_SHIFT 26
7781#define DUAL_LINK_MODE_MASK (1 << 26)
7782#define DUAL_LINK_MODE_FRONT_BACK (0 << 26)
7783#define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26)
7784#define DITHERING_ENABLE (1 << 25) /* A + C */
7785#define FLOPPED_HSTX (1 << 23)
7786#define DE_INVERT (1 << 19) /* XXX */
7787#define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18
7788#define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18)
7789#define AFE_LATCHOUT (1 << 17)
7790#define LP_OUTPUT_HOLD (1 << 16)
7791#define MIPIC_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15
7792#define MIPIC_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15)
7793#define MIPIC_MIPI4DPHY_DELAY_COUNT_SHIFT 11
7794#define MIPIC_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11)
7795#define CSB_SHIFT 9
7796#define CSB_MASK (3 << 9)
7797#define CSB_20MHZ (0 << 9)
7798#define CSB_10MHZ (1 << 9)
7799#define CSB_40MHZ (2 << 9)
7800#define BANDGAP_MASK (1 << 8)
7801#define BANDGAP_PNW_CIRCUIT (0 << 8)
7802#define BANDGAP_LNC_CIRCUIT (1 << 8)
7803#define MIPIC_FLISDSI_DELAY_COUNT_LOW_SHIFT 5
7804#define MIPIC_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5)
7805#define TEARING_EFFECT_DELAY (1 << 4) /* A + C */
7806#define TEARING_EFFECT_SHIFT 2 /* A + C */
7807#define TEARING_EFFECT_MASK (3 << 2)
7808#define TEARING_EFFECT_OFF (0 << 2)
7809#define TEARING_EFFECT_DSI (1 << 2)
7810#define TEARING_EFFECT_GPIO (2 << 2)
7811#define LANE_CONFIGURATION_SHIFT 0
7812#define LANE_CONFIGURATION_MASK (3 << 0)
7813#define LANE_CONFIGURATION_4LANE (0 << 0)
7814#define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0)
7815#define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0)
7816
7817#define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194)
7818#define _MIPIC_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704)
7819#define MIPI_TEARING_CTRL(port) _MMIO_MIPI(port, _MIPIA_TEARING_CTRL, _MIPIC_TEARING_CTRL)
7820#define TEARING_EFFECT_DELAY_SHIFT 0
7821#define TEARING_EFFECT_DELAY_MASK (0xffff << 0)
7822
7823/* XXX: all bits reserved */
7824#define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0)
7825
7826/* MIPI DSI Controller and D-PHY registers */
7827
7828#define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000)
7829#define _MIPIC_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800)
7830#define MIPI_DEVICE_READY(port) _MMIO_MIPI(port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY)
7831#define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */
7832#define ULPS_STATE_MASK (3 << 1)
7833#define ULPS_STATE_ENTER (2 << 1)
7834#define ULPS_STATE_EXIT (1 << 1)
7835#define ULPS_STATE_NORMAL_OPERATION (0 << 1)
7836#define DEVICE_READY (1 << 0)
7837
7838#define _MIPIA_INTR_STAT (dev_priv->mipi_mmio_base + 0xb004)
7839#define _MIPIC_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804)
7840#define MIPI_INTR_STAT(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT)
7841#define _MIPIA_INTR_EN (dev_priv->mipi_mmio_base + 0xb008)
7842#define _MIPIC_INTR_EN (dev_priv->mipi_mmio_base + 0xb808)
7843#define MIPI_INTR_EN(port) _MMIO_MIPI(port, _MIPIA_INTR_EN, _MIPIC_INTR_EN)
7844#define TEARING_EFFECT (1 << 31)
7845#define SPL_PKT_SENT_INTERRUPT (1 << 30)
7846#define GEN_READ_DATA_AVAIL (1 << 29)
7847#define LP_GENERIC_WR_FIFO_FULL (1 << 28)
7848#define HS_GENERIC_WR_FIFO_FULL (1 << 27)
7849#define RX_PROT_VIOLATION (1 << 26)
7850#define RX_INVALID_TX_LENGTH (1 << 25)
7851#define ACK_WITH_NO_ERROR (1 << 24)
7852#define TURN_AROUND_ACK_TIMEOUT (1 << 23)
7853#define LP_RX_TIMEOUT (1 << 22)
7854#define HS_TX_TIMEOUT (1 << 21)
7855#define DPI_FIFO_UNDERRUN (1 << 20)
7856#define LOW_CONTENTION (1 << 19)
7857#define HIGH_CONTENTION (1 << 18)
7858#define TXDSI_VC_ID_INVALID (1 << 17)
7859#define TXDSI_DATA_TYPE_NOT_RECOGNISED (1 << 16)
7860#define TXCHECKSUM_ERROR (1 << 15)
7861#define TXECC_MULTIBIT_ERROR (1 << 14)
7862#define TXECC_SINGLE_BIT_ERROR (1 << 13)
7863#define TXFALSE_CONTROL_ERROR (1 << 12)
7864#define RXDSI_VC_ID_INVALID (1 << 11)
7865#define RXDSI_DATA_TYPE_NOT_REGOGNISED (1 << 10)
7866#define RXCHECKSUM_ERROR (1 << 9)
7867#define RXECC_MULTIBIT_ERROR (1 << 8)
7868#define RXECC_SINGLE_BIT_ERROR (1 << 7)
7869#define RXFALSE_CONTROL_ERROR (1 << 6)
7870#define RXHS_RECEIVE_TIMEOUT_ERROR (1 << 5)
7871#define RX_LP_TX_SYNC_ERROR (1 << 4)
7872#define RXEXCAPE_MODE_ENTRY_ERROR (1 << 3)
7873#define RXEOT_SYNC_ERROR (1 << 2)
7874#define RXSOT_SYNC_ERROR (1 << 1)
7875#define RXSOT_ERROR (1 << 0)
7876
7877#define _MIPIA_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb00c)
7878#define _MIPIC_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c)
7879#define MIPI_DSI_FUNC_PRG(port) _MMIO_MIPI(port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG)
7880#define CMD_MODE_DATA_WIDTH_MASK (7 << 13)
7881#define CMD_MODE_NOT_SUPPORTED (0 << 13)
7882#define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13)
7883#define CMD_MODE_DATA_WIDTH_9_BIT (2 << 13)
7884#define CMD_MODE_DATA_WIDTH_8_BIT (3 << 13)
7885#define CMD_MODE_DATA_WIDTH_OPTION1 (4 << 13)
7886#define CMD_MODE_DATA_WIDTH_OPTION2 (5 << 13)
7887#define VID_MODE_FORMAT_MASK (0xf << 7)
7888#define VID_MODE_NOT_SUPPORTED (0 << 7)
7889#define VID_MODE_FORMAT_RGB565 (1 << 7)
7890#define VID_MODE_FORMAT_RGB666 (2 << 7)
7891#define VID_MODE_FORMAT_RGB666_LOOSE (3 << 7)
7892#define VID_MODE_FORMAT_RGB888 (4 << 7)
7893#define CMD_MODE_CHANNEL_NUMBER_SHIFT 5
7894#define CMD_MODE_CHANNEL_NUMBER_MASK (3 << 5)
7895#define VID_MODE_CHANNEL_NUMBER_SHIFT 3
7896#define VID_MODE_CHANNEL_NUMBER_MASK (3 << 3)
7897#define DATA_LANES_PRG_REG_SHIFT 0
7898#define DATA_LANES_PRG_REG_MASK (7 << 0)
7899
7900#define _MIPIA_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb010)
7901#define _MIPIC_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810)
7902#define MIPI_HS_TX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT)
7903#define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff
7904
7905#define _MIPIA_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb014)
7906#define _MIPIC_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814)
7907#define MIPI_LP_RX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT)
7908#define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff
7909
7910#define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb018)
7911#define _MIPIC_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818)
7912#define MIPI_TURN_AROUND_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT)
7913#define TURN_AROUND_TIMEOUT_MASK 0x3f
7914
7915#define _MIPIA_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb01c)
7916#define _MIPIC_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c)
7917#define MIPI_DEVICE_RESET_TIMER(port) _MMIO_MIPI(port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER)
7918#define DEVICE_RESET_TIMER_MASK 0xffff
7919
7920#define _MIPIA_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb020)
7921#define _MIPIC_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820)
7922#define MIPI_DPI_RESOLUTION(port) _MMIO_MIPI(port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION)
7923#define VERTICAL_ADDRESS_SHIFT 16
7924#define VERTICAL_ADDRESS_MASK (0xffff << 16)
7925#define HORIZONTAL_ADDRESS_SHIFT 0
7926#define HORIZONTAL_ADDRESS_MASK 0xffff
7927
7928#define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb024)
7929#define _MIPIC_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824)
7930#define MIPI_DBI_FIFO_THROTTLE(port) _MMIO_MIPI(port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE)
7931#define DBI_FIFO_EMPTY_HALF (0 << 0)
7932#define DBI_FIFO_EMPTY_QUARTER (1 << 0)
7933#define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0)
7934
7935/* regs below are bits 15:0 */
7936#define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb028)
7937#define _MIPIC_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828)
7938#define MIPI_HSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT)
7939
7940#define _MIPIA_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb02c)
7941#define _MIPIC_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c)
7942#define MIPI_HBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT)
7943
7944#define _MIPIA_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb030)
7945#define _MIPIC_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830)
7946#define MIPI_HFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT)
7947
7948#define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb034)
7949#define _MIPIC_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834)
7950#define MIPI_HACTIVE_AREA_COUNT(port) _MMIO_MIPI(port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT)
7951
7952#define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb038)
7953#define _MIPIC_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838)
7954#define MIPI_VSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT)
7955
7956#define _MIPIA_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb03c)
7957#define _MIPIC_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c)
7958#define MIPI_VBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT)
7959
7960#define _MIPIA_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb040)
7961#define _MIPIC_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840)
7962#define MIPI_VFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT)
7963
7964#define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb044)
7965#define _MIPIC_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844)
7966#define MIPI_HIGH_LOW_SWITCH_COUNT(port) _MMIO_MIPI(port, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT)
7967
7968/* regs above are bits 15:0 */
7969
7970#define _MIPIA_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb048)
7971#define _MIPIC_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848)
7972#define MIPI_DPI_CONTROL(port) _MMIO_MIPI(port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL)
7973#define DPI_LP_MODE (1 << 6)
7974#define BACKLIGHT_OFF (1 << 5)
7975#define BACKLIGHT_ON (1 << 4)
7976#define COLOR_MODE_OFF (1 << 3)
7977#define COLOR_MODE_ON (1 << 2)
7978#define TURN_ON (1 << 1)
7979#define SHUTDOWN (1 << 0)
7980
7981#define _MIPIA_DPI_DATA (dev_priv->mipi_mmio_base + 0xb04c)
7982#define _MIPIC_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c)
7983#define MIPI_DPI_DATA(port) _MMIO_MIPI(port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA)
7984#define COMMAND_BYTE_SHIFT 0
7985#define COMMAND_BYTE_MASK (0x3f << 0)
7986
7987#define _MIPIA_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb050)
7988#define _MIPIC_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850)
7989#define MIPI_INIT_COUNT(port) _MMIO_MIPI(port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT)
7990#define MASTER_INIT_TIMER_SHIFT 0
7991#define MASTER_INIT_TIMER_MASK (0xffff << 0)
7992
7993#define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb054)
7994#define _MIPIC_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854)
7995#define MIPI_MAX_RETURN_PKT_SIZE(port) _MMIO_MIPI(port, \
7996 _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE)
7997#define MAX_RETURN_PKT_SIZE_SHIFT 0
7998#define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0)
7999
8000#define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb058)
8001#define _MIPIC_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858)
8002#define MIPI_VIDEO_MODE_FORMAT(port) _MMIO_MIPI(port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT)
8003#define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4)
8004#define DISABLE_VIDEO_BTA (1 << 3)
8005#define IP_TG_CONFIG (1 << 2)
8006#define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE (1 << 0)
8007#define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0)
8008#define VIDEO_MODE_BURST (3 << 0)
8009
8010#define _MIPIA_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb05c)
8011#define _MIPIC_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c)
8012#define MIPI_EOT_DISABLE(port) _MMIO_MIPI(port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE)
8013#define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7)
8014#define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6)
8015#define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5)
8016#define HIGH_CONTENTION_RECOVERY_DISABLE (1 << 4)
8017#define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3)
8018#define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE (1 << 2)
8019#define CLOCKSTOP (1 << 1)
8020#define EOT_DISABLE (1 << 0)
8021
8022#define _MIPIA_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb060)
8023#define _MIPIC_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860)
8024#define MIPI_LP_BYTECLK(port) _MMIO_MIPI(port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK)
8025#define LP_BYTECLK_SHIFT 0
8026#define LP_BYTECLK_MASK (0xffff << 0)
8027
8028/* bits 31:0 */
8029#define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064)
8030#define _MIPIC_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864)
8031#define MIPI_LP_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA)
8032
8033/* bits 31:0 */
8034#define _MIPIA_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb068)
8035#define _MIPIC_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868)
8036#define MIPI_HS_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA)
8037
8038#define _MIPIA_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb06c)
8039#define _MIPIC_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb86c)
8040#define MIPI_LP_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL)
8041#define _MIPIA_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb070)
8042#define _MIPIC_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb870)
8043#define MIPI_HS_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL)
8044#define LONG_PACKET_WORD_COUNT_SHIFT 8
8045#define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8)
8046#define SHORT_PACKET_PARAM_SHIFT 8
8047#define SHORT_PACKET_PARAM_MASK (0xffff << 8)
8048#define VIRTUAL_CHANNEL_SHIFT 6
8049#define VIRTUAL_CHANNEL_MASK (3 << 6)
8050#define DATA_TYPE_SHIFT 0
8051#define DATA_TYPE_MASK (0x3f << 0)
8052/* data type values, see include/video/mipi_display.h */
8053
8054#define _MIPIA_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb074)
8055#define _MIPIC_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb874)
8056#define MIPI_GEN_FIFO_STAT(port) _MMIO_MIPI(port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT)
8057#define DPI_FIFO_EMPTY (1 << 28)
8058#define DBI_FIFO_EMPTY (1 << 27)
8059#define LP_CTRL_FIFO_EMPTY (1 << 26)
8060#define LP_CTRL_FIFO_HALF_EMPTY (1 << 25)
8061#define LP_CTRL_FIFO_FULL (1 << 24)
8062#define HS_CTRL_FIFO_EMPTY (1 << 18)
8063#define HS_CTRL_FIFO_HALF_EMPTY (1 << 17)
8064#define HS_CTRL_FIFO_FULL (1 << 16)
8065#define LP_DATA_FIFO_EMPTY (1 << 10)
8066#define LP_DATA_FIFO_HALF_EMPTY (1 << 9)
8067#define LP_DATA_FIFO_FULL (1 << 8)
8068#define HS_DATA_FIFO_EMPTY (1 << 2)
8069#define HS_DATA_FIFO_HALF_EMPTY (1 << 1)
8070#define HS_DATA_FIFO_FULL (1 << 0)
8071
8072#define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb078)
8073#define _MIPIC_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878)
8074#define MIPI_HS_LP_DBI_ENABLE(port) _MMIO_MIPI(port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE)
8075#define DBI_HS_LP_MODE_MASK (1 << 0)
8076#define DBI_LP_MODE (1 << 0)
8077#define DBI_HS_MODE (0 << 0)
8078
8079#define _MIPIA_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb080)
8080#define _MIPIC_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880)
8081#define MIPI_DPHY_PARAM(port) _MMIO_MIPI(port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM)
8082#define EXIT_ZERO_COUNT_SHIFT 24
8083#define EXIT_ZERO_COUNT_MASK (0x3f << 24)
8084#define TRAIL_COUNT_SHIFT 16
8085#define TRAIL_COUNT_MASK (0x1f << 16)
8086#define CLK_ZERO_COUNT_SHIFT 8
8087#define CLK_ZERO_COUNT_MASK (0xff << 8)
8088#define PREPARE_COUNT_SHIFT 0
8089#define PREPARE_COUNT_MASK (0x3f << 0)
8090
8091/* bits 31:0 */
8092#define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084)
8093#define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884)
8094#define MIPI_DBI_BW_CTRL(port) _MMIO_MIPI(port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL)
8095
8096#define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb088)
8097#define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb888)
8098#define MIPI_CLK_LANE_SWITCH_TIME_CNT(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT)
8099#define LP_HS_SSW_CNT_SHIFT 16
8100#define LP_HS_SSW_CNT_MASK (0xffff << 16)
8101#define HS_LP_PWR_SW_CNT_SHIFT 0
8102#define HS_LP_PWR_SW_CNT_MASK (0xffff << 0)
8103
8104#define _MIPIA_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb08c)
8105#define _MIPIC_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c)
8106#define MIPI_STOP_STATE_STALL(port) _MMIO_MIPI(port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL)
8107#define STOP_STATE_STALL_COUNTER_SHIFT 0
8108#define STOP_STATE_STALL_COUNTER_MASK (0xff << 0)
8109
8110#define _MIPIA_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb090)
8111#define _MIPIC_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890)
8112#define MIPI_INTR_STAT_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1)
8113#define _MIPIA_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb094)
8114#define _MIPIC_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894)
8115#define MIPI_INTR_EN_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1)
8116#define RX_CONTENTION_DETECTED (1 << 0)
8117
8118/* XXX: only pipe A ?!? */
8119#define MIPIA_DBI_TYPEC_CTRL (dev_priv->mipi_mmio_base + 0xb100)
8120#define DBI_TYPEC_ENABLE (1 << 31)
8121#define DBI_TYPEC_WIP (1 << 30)
8122#define DBI_TYPEC_OPTION_SHIFT 28
8123#define DBI_TYPEC_OPTION_MASK (3 << 28)
8124#define DBI_TYPEC_FREQ_SHIFT 24
8125#define DBI_TYPEC_FREQ_MASK (0xf << 24)
8126#define DBI_TYPEC_OVERRIDE (1 << 8)
8127#define DBI_TYPEC_OVERRIDE_COUNTER_SHIFT 0
8128#define DBI_TYPEC_OVERRIDE_COUNTER_MASK (0xff << 0)
8129
8130
8131/* MIPI adapter registers */
8132
8133#define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104)
8134#define _MIPIC_CTRL (dev_priv->mipi_mmio_base + 0xb904)
8135#define MIPI_CTRL(port) _MMIO_MIPI(port, _MIPIA_CTRL, _MIPIC_CTRL)
8136#define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */
8137#define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5)
8138#define ESCAPE_CLOCK_DIVIDER_1 (0 << 5)
8139#define ESCAPE_CLOCK_DIVIDER_2 (1 << 5)
8140#define ESCAPE_CLOCK_DIVIDER_4 (2 << 5)
8141#define READ_REQUEST_PRIORITY_SHIFT 3
8142#define READ_REQUEST_PRIORITY_MASK (3 << 3)
8143#define READ_REQUEST_PRIORITY_LOW (0 << 3)
8144#define READ_REQUEST_PRIORITY_HIGH (3 << 3)
8145#define RGB_FLIP_TO_BGR (1 << 2)
8146
8147#define BXT_PIPE_SELECT_MASK (7 << 7)
8148#define BXT_PIPE_SELECT(pipe) ((pipe) << 7)
8149
8150#define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108)
8151#define _MIPIC_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908)
8152#define MIPI_DATA_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS)
8153#define DATA_MEM_ADDRESS_SHIFT 5
8154#define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5)
8155#define DATA_VALID (1 << 0)
8156
8157#define _MIPIA_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb10c)
8158#define _MIPIC_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c)
8159#define MIPI_DATA_LENGTH(port) _MMIO_MIPI(port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH)
8160#define DATA_LENGTH_SHIFT 0
8161#define DATA_LENGTH_MASK (0xfffff << 0)
8162
8163#define _MIPIA_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb110)
8164#define _MIPIC_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910)
8165#define MIPI_COMMAND_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS)
8166#define COMMAND_MEM_ADDRESS_SHIFT 5
8167#define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5)
8168#define AUTO_PWG_ENABLE (1 << 2)
8169#define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1)
8170#define COMMAND_VALID (1 << 0)
8171
8172#define _MIPIA_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb114)
8173#define _MIPIC_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914)
8174#define MIPI_COMMAND_LENGTH(port) _MMIO_MIPI(port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH)
8175#define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */
8176#define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n)))
8177
8178#define _MIPIA_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb118)
8179#define _MIPIC_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918)
8180#define MIPI_READ_DATA_RETURN(port, n) _MMIO(_MIPI(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */
8181
8182#define _MIPIA_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb138)
8183#define _MIPIC_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938)
8184#define MIPI_READ_DATA_VALID(port) _MMIO_MIPI(port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID)
8185#define READ_DATA_VALID(n) (1 << (n))
8186
8187/* For UMS only (deprecated): */
8188#define _PALETTE_A (dev_priv->info.display_mmio_offset + 0xa000)
8189#define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800)
8190
8191/* MOCS (Memory Object Control State) registers */
8192#define GEN9_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */
8193
8194#define GEN9_GFX_MOCS(i) _MMIO(0xc800 + (i) * 4) /* Graphics MOCS registers */
8195#define GEN9_MFX0_MOCS(i) _MMIO(0xc900 + (i) * 4) /* Media 0 MOCS registers */
8196#define GEN9_MFX1_MOCS(i) _MMIO(0xca00 + (i) * 4) /* Media 1 MOCS registers */
8197#define GEN9_VEBOX_MOCS(i) _MMIO(0xcb00 + (i) * 4) /* Video MOCS registers */
8198#define GEN9_BLT_MOCS(i) _MMIO(0xcc00 + (i) * 4) /* Blitter MOCS registers */
8199
8200/* gamt regs */
8201#define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
8202#define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for LRA1/2 */
8203#define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV 0x5FF101FF /* max/min for LRA1/2 */
8204#define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL 0x67F1427F /* " " */
8205#define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT 0x5FF101FF /* " " */
8206
8207#endif /* _I915_REG_H_ */
1/* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
2 * All Rights Reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
14 * of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef _I915_REG_H_
26#define _I915_REG_H_
27
28#include "i915_reg_defs.h"
29#include "display/intel_display_reg_defs.h"
30
31/**
32 * DOC: The i915 register macro definition style guide
33 *
34 * Follow the style described here for new macros, and while changing existing
35 * macros. Do **not** mass change existing definitions just to update the style.
36 *
37 * File Layout
38 * ~~~~~~~~~~~
39 *
40 * Keep helper macros near the top. For example, _PIPE() and friends.
41 *
42 * Prefix macros that generally should not be used outside of this file with
43 * underscore '_'. For example, _PIPE() and friends, single instances of
44 * registers that are defined solely for the use by function-like macros.
45 *
46 * Avoid using the underscore prefixed macros outside of this file. There are
47 * exceptions, but keep them to a minimum.
48 *
49 * There are two basic types of register definitions: Single registers and
50 * register groups. Register groups are registers which have two or more
51 * instances, for example one per pipe, port, transcoder, etc. Register groups
52 * should be defined using function-like macros.
53 *
54 * For single registers, define the register offset first, followed by register
55 * contents.
56 *
57 * For register groups, define the register instance offsets first, prefixed
58 * with underscore, followed by a function-like macro choosing the right
59 * instance based on the parameter, followed by register contents.
60 *
61 * Define the register contents (i.e. bit and bit field macros) from most
62 * significant to least significant bit. Indent the register content macros
63 * using two extra spaces between ``#define`` and the macro name.
64 *
65 * Define bit fields using ``REG_GENMASK(h, l)``. Define bit field contents
66 * using ``REG_FIELD_PREP(mask, value)``. This will define the values already
67 * shifted in place, so they can be directly OR'd together. For convenience,
68 * function-like macros may be used to define bit fields, but do note that the
69 * macros may be needed to read as well as write the register contents.
70 *
71 * Define bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the name.
72 *
73 * Group the register and its contents together without blank lines, separate
74 * from other registers and their contents with one blank line.
75 *
76 * Indent macro values from macro names using TABs. Align values vertically. Use
77 * braces in macro values as needed to avoid unintended precedence after macro
78 * substitution. Use spaces in macro values according to kernel coding
79 * style. Use lower case in hexadecimal values.
80 *
81 * Naming
82 * ~~~~~~
83 *
84 * Try to name registers according to the specs. If the register name changes in
85 * the specs from platform to another, stick to the original name.
86 *
87 * Try to re-use existing register macro definitions. Only add new macros for
88 * new register offsets, or when the register contents have changed enough to
89 * warrant a full redefinition.
90 *
91 * When a register macro changes for a new platform, prefix the new macro using
92 * the platform acronym or generation. For example, ``SKL_`` or ``GEN8_``. The
93 * prefix signifies the start platform/generation using the register.
94 *
95 * When a bit (field) macro changes or gets added for a new platform, while
96 * retaining the existing register macro, add a platform acronym or generation
97 * suffix to the name. For example, ``_SKL`` or ``_GEN8``.
98 *
99 * Examples
100 * ~~~~~~~~
101 *
102 * (Note that the values in the example are indented using spaces instead of
103 * TABs to avoid misalignment in generated documentation. Use TABs in the
104 * definitions.)::
105 *
106 * #define _FOO_A 0xf000
107 * #define _FOO_B 0xf001
108 * #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B)
109 * #define FOO_ENABLE REG_BIT(31)
110 * #define FOO_MODE_MASK REG_GENMASK(19, 16)
111 * #define FOO_MODE_BAR REG_FIELD_PREP(FOO_MODE_MASK, 0)
112 * #define FOO_MODE_BAZ REG_FIELD_PREP(FOO_MODE_MASK, 1)
113 * #define FOO_MODE_QUX_SNB REG_FIELD_PREP(FOO_MODE_MASK, 2)
114 *
115 * #define BAR _MMIO(0xb000)
116 * #define GEN8_BAR _MMIO(0xb888)
117 */
118
119#define GU_CNTL_PROTECTED _MMIO(0x10100C)
120#define DEPRESENT REG_BIT(9)
121
122#define GU_CNTL _MMIO(0x101010)
123#define LMEM_INIT REG_BIT(7)
124#define DRIVERFLR REG_BIT(31)
125#define GU_DEBUG _MMIO(0x101018)
126#define DRIVERFLR_STATUS REG_BIT(31)
127
128#define GEN6_STOLEN_RESERVED _MMIO(0x1082C0)
129#define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20)
130#define GEN7_STOLEN_RESERVED_ADDR_MASK (0x3FFF << 18)
131#define GEN6_STOLEN_RESERVED_SIZE_MASK (3 << 4)
132#define GEN6_STOLEN_RESERVED_1M (0 << 4)
133#define GEN6_STOLEN_RESERVED_512K (1 << 4)
134#define GEN6_STOLEN_RESERVED_256K (2 << 4)
135#define GEN6_STOLEN_RESERVED_128K (3 << 4)
136#define GEN7_STOLEN_RESERVED_SIZE_MASK (1 << 5)
137#define GEN7_STOLEN_RESERVED_1M (0 << 5)
138#define GEN7_STOLEN_RESERVED_256K (1 << 5)
139#define GEN8_STOLEN_RESERVED_SIZE_MASK (3 << 7)
140#define GEN8_STOLEN_RESERVED_1M (0 << 7)
141#define GEN8_STOLEN_RESERVED_2M (1 << 7)
142#define GEN8_STOLEN_RESERVED_4M (2 << 7)
143#define GEN8_STOLEN_RESERVED_8M (3 << 7)
144#define GEN6_STOLEN_RESERVED_ENABLE (1 << 0)
145#define GEN11_STOLEN_RESERVED_ADDR_MASK (0xFFFFFFFFFFFULL << 20)
146
147#define _VGA_MSR_WRITE _MMIO(0x3c2)
148
149#define _GEN7_PIPEA_DE_LOAD_SL 0x70068
150#define _GEN7_PIPEB_DE_LOAD_SL 0x71068
151#define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL)
152
153/*
154 * Reset registers
155 */
156#define DEBUG_RESET_I830 _MMIO(0x6070)
157#define DEBUG_RESET_FULL (1 << 7)
158#define DEBUG_RESET_RENDER (1 << 8)
159#define DEBUG_RESET_DISPLAY (1 << 9)
160
161/*
162 * IOSF sideband
163 */
164#define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100)
165#define IOSF_DEVFN_SHIFT 24
166#define IOSF_OPCODE_SHIFT 16
167#define IOSF_PORT_SHIFT 8
168#define IOSF_BYTE_ENABLES_SHIFT 4
169#define IOSF_BAR_SHIFT 1
170#define IOSF_SB_BUSY (1 << 0)
171#define IOSF_PORT_BUNIT 0x03
172#define IOSF_PORT_PUNIT 0x04
173#define IOSF_PORT_NC 0x11
174#define IOSF_PORT_DPIO 0x12
175#define IOSF_PORT_GPIO_NC 0x13
176#define IOSF_PORT_CCK 0x14
177#define IOSF_PORT_DPIO_2 0x1a
178#define IOSF_PORT_FLISDSI 0x1b
179#define IOSF_PORT_GPIO_SC 0x48
180#define IOSF_PORT_GPIO_SUS 0xa8
181#define IOSF_PORT_CCU 0xa9
182#define CHV_IOSF_PORT_GPIO_N 0x13
183#define CHV_IOSF_PORT_GPIO_SE 0x48
184#define CHV_IOSF_PORT_GPIO_E 0xa8
185#define CHV_IOSF_PORT_GPIO_SW 0xb2
186#define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104)
187#define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108)
188
189/* DPIO registers */
190#define DPIO_DEVFN 0
191
192#define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110)
193#define DPIO_MODSEL1 (1 << 3) /* if ref clk b == 27 */
194#define DPIO_MODSEL0 (1 << 2) /* if ref clk a == 27 */
195#define DPIO_SFR_BYPASS (1 << 1)
196#define DPIO_CMNRST (1 << 0)
197
198#define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090)
199#define MIPIO_RST_CTRL (1 << 2)
200
201#define _BXT_PHY_CTL_DDI_A 0x64C00
202#define _BXT_PHY_CTL_DDI_B 0x64C10
203#define _BXT_PHY_CTL_DDI_C 0x64C20
204#define BXT_PHY_CMNLANE_POWERDOWN_ACK (1 << 10)
205#define BXT_PHY_LANE_POWERDOWN_ACK (1 << 9)
206#define BXT_PHY_LANE_ENABLED (1 << 8)
207#define BXT_PHY_CTL(port) _MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \
208 _BXT_PHY_CTL_DDI_B)
209
210#define _PHY_CTL_FAMILY_DDI 0x64C90
211#define _PHY_CTL_FAMILY_EDP 0x64C80
212#define _PHY_CTL_FAMILY_DDI_C 0x64CA0
213#define COMMON_RESET_DIS (1 << 31)
214#define BXT_PHY_CTL_FAMILY(phy) \
215 _MMIO(_PICK_EVEN_2RANGES(phy, 1, \
216 _PHY_CTL_FAMILY_DDI, _PHY_CTL_FAMILY_DDI, \
217 _PHY_CTL_FAMILY_EDP, _PHY_CTL_FAMILY_DDI_C))
218
219/* UAIMI scratch pad register 1 */
220#define UAIMI_SPR1 _MMIO(0x4F074)
221/* SKL VccIO mask */
222#define SKL_VCCIO_MASK 0x1
223/* SKL balance leg register */
224#define DISPIO_CR_TX_BMU_CR0 _MMIO(0x6C00C)
225/* I_boost values */
226#define BALANCE_LEG_SHIFT(port) (8 + 3 * (port))
227#define BALANCE_LEG_MASK(port) (7 << (8 + 3 * (port)))
228/* Balance leg disable bits */
229#define BALANCE_LEG_DISABLE_SHIFT 23
230#define BALANCE_LEG_DISABLE(port) (1 << (23 + (port)))
231
232/*
233 * Fence registers
234 * [0-7] @ 0x2000 gen2,gen3
235 * [8-15] @ 0x3000 945,g33,pnv
236 *
237 * [0-15] @ 0x3000 gen4,gen5
238 *
239 * [0-15] @ 0x100000 gen6,vlv,chv
240 * [0-31] @ 0x100000 gen7+
241 */
242#define FENCE_REG(i) _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4)
243#define I830_FENCE_START_MASK 0x07f80000
244#define I830_FENCE_TILING_Y_SHIFT 12
245#define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
246#define I830_FENCE_PITCH_SHIFT 4
247#define I830_FENCE_REG_VALID (1 << 0)
248#define I915_FENCE_MAX_PITCH_VAL 4
249#define I830_FENCE_MAX_PITCH_VAL 6
250#define I830_FENCE_MAX_SIZE_VAL (1 << 8)
251
252#define I915_FENCE_START_MASK 0x0ff00000
253#define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
254
255#define FENCE_REG_965_LO(i) _MMIO(0x03000 + (i) * 8)
256#define FENCE_REG_965_HI(i) _MMIO(0x03000 + (i) * 8 + 4)
257#define I965_FENCE_PITCH_SHIFT 2
258#define I965_FENCE_TILING_Y_SHIFT 1
259#define I965_FENCE_REG_VALID (1 << 0)
260#define I965_FENCE_MAX_PITCH_VAL 0x0400
261
262#define FENCE_REG_GEN6_LO(i) _MMIO(0x100000 + (i) * 8)
263#define FENCE_REG_GEN6_HI(i) _MMIO(0x100000 + (i) * 8 + 4)
264#define GEN6_FENCE_PITCH_SHIFT 32
265#define GEN7_FENCE_MAX_PITCH_VAL 0x0800
266
267
268/* control register for cpu gtt access */
269#define TILECTL _MMIO(0x101000)
270#define TILECTL_SWZCTL (1 << 0)
271#define TILECTL_TLBPF (1 << 1)
272#define TILECTL_TLB_PREFETCH_DIS (1 << 2)
273#define TILECTL_BACKSNOOP_DIS (1 << 3)
274
275/*
276 * Instruction and interrupt control regs
277 */
278#define PGTBL_CTL _MMIO(0x02020)
279#define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */
280#define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */
281#define PGTBL_ER _MMIO(0x02024)
282#define PRB0_BASE (0x2030 - 0x30)
283#define PRB1_BASE (0x2040 - 0x30) /* 830,gen3 */
284#define PRB2_BASE (0x2050 - 0x30) /* gen3 */
285#define SRB0_BASE (0x2100 - 0x30) /* gen2 */
286#define SRB1_BASE (0x2110 - 0x30) /* gen2 */
287#define SRB2_BASE (0x2120 - 0x30) /* 830 */
288#define SRB3_BASE (0x2130 - 0x30) /* 830 */
289#define RENDER_RING_BASE 0x02000
290#define BSD_RING_BASE 0x04000
291#define GEN6_BSD_RING_BASE 0x12000
292#define GEN8_BSD2_RING_BASE 0x1c000
293#define GEN11_BSD_RING_BASE 0x1c0000
294#define GEN11_BSD2_RING_BASE 0x1c4000
295#define GEN11_BSD3_RING_BASE 0x1d0000
296#define GEN11_BSD4_RING_BASE 0x1d4000
297#define XEHP_BSD5_RING_BASE 0x1e0000
298#define XEHP_BSD6_RING_BASE 0x1e4000
299#define XEHP_BSD7_RING_BASE 0x1f0000
300#define XEHP_BSD8_RING_BASE 0x1f4000
301#define VEBOX_RING_BASE 0x1a000
302#define GEN11_VEBOX_RING_BASE 0x1c8000
303#define GEN11_VEBOX2_RING_BASE 0x1d8000
304#define XEHP_VEBOX3_RING_BASE 0x1e8000
305#define XEHP_VEBOX4_RING_BASE 0x1f8000
306#define MTL_GSC_RING_BASE 0x11a000
307#define GEN12_COMPUTE0_RING_BASE 0x1a000
308#define GEN12_COMPUTE1_RING_BASE 0x1c000
309#define GEN12_COMPUTE2_RING_BASE 0x1e000
310#define GEN12_COMPUTE3_RING_BASE 0x26000
311#define BLT_RING_BASE 0x22000
312#define XEHPC_BCS1_RING_BASE 0x3e0000
313#define XEHPC_BCS2_RING_BASE 0x3e2000
314#define XEHPC_BCS3_RING_BASE 0x3e4000
315#define XEHPC_BCS4_RING_BASE 0x3e6000
316#define XEHPC_BCS5_RING_BASE 0x3e8000
317#define XEHPC_BCS6_RING_BASE 0x3ea000
318#define XEHPC_BCS7_RING_BASE 0x3ec000
319#define XEHPC_BCS8_RING_BASE 0x3ee000
320#define DG1_GSC_HECI1_BASE 0x00258000
321#define DG1_GSC_HECI2_BASE 0x00259000
322#define DG2_GSC_HECI1_BASE 0x00373000
323#define DG2_GSC_HECI2_BASE 0x00374000
324#define MTL_GSC_HECI1_BASE 0x00116000
325#define MTL_GSC_HECI2_BASE 0x00117000
326
327#define HECI_H_CSR(base) _MMIO((base) + 0x4)
328#define HECI_H_CSR_IE REG_BIT(0)
329#define HECI_H_CSR_IS REG_BIT(1)
330#define HECI_H_CSR_IG REG_BIT(2)
331#define HECI_H_CSR_RDY REG_BIT(3)
332#define HECI_H_CSR_RST REG_BIT(4)
333
334#define HECI_H_GS1(base) _MMIO((base) + 0xc4c)
335#define HECI_H_GS1_ER_PREP REG_BIT(0)
336
337/*
338 * The FWSTS register values are FW defined and can be different between
339 * HECI1 and HECI2
340 */
341#define HECI_FWSTS1 0xc40
342#define HECI1_FWSTS1_CURRENT_STATE REG_GENMASK(3, 0)
343#define HECI1_FWSTS1_CURRENT_STATE_RESET 0
344#define HECI1_FWSTS1_PROXY_STATE_NORMAL 5
345#define HECI1_FWSTS1_INIT_COMPLETE REG_BIT(9)
346#define HECI_FWSTS2 0xc48
347#define HECI_FWSTS3 0xc60
348#define HECI_FWSTS4 0xc64
349#define HECI_FWSTS5 0xc68
350#define HECI1_FWSTS5_HUC_AUTH_DONE (1 << 19)
351#define HECI_FWSTS6 0xc6c
352
353/* the FWSTS regs are 1-based, so we use -base for index 0 to get an invalid reg */
354#define HECI_FWSTS(base, x) _MMIO((base) + _PICK(x, -(base), \
355 HECI_FWSTS1, \
356 HECI_FWSTS2, \
357 HECI_FWSTS3, \
358 HECI_FWSTS4, \
359 HECI_FWSTS5, \
360 HECI_FWSTS6))
361
362#define HSW_GTT_CACHE_EN _MMIO(0x4024)
363#define GTT_CACHE_EN_ALL 0xF0007FFF
364#define GEN7_WR_WATERMARK _MMIO(0x4028)
365#define GEN7_GFX_PRIO_CTRL _MMIO(0x402C)
366#define ARB_MODE _MMIO(0x4030)
367#define ARB_MODE_SWIZZLE_SNB (1 << 4)
368#define ARB_MODE_SWIZZLE_IVB (1 << 5)
369#define GEN7_GFX_PEND_TLB0 _MMIO(0x4034)
370#define GEN7_GFX_PEND_TLB1 _MMIO(0x4038)
371/* L3, CVS, ZTLB, RCC, CASC LRA min, max values */
372#define GEN7_LRA_LIMITS(i) _MMIO(0x403C + (i) * 4)
373#define GEN7_LRA_LIMITS_REG_NUM 13
374#define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070)
375#define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074)
376
377#define GEN7_ERR_INT _MMIO(0x44040)
378#define ERR_INT_POISON (1 << 31)
379#define ERR_INT_MMIO_UNCLAIMED (1 << 13)
380#define ERR_INT_PIPE_CRC_DONE_C (1 << 8)
381#define ERR_INT_FIFO_UNDERRUN_C (1 << 6)
382#define ERR_INT_PIPE_CRC_DONE_B (1 << 5)
383#define ERR_INT_FIFO_UNDERRUN_B (1 << 3)
384#define ERR_INT_PIPE_CRC_DONE_A (1 << 2)
385#define ERR_INT_PIPE_CRC_DONE(pipe) (1 << (2 + (pipe) * 3))
386#define ERR_INT_FIFO_UNDERRUN_A (1 << 0)
387#define ERR_INT_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3))
388
389#define FPGA_DBG _MMIO(0x42300)
390#define FPGA_DBG_RM_NOCLAIM REG_BIT(31)
391
392#define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028)
393#define CLAIM_ER_CLR REG_BIT(31)
394#define CLAIM_ER_OVERFLOW REG_BIT(16)
395#define CLAIM_ER_CTR_MASK REG_GENMASK(15, 0)
396
397#define DERRMR _MMIO(0x44050)
398/* Note that HBLANK events are reserved on bdw+ */
399#define DERRMR_PIPEA_SCANLINE (1 << 0)
400#define DERRMR_PIPEA_PRI_FLIP_DONE (1 << 1)
401#define DERRMR_PIPEA_SPR_FLIP_DONE (1 << 2)
402#define DERRMR_PIPEA_VBLANK (1 << 3)
403#define DERRMR_PIPEA_HBLANK (1 << 5)
404#define DERRMR_PIPEB_SCANLINE (1 << 8)
405#define DERRMR_PIPEB_PRI_FLIP_DONE (1 << 9)
406#define DERRMR_PIPEB_SPR_FLIP_DONE (1 << 10)
407#define DERRMR_PIPEB_VBLANK (1 << 11)
408#define DERRMR_PIPEB_HBLANK (1 << 13)
409/* Note that PIPEC is not a simple translation of PIPEA/PIPEB */
410#define DERRMR_PIPEC_SCANLINE (1 << 14)
411#define DERRMR_PIPEC_PRI_FLIP_DONE (1 << 15)
412#define DERRMR_PIPEC_SPR_FLIP_DONE (1 << 20)
413#define DERRMR_PIPEC_VBLANK (1 << 21)
414#define DERRMR_PIPEC_HBLANK (1 << 22)
415
416#define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030)
417#define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034)
418#define SCPD0 _MMIO(0x209c) /* 915+ only */
419#define SCPD_FBC_IGNORE_3D (1 << 6)
420#define CSTATE_RENDER_CLOCK_GATE_DISABLE (1 << 5)
421#define GEN2_IER _MMIO(0x20a0)
422#define GEN2_IIR _MMIO(0x20a4)
423#define GEN2_IMR _MMIO(0x20a8)
424#define GEN2_ISR _MMIO(0x20ac)
425
426#define GEN2_IRQ_REGS I915_IRQ_REGS(GEN2_IMR, \
427 GEN2_IER, \
428 GEN2_IIR)
429
430#define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060)
431#define GINT_DIS (1 << 22)
432#define GCFG_DIS (1 << 8)
433#define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064)
434#define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084)
435#define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0)
436#define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4)
437#define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8)
438#define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac)
439#define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120)
440#define VLV_PCBR_ADDR_SHIFT 12
441
442#define VLV_IRQ_REGS I915_IRQ_REGS(VLV_IMR, \
443 VLV_IER, \
444 VLV_IIR)
445
446#define DISPLAY_PLANE_FLIP_PENDING(plane) (1 << (11 - (plane))) /* A and B only */
447#define EIR _MMIO(0x20b0)
448#define EMR _MMIO(0x20b4)
449#define ESR _MMIO(0x20b8)
450#define GM45_ERROR_PAGE_TABLE (1 << 5)
451#define GM45_ERROR_MEM_PRIV (1 << 4)
452#define I915_ERROR_PAGE_TABLE (1 << 4)
453#define GM45_ERROR_CP_PRIV (1 << 3)
454#define I915_ERROR_MEMORY_REFRESH (1 << 1)
455#define I915_ERROR_INSTRUCTION (1 << 0)
456#define INSTPM _MMIO(0x20c0)
457#define INSTPM_SELF_EN (1 << 12) /* 915GM only */
458#define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts
459 will not assert AGPBUSY# and will only
460 be delivered when out of C3. */
461#define INSTPM_FORCE_ORDERING (1 << 7) /* GEN6+ */
462#define INSTPM_TLB_INVALIDATE (1 << 9)
463#define INSTPM_SYNC_FLUSH (1 << 5)
464#define MEM_MODE _MMIO(0x20cc)
465#define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */
466#define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */
467#define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) /* 85x only */
468#define FW_BLC _MMIO(0x20d8)
469#define FW_BLC2 _MMIO(0x20dc)
470#define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */
471#define FW_BLC_SELF_EN_MASK (1 << 31)
472#define FW_BLC_SELF_FIFO_MASK (1 << 16) /* 945 only */
473#define FW_BLC_SELF_EN (1 << 15) /* 945 only */
474#define MM_BURST_LENGTH 0x00700000
475#define MM_FIFO_WATERMARK 0x0001F000
476#define LM_BURST_LENGTH 0x00000700
477#define LM_FIFO_WATERMARK 0x0000001F
478#define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */
479
480#define _MBUS_ABOX0_CTL 0x45038
481#define _MBUS_ABOX1_CTL 0x45048
482#define _MBUS_ABOX2_CTL 0x4504C
483#define MBUS_ABOX_CTL(x) \
484 _MMIO(_PICK_EVEN_2RANGES(x, 2, \
485 _MBUS_ABOX0_CTL, _MBUS_ABOX1_CTL, \
486 _MBUS_ABOX2_CTL, _MBUS_ABOX2_CTL))
487
488#define MBUS_ABOX_BW_CREDIT_MASK (3 << 20)
489#define MBUS_ABOX_BW_CREDIT(x) ((x) << 20)
490#define MBUS_ABOX_B_CREDIT_MASK (0xF << 16)
491#define MBUS_ABOX_B_CREDIT(x) ((x) << 16)
492#define MBUS_ABOX_BT_CREDIT_POOL2_MASK (0x1F << 8)
493#define MBUS_ABOX_BT_CREDIT_POOL2(x) ((x) << 8)
494#define MBUS_ABOX_BT_CREDIT_POOL1_MASK (0x1F << 0)
495#define MBUS_ABOX_BT_CREDIT_POOL1(x) ((x) << 0)
496
497/* Make render/texture TLB fetches lower priorty than associated data
498 * fetches. This is not turned on by default
499 */
500#define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15)
501
502/* Isoch request wait on GTT enable (Display A/B/C streams).
503 * Make isoch requests stall on the TLB update. May cause
504 * display underruns (test mode only)
505 */
506#define MI_ARB_ISOCH_WAIT_GTT (1 << 14)
507
508/* Block grant count for isoch requests when block count is
509 * set to a finite value.
510 */
511#define MI_ARB_BLOCK_GRANT_MASK (3 << 12)
512#define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */
513#define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */
514#define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */
515#define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */
516
517/* Enable render writes to complete in C2/C3/C4 power states.
518 * If this isn't enabled, render writes are prevented in low
519 * power states. That seems bad to me.
520 */
521#define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11)
522
523/* This acknowledges an async flip immediately instead
524 * of waiting for 2TLB fetches.
525 */
526#define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10)
527
528/* Enables non-sequential data reads through arbiter
529 */
530#define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9)
531
532/* Disable FSB snooping of cacheable write cycles from binner/render
533 * command stream
534 */
535#define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8)
536
537/* Arbiter time slice for non-isoch streams */
538#define MI_ARB_TIME_SLICE_MASK (7 << 5)
539#define MI_ARB_TIME_SLICE_1 (0 << 5)
540#define MI_ARB_TIME_SLICE_2 (1 << 5)
541#define MI_ARB_TIME_SLICE_4 (2 << 5)
542#define MI_ARB_TIME_SLICE_6 (3 << 5)
543#define MI_ARB_TIME_SLICE_8 (4 << 5)
544#define MI_ARB_TIME_SLICE_10 (5 << 5)
545#define MI_ARB_TIME_SLICE_14 (6 << 5)
546#define MI_ARB_TIME_SLICE_16 (7 << 5)
547
548/* Low priority grace period page size */
549#define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
550#define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
551
552/* Disable display A/B trickle feed */
553#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
554
555/* Set display plane priority */
556#define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
557#define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
558
559#define MI_STATE _MMIO(0x20e4) /* gen2 only */
560#define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */
561#define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */
562
563/* On modern GEN architectures interrupt control consists of two sets
564 * of registers. The first set pertains to the ring generating the
565 * interrupt. The second control is for the functional block generating the
566 * interrupt. These are PM, GT, DE, etc.
567 *
568 * Luckily *knocks on wood* all the ring interrupt bits match up with the
569 * GT interrupt bits, so we don't need to duplicate the defines.
570 *
571 * These defines should cover us well from SNB->HSW with minor exceptions
572 * it can also work on ILK.
573 */
574#define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26)
575#define GT_BLT_CS_ERROR_INTERRUPT (1 << 25)
576#define GT_BLT_USER_INTERRUPT (1 << 22)
577#define GT_BSD_CS_ERROR_INTERRUPT (1 << 15)
578#define GT_BSD_USER_INTERRUPT (1 << 12)
579#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */
580#define GT_WAIT_SEMAPHORE_INTERRUPT REG_BIT(11) /* bdw+ */
581#define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8)
582#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */
583#define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4)
584#define GT_CS_MASTER_ERROR_INTERRUPT REG_BIT(3)
585#define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2)
586#define GT_RENDER_DEBUG_INTERRUPT (1 << 1)
587#define GT_RENDER_USER_INTERRUPT (1 << 0)
588
589#define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */
590#define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */
591
592#define GT_PARITY_ERROR(dev_priv) \
593 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \
594 (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
595
596/* These are all the "old" interrupts */
597#define ILK_BSD_USER_INTERRUPT (1 << 5)
598
599#define I915_PM_INTERRUPT (1 << 31)
600#define I915_ISP_INTERRUPT (1 << 22)
601#define I915_LPE_PIPE_B_INTERRUPT (1 << 21)
602#define I915_LPE_PIPE_A_INTERRUPT (1 << 20)
603#define I915_MIPIC_INTERRUPT (1 << 19)
604#define I915_MIPIA_INTERRUPT (1 << 18)
605#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 18)
606#define I915_DISPLAY_PORT_INTERRUPT (1 << 17)
607#define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1 << 16)
608#define I915_MASTER_ERROR_INTERRUPT (1 << 15)
609#define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1 << 14)
610#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1 << 14) /* p-state */
611#define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1 << 13)
612#define I915_HWB_OOM_INTERRUPT (1 << 13)
613#define I915_LPE_PIPE_C_INTERRUPT (1 << 12)
614#define I915_SYNC_STATUS_INTERRUPT (1 << 12)
615#define I915_MISC_INTERRUPT (1 << 11)
616#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1 << 11)
617#define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1 << 10)
618#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1 << 10)
619#define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1 << 9)
620#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1 << 9)
621#define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1 << 8)
622#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1 << 8)
623#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1 << 7)
624#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1 << 6)
625#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1 << 5)
626#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1 << 4)
627#define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1 << 3)
628#define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1 << 2)
629#define I915_DEBUG_INTERRUPT (1 << 2)
630#define I915_WINVALID_INTERRUPT (1 << 1)
631#define I915_USER_INTERRUPT (1 << 1)
632#define I915_ASLE_INTERRUPT (1 << 0)
633#define I915_BSD_USER_INTERRUPT (1 << 25)
634
635#define GEN6_BSD_RNCID _MMIO(0x12198)
636
637#define GEN7_FF_THREAD_MODE _MMIO(0x20a0)
638#define GEN7_FF_SCHED_MASK 0x0077070
639#define GEN8_FF_DS_REF_CNT_FFME (1 << 19)
640#define GEN12_FF_TESSELATION_DOP_GATE_DISABLE BIT(19)
641#define GEN7_FF_TS_SCHED_HS1 (0x5 << 16)
642#define GEN7_FF_TS_SCHED_HS0 (0x3 << 16)
643#define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1 << 16)
644#define GEN7_FF_TS_SCHED_HW (0x0 << 16) /* Default */
645#define GEN7_FF_VS_REF_CNT_FFME (1 << 15)
646#define GEN7_FF_VS_SCHED_HS1 (0x5 << 12)
647#define GEN7_FF_VS_SCHED_HS0 (0x3 << 12)
648#define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1 << 12) /* Default */
649#define GEN7_FF_VS_SCHED_HW (0x0 << 12)
650#define GEN7_FF_DS_SCHED_HS1 (0x5 << 4)
651#define GEN7_FF_DS_SCHED_HS0 (0x3 << 4)
652#define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1 << 4) /* Default */
653#define GEN7_FF_DS_SCHED_HW (0x0 << 4)
654
655#define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000)
656#define ILK_FBCQ_DIS REG_BIT(22)
657#define ILK_PABSTRETCH_DIS REG_BIT(21)
658#define ILK_SABSTRETCH_DIS REG_BIT(20)
659#define IVB_PRI_STRETCH_MAX_MASK REG_GENMASK(21, 20)
660#define IVB_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 0)
661#define IVB_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 1)
662#define IVB_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 2)
663#define IVB_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 3)
664#define IVB_SPR_STRETCH_MAX_MASK REG_GENMASK(19, 18)
665#define IVB_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 0)
666#define IVB_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 1)
667#define IVB_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 2)
668#define IVB_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 3)
669
670#define IPS_CTL _MMIO(0x43408)
671#define IPS_ENABLE REG_BIT(31)
672#define IPS_FALSE_COLOR REG_BIT(4)
673
674/*
675 * Clock control & power management
676 */
677#define _DPLL_A 0x6014
678#define _DPLL_B 0x6018
679#define _CHV_DPLL_C 0x6030
680#define DPLL(dev_priv, pipe) _MMIO_BASE_PIPE3(DISPLAY_MMIO_BASE(dev_priv), \
681 (pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
682
683#define VGA0 _MMIO(0x6000)
684#define VGA1 _MMIO(0x6004)
685#define VGA_PD _MMIO(0x6010)
686#define VGA0_PD_P2_DIV_4 (1 << 7)
687#define VGA0_PD_P1_DIV_2 (1 << 5)
688#define VGA0_PD_P1_SHIFT 0
689#define VGA0_PD_P1_MASK (0x1f << 0)
690#define VGA1_PD_P2_DIV_4 (1 << 15)
691#define VGA1_PD_P1_DIV_2 (1 << 13)
692#define VGA1_PD_P1_SHIFT 8
693#define VGA1_PD_P1_MASK (0x1f << 8)
694#define DPLL_VCO_ENABLE (1 << 31)
695#define DPLL_SDVO_HIGH_SPEED (1 << 30)
696#define DPLL_DVO_2X_MODE (1 << 30)
697#define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30)
698#define DPLL_SYNCLOCK_ENABLE (1 << 29)
699#define DPLL_REF_CLK_ENABLE_VLV (1 << 29)
700#define DPLL_VGA_MODE_DIS (1 << 28)
701#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
702#define DPLLB_MODE_LVDS (2 << 26) /* i915 */
703#define DPLL_MODE_MASK (3 << 26)
704#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
705#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
706#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
707#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
708#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
709#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
710#define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
711#define DPLL_LOCK_VLV (1 << 15)
712#define DPLL_INTEGRATED_CRI_CLK_VLV (1 << 14)
713#define DPLL_INTEGRATED_REF_CLK_VLV (1 << 13)
714#define DPLL_SSC_REF_CLK_CHV (1 << 13)
715#define DPLL_PORTC_READY_MASK (0xf << 4)
716#define DPLL_PORTB_READY_MASK (0xf)
717
718#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
719
720/* Additional CHV pll/phy registers */
721#define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240)
722#define DPLL_PORTD_READY_MASK (0xf)
723#define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100)
724#define PHY_CH_POWER_DOWN_OVRD_EN(phy, ch) (1 << (2 * (phy) + (ch) + 27))
725#define PHY_LDO_DELAY_0NS 0x0
726#define PHY_LDO_DELAY_200NS 0x1
727#define PHY_LDO_DELAY_600NS 0x2
728#define PHY_LDO_SEQ_DELAY(delay, phy) ((delay) << (2 * (phy) + 23))
729#define PHY_CH_POWER_DOWN_OVRD(mask, phy, ch) ((mask) << (8 * (phy) + 4 * (ch) + 11))
730#define PHY_CH_SU_PSR 0x1
731#define PHY_CH_DEEP_PSR 0x7
732#define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6 * (phy) + 3 * (ch) + 2))
733#define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy))
734#define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104)
735#define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1 << 31) : (1 << 30))
736#define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6 - (6 * (phy) + 3 * (ch))))
737#define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8 - (6 * (phy) + 3 * (ch) + (spline))))
738
739/*
740 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
741 * this field (only one bit may be set).
742 */
743#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
744#define DPLL_FPA01_P1_POST_DIV_SHIFT 16
745#define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
746/* i830, required in DVO non-gang */
747#define PLL_P2_DIVIDE_BY_4 (1 << 23)
748#define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
749#define PLL_REF_INPUT_DREFCLK (0 << 13)
750#define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
751#define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
752#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
753#define PLL_REF_INPUT_MASK (3 << 13)
754#define PLL_LOAD_PULSE_PHASE_SHIFT 9
755/* Ironlake */
756# define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
757# define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
758# define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x) - 1) << 9)
759# define DPLL_FPA1_P1_POST_DIV_SHIFT 0
760# define DPLL_FPA1_P1_POST_DIV_MASK 0xff
761
762/*
763 * Parallel to Serial Load Pulse phase selection.
764 * Selects the phase for the 10X DPLL clock for the PCIe
765 * digital display port. The range is 4 to 13; 10 or more
766 * is just a flip delay. The default is 6
767 */
768#define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
769#define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
770/*
771 * SDVO multiplier for 945G/GM. Not used on 965.
772 */
773#define SDVO_MULTIPLIER_MASK 0x000000ff
774#define SDVO_MULTIPLIER_SHIFT_HIRES 4
775#define SDVO_MULTIPLIER_SHIFT_VGA 0
776
777#define _DPLL_A_MD 0x601c
778#define _DPLL_B_MD 0x6020
779#define _CHV_DPLL_C_MD 0x603c
780#define DPLL_MD(dev_priv, pipe) _MMIO_BASE_PIPE3(DISPLAY_MMIO_BASE(dev_priv), \
781 (pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
782
783/*
784 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
785 *
786 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
787 */
788#define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
789#define DPLL_MD_UDI_DIVIDER_SHIFT 24
790/* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
791#define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
792#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
793/*
794 * SDVO/UDI pixel multiplier.
795 *
796 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
797 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
798 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
799 * dummy bytes in the datastream at an increased clock rate, with both sides of
800 * the link knowing how many bytes are fill.
801 *
802 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
803 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
804 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
805 * through an SDVO command.
806 *
807 * This register field has values of multiplication factor minus 1, with
808 * a maximum multiplier of 5 for SDVO.
809 */
810#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
811#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
812/*
813 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
814 * This best be set to the default value (3) or the CRT won't work. No,
815 * I don't entirely understand what this does...
816 */
817#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
818#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
819
820#define RAWCLK_FREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6024)
821
822#define _FPA0 0x6040
823#define _FPA1 0x6044
824#define _FPB0 0x6048
825#define _FPB1 0x604c
826#define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0)
827#define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1)
828#define FP_N_DIV_MASK 0x003f0000
829#define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
830#define FP_N_DIV_SHIFT 16
831#define FP_M1_DIV_MASK 0x00003f00
832#define FP_M1_DIV_SHIFT 8
833#define FP_M2_DIV_MASK 0x0000003f
834#define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
835#define FP_M2_DIV_SHIFT 0
836#define DPLL_TEST _MMIO(0x606c)
837#define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
838#define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
839#define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
840#define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
841#define DPLLB_TEST_N_BYPASS (1 << 19)
842#define DPLLB_TEST_M_BYPASS (1 << 18)
843#define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
844#define DPLLA_TEST_N_BYPASS (1 << 3)
845#define DPLLA_TEST_M_BYPASS (1 << 2)
846#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
847#define D_STATE _MMIO(0x6104)
848#define DSTATE_GFX_RESET_I830 (1 << 6)
849#define DSTATE_PLL_D3_OFF (1 << 3)
850#define DSTATE_GFX_CLOCK_GATING (1 << 1)
851#define DSTATE_DOT_CLOCK_GATING (1 << 0)
852#define DSPCLK_GATE_D(__i915) _MMIO(DISPLAY_MMIO_BASE(__i915) + 0x6200)
853# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
854# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
855# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
856# define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
857# define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
858# define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
859# define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
860# define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 24) /* pnv */
861# define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
862# define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
863# define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
864# define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
865# define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
866# define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
867# define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
868# define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
869# define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
870# define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
871# define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
872# define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
873# define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
874# define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
875# define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
876# define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
877# define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
878# define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
879# define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
880# define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
881# define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
882/*
883 * This bit must be set on the 830 to prevent hangs when turning off the
884 * overlay scaler.
885 */
886# define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
887# define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
888# define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
889# define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
890# define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
891
892#define RENCLK_GATE_D1 _MMIO(0x6204)
893# define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
894# define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
895# define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
896# define PC_BE_CLOCK_GATE_DISABLE (1 << 10)
897# define WINDOWER_CLOCK_GATE_DISABLE (1 << 9)
898# define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8)
899# define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7)
900# define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6)
901# define MAG_CLOCK_GATE_DISABLE (1 << 5)
902/* This bit must be unset on 855,865 */
903# define MECI_CLOCK_GATE_DISABLE (1 << 4)
904# define DCMP_CLOCK_GATE_DISABLE (1 << 3)
905# define MEC_CLOCK_GATE_DISABLE (1 << 2)
906# define MECO_CLOCK_GATE_DISABLE (1 << 1)
907/* This bit must be set on 855,865. */
908# define SV_CLOCK_GATE_DISABLE (1 << 0)
909# define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16)
910# define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15)
911# define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14)
912# define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13)
913# define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12)
914# define I915_WM_CLOCK_GATE_DISABLE (1 << 11)
915# define I915_IZ_CLOCK_GATE_DISABLE (1 << 10)
916# define I915_PI_CLOCK_GATE_DISABLE (1 << 9)
917# define I915_DI_CLOCK_GATE_DISABLE (1 << 8)
918# define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7)
919# define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6)
920# define I915_SC_CLOCK_GATE_DISABLE (1 << 5)
921# define I915_FL_CLOCK_GATE_DISABLE (1 << 4)
922# define I915_DM_CLOCK_GATE_DISABLE (1 << 3)
923# define I915_PS_CLOCK_GATE_DISABLE (1 << 2)
924# define I915_CC_CLOCK_GATE_DISABLE (1 << 1)
925# define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
926
927# define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30)
928/* This bit must always be set on 965G/965GM */
929# define I965_RCC_CLOCK_GATE_DISABLE (1 << 29)
930# define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28)
931# define I965_DAP_CLOCK_GATE_DISABLE (1 << 27)
932# define I965_ROC_CLOCK_GATE_DISABLE (1 << 26)
933# define I965_GW_CLOCK_GATE_DISABLE (1 << 25)
934# define I965_TD_CLOCK_GATE_DISABLE (1 << 24)
935/* This bit must always be set on 965G */
936# define I965_ISC_CLOCK_GATE_DISABLE (1 << 23)
937# define I965_IC_CLOCK_GATE_DISABLE (1 << 22)
938# define I965_EU_CLOCK_GATE_DISABLE (1 << 21)
939# define I965_IF_CLOCK_GATE_DISABLE (1 << 20)
940# define I965_TC_CLOCK_GATE_DISABLE (1 << 19)
941# define I965_SO_CLOCK_GATE_DISABLE (1 << 17)
942# define I965_FBC_CLOCK_GATE_DISABLE (1 << 16)
943# define I965_MARI_CLOCK_GATE_DISABLE (1 << 15)
944# define I965_MASF_CLOCK_GATE_DISABLE (1 << 14)
945# define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13)
946# define I965_EM_CLOCK_GATE_DISABLE (1 << 12)
947# define I965_UC_CLOCK_GATE_DISABLE (1 << 11)
948# define I965_SI_CLOCK_GATE_DISABLE (1 << 6)
949# define I965_MT_CLOCK_GATE_DISABLE (1 << 5)
950# define I965_PL_CLOCK_GATE_DISABLE (1 << 4)
951# define I965_DG_CLOCK_GATE_DISABLE (1 << 3)
952# define I965_QC_CLOCK_GATE_DISABLE (1 << 2)
953# define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
954# define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
955
956#define RENCLK_GATE_D2 _MMIO(0x6208)
957#define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
958#define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
959#define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
960
961#define VDECCLK_GATE_D _MMIO(0x620C) /* g4x only */
962#define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4)
963
964#define RAMCLK_GATE_D _MMIO(0x6210) /* CRL only */
965#define DEUC _MMIO(0x6214) /* CRL only */
966
967#define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500)
968#define FW_CSPWRDWNEN (1 << 15)
969
970#define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504)
971
972#define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508)
973#define CDCLK_FREQ_SHIFT 4
974#define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT)
975#define CZCLK_FREQ_MASK 0xf
976
977#define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C)
978#define PFI_CREDIT_63 (9 << 28) /* chv only */
979#define PFI_CREDIT_31 (8 << 28) /* chv only */
980#define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */
981#define PFI_CREDIT_RESEND (1 << 27)
982#define VGA_FAST_MODE_DISABLE (1 << 14)
983
984#define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510)
985
986#define PEG_BAND_GAP_DATA _MMIO(0x14d68)
987
988#define BXT_RP_STATE_CAP _MMIO(0x138170)
989#define GEN9_RP_STATE_LIMITS _MMIO(0x138148)
990
991#define MTL_RP_STATE_CAP _MMIO(0x138000)
992#define MTL_MEDIAP_STATE_CAP _MMIO(0x138020)
993#define MTL_RP0_CAP_MASK REG_GENMASK(8, 0)
994#define MTL_RPN_CAP_MASK REG_GENMASK(24, 16)
995
996#define MTL_GT_RPE_FREQUENCY _MMIO(0x13800c)
997#define MTL_MPE_FREQUENCY _MMIO(0x13802c)
998#define MTL_RPE_MASK REG_GENMASK(8, 0)
999
1000#define GT0_PERF_LIMIT_REASONS _MMIO(0x1381a8)
1001#define GT0_PERF_LIMIT_REASONS_MASK 0xde3
1002#define PROCHOT_MASK REG_BIT(0)
1003#define THERMAL_LIMIT_MASK REG_BIT(1)
1004#define RATL_MASK REG_BIT(5)
1005#define VR_THERMALERT_MASK REG_BIT(6)
1006#define VR_TDC_MASK REG_BIT(7)
1007#define POWER_LIMIT_4_MASK REG_BIT(8)
1008#define POWER_LIMIT_1_MASK REG_BIT(10)
1009#define POWER_LIMIT_2_MASK REG_BIT(11)
1010#define GT0_PERF_LIMIT_REASONS_LOG_MASK REG_GENMASK(31, 16)
1011#define MTL_MEDIA_PERF_LIMIT_REASONS _MMIO(0x138030)
1012
1013#define CHV_CLK_CTL1 _MMIO(0x101100)
1014#define VLV_CLK_CTL2 _MMIO(0x101104)
1015#define CLK_CTL2_CZCOUNT_30NS_SHIFT 28
1016
1017/*
1018 * Overlay regs
1019 */
1020
1021#define OVADD _MMIO(0x30000)
1022#define DOVSTA _MMIO(0x30008)
1023#define OC_BUF (0x3 << 20)
1024#define OGAMC5 _MMIO(0x30010)
1025#define OGAMC4 _MMIO(0x30014)
1026#define OGAMC3 _MMIO(0x30018)
1027#define OGAMC2 _MMIO(0x3001c)
1028#define OGAMC1 _MMIO(0x30020)
1029#define OGAMC0 _MMIO(0x30024)
1030
1031/*
1032 * GEN9 clock gating regs
1033 */
1034#define GEN9_CLKGATE_DIS_0 _MMIO(0x46530)
1035#define DARBF_GATING_DIS REG_BIT(27)
1036#define MTL_PIPEDMC_GATING_DIS_A REG_BIT(15)
1037#define MTL_PIPEDMC_GATING_DIS_B REG_BIT(14)
1038#define PWM2_GATING_DIS REG_BIT(14)
1039#define PWM1_GATING_DIS REG_BIT(13)
1040
1041#define GEN9_CLKGATE_DIS_3 _MMIO(0x46538)
1042#define TGL_VRH_GATING_DIS REG_BIT(31)
1043#define DPT_GATING_DIS REG_BIT(22)
1044
1045#define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C)
1046#define BXT_GMBUS_GATING_DIS (1 << 14)
1047
1048#define GEN9_CLKGATE_DIS_5 _MMIO(0x46540)
1049#define DPCE_GATING_DIS REG_BIT(17)
1050
1051#define _CLKGATE_DIS_PSL_A 0x46520
1052#define _CLKGATE_DIS_PSL_B 0x46524
1053#define _CLKGATE_DIS_PSL_C 0x46528
1054#define DUPS1_GATING_DIS (1 << 15)
1055#define DUPS2_GATING_DIS (1 << 19)
1056#define DUPS3_GATING_DIS (1 << 23)
1057#define CURSOR_GATING_DIS REG_BIT(28)
1058#define DPF_GATING_DIS (1 << 10)
1059#define DPF_RAM_GATING_DIS (1 << 9)
1060#define DPFR_GATING_DIS (1 << 8)
1061
1062#define CLKGATE_DIS_PSL(pipe) \
1063 _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B)
1064
1065#define _CLKGATE_DIS_PSL_EXT_A 0x4654C
1066#define _CLKGATE_DIS_PSL_EXT_B 0x46550
1067#define PIPEDMC_GATING_DIS REG_BIT(12)
1068
1069#define CLKGATE_DIS_PSL_EXT(pipe) \
1070 _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_EXT_A, _CLKGATE_DIS_PSL_EXT_B)
1071
1072/* DDI Buffer Control */
1073#define _DDI_CLK_VALFREQ_A 0x64030
1074#define _DDI_CLK_VALFREQ_B 0x64130
1075#define DDI_CLK_VALFREQ(port) _MMIO_PORT(port, _DDI_CLK_VALFREQ_A, _DDI_CLK_VALFREQ_B)
1076
1077/*
1078 * Display engine regs
1079 */
1080
1081/* Pipe/transcoder A timing regs */
1082#define _TRANS_HTOTAL_A 0x60000
1083#define _TRANS_HTOTAL_B 0x61000
1084#define TRANS_HTOTAL(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HTOTAL_A)
1085#define HTOTAL_MASK REG_GENMASK(31, 16)
1086#define HTOTAL(htotal) REG_FIELD_PREP(HTOTAL_MASK, (htotal))
1087#define HACTIVE_MASK REG_GENMASK(15, 0)
1088#define HACTIVE(hdisplay) REG_FIELD_PREP(HACTIVE_MASK, (hdisplay))
1089
1090#define _TRANS_HBLANK_A 0x60004
1091#define _TRANS_HBLANK_B 0x61004
1092#define TRANS_HBLANK(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HBLANK_A)
1093#define HBLANK_END_MASK REG_GENMASK(31, 16)
1094#define HBLANK_END(hblank_end) REG_FIELD_PREP(HBLANK_END_MASK, (hblank_end))
1095#define HBLANK_START_MASK REG_GENMASK(15, 0)
1096#define HBLANK_START(hblank_start) REG_FIELD_PREP(HBLANK_START_MASK, (hblank_start))
1097
1098#define _TRANS_HSYNC_A 0x60008
1099#define _TRANS_HSYNC_B 0x61008
1100#define TRANS_HSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HSYNC_A)
1101#define HSYNC_END_MASK REG_GENMASK(31, 16)
1102#define HSYNC_END(hsync_end) REG_FIELD_PREP(HSYNC_END_MASK, (hsync_end))
1103#define HSYNC_START_MASK REG_GENMASK(15, 0)
1104#define HSYNC_START(hsync_start) REG_FIELD_PREP(HSYNC_START_MASK, (hsync_start))
1105
1106#define _TRANS_VTOTAL_A 0x6000c
1107#define _TRANS_VTOTAL_B 0x6100c
1108#define TRANS_VTOTAL(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VTOTAL_A)
1109#define VTOTAL_MASK REG_GENMASK(31, 16)
1110#define VTOTAL(vtotal) REG_FIELD_PREP(VTOTAL_MASK, (vtotal))
1111#define VACTIVE_MASK REG_GENMASK(15, 0)
1112#define VACTIVE(vdisplay) REG_FIELD_PREP(VACTIVE_MASK, (vdisplay))
1113
1114#define _TRANS_VBLANK_A 0x60010
1115#define _TRANS_VBLANK_B 0x61010
1116#define TRANS_VBLANK(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VBLANK_A)
1117#define VBLANK_END_MASK REG_GENMASK(31, 16)
1118#define VBLANK_END(vblank_end) REG_FIELD_PREP(VBLANK_END_MASK, (vblank_end))
1119#define VBLANK_START_MASK REG_GENMASK(15, 0)
1120#define VBLANK_START(vblank_start) REG_FIELD_PREP(VBLANK_START_MASK, (vblank_start))
1121
1122#define _TRANS_VSYNC_A 0x60014
1123#define _TRANS_VSYNC_B 0x61014
1124#define TRANS_VSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNC_A)
1125#define VSYNC_END_MASK REG_GENMASK(31, 16)
1126#define VSYNC_END(vsync_end) REG_FIELD_PREP(VSYNC_END_MASK, (vsync_end))
1127#define VSYNC_START_MASK REG_GENMASK(15, 0)
1128#define VSYNC_START(vsync_start) REG_FIELD_PREP(VSYNC_START_MASK, (vsync_start))
1129
1130#define _PIPEASRC 0x6001c
1131#define _PIPEBSRC 0x6101c
1132#define PIPESRC(dev_priv, pipe) _MMIO_TRANS2(dev_priv, (pipe), _PIPEASRC)
1133#define PIPESRC_WIDTH_MASK REG_GENMASK(31, 16)
1134#define PIPESRC_WIDTH(w) REG_FIELD_PREP(PIPESRC_WIDTH_MASK, (w))
1135#define PIPESRC_HEIGHT_MASK REG_GENMASK(15, 0)
1136#define PIPESRC_HEIGHT(h) REG_FIELD_PREP(PIPESRC_HEIGHT_MASK, (h))
1137
1138#define _BCLRPAT_A 0x60020
1139#define _BCLRPAT_B 0x61020
1140#define BCLRPAT(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _BCLRPAT_A)
1141
1142#define _TRANS_VSYNCSHIFT_A 0x60028
1143#define _TRANS_VSYNCSHIFT_B 0x61028
1144#define TRANS_VSYNCSHIFT(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNCSHIFT_A)
1145
1146#define _TRANS_MULT_A 0x6002c
1147#define _TRANS_MULT_B 0x6102c
1148#define TRANS_MULT(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_MULT_A)
1149
1150/* VGA port control */
1151#define ADPA _MMIO(0x61100)
1152#define PCH_ADPA _MMIO(0xe1100)
1153#define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100)
1154#define ADPA_DAC_ENABLE (1 << 31)
1155#define ADPA_DAC_DISABLE 0
1156#define ADPA_PIPE_SEL_SHIFT 30
1157#define ADPA_PIPE_SEL_MASK (1 << 30)
1158#define ADPA_PIPE_SEL(pipe) ((pipe) << 30)
1159#define ADPA_PIPE_SEL_SHIFT_CPT 29
1160#define ADPA_PIPE_SEL_MASK_CPT (3 << 29)
1161#define ADPA_PIPE_SEL_CPT(pipe) ((pipe) << 29)
1162#define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
1163#define ADPA_CRT_HOTPLUG_MONITOR_NONE (0 << 24)
1164#define ADPA_CRT_HOTPLUG_MONITOR_MASK (3 << 24)
1165#define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3 << 24)
1166#define ADPA_CRT_HOTPLUG_MONITOR_MONO (2 << 24)
1167#define ADPA_CRT_HOTPLUG_ENABLE (1 << 23)
1168#define ADPA_CRT_HOTPLUG_PERIOD_64 (0 << 22)
1169#define ADPA_CRT_HOTPLUG_PERIOD_128 (1 << 22)
1170#define ADPA_CRT_HOTPLUG_WARMUP_5MS (0 << 21)
1171#define ADPA_CRT_HOTPLUG_WARMUP_10MS (1 << 21)
1172#define ADPA_CRT_HOTPLUG_SAMPLE_2S (0 << 20)
1173#define ADPA_CRT_HOTPLUG_SAMPLE_4S (1 << 20)
1174#define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0 << 18)
1175#define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1 << 18)
1176#define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2 << 18)
1177#define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3 << 18)
1178#define ADPA_CRT_HOTPLUG_VOLREF_325MV (0 << 17)
1179#define ADPA_CRT_HOTPLUG_VOLREF_475MV (1 << 17)
1180#define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1 << 16)
1181#define ADPA_USE_VGA_HVPOLARITY (1 << 15)
1182#define ADPA_SETS_HVPOLARITY 0
1183#define ADPA_VSYNC_CNTL_DISABLE (1 << 10)
1184#define ADPA_VSYNC_CNTL_ENABLE 0
1185#define ADPA_HSYNC_CNTL_DISABLE (1 << 11)
1186#define ADPA_HSYNC_CNTL_ENABLE 0
1187#define ADPA_VSYNC_ACTIVE_HIGH (1 << 4)
1188#define ADPA_VSYNC_ACTIVE_LOW 0
1189#define ADPA_HSYNC_ACTIVE_HIGH (1 << 3)
1190#define ADPA_HSYNC_ACTIVE_LOW 0
1191#define ADPA_DPMS_MASK (~(3 << 10))
1192#define ADPA_DPMS_ON (0 << 10)
1193#define ADPA_DPMS_SUSPEND (1 << 10)
1194#define ADPA_DPMS_STANDBY (2 << 10)
1195#define ADPA_DPMS_OFF (3 << 10)
1196
1197/* Hotplug control (945+ only) */
1198#define PORT_HOTPLUG_EN(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110)
1199#define PORTB_HOTPLUG_INT_EN (1 << 29)
1200#define PORTC_HOTPLUG_INT_EN (1 << 28)
1201#define PORTD_HOTPLUG_INT_EN (1 << 27)
1202#define SDVOB_HOTPLUG_INT_EN (1 << 26)
1203#define SDVOC_HOTPLUG_INT_EN (1 << 25)
1204#define TV_HOTPLUG_INT_EN (1 << 18)
1205#define CRT_HOTPLUG_INT_EN (1 << 9)
1206#define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \
1207 PORTC_HOTPLUG_INT_EN | \
1208 PORTD_HOTPLUG_INT_EN | \
1209 SDVOC_HOTPLUG_INT_EN | \
1210 SDVOB_HOTPLUG_INT_EN | \
1211 CRT_HOTPLUG_INT_EN)
1212#define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
1213#define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
1214/* must use period 64 on GM45 according to docs */
1215#define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
1216#define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
1217#define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
1218#define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
1219#define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
1220#define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
1221#define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
1222#define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
1223#define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
1224#define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
1225#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
1226#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
1227
1228#define PORT_HOTPLUG_STAT(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114)
1229/* HDMI/DP bits are g4x+ */
1230#define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 27)
1231#define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28)
1232#define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 29)
1233#define PORTD_HOTPLUG_INT_STATUS (3 << 21)
1234#define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21)
1235#define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21)
1236#define PORTC_HOTPLUG_INT_STATUS (3 << 19)
1237#define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19)
1238#define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19)
1239#define PORTB_HOTPLUG_INT_STATUS (3 << 17)
1240#define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17)
1241#define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17)
1242/* CRT/TV common between gen3+ */
1243#define CRT_HOTPLUG_INT_STATUS (1 << 11)
1244#define TV_HOTPLUG_INT_STATUS (1 << 10)
1245#define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
1246#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
1247#define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
1248#define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
1249#define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6)
1250#define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5)
1251#define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4)
1252#define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4)
1253
1254/* SDVO is different across gen3/4 */
1255#define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3)
1256#define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2)
1257/*
1258 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm,
1259 * since reality corrobates that they're the same as on gen3. But keep these
1260 * bits here (and the comment!) to help any other lost wanderers back onto the
1261 * right tracks.
1262 */
1263#define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4)
1264#define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2)
1265#define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7)
1266#define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6)
1267#define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \
1268 SDVOB_HOTPLUG_INT_STATUS_G4X | \
1269 SDVOC_HOTPLUG_INT_STATUS_G4X | \
1270 PORTB_HOTPLUG_INT_STATUS | \
1271 PORTC_HOTPLUG_INT_STATUS | \
1272 PORTD_HOTPLUG_INT_STATUS)
1273
1274#define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \
1275 SDVOB_HOTPLUG_INT_STATUS_I915 | \
1276 SDVOC_HOTPLUG_INT_STATUS_I915 | \
1277 PORTB_HOTPLUG_INT_STATUS | \
1278 PORTC_HOTPLUG_INT_STATUS | \
1279 PORTD_HOTPLUG_INT_STATUS)
1280
1281/* SDVO and HDMI port control.
1282 * The same register may be used for SDVO or HDMI */
1283#define _GEN3_SDVOB 0x61140
1284#define _GEN3_SDVOC 0x61160
1285#define GEN3_SDVOB _MMIO(_GEN3_SDVOB)
1286#define GEN3_SDVOC _MMIO(_GEN3_SDVOC)
1287#define GEN4_HDMIB GEN3_SDVOB
1288#define GEN4_HDMIC GEN3_SDVOC
1289#define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140)
1290#define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160)
1291#define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C)
1292#define PCH_SDVOB _MMIO(0xe1140)
1293#define PCH_HDMIB PCH_SDVOB
1294#define PCH_HDMIC _MMIO(0xe1150)
1295#define PCH_HDMID _MMIO(0xe1160)
1296
1297#define PORT_DFT_I9XX _MMIO(0x61150)
1298#define DC_BALANCE_RESET (1 << 25)
1299#define PORT_DFT2_G4X(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154)
1300#define DC_BALANCE_RESET_VLV (1 << 31)
1301#define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0))
1302#define PIPE_C_SCRAMBLE_RESET REG_BIT(14) /* chv */
1303#define PIPE_B_SCRAMBLE_RESET REG_BIT(1)
1304#define PIPE_A_SCRAMBLE_RESET REG_BIT(0)
1305
1306/* Gen 3 SDVO bits: */
1307#define SDVO_ENABLE (1 << 31)
1308#define SDVO_PIPE_SEL_SHIFT 30
1309#define SDVO_PIPE_SEL_MASK (1 << 30)
1310#define SDVO_PIPE_SEL(pipe) ((pipe) << 30)
1311#define SDVO_STALL_SELECT (1 << 29)
1312#define SDVO_INTERRUPT_ENABLE (1 << 26)
1313/*
1314 * 915G/GM SDVO pixel multiplier.
1315 * Programmed value is multiplier - 1, up to 5x.
1316 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
1317 */
1318#define SDVO_PORT_MULTIPLY_MASK (7 << 23)
1319#define SDVO_PORT_MULTIPLY_SHIFT 23
1320#define SDVO_PHASE_SELECT_MASK (15 << 19)
1321#define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
1322#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
1323#define SDVOC_GANG_MODE (1 << 16) /* Port C only */
1324#define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */
1325#define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */
1326#define SDVO_DETECTED (1 << 2)
1327/* Bits to be preserved when writing */
1328#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \
1329 SDVO_INTERRUPT_ENABLE)
1330#define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE)
1331
1332/* Gen 4 SDVO/HDMI bits: */
1333#define SDVO_COLOR_FORMAT_8bpc (0 << 26)
1334#define SDVO_COLOR_FORMAT_MASK (7 << 26)
1335#define SDVO_ENCODING_SDVO (0 << 10)
1336#define SDVO_ENCODING_HDMI (2 << 10)
1337#define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */
1338#define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */
1339#define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */
1340#define HDMI_AUDIO_ENABLE (1 << 6) /* HDMI only */
1341/* VSYNC/HSYNC bits new with 965, default is to be set */
1342#define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
1343#define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
1344
1345/* Gen 5 (IBX) SDVO/HDMI bits: */
1346#define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */
1347#define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */
1348
1349/* Gen 6 (CPT) SDVO/HDMI bits: */
1350#define SDVO_PIPE_SEL_SHIFT_CPT 29
1351#define SDVO_PIPE_SEL_MASK_CPT (3 << 29)
1352#define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29)
1353
1354/* CHV SDVO/HDMI bits: */
1355#define SDVO_PIPE_SEL_SHIFT_CHV 24
1356#define SDVO_PIPE_SEL_MASK_CHV (3 << 24)
1357#define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24)
1358
1359/* Video Data Island Packet control */
1360#define VIDEO_DIP_DATA _MMIO(0x61178)
1361/* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC
1362 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
1363 * of the infoframe structure specified by CEA-861. */
1364#define VIDEO_DIP_DATA_SIZE 32
1365#define VIDEO_DIP_ASYNC_DATA_SIZE 36
1366#define VIDEO_DIP_GMP_DATA_SIZE 36
1367#define VIDEO_DIP_VSC_DATA_SIZE 36
1368#define VIDEO_DIP_PPS_DATA_SIZE 132
1369#define VIDEO_DIP_CTL _MMIO(0x61170)
1370/* Pre HSW: */
1371#define VIDEO_DIP_ENABLE (1 << 31)
1372#define VIDEO_DIP_PORT(port) ((port) << 29)
1373#define VIDEO_DIP_PORT_MASK (3 << 29)
1374#define VIDEO_DIP_ENABLE_GCP (1 << 25) /* ilk+ */
1375#define VIDEO_DIP_ENABLE_AVI (1 << 21)
1376#define VIDEO_DIP_ENABLE_VENDOR (2 << 21)
1377#define VIDEO_DIP_ENABLE_GAMUT (4 << 21) /* ilk+ */
1378#define VIDEO_DIP_ENABLE_SPD (8 << 21)
1379#define VIDEO_DIP_SELECT_AVI (0 << 19)
1380#define VIDEO_DIP_SELECT_VENDOR (1 << 19)
1381#define VIDEO_DIP_SELECT_GAMUT (2 << 19)
1382#define VIDEO_DIP_SELECT_SPD (3 << 19)
1383#define VIDEO_DIP_SELECT_MASK (3 << 19)
1384#define VIDEO_DIP_FREQ_ONCE (0 << 16)
1385#define VIDEO_DIP_FREQ_VSYNC (1 << 16)
1386#define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
1387#define VIDEO_DIP_FREQ_MASK (3 << 16)
1388/* HSW and later: */
1389#define VIDEO_DIP_ENABLE_DRM_GLK (1 << 28)
1390#define PSR_VSC_BIT_7_SET (1 << 27)
1391#define VSC_SELECT_MASK (0x3 << 25)
1392#define VSC_SELECT_SHIFT 25
1393#define VSC_DIP_HW_HEA_DATA (0 << 25)
1394#define VSC_DIP_HW_HEA_SW_DATA (1 << 25)
1395#define VSC_DIP_HW_DATA_SW_HEA (2 << 25)
1396#define VSC_DIP_SW_HEA_DATA (3 << 25)
1397#define VDIP_ENABLE_PPS (1 << 24)
1398#define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20)
1399#define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16)
1400#define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12)
1401#define VIDEO_DIP_ENABLE_VS_HSW (1 << 8)
1402#define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
1403#define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
1404/* ADL and later: */
1405#define VIDEO_DIP_ENABLE_AS_ADL REG_BIT(23)
1406
1407/* Panel fitting */
1408#define PFIT_CONTROL(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230)
1409#define PFIT_ENABLE REG_BIT(31)
1410#define PFIT_PIPE_MASK REG_GENMASK(30, 29) /* 965+ */
1411#define PFIT_PIPE(pipe) REG_FIELD_PREP(PFIT_PIPE_MASK, (pipe))
1412#define PFIT_SCALING_MASK REG_GENMASK(28, 26) /* 965+ */
1413#define PFIT_SCALING_AUTO REG_FIELD_PREP(PFIT_SCALING_MASK, 0)
1414#define PFIT_SCALING_PROGRAMMED REG_FIELD_PREP(PFIT_SCALING_MASK, 1)
1415#define PFIT_SCALING_PILLAR REG_FIELD_PREP(PFIT_SCALING_MASK, 2)
1416#define PFIT_SCALING_LETTER REG_FIELD_PREP(PFIT_SCALING_MASK, 3)
1417#define PFIT_FILTER_MASK REG_GENMASK(25, 24) /* 965+ */
1418#define PFIT_FILTER_FUZZY REG_FIELD_PREP(PFIT_FILTER_MASK, 0)
1419#define PFIT_FILTER_CRISP REG_FIELD_PREP(PFIT_FILTER_MASK, 1)
1420#define PFIT_FILTER_MEDIAN REG_FIELD_PREP(PFIT_FILTER_MASK, 2)
1421#define PFIT_VERT_INTERP_MASK REG_GENMASK(11, 10) /* pre-965 */
1422#define PFIT_VERT_INTERP_BILINEAR REG_FIELD_PREP(PFIT_VERT_INTERP_MASK, 1)
1423#define PFIT_VERT_AUTO_SCALE REG_BIT(9) /* pre-965 */
1424#define PFIT_HORIZ_INTERP_MASK REG_GENMASK(7, 6) /* pre-965 */
1425#define PFIT_HORIZ_INTERP_BILINEAR REG_FIELD_PREP(PFIT_HORIZ_INTERP_MASK, 1)
1426#define PFIT_HORIZ_AUTO_SCALE REG_BIT(5) /* pre-965 */
1427#define PFIT_PANEL_8TO6_DITHER_ENABLE REG_BIT(3) /* pre-965 */
1428
1429#define PFIT_PGM_RATIOS(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234)
1430#define PFIT_VERT_SCALE_MASK REG_GENMASK(31, 20) /* pre-965 */
1431#define PFIT_VERT_SCALE(x) REG_FIELD_PREP(PFIT_VERT_SCALE_MASK, (x))
1432#define PFIT_HORIZ_SCALE_MASK REG_GENMASK(15, 4) /* pre-965 */
1433#define PFIT_HORIZ_SCALE(x) REG_FIELD_PREP(PFIT_HORIZ_SCALE_MASK, (x))
1434#define PFIT_VERT_SCALE_MASK_965 REG_GENMASK(28, 16) /* 965+ */
1435#define PFIT_HORIZ_SCALE_MASK_965 REG_GENMASK(12, 0) /* 965+ */
1436
1437#define PFIT_AUTO_RATIOS(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238)
1438
1439#define PCH_GTC_CTL _MMIO(0xe7000)
1440#define PCH_GTC_ENABLE (1 << 31)
1441
1442/* Display Port */
1443#define DP_A _MMIO(0x64000) /* eDP */
1444#define DP_B _MMIO(0x64100)
1445#define DP_C _MMIO(0x64200)
1446#define DP_D _MMIO(0x64300)
1447#define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100)
1448#define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200)
1449#define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300)
1450#define DP_PORT_EN (1 << 31)
1451#define DP_PIPE_SEL_SHIFT 30
1452#define DP_PIPE_SEL_MASK (1 << 30)
1453#define DP_PIPE_SEL(pipe) ((pipe) << 30)
1454#define DP_PIPE_SEL_SHIFT_IVB 29
1455#define DP_PIPE_SEL_MASK_IVB (3 << 29)
1456#define DP_PIPE_SEL_IVB(pipe) ((pipe) << 29)
1457#define DP_PIPE_SEL_SHIFT_CHV 16
1458#define DP_PIPE_SEL_MASK_CHV (3 << 16)
1459#define DP_PIPE_SEL_CHV(pipe) ((pipe) << 16)
1460
1461/* Link training mode - select a suitable mode for each stage */
1462#define DP_LINK_TRAIN_PAT_1 (0 << 28)
1463#define DP_LINK_TRAIN_PAT_2 (1 << 28)
1464#define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
1465#define DP_LINK_TRAIN_OFF (3 << 28)
1466#define DP_LINK_TRAIN_MASK (3 << 28)
1467#define DP_LINK_TRAIN_SHIFT 28
1468
1469/* CPT Link training mode */
1470#define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
1471#define DP_LINK_TRAIN_PAT_2_CPT (1 << 8)
1472#define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8)
1473#define DP_LINK_TRAIN_OFF_CPT (3 << 8)
1474#define DP_LINK_TRAIN_MASK_CPT (7 << 8)
1475#define DP_LINK_TRAIN_SHIFT_CPT 8
1476
1477/* Signal voltages. These are mostly controlled by the other end */
1478#define DP_VOLTAGE_0_4 (0 << 25)
1479#define DP_VOLTAGE_0_6 (1 << 25)
1480#define DP_VOLTAGE_0_8 (2 << 25)
1481#define DP_VOLTAGE_1_2 (3 << 25)
1482#define DP_VOLTAGE_MASK (7 << 25)
1483#define DP_VOLTAGE_SHIFT 25
1484
1485/* Signal pre-emphasis levels, like voltages, the other end tells us what
1486 * they want
1487 */
1488#define DP_PRE_EMPHASIS_0 (0 << 22)
1489#define DP_PRE_EMPHASIS_3_5 (1 << 22)
1490#define DP_PRE_EMPHASIS_6 (2 << 22)
1491#define DP_PRE_EMPHASIS_9_5 (3 << 22)
1492#define DP_PRE_EMPHASIS_MASK (7 << 22)
1493#define DP_PRE_EMPHASIS_SHIFT 22
1494
1495/* How many wires to use. I guess 3 was too hard */
1496#define DP_PORT_WIDTH(width) (((width) - 1) << 19)
1497#define DP_PORT_WIDTH_MASK (7 << 19)
1498#define DP_PORT_WIDTH_SHIFT 19
1499
1500/* Mystic DPCD version 1.1 special mode */
1501#define DP_ENHANCED_FRAMING (1 << 18)
1502
1503/* eDP */
1504#define DP_PLL_FREQ_270MHZ (0 << 16)
1505#define DP_PLL_FREQ_162MHZ (1 << 16)
1506#define DP_PLL_FREQ_MASK (3 << 16)
1507
1508/* locked once port is enabled */
1509#define DP_PORT_REVERSAL (1 << 15)
1510
1511/* eDP */
1512#define DP_PLL_ENABLE (1 << 14)
1513
1514/* sends the clock on lane 15 of the PEG for debug */
1515#define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
1516
1517#define DP_SCRAMBLING_DISABLE (1 << 12)
1518#define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
1519
1520/* limit RGB values to avoid confusing TVs */
1521#define DP_COLOR_RANGE_16_235 (1 << 8)
1522
1523/* Turn on the audio link */
1524#define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
1525
1526/* vs and hs sync polarity */
1527#define DP_SYNC_VS_HIGH (1 << 4)
1528#define DP_SYNC_HS_HIGH (1 << 3)
1529
1530/* A fantasy */
1531#define DP_DETECTED (1 << 2)
1532
1533/*
1534 * Computing GMCH M and N values for the Display Port link
1535 *
1536 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
1537 *
1538 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
1539 *
1540 * The GMCH value is used internally
1541 *
1542 * bytes_per_pixel is the number of bytes coming out of the plane,
1543 * which is after the LUTs, so we want the bytes for our color format.
1544 * For our current usage, this is always 3, one byte for R, G and B.
1545 */
1546#define _PIPEA_DATA_M_G4X 0x70050
1547#define _PIPEB_DATA_M_G4X 0x71050
1548#define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
1549/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
1550#define TU_SIZE_MASK REG_GENMASK(30, 25)
1551#define TU_SIZE(x) REG_FIELD_PREP(TU_SIZE_MASK, (x) - 1) /* default size 64 */
1552#define DATA_LINK_M_N_MASK REG_GENMASK(23, 0)
1553#define DATA_LINK_N_MAX (0x800000)
1554
1555#define _PIPEA_DATA_N_G4X 0x70054
1556#define _PIPEB_DATA_N_G4X 0x71054
1557#define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
1558
1559/*
1560 * Computing Link M and N values for the Display Port link
1561 *
1562 * Link M / N = pixel_clock / ls_clk
1563 *
1564 * (the DP spec calls pixel_clock the 'strm_clk')
1565 *
1566 * The Link value is transmitted in the Main Stream
1567 * Attributes and VB-ID.
1568 */
1569#define _PIPEA_LINK_M_G4X 0x70060
1570#define _PIPEB_LINK_M_G4X 0x71060
1571#define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)
1572
1573#define _PIPEA_LINK_N_G4X 0x70064
1574#define _PIPEB_LINK_N_G4X 0x71064
1575#define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)
1576
1577/* Pipe A */
1578#define _PIPEADSL 0x70000
1579#define PIPEDSL(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEADSL)
1580#define PIPEDSL_CURR_FIELD REG_BIT(31) /* ctg+ */
1581#define PIPEDSL_LINE_MASK REG_GENMASK(19, 0)
1582
1583#define _TRANSACONF 0x70008
1584#define TRANSCONF(dev_priv, trans) _MMIO_PIPE2(dev_priv, (trans), _TRANSACONF)
1585#define TRANSCONF_ENABLE REG_BIT(31)
1586#define TRANSCONF_DOUBLE_WIDE REG_BIT(30) /* pre-i965 */
1587#define TRANSCONF_STATE_ENABLE REG_BIT(30) /* i965+ */
1588#define TRANSCONF_DSI_PLL_LOCKED REG_BIT(29) /* vlv & pipe A only */
1589#define TRANSCONF_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* pre-hsw */
1590#define TRANSCONF_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANSCONF_FRAME_START_DELAY_MASK, (x)) /* pre-hsw: 0-3 */
1591#define TRANSCONF_PIPE_LOCKED REG_BIT(25)
1592#define TRANSCONF_FORCE_BORDER REG_BIT(25)
1593#define TRANSCONF_GAMMA_MODE_MASK_I9XX REG_BIT(24) /* gmch */
1594#define TRANSCONF_GAMMA_MODE_MASK_ILK REG_GENMASK(25, 24) /* ilk-ivb */
1595#define TRANSCONF_GAMMA_MODE_8BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK, 0)
1596#define TRANSCONF_GAMMA_MODE_10BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK, 1)
1597#define TRANSCONF_GAMMA_MODE_12BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, 2) /* ilk-ivb */
1598#define TRANSCONF_GAMMA_MODE_SPLIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, 3) /* ivb */
1599#define TRANSCONF_GAMMA_MODE(x) REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, (x)) /* pass in GAMMA_MODE_MODE_* */
1600#define TRANSCONF_INTERLACE_MASK REG_GENMASK(23, 21) /* gen3+ */
1601#define TRANSCONF_INTERLACE_PROGRESSIVE REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 0)
1602#define TRANSCONF_INTERLACE_W_SYNC_SHIFT_PANEL REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 4) /* gen4 only */
1603#define TRANSCONF_INTERLACE_W_SYNC_SHIFT REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 5) /* gen4 only */
1604#define TRANSCONF_INTERLACE_W_FIELD_INDICATION REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 6)
1605#define TRANSCONF_INTERLACE_FIELD_0_ONLY REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 7) /* gen3 only */
1606/*
1607 * ilk+: PF/D=progressive fetch/display, IF/D=interlaced fetch/display,
1608 * DBL=power saving pixel doubling, PF-ID* requires panel fitter
1609 */
1610#define TRANSCONF_INTERLACE_MASK_ILK REG_GENMASK(23, 21) /* ilk+ */
1611#define TRANSCONF_INTERLACE_MASK_HSW REG_GENMASK(22, 21) /* hsw+ */
1612#define TRANSCONF_INTERLACE_PF_PD_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 0)
1613#define TRANSCONF_INTERLACE_PF_ID_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 1)
1614#define TRANSCONF_INTERLACE_IF_ID_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 3)
1615#define TRANSCONF_INTERLACE_IF_ID_DBL_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 4) /* ilk/snb only */
1616#define TRANSCONF_INTERLACE_PF_ID_DBL_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 5) /* ilk/snb only */
1617#define TRANSCONF_REFRESH_RATE_ALT_ILK REG_BIT(20)
1618#define TRANSCONF_MSA_TIMING_DELAY_MASK REG_GENMASK(19, 18) /* ilk/snb/ivb */
1619#define TRANSCONF_MSA_TIMING_DELAY(x) REG_FIELD_PREP(TRANSCONF_MSA_TIMING_DELAY_MASK, (x))
1620#define TRANSCONF_CXSR_DOWNCLOCK REG_BIT(16)
1621#define TRANSCONF_WGC_ENABLE REG_BIT(15) /* vlv/chv only */
1622#define TRANSCONF_REFRESH_RATE_ALT_VLV REG_BIT(14)
1623#define TRANSCONF_COLOR_RANGE_SELECT REG_BIT(13)
1624#define TRANSCONF_OUTPUT_COLORSPACE_MASK REG_GENMASK(12, 11) /* ilk-ivb */
1625#define TRANSCONF_OUTPUT_COLORSPACE_RGB REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 0) /* ilk-ivb */
1626#define TRANSCONF_OUTPUT_COLORSPACE_YUV601 REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 1) /* ilk-ivb */
1627#define TRANSCONF_OUTPUT_COLORSPACE_YUV709 REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 2) /* ilk-ivb */
1628#define TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW REG_BIT(11) /* hsw only */
1629#define TRANSCONF_BPC_MASK REG_GENMASK(7, 5) /* ctg-ivb */
1630#define TRANSCONF_BPC_8 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 0)
1631#define TRANSCONF_BPC_10 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 1)
1632#define TRANSCONF_BPC_6 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 2)
1633#define TRANSCONF_BPC_12 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 3)
1634#define TRANSCONF_DITHER_EN REG_BIT(4)
1635#define TRANSCONF_DITHER_TYPE_MASK REG_GENMASK(3, 2)
1636#define TRANSCONF_DITHER_TYPE_SP REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 0)
1637#define TRANSCONF_DITHER_TYPE_ST1 REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 1)
1638#define TRANSCONF_DITHER_TYPE_ST2 REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 2)
1639#define TRANSCONF_DITHER_TYPE_TEMP REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 3)
1640#define TRANSCONF_PIXEL_COUNT_SCALING_MASK REG_GENMASK(1, 0)
1641#define TRANSCONF_PIXEL_COUNT_SCALING_X4 1
1642
1643#define _PIPEASTAT 0x70024
1644#define PIPESTAT(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEASTAT)
1645#define PIPE_FIFO_UNDERRUN_STATUS (1UL << 31)
1646#define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL << 30)
1647#define PIPE_CRC_ERROR_ENABLE (1UL << 29)
1648#define PIPE_CRC_DONE_ENABLE (1UL << 28)
1649#define PERF_COUNTER2_INTERRUPT_EN (1UL << 27)
1650#define PIPE_GMBUS_EVENT_ENABLE (1UL << 27)
1651#define PLANE_FLIP_DONE_INT_EN_VLV (1UL << 26)
1652#define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL << 26)
1653#define PIPE_VSYNC_INTERRUPT_ENABLE (1UL << 25)
1654#define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL << 24)
1655#define PIPE_DPST_EVENT_ENABLE (1UL << 23)
1656#define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL << 22)
1657#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL << 22)
1658#define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL << 21)
1659#define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL << 20)
1660#define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL << 19)
1661#define PERF_COUNTER_INTERRUPT_EN (1UL << 19)
1662#define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL << 18) /* pre-965 */
1663#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL << 18) /* 965 or later */
1664#define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL << 17)
1665#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL << 17)
1666#define PIPEA_HBLANK_INT_EN_VLV (1UL << 16)
1667#define PIPE_OVERLAY_UPDATED_ENABLE (1UL << 16)
1668#define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL << 15)
1669#define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL << 14)
1670#define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL << 13)
1671#define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL << 12)
1672#define PERF_COUNTER2_INTERRUPT_STATUS (1UL << 11)
1673#define PIPE_GMBUS_INTERRUPT_STATUS (1UL << 11)
1674#define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL << 10)
1675#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL << 10)
1676#define PIPE_VSYNC_INTERRUPT_STATUS (1UL << 9)
1677#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL << 8)
1678#define PIPE_DPST_EVENT_STATUS (1UL << 7)
1679#define PIPE_A_PSR_STATUS_VLV (1UL << 6)
1680#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL << 6)
1681#define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL << 5)
1682#define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL << 4)
1683#define PIPE_B_PSR_STATUS_VLV (1UL << 3)
1684#define PERF_COUNTER_INTERRUPT_STATUS (1UL << 3)
1685#define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL << 2) /* pre-965 */
1686#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL << 2) /* 965 or later */
1687#define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL << 1)
1688#define PIPE_VBLANK_INTERRUPT_STATUS (1UL << 1)
1689#define PIPE_HBLANK_INT_STATUS (1UL << 0)
1690#define PIPE_OVERLAY_UPDATED_STATUS (1UL << 0)
1691#define PIPESTAT_INT_ENABLE_MASK 0x7fff0000
1692#define PIPESTAT_INT_STATUS_MASK 0x0000ffff
1693
1694#define _PIPE_ARB_CTL_A 0x70028 /* icl+ */
1695#define PIPE_ARB_CTL(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPE_ARB_CTL_A)
1696#define PIPE_ARB_USE_PROG_SLOTS REG_BIT(13)
1697
1698#define _PIPE_MISC_A 0x70030
1699#define _PIPE_MISC_B 0x71030
1700#define PIPE_MISC(pipe) _MMIO_PIPE(pipe, _PIPE_MISC_A, _PIPE_MISC_B)
1701#define PIPE_MISC_YUV420_ENABLE REG_BIT(27) /* glk+ */
1702#define PIPE_MISC_YUV420_MODE_FULL_BLEND REG_BIT(26) /* glk+ */
1703#define PIPE_MISC_HDR_MODE_PRECISION REG_BIT(23) /* icl+ */
1704#define PIPE_MISC_PSR_MASK_PRIMARY_FLIP REG_BIT(23) /* bdw */
1705#define PIPE_MISC_PSR_MASK_SPRITE_ENABLE REG_BIT(22) /* bdw */
1706#define PIPE_MISC_PSR_MASK_PIPE_REG_WRITE REG_BIT(21) /* skl+ */
1707#define PIPE_MISC_PSR_MASK_CURSOR_MOVE REG_BIT(21) /* bdw */
1708#define PIPE_MISC_PSR_MASK_VBLANK_VSYNC_INT REG_BIT(20)
1709#define PIPE_MISC_OUTPUT_COLORSPACE_YUV REG_BIT(11)
1710#define PIPE_MISC_PIXEL_ROUNDING_TRUNC REG_BIT(8) /* tgl+ */
1711/*
1712 * For Display < 13, Bits 5-7 of PIPE MISC represent DITHER BPC with
1713 * valid values of: 6, 8, 10 BPC.
1714 * ADLP+, the bits 5-7 represent PORT OUTPUT BPC with valid values of:
1715 * 6, 8, 10, 12 BPC.
1716 */
1717#define PIPE_MISC_BPC_MASK REG_GENMASK(7, 5)
1718#define PIPE_MISC_BPC_8 REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 0)
1719#define PIPE_MISC_BPC_10 REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 1)
1720#define PIPE_MISC_BPC_6 REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 2)
1721#define PIPE_MISC_BPC_12_ADLP REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 4) /* adlp+ */
1722#define PIPE_MISC_DITHER_ENABLE REG_BIT(4)
1723#define PIPE_MISC_DITHER_TYPE_MASK REG_GENMASK(3, 2)
1724#define PIPE_MISC_DITHER_TYPE_SP REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 0)
1725#define PIPE_MISC_DITHER_TYPE_ST1 REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 1)
1726#define PIPE_MISC_DITHER_TYPE_ST2 REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 2)
1727#define PIPE_MISC_DITHER_TYPE_TEMP REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 3)
1728
1729#define _PIPE_MISC2_A 0x7002C
1730#define _PIPE_MISC2_B 0x7102C
1731#define PIPE_MISC2(pipe) _MMIO_PIPE(pipe, _PIPE_MISC2_A, _PIPE_MISC2_B)
1732#define PIPE_MISC2_BUBBLE_COUNTER_MASK REG_GENMASK(31, 24)
1733#define PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 80)
1734#define PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 20)
1735#define PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK REG_GENMASK(2, 0) /* tgl+ */
1736#define PIPE_MISC2_FLIP_INFO_PLANE_SEL(plane_id) REG_FIELD_PREP(PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK, (plane_id))
1737
1738#define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028)
1739#define PIPEB_LINE_COMPARE_INT_EN REG_BIT(29)
1740#define PIPEB_HLINE_INT_EN REG_BIT(28)
1741#define PIPEB_VBLANK_INT_EN REG_BIT(27)
1742#define SPRITED_FLIP_DONE_INT_EN REG_BIT(26)
1743#define SPRITEC_FLIP_DONE_INT_EN REG_BIT(25)
1744#define PLANEB_FLIP_DONE_INT_EN REG_BIT(24)
1745#define PIPE_PSR_INT_EN REG_BIT(22)
1746#define PIPEA_LINE_COMPARE_INT_EN REG_BIT(21)
1747#define PIPEA_HLINE_INT_EN REG_BIT(20)
1748#define PIPEA_VBLANK_INT_EN REG_BIT(19)
1749#define SPRITEB_FLIP_DONE_INT_EN REG_BIT(18)
1750#define SPRITEA_FLIP_DONE_INT_EN REG_BIT(17)
1751#define PLANEA_FLIPDONE_INT_EN REG_BIT(16)
1752#define PIPEC_LINE_COMPARE_INT_EN REG_BIT(13)
1753#define PIPEC_HLINE_INT_EN REG_BIT(12)
1754#define PIPEC_VBLANK_INT_EN REG_BIT(11)
1755#define SPRITEF_FLIPDONE_INT_EN REG_BIT(10)
1756#define SPRITEE_FLIPDONE_INT_EN REG_BIT(9)
1757#define PLANEC_FLIPDONE_INT_EN REG_BIT(8)
1758
1759#define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
1760#define DPINVGTT_EN_MASK_CHV REG_GENMASK(27, 16)
1761#define DPINVGTT_EN_MASK_VLV REG_GENMASK(23, 16)
1762#define SPRITEF_INVALID_GTT_INT_EN REG_BIT(27)
1763#define SPRITEE_INVALID_GTT_INT_EN REG_BIT(26)
1764#define PLANEC_INVALID_GTT_INT_EN REG_BIT(25)
1765#define CURSORC_INVALID_GTT_INT_EN REG_BIT(24)
1766#define CURSORB_INVALID_GTT_INT_EN REG_BIT(23)
1767#define CURSORA_INVALID_GTT_INT_EN REG_BIT(22)
1768#define SPRITED_INVALID_GTT_INT_EN REG_BIT(21)
1769#define SPRITEC_INVALID_GTT_INT_EN REG_BIT(20)
1770#define PLANEB_INVALID_GTT_INT_EN REG_BIT(19)
1771#define SPRITEB_INVALID_GTT_INT_EN REG_BIT(18)
1772#define SPRITEA_INVALID_GTT_INT_EN REG_BIT(17)
1773#define PLANEA_INVALID_GTT_INT_EN REG_BIT(16)
1774#define DPINVGTT_STATUS_MASK_CHV REG_GENMASK(11, 0)
1775#define DPINVGTT_STATUS_MASK_VLV REG_GENMASK(7, 0)
1776#define SPRITEF_INVALID_GTT_STATUS REG_BIT(11)
1777#define SPRITEE_INVALID_GTT_STATUS REG_BIT(10)
1778#define PLANEC_INVALID_GTT_STATUS REG_BIT(9)
1779#define CURSORC_INVALID_GTT_STATUS REG_BIT(8)
1780#define CURSORB_INVALID_GTT_STATUS REG_BIT(7)
1781#define CURSORA_INVALID_GTT_STATUS REG_BIT(6)
1782#define SPRITED_INVALID_GTT_STATUS REG_BIT(5)
1783#define SPRITEC_INVALID_GTT_STATUS REG_BIT(4)
1784#define PLANEB_INVALID_GTT_STATUS REG_BIT(3)
1785#define SPRITEB_INVALID_GTT_STATUS REG_BIT(2)
1786#define SPRITEA_INVALID_GTT_STATUS REG_BIT(1)
1787#define PLANEA_INVALID_GTT_STATUS REG_BIT(0)
1788
1789#define DSPARB(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030)
1790#define DSPARB_CSTART_MASK (0x7f << 7)
1791#define DSPARB_CSTART_SHIFT 7
1792#define DSPARB_BSTART_MASK (0x7f)
1793#define DSPARB_BSTART_SHIFT 0
1794#define DSPARB_BEND_SHIFT 9 /* on 855 */
1795#define DSPARB_AEND_SHIFT 0
1796#define DSPARB_SPRITEA_SHIFT_VLV 0
1797#define DSPARB_SPRITEA_MASK_VLV (0xff << 0)
1798#define DSPARB_SPRITEB_SHIFT_VLV 8
1799#define DSPARB_SPRITEB_MASK_VLV (0xff << 8)
1800#define DSPARB_SPRITEC_SHIFT_VLV 16
1801#define DSPARB_SPRITEC_MASK_VLV (0xff << 16)
1802#define DSPARB_SPRITED_SHIFT_VLV 24
1803#define DSPARB_SPRITED_MASK_VLV (0xff << 24)
1804#define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */
1805#define DSPARB_SPRITEA_HI_SHIFT_VLV 0
1806#define DSPARB_SPRITEA_HI_MASK_VLV (0x1 << 0)
1807#define DSPARB_SPRITEB_HI_SHIFT_VLV 4
1808#define DSPARB_SPRITEB_HI_MASK_VLV (0x1 << 4)
1809#define DSPARB_SPRITEC_HI_SHIFT_VLV 8
1810#define DSPARB_SPRITEC_HI_MASK_VLV (0x1 << 8)
1811#define DSPARB_SPRITED_HI_SHIFT_VLV 12
1812#define DSPARB_SPRITED_HI_MASK_VLV (0x1 << 12)
1813#define DSPARB_SPRITEE_HI_SHIFT_VLV 16
1814#define DSPARB_SPRITEE_HI_MASK_VLV (0x1 << 16)
1815#define DSPARB_SPRITEF_HI_SHIFT_VLV 20
1816#define DSPARB_SPRITEF_HI_MASK_VLV (0x1 << 20)
1817#define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */
1818#define DSPARB_SPRITEE_SHIFT_VLV 0
1819#define DSPARB_SPRITEE_MASK_VLV (0xff << 0)
1820#define DSPARB_SPRITEF_SHIFT_VLV 8
1821#define DSPARB_SPRITEF_MASK_VLV (0xff << 8)
1822
1823/* pnv/gen4/g4x/vlv/chv */
1824#define DSPFW1(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034)
1825#define DSPFW_SR_SHIFT 23
1826#define DSPFW_SR_MASK (0x1ff << 23)
1827#define DSPFW_CURSORB_SHIFT 16
1828#define DSPFW_CURSORB_MASK (0x3f << 16)
1829#define DSPFW_PLANEB_SHIFT 8
1830#define DSPFW_PLANEB_MASK (0x7f << 8)
1831#define DSPFW_PLANEB_MASK_VLV (0xff << 8) /* vlv/chv */
1832#define DSPFW_PLANEA_SHIFT 0
1833#define DSPFW_PLANEA_MASK (0x7f << 0)
1834#define DSPFW_PLANEA_MASK_VLV (0xff << 0) /* vlv/chv */
1835#define DSPFW2(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038)
1836#define DSPFW_FBC_SR_EN (1 << 31) /* g4x */
1837#define DSPFW_FBC_SR_SHIFT 28
1838#define DSPFW_FBC_SR_MASK (0x7 << 28) /* g4x */
1839#define DSPFW_FBC_HPLL_SR_SHIFT 24
1840#define DSPFW_FBC_HPLL_SR_MASK (0xf << 24) /* g4x */
1841#define DSPFW_SPRITEB_SHIFT (16)
1842#define DSPFW_SPRITEB_MASK (0x7f << 16) /* g4x */
1843#define DSPFW_SPRITEB_MASK_VLV (0xff << 16) /* vlv/chv */
1844#define DSPFW_CURSORA_SHIFT 8
1845#define DSPFW_CURSORA_MASK (0x3f << 8)
1846#define DSPFW_PLANEC_OLD_SHIFT 0
1847#define DSPFW_PLANEC_OLD_MASK (0x7f << 0) /* pre-gen4 sprite C */
1848#define DSPFW_SPRITEA_SHIFT 0
1849#define DSPFW_SPRITEA_MASK (0x7f << 0) /* g4x */
1850#define DSPFW_SPRITEA_MASK_VLV (0xff << 0) /* vlv/chv */
1851#define DSPFW3(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c)
1852#define DSPFW_HPLL_SR_EN (1 << 31)
1853#define PINEVIEW_SELF_REFRESH_EN (1 << 30)
1854#define DSPFW_CURSOR_SR_SHIFT 24
1855#define DSPFW_CURSOR_SR_MASK (0x3f << 24)
1856#define DSPFW_HPLL_CURSOR_SHIFT 16
1857#define DSPFW_HPLL_CURSOR_MASK (0x3f << 16)
1858#define DSPFW_HPLL_SR_SHIFT 0
1859#define DSPFW_HPLL_SR_MASK (0x1ff << 0)
1860
1861/* vlv/chv */
1862#define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070)
1863#define DSPFW_SPRITEB_WM1_SHIFT 16
1864#define DSPFW_SPRITEB_WM1_MASK (0xff << 16)
1865#define DSPFW_CURSORA_WM1_SHIFT 8
1866#define DSPFW_CURSORA_WM1_MASK (0x3f << 8)
1867#define DSPFW_SPRITEA_WM1_SHIFT 0
1868#define DSPFW_SPRITEA_WM1_MASK (0xff << 0)
1869#define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074)
1870#define DSPFW_PLANEB_WM1_SHIFT 24
1871#define DSPFW_PLANEB_WM1_MASK (0xff << 24)
1872#define DSPFW_PLANEA_WM1_SHIFT 16
1873#define DSPFW_PLANEA_WM1_MASK (0xff << 16)
1874#define DSPFW_CURSORB_WM1_SHIFT 8
1875#define DSPFW_CURSORB_WM1_MASK (0x3f << 8)
1876#define DSPFW_CURSOR_SR_WM1_SHIFT 0
1877#define DSPFW_CURSOR_SR_WM1_MASK (0x3f << 0)
1878#define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078)
1879#define DSPFW_SR_WM1_SHIFT 0
1880#define DSPFW_SR_WM1_MASK (0x1ff << 0)
1881#define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c)
1882#define DSPFW7_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
1883#define DSPFW_SPRITED_WM1_SHIFT 24
1884#define DSPFW_SPRITED_WM1_MASK (0xff << 24)
1885#define DSPFW_SPRITED_SHIFT 16
1886#define DSPFW_SPRITED_MASK_VLV (0xff << 16)
1887#define DSPFW_SPRITEC_WM1_SHIFT 8
1888#define DSPFW_SPRITEC_WM1_MASK (0xff << 8)
1889#define DSPFW_SPRITEC_SHIFT 0
1890#define DSPFW_SPRITEC_MASK_VLV (0xff << 0)
1891#define DSPFW8_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b8)
1892#define DSPFW_SPRITEF_WM1_SHIFT 24
1893#define DSPFW_SPRITEF_WM1_MASK (0xff << 24)
1894#define DSPFW_SPRITEF_SHIFT 16
1895#define DSPFW_SPRITEF_MASK_VLV (0xff << 16)
1896#define DSPFW_SPRITEE_WM1_SHIFT 8
1897#define DSPFW_SPRITEE_WM1_MASK (0xff << 8)
1898#define DSPFW_SPRITEE_SHIFT 0
1899#define DSPFW_SPRITEE_MASK_VLV (0xff << 0)
1900#define DSPFW9_CHV _MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
1901#define DSPFW_PLANEC_WM1_SHIFT 24
1902#define DSPFW_PLANEC_WM1_MASK (0xff << 24)
1903#define DSPFW_PLANEC_SHIFT 16
1904#define DSPFW_PLANEC_MASK_VLV (0xff << 16)
1905#define DSPFW_CURSORC_WM1_SHIFT 8
1906#define DSPFW_CURSORC_WM1_MASK (0x3f << 16)
1907#define DSPFW_CURSORC_SHIFT 0
1908#define DSPFW_CURSORC_MASK (0x3f << 0)
1909
1910/* vlv/chv high order bits */
1911#define DSPHOWM _MMIO(VLV_DISPLAY_BASE + 0x70064)
1912#define DSPFW_SR_HI_SHIFT 24
1913#define DSPFW_SR_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */
1914#define DSPFW_SPRITEF_HI_SHIFT 23
1915#define DSPFW_SPRITEF_HI_MASK (1 << 23)
1916#define DSPFW_SPRITEE_HI_SHIFT 22
1917#define DSPFW_SPRITEE_HI_MASK (1 << 22)
1918#define DSPFW_PLANEC_HI_SHIFT 21
1919#define DSPFW_PLANEC_HI_MASK (1 << 21)
1920#define DSPFW_SPRITED_HI_SHIFT 20
1921#define DSPFW_SPRITED_HI_MASK (1 << 20)
1922#define DSPFW_SPRITEC_HI_SHIFT 16
1923#define DSPFW_SPRITEC_HI_MASK (1 << 16)
1924#define DSPFW_PLANEB_HI_SHIFT 12
1925#define DSPFW_PLANEB_HI_MASK (1 << 12)
1926#define DSPFW_SPRITEB_HI_SHIFT 8
1927#define DSPFW_SPRITEB_HI_MASK (1 << 8)
1928#define DSPFW_SPRITEA_HI_SHIFT 4
1929#define DSPFW_SPRITEA_HI_MASK (1 << 4)
1930#define DSPFW_PLANEA_HI_SHIFT 0
1931#define DSPFW_PLANEA_HI_MASK (1 << 0)
1932#define DSPHOWM1 _MMIO(VLV_DISPLAY_BASE + 0x70068)
1933#define DSPFW_SR_WM1_HI_SHIFT 24
1934#define DSPFW_SR_WM1_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */
1935#define DSPFW_SPRITEF_WM1_HI_SHIFT 23
1936#define DSPFW_SPRITEF_WM1_HI_MASK (1 << 23)
1937#define DSPFW_SPRITEE_WM1_HI_SHIFT 22
1938#define DSPFW_SPRITEE_WM1_HI_MASK (1 << 22)
1939#define DSPFW_PLANEC_WM1_HI_SHIFT 21
1940#define DSPFW_PLANEC_WM1_HI_MASK (1 << 21)
1941#define DSPFW_SPRITED_WM1_HI_SHIFT 20
1942#define DSPFW_SPRITED_WM1_HI_MASK (1 << 20)
1943#define DSPFW_SPRITEC_WM1_HI_SHIFT 16
1944#define DSPFW_SPRITEC_WM1_HI_MASK (1 << 16)
1945#define DSPFW_PLANEB_WM1_HI_SHIFT 12
1946#define DSPFW_PLANEB_WM1_HI_MASK (1 << 12)
1947#define DSPFW_SPRITEB_WM1_HI_SHIFT 8
1948#define DSPFW_SPRITEB_WM1_HI_MASK (1 << 8)
1949#define DSPFW_SPRITEA_WM1_HI_SHIFT 4
1950#define DSPFW_SPRITEA_WM1_HI_MASK (1 << 4)
1951#define DSPFW_PLANEA_WM1_HI_SHIFT 0
1952#define DSPFW_PLANEA_WM1_HI_MASK (1 << 0)
1953
1954/* drain latency register values*/
1955#define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
1956#define DDL_CURSOR_SHIFT 24
1957#define DDL_SPRITE_SHIFT(sprite) (8 + 8 * (sprite))
1958#define DDL_PLANE_SHIFT 0
1959#define DDL_PRECISION_HIGH (1 << 7)
1960#define DDL_PRECISION_LOW (0 << 7)
1961#define DRAIN_LATENCY_MASK 0x7f
1962
1963#define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400)
1964#define CBR_PND_DEADLINE_DISABLE (1 << 31)
1965#define CBR_PWM_CLOCK_MUX_SELECT (1 << 30)
1966
1967#define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450)
1968#define CBR_DPLLBMD_PIPE(pipe) (1 << (7 + (pipe) * 11)) /* pipes B and C */
1969
1970/* FIFO watermark sizes etc */
1971#define G4X_FIFO_LINE_SIZE 64
1972#define I915_FIFO_LINE_SIZE 64
1973#define I830_FIFO_LINE_SIZE 32
1974
1975#define VALLEYVIEW_FIFO_SIZE 255
1976#define G4X_FIFO_SIZE 127
1977#define I965_FIFO_SIZE 512
1978#define I945_FIFO_SIZE 127
1979#define I915_FIFO_SIZE 95
1980#define I855GM_FIFO_SIZE 127 /* In cachelines */
1981#define I830_FIFO_SIZE 95
1982
1983#define VALLEYVIEW_MAX_WM 0xff
1984#define G4X_MAX_WM 0x3f
1985#define I915_MAX_WM 0x3f
1986
1987#define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */
1988#define PINEVIEW_FIFO_LINE_SIZE 64
1989#define PINEVIEW_MAX_WM 0x1ff
1990#define PINEVIEW_DFT_WM 0x3f
1991#define PINEVIEW_DFT_HPLLOFF_WM 0
1992#define PINEVIEW_GUARD_WM 10
1993#define PINEVIEW_CURSOR_FIFO 64
1994#define PINEVIEW_CURSOR_MAX_WM 0x3f
1995#define PINEVIEW_CURSOR_DFT_WM 0
1996#define PINEVIEW_CURSOR_GUARD_WM 5
1997
1998#define VALLEYVIEW_CURSOR_MAX_WM 64
1999#define I965_CURSOR_FIFO 64
2000#define I965_CURSOR_MAX_WM 32
2001#define I965_CURSOR_DFT_WM 8
2002
2003/* define the Watermark register on Ironlake */
2004#define _WM0_PIPEA_ILK 0x45100
2005#define _WM0_PIPEB_ILK 0x45104
2006#define _WM0_PIPEC_IVB 0x45200
2007#define WM0_PIPE_ILK(pipe) _MMIO_BASE_PIPE3(0, (pipe), _WM0_PIPEA_ILK, \
2008 _WM0_PIPEB_ILK, _WM0_PIPEC_IVB)
2009#define WM0_PIPE_PRIMARY_MASK REG_GENMASK(31, 16)
2010#define WM0_PIPE_SPRITE_MASK REG_GENMASK(15, 8)
2011#define WM0_PIPE_CURSOR_MASK REG_GENMASK(7, 0)
2012#define WM0_PIPE_PRIMARY(x) REG_FIELD_PREP(WM0_PIPE_PRIMARY_MASK, (x))
2013#define WM0_PIPE_SPRITE(x) REG_FIELD_PREP(WM0_PIPE_SPRITE_MASK, (x))
2014#define WM0_PIPE_CURSOR(x) REG_FIELD_PREP(WM0_PIPE_CURSOR_MASK, (x))
2015#define WM1_LP_ILK _MMIO(0x45108)
2016#define WM2_LP_ILK _MMIO(0x4510c)
2017#define WM3_LP_ILK _MMIO(0x45110)
2018#define WM_LP_ENABLE REG_BIT(31)
2019#define WM_LP_LATENCY_MASK REG_GENMASK(30, 24)
2020#define WM_LP_FBC_MASK_BDW REG_GENMASK(23, 19)
2021#define WM_LP_FBC_MASK_ILK REG_GENMASK(23, 20)
2022#define WM_LP_PRIMARY_MASK REG_GENMASK(18, 8)
2023#define WM_LP_CURSOR_MASK REG_GENMASK(7, 0)
2024#define WM_LP_LATENCY(x) REG_FIELD_PREP(WM_LP_LATENCY_MASK, (x))
2025#define WM_LP_FBC_BDW(x) REG_FIELD_PREP(WM_LP_FBC_MASK_BDW, (x))
2026#define WM_LP_FBC_ILK(x) REG_FIELD_PREP(WM_LP_FBC_MASK_ILK, (x))
2027#define WM_LP_PRIMARY(x) REG_FIELD_PREP(WM_LP_PRIMARY_MASK, (x))
2028#define WM_LP_CURSOR(x) REG_FIELD_PREP(WM_LP_CURSOR_MASK, (x))
2029#define WM1S_LP_ILK _MMIO(0x45120)
2030#define WM2S_LP_IVB _MMIO(0x45124)
2031#define WM3S_LP_IVB _MMIO(0x45128)
2032#define WM_LP_SPRITE_ENABLE REG_BIT(31) /* ilk/snb WM1S only */
2033#define WM_LP_SPRITE_MASK REG_GENMASK(10, 0)
2034#define WM_LP_SPRITE(x) REG_FIELD_PREP(WM_LP_SPRITE_MASK, (x))
2035
2036/*
2037 * The two pipe frame counter registers are not synchronized, so
2038 * reading a stable value is somewhat tricky. The following code
2039 * should work:
2040 *
2041 * do {
2042 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
2043 * PIPE_FRAME_HIGH_SHIFT;
2044 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
2045 * PIPE_FRAME_LOW_SHIFT);
2046 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
2047 * PIPE_FRAME_HIGH_SHIFT);
2048 * } while (high1 != high2);
2049 * frame = (high1 << 8) | low1;
2050 */
2051#define _PIPEAFRAMEHIGH 0x70040
2052#define PIPEFRAME(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEHIGH)
2053#define PIPE_FRAME_HIGH_MASK 0x0000ffff
2054#define PIPE_FRAME_HIGH_SHIFT 0
2055
2056#define _PIPEAFRAMEPIXEL 0x70044
2057#define PIPEFRAMEPIXEL(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEPIXEL)
2058#define PIPE_FRAME_LOW_MASK 0xff000000
2059#define PIPE_FRAME_LOW_SHIFT 24
2060#define PIPE_PIXEL_MASK 0x00ffffff
2061#define PIPE_PIXEL_SHIFT 0
2062
2063/* GM45+ just has to be different */
2064#define _PIPEA_FRMCOUNT_G4X 0x70040
2065#define PIPE_FRMCOUNT_G4X(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FRMCOUNT_G4X)
2066
2067#define _PIPEA_FLIPCOUNT_G4X 0x70044
2068#define PIPE_FLIPCOUNT_G4X(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FLIPCOUNT_G4X)
2069
2070/* CHV pipe B blender */
2071#define _CHV_BLEND_A 0x60a00
2072#define CHV_BLEND(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _CHV_BLEND_A)
2073#define CHV_BLEND_MASK REG_GENMASK(31, 30)
2074#define CHV_BLEND_LEGACY REG_FIELD_PREP(CHV_BLEND_MASK, 0)
2075#define CHV_BLEND_ANDROID REG_FIELD_PREP(CHV_BLEND_MASK, 1)
2076#define CHV_BLEND_MPO REG_FIELD_PREP(CHV_BLEND_MASK, 2)
2077
2078#define _CHV_CANVAS_A 0x60a04
2079#define CHV_CANVAS(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _CHV_CANVAS_A)
2080#define CHV_CANVAS_RED_MASK REG_GENMASK(29, 20)
2081#define CHV_CANVAS_GREEN_MASK REG_GENMASK(19, 10)
2082#define CHV_CANVAS_BLUE_MASK REG_GENMASK(9, 0)
2083
2084/* Display/Sprite base address macros */
2085#define DISP_BASEADDR_MASK (0xfffff000)
2086#define I915_LO_DISPBASE(val) ((val) & ~DISP_BASEADDR_MASK)
2087#define I915_HI_DISPBASE(val) ((val) & DISP_BASEADDR_MASK)
2088
2089/*
2090 * VBIOS flags
2091 * gen2:
2092 * [00:06] alm,mgm
2093 * [10:16] all
2094 * [30:32] alm,mgm
2095 * gen3+:
2096 * [00:0f] all
2097 * [10:1f] all
2098 * [30:32] all
2099 */
2100#define SWF0(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4)
2101#define SWF1(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4)
2102#define SWF3(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4)
2103#define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4)
2104
2105/* VBIOS regs */
2106#define VGACNTRL _MMIO(0x71400)
2107# define VGA_DISP_DISABLE (1 << 31)
2108# define VGA_2X_MODE (1 << 30)
2109# define VGA_PIPE_B_SELECT (1 << 29)
2110
2111#define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400)
2112
2113/* Ironlake */
2114
2115#define CPU_VGACNTRL _MMIO(0x41000)
2116
2117#define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030)
2118#define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
2119#define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */
2120#define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2) /* pre-HSW */
2121#define DIGITAL_PORTA_PULSE_DURATION_6ms (2 << 2) /* pre-HSW */
2122#define DIGITAL_PORTA_PULSE_DURATION_100ms (3 << 2) /* pre-HSW */
2123#define DIGITAL_PORTA_PULSE_DURATION_MASK (3 << 2) /* pre-HSW */
2124#define DIGITAL_PORTA_HOTPLUG_STATUS_MASK (3 << 0)
2125#define DIGITAL_PORTA_HOTPLUG_NO_DETECT (0 << 0)
2126#define DIGITAL_PORTA_HOTPLUG_SHORT_DETECT (1 << 0)
2127#define DIGITAL_PORTA_HOTPLUG_LONG_DETECT (2 << 0)
2128
2129/* refresh rate hardware control */
2130#define RR_HW_CTL _MMIO(0x45300)
2131#define RR_HW_LOW_POWER_FRAMES_MASK 0xff
2132#define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
2133
2134#define PCH_3DCGDIS0 _MMIO(0x46020)
2135# define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
2136# define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
2137
2138#define PCH_3DCGDIS1 _MMIO(0x46024)
2139# define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
2140
2141#define _PIPEA_DATA_M1 0x60030
2142#define _PIPEB_DATA_M1 0x61030
2143#define PIPE_DATA_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M1)
2144
2145#define _PIPEA_DATA_N1 0x60034
2146#define _PIPEB_DATA_N1 0x61034
2147#define PIPE_DATA_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N1)
2148
2149#define _PIPEA_DATA_M2 0x60038
2150#define _PIPEB_DATA_M2 0x61038
2151#define PIPE_DATA_M2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M2)
2152
2153#define _PIPEA_DATA_N2 0x6003c
2154#define _PIPEB_DATA_N2 0x6103c
2155#define PIPE_DATA_N2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N2)
2156
2157#define _PIPEA_LINK_M1 0x60040
2158#define _PIPEB_LINK_M1 0x61040
2159#define PIPE_LINK_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M1)
2160
2161#define _PIPEA_LINK_N1 0x60044
2162#define _PIPEB_LINK_N1 0x61044
2163#define PIPE_LINK_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1)
2164
2165#define _PIPEA_LINK_M2 0x60048
2166#define _PIPEB_LINK_M2 0x61048
2167#define PIPE_LINK_M2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M2)
2168
2169#define _PIPEA_LINK_N2 0x6004c
2170#define _PIPEB_LINK_N2 0x6104c
2171#define PIPE_LINK_N2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N2)
2172
2173/* CPU panel fitter */
2174/* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
2175#define _PFA_CTL_1 0x68080
2176#define _PFB_CTL_1 0x68880
2177#define PF_CTL(pipe) _MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
2178#define PF_ENABLE REG_BIT(31)
2179#define PF_PIPE_SEL_MASK_IVB REG_GENMASK(30, 29) /* ivb/hsw */
2180#define PF_PIPE_SEL_IVB(pipe) REG_FIELD_PREP(PF_PIPE_SEL_MASK_IVB, (pipe))
2181#define PF_FILTER_MASK REG_GENMASK(24, 23)
2182#define PF_FILTER_PROGRAMMED REG_FIELD_PREP(PF_FILTER_MASK, 0)
2183#define PF_FILTER_MED_3x3 REG_FIELD_PREP(PF_FILTER_MASK, 1)
2184#define PF_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PF_FILTER_EDGE_MASK, 2)
2185#define PF_FILTER_EDGE_SOFTEN REG_FIELD_PREP(PF_FILTER_EDGE_MASK, 3)
2186
2187#define _PFA_WIN_SZ 0x68074
2188#define _PFB_WIN_SZ 0x68874
2189#define PF_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
2190#define PF_WIN_XSIZE_MASK REG_GENMASK(31, 16)
2191#define PF_WIN_XSIZE(w) REG_FIELD_PREP(PF_WIN_XSIZE_MASK, (w))
2192#define PF_WIN_YSIZE_MASK REG_GENMASK(15, 0)
2193#define PF_WIN_YSIZE(h) REG_FIELD_PREP(PF_WIN_YSIZE_MASK, (h))
2194
2195#define _PFA_WIN_POS 0x68070
2196#define _PFB_WIN_POS 0x68870
2197#define PF_WIN_POS(pipe) _MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
2198#define PF_WIN_XPOS_MASK REG_GENMASK(31, 16)
2199#define PF_WIN_XPOS(x) REG_FIELD_PREP(PF_WIN_XPOS_MASK, (x))
2200#define PF_WIN_YPOS_MASK REG_GENMASK(15, 0)
2201#define PF_WIN_YPOS(y) REG_FIELD_PREP(PF_WIN_YPOS_MASK, (y))
2202
2203#define _PFA_VSCALE 0x68084
2204#define _PFB_VSCALE 0x68884
2205#define PF_VSCALE(pipe) _MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
2206
2207#define _PFA_HSCALE 0x68090
2208#define _PFB_HSCALE 0x68890
2209#define PF_HSCALE(pipe) _MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
2210
2211/*
2212 * Skylake scalers
2213 */
2214#define _ID(id, a, b) _PICK_EVEN(id, a, b)
2215#define _PS_1A_CTRL 0x68180
2216#define _PS_2A_CTRL 0x68280
2217#define _PS_1B_CTRL 0x68980
2218#define _PS_2B_CTRL 0x68A80
2219#define _PS_1C_CTRL 0x69180
2220#define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \
2221 _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \
2222 _ID(id, _PS_1B_CTRL, _PS_2B_CTRL))
2223#define PS_SCALER_EN REG_BIT(31)
2224#define PS_SCALER_TYPE_MASK REG_BIT(30) /* icl+ */
2225#define PS_SCALER_TYPE_NON_LINEAR REG_FIELD_PREP(PS_SCALER_TYPE_MASK, 0)
2226#define PS_SCALER_TYPE_LINEAR REG_FIELD_PREP(PS_SCALER_TYPE_MASK, 1)
2227#define SKL_PS_SCALER_MODE_MASK REG_GENMASK(29, 28) /* skl/bxt */
2228#define SKL_PS_SCALER_MODE_DYN REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 0)
2229#define SKL_PS_SCALER_MODE_HQ REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 1)
2230#define SKL_PS_SCALER_MODE_NV12 REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 2)
2231#define PS_SCALER_MODE_MASK REG_BIT(29) /* glk-tgl */
2232#define PS_SCALER_MODE_NORMAL REG_FIELD_PREP(PS_SCALER_MODE_MASK, 0)
2233#define PS_SCALER_MODE_PLANAR REG_FIELD_PREP(PS_SCALER_MODE_MASK, 1)
2234#define PS_ADAPTIVE_FILTERING_EN REG_BIT(28) /* icl+ */
2235#define PS_BINDING_MASK REG_GENMASK(27, 25)
2236#define PS_BINDING_PIPE REG_FIELD_PREP(PS_BINDING_MASK, 0)
2237#define PS_BINDING_PLANE(plane_id) REG_FIELD_PREP(PS_BINDING_MASK, (plane_id) + 1)
2238#define PS_FILTER_MASK REG_GENMASK(24, 23)
2239#define PS_FILTER_MEDIUM REG_FIELD_PREP(PS_FILTER_MASK, 0)
2240#define PS_FILTER_PROGRAMMED REG_FIELD_PREP(PS_FILTER_MASK, 1)
2241#define PS_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PS_FILTER_MASK, 2)
2242#define PS_FILTER_BILINEAR REG_FIELD_PREP(PS_FILTER_MASK, 3)
2243#define PS_ADAPTIVE_FILTER_MASK REG_BIT(22) /* icl+ */
2244#define PS_ADAPTIVE_FILTER_MEDIUM REG_FIELD_PREP(PS_ADAPTIVE_FILTER_MASK, 0)
2245#define PS_ADAPTIVE_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PS_ADAPTIVE_FILTER_MASK, 1)
2246#define PS_PIPE_SCALER_LOC_MASK REG_BIT(21) /* icl+ */
2247#define PS_PIPE_SCALER_LOC_AFTER_OUTPUT_CSC REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 0) /* non-linear */
2248#define PS_PIPE_SCALER_LOC_AFTER_CSC REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 1) /* linear */
2249#define PS_VERT3TAP REG_BIT(21) /* skl/bxt */
2250#define PS_VERT_INT_INVERT_FIELD REG_BIT(20)
2251#define PS_PROG_SCALE_FACTOR REG_BIT(19) /* tgl+ */
2252#define PS_PWRUP_PROGRESS REG_BIT(17)
2253#define PS_V_FILTER_BYPASS REG_BIT(8)
2254#define PS_VADAPT_EN REG_BIT(7) /* skl/bxt */
2255#define PS_VADAPT_MODE_MASK REG_GENMASK(6, 5) /* skl/bxt */
2256#define PS_VADAPT_MODE_LEAST_ADAPT REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 0)
2257#define PS_VADAPT_MODE_MOD_ADAPT REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 1)
2258#define PS_VADAPT_MODE_MOST_ADAPT REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 3)
2259#define PS_BINDING_Y_MASK REG_GENMASK(7, 5) /* icl-tgl */
2260#define PS_BINDING_Y_PLANE(plane_id) REG_FIELD_PREP(PS_BINDING_Y_MASK, (plane_id) + 1)
2261#define PS_Y_VERT_FILTER_SELECT_MASK REG_BIT(4) /* glk+ */
2262#define PS_Y_VERT_FILTER_SELECT(set) REG_FIELD_PREP(PS_Y_VERT_FILTER_SELECT_MASK, (set))
2263#define PS_Y_HORZ_FILTER_SELECT_MASK REG_BIT(3) /* glk+ */
2264#define PS_Y_HORZ_FILTER_SELECT(set) REG_FIELD_PREP(PS_Y_HORZ_FILTER_SELECT_MASK, (set))
2265#define PS_UV_VERT_FILTER_SELECT_MASK REG_BIT(2) /* glk+ */
2266#define PS_UV_VERT_FILTER_SELECT(set) REG_FIELD_PREP(PS_UV_VERT_FILTER_SELECT_MASK, (set))
2267#define PS_UV_HORZ_FILTER_SELECT_MASK REG_BIT(1) /* glk+ */
2268#define PS_UV_HORZ_FILTER_SELECT(set) REG_FIELD_PREP(PS_UV_HORZ_FILTER_SELECT_MASK, (set))
2269
2270#define _PS_PWR_GATE_1A 0x68160
2271#define _PS_PWR_GATE_2A 0x68260
2272#define _PS_PWR_GATE_1B 0x68960
2273#define _PS_PWR_GATE_2B 0x68A60
2274#define _PS_PWR_GATE_1C 0x69160
2275#define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe, \
2276 _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \
2277 _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B))
2278#define PS_PWR_GATE_DIS_OVERRIDE REG_BIT(31)
2279#define PS_PWR_GATE_SETTLING_TIME_MASK REG_GENMASK(4, 3)
2280#define PS_PWR_GATE_SETTLING_TIME_32 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 0)
2281#define PS_PWR_GATE_SETTLING_TIME_64 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 1)
2282#define PS_PWR_GATE_SETTLING_TIME_96 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 2)
2283#define PS_PWR_GATE_SETTLING_TIME_128 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 3)
2284#define PS_PWR_GATE_SLPEN_MASK REG_GENMASK(1, 0)
2285#define PS_PWR_GATE_SLPEN_8 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 0)
2286#define PS_PWR_GATE_SLPEN_16 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 1)
2287#define PS_PWR_GATE_SLPEN_24 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 2)
2288#define PS_PWR_GATE_SLPEN_32 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 3)
2289
2290#define _PS_WIN_POS_1A 0x68170
2291#define _PS_WIN_POS_2A 0x68270
2292#define _PS_WIN_POS_1B 0x68970
2293#define _PS_WIN_POS_2B 0x68A70
2294#define _PS_WIN_POS_1C 0x69170
2295#define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe, \
2296 _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \
2297 _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B))
2298#define PS_WIN_XPOS_MASK REG_GENMASK(31, 16)
2299#define PS_WIN_XPOS(x) REG_FIELD_PREP(PS_WIN_XPOS_MASK, (x))
2300#define PS_WIN_YPOS_MASK REG_GENMASK(15, 0)
2301#define PS_WIN_YPOS(y) REG_FIELD_PREP(PS_WIN_YPOS_MASK, (y))
2302
2303#define _PS_WIN_SZ_1A 0x68174
2304#define _PS_WIN_SZ_2A 0x68274
2305#define _PS_WIN_SZ_1B 0x68974
2306#define _PS_WIN_SZ_2B 0x68A74
2307#define _PS_WIN_SZ_1C 0x69174
2308#define SKL_PS_WIN_SZ(pipe, id) _MMIO_PIPE(pipe, \
2309 _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \
2310 _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B))
2311#define PS_WIN_XSIZE_MASK REG_GENMASK(31, 16)
2312#define PS_WIN_XSIZE(w) REG_FIELD_PREP(PS_WIN_XSIZE_MASK, (w))
2313#define PS_WIN_YSIZE_MASK REG_GENMASK(15, 0)
2314#define PS_WIN_YSIZE(h) REG_FIELD_PREP(PS_WIN_YSIZE_MASK, (h))
2315
2316#define _PS_VSCALE_1A 0x68184
2317#define _PS_VSCALE_2A 0x68284
2318#define _PS_VSCALE_1B 0x68984
2319#define _PS_VSCALE_2B 0x68A84
2320#define _PS_VSCALE_1C 0x69184
2321#define SKL_PS_VSCALE(pipe, id) _MMIO_PIPE(pipe, \
2322 _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \
2323 _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B))
2324
2325#define _PS_HSCALE_1A 0x68190
2326#define _PS_HSCALE_2A 0x68290
2327#define _PS_HSCALE_1B 0x68990
2328#define _PS_HSCALE_2B 0x68A90
2329#define _PS_HSCALE_1C 0x69190
2330#define SKL_PS_HSCALE(pipe, id) _MMIO_PIPE(pipe, \
2331 _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \
2332 _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B))
2333
2334#define _PS_VPHASE_1A 0x68188
2335#define _PS_VPHASE_2A 0x68288
2336#define _PS_VPHASE_1B 0x68988
2337#define _PS_VPHASE_2B 0x68A88
2338#define _PS_VPHASE_1C 0x69188
2339#define SKL_PS_VPHASE(pipe, id) _MMIO_PIPE(pipe, \
2340 _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \
2341 _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B))
2342#define PS_Y_PHASE_MASK REG_GENMASK(31, 16)
2343#define PS_Y_PHASE(x) REG_FIELD_PREP(PS_Y_PHASE_MASK, (x))
2344#define PS_UV_RGB_PHASE_MASK REG_GENMASK(15, 0)
2345#define PS_UV_RGB_PHASE(x) REG_FIELD_PREP(PS_UV_RGB_PHASE_MASK, (x))
2346#define PS_PHASE_MASK (0x7fff << 1) /* u2.13 */
2347#define PS_PHASE_TRIP (1 << 0)
2348
2349#define _PS_HPHASE_1A 0x68194
2350#define _PS_HPHASE_2A 0x68294
2351#define _PS_HPHASE_1B 0x68994
2352#define _PS_HPHASE_2B 0x68A94
2353#define _PS_HPHASE_1C 0x69194
2354#define SKL_PS_HPHASE(pipe, id) _MMIO_PIPE(pipe, \
2355 _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \
2356 _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B))
2357
2358#define _PS_ECC_STAT_1A 0x681D0
2359#define _PS_ECC_STAT_2A 0x682D0
2360#define _PS_ECC_STAT_1B 0x689D0
2361#define _PS_ECC_STAT_2B 0x68AD0
2362#define _PS_ECC_STAT_1C 0x691D0
2363#define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \
2364 _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \
2365 _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
2366
2367#define _PS_COEF_SET0_INDEX_1A 0x68198
2368#define _PS_COEF_SET0_INDEX_2A 0x68298
2369#define _PS_COEF_SET0_INDEX_1B 0x68998
2370#define _PS_COEF_SET0_INDEX_2B 0x68A98
2371#define GLK_PS_COEF_INDEX_SET(pipe, id, set) _MMIO_PIPE(pipe, \
2372 _ID(id, _PS_COEF_SET0_INDEX_1A, _PS_COEF_SET0_INDEX_2A) + (set) * 8, \
2373 _ID(id, _PS_COEF_SET0_INDEX_1B, _PS_COEF_SET0_INDEX_2B) + (set) * 8)
2374#define PS_COEF_INDEX_AUTO_INC REG_BIT(10)
2375
2376#define _PS_COEF_SET0_DATA_1A 0x6819C
2377#define _PS_COEF_SET0_DATA_2A 0x6829C
2378#define _PS_COEF_SET0_DATA_1B 0x6899C
2379#define _PS_COEF_SET0_DATA_2B 0x68A9C
2380#define GLK_PS_COEF_DATA_SET(pipe, id, set) _MMIO_PIPE(pipe, \
2381 _ID(id, _PS_COEF_SET0_DATA_1A, _PS_COEF_SET0_DATA_2A) + (set) * 8, \
2382 _ID(id, _PS_COEF_SET0_DATA_1B, _PS_COEF_SET0_DATA_2B) + (set) * 8)
2383
2384/* Display Internal Timeout Register */
2385#define RM_TIMEOUT _MMIO(0x42060)
2386#define RM_TIMEOUT_REG_CAPTURE _MMIO(0x420E0)
2387#define MMIO_TIMEOUT_US(us) ((us) << 0)
2388
2389/* interrupts */
2390#define DE_MASTER_IRQ_CONTROL (1 << 31)
2391#define DE_SPRITEB_FLIP_DONE (1 << 29)
2392#define DE_SPRITEA_FLIP_DONE (1 << 28)
2393#define DE_PLANEB_FLIP_DONE (1 << 27)
2394#define DE_PLANEA_FLIP_DONE (1 << 26)
2395#define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane)))
2396#define DE_PCU_EVENT (1 << 25)
2397#define DE_GTT_FAULT (1 << 24)
2398#define DE_POISON (1 << 23)
2399#define DE_PERFORM_COUNTER (1 << 22)
2400#define DE_PCH_EVENT (1 << 21)
2401#define DE_AUX_CHANNEL_A (1 << 20)
2402#define DE_DP_A_HOTPLUG (1 << 19)
2403#define DE_GSE (1 << 18)
2404#define DE_PIPEB_VBLANK (1 << 15)
2405#define DE_PIPEB_EVEN_FIELD (1 << 14)
2406#define DE_PIPEB_ODD_FIELD (1 << 13)
2407#define DE_PIPEB_LINE_COMPARE (1 << 12)
2408#define DE_PIPEB_VSYNC (1 << 11)
2409#define DE_PIPEB_CRC_DONE (1 << 10)
2410#define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
2411#define DE_PIPEA_VBLANK (1 << 7)
2412#define DE_PIPE_VBLANK(pipe) (1 << (7 + 8 * (pipe)))
2413#define DE_PIPEA_EVEN_FIELD (1 << 6)
2414#define DE_PIPEA_ODD_FIELD (1 << 5)
2415#define DE_PIPEA_LINE_COMPARE (1 << 4)
2416#define DE_PIPEA_VSYNC (1 << 3)
2417#define DE_PIPEA_CRC_DONE (1 << 2)
2418#define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8 * (pipe)))
2419#define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
2420#define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8 * (pipe)))
2421
2422/* More Ivybridge lolz */
2423#define DE_ERR_INT_IVB (1 << 30)
2424#define DE_GSE_IVB (1 << 29)
2425#define DE_PCH_EVENT_IVB (1 << 28)
2426#define DE_DP_A_HOTPLUG_IVB (1 << 27)
2427#define DE_AUX_CHANNEL_A_IVB (1 << 26)
2428#define DE_EDP_PSR_INT_HSW (1 << 19)
2429#define DE_SPRITEC_FLIP_DONE_IVB (1 << 14)
2430#define DE_PLANEC_FLIP_DONE_IVB (1 << 13)
2431#define DE_PIPEC_VBLANK_IVB (1 << 10)
2432#define DE_SPRITEB_FLIP_DONE_IVB (1 << 9)
2433#define DE_PLANEB_FLIP_DONE_IVB (1 << 8)
2434#define DE_PIPEB_VBLANK_IVB (1 << 5)
2435#define DE_SPRITEA_FLIP_DONE_IVB (1 << 4)
2436#define DE_PLANEA_FLIP_DONE_IVB (1 << 3)
2437#define DE_PLANE_FLIP_DONE_IVB(plane) (1 << (3 + 5 * (plane)))
2438#define DE_PIPEA_VBLANK_IVB (1 << 0)
2439#define DE_PIPE_VBLANK_IVB(pipe) (1 << ((pipe) * 5))
2440
2441#define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */
2442#define MASTER_INTERRUPT_ENABLE (1 << 31)
2443
2444#define DEISR _MMIO(0x44000)
2445#define DEIMR _MMIO(0x44004)
2446#define DEIIR _MMIO(0x44008)
2447#define DEIER _MMIO(0x4400c)
2448
2449#define DE_IRQ_REGS I915_IRQ_REGS(DEIMR, \
2450 DEIER, \
2451 DEIIR)
2452
2453#define GTISR _MMIO(0x44010)
2454#define GTIMR _MMIO(0x44014)
2455#define GTIIR _MMIO(0x44018)
2456#define GTIER _MMIO(0x4401c)
2457
2458#define GT_IRQ_REGS I915_IRQ_REGS(GTIMR, \
2459 GTIER, \
2460 GTIIR)
2461
2462#define GEN8_MASTER_IRQ _MMIO(0x44200)
2463#define GEN8_MASTER_IRQ_CONTROL (1 << 31)
2464#define GEN8_PCU_IRQ (1 << 30)
2465#define GEN8_DE_PCH_IRQ (1 << 23)
2466#define GEN8_DE_MISC_IRQ (1 << 22)
2467#define GEN8_DE_PORT_IRQ (1 << 20)
2468#define GEN8_DE_PIPE_C_IRQ (1 << 18)
2469#define GEN8_DE_PIPE_B_IRQ (1 << 17)
2470#define GEN8_DE_PIPE_A_IRQ (1 << 16)
2471#define GEN8_DE_PIPE_IRQ(pipe) (1 << (16 + (pipe)))
2472#define GEN8_GT_VECS_IRQ (1 << 6)
2473#define GEN8_GT_GUC_IRQ (1 << 5)
2474#define GEN8_GT_PM_IRQ (1 << 4)
2475#define GEN8_GT_VCS1_IRQ (1 << 3) /* NB: VCS2 in bspec! */
2476#define GEN8_GT_VCS0_IRQ (1 << 2) /* NB: VCS1 in bpsec! */
2477#define GEN8_GT_BCS_IRQ (1 << 1)
2478#define GEN8_GT_RCS_IRQ (1 << 0)
2479
2480#define XELPD_DISPLAY_ERR_FATAL_MASK _MMIO(0x4421c)
2481
2482#define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which)))
2483#define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which)))
2484#define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))
2485#define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which)))
2486
2487#define GEN8_GT_IRQ_REGS(which) I915_IRQ_REGS(GEN8_GT_IMR(which), \
2488 GEN8_GT_IER(which), \
2489 GEN8_GT_IIR(which))
2490
2491#define GEN8_RCS_IRQ_SHIFT 0
2492#define GEN8_BCS_IRQ_SHIFT 16
2493#define GEN8_VCS0_IRQ_SHIFT 0 /* NB: VCS1 in bspec! */
2494#define GEN8_VCS1_IRQ_SHIFT 16 /* NB: VCS2 in bpsec! */
2495#define GEN8_VECS_IRQ_SHIFT 0
2496#define GEN8_WD_IRQ_SHIFT 16
2497
2498#define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe)))
2499#define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe)))
2500#define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe)))
2501#define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe)))
2502#define GEN8_PIPE_FIFO_UNDERRUN REG_BIT(31)
2503#define GEN8_PIPE_CDCLK_CRC_ERROR REG_BIT(29)
2504#define GEN8_PIPE_CDCLK_CRC_DONE REG_BIT(28)
2505#define GEN12_PIPEDMC_INTERRUPT REG_BIT(26) /* tgl+ */
2506#define GEN12_PIPEDMC_FAULT REG_BIT(25) /* tgl+ */
2507#define MTL_PIPEDMC_ATS_FAULT REG_BIT(24) /* mtl+ */
2508#define GEN11_PIPE_PLANE7_FAULT REG_BIT(22) /* icl/tgl */
2509#define GEN11_PIPE_PLANE6_FAULT REG_BIT(21) /* icl/tgl */
2510#define GEN11_PIPE_PLANE5_FAULT REG_BIT(20) /* icl+ */
2511#define GEN12_PIPE_VBLANK_UNMOD REG_BIT(19) /* tgl+ */
2512#define MTL_PLANE_ATS_FAULT REG_BIT(18) /* mtl+ */
2513#define GEN11_PIPE_PLANE7_FLIP_DONE REG_BIT(18) /* icl/tgl */
2514#define GEN11_PIPE_PLANE6_FLIP_DONE REG_BIT(17) /* icl/tgl */
2515#define GEN11_PIPE_PLANE5_FLIP_DONE REG_BIT(16) /* icl+ */
2516#define GEN12_DSB_2_INT REG_BIT(15) /* tgl+ */
2517#define GEN12_DSB_1_INT REG_BIT(14) /* tgl+ */
2518#define GEN12_DSB_0_INT REG_BIT(13) /* tgl+ */
2519#define GEN12_DSB_INT(dsb_id) REG_BIT(13 + (dsb_id))
2520#define GEN9_PIPE_CURSOR_FAULT REG_BIT(11) /* skl+ */
2521#define GEN9_PIPE_PLANE4_FAULT REG_BIT(10) /* skl+ */
2522#define GEN8_PIPE_CURSOR_FAULT REG_BIT(10) /* bdw */
2523#define GEN9_PIPE_PLANE3_FAULT REG_BIT(9) /* skl+ */
2524#define GEN8_PIPE_SPRITE_FAULT REG_BIT(9) /* bdw */
2525#define GEN9_PIPE_PLANE2_FAULT REG_BIT(8) /* skl+ */
2526#define GEN8_PIPE_PRIMARY_FAULT REG_BIT(8) /* bdw */
2527#define GEN9_PIPE_PLANE1_FAULT REG_BIT(7) /* skl+ */
2528#define GEN9_PIPE_PLANE4_FLIP_DONE REG_BIT(6) /* skl+ */
2529#define GEN9_PIPE_PLANE3_FLIP_DONE REG_BIT(5) /* skl+ */
2530#define GEN8_PIPE_SPRITE_FLIP_DONE REG_BIT(5) /* bdw */
2531#define GEN9_PIPE_PLANE2_FLIP_DONE REG_BIT(4) /* skl+ */
2532#define GEN8_PIPE_PRIMARY_FLIP_DONE REG_BIT(4) /* bdw */
2533#define GEN9_PIPE_PLANE1_FLIP_DONE REG_BIT(3) /* skl+ */
2534#define GEN9_PIPE_PLANE_FLIP_DONE(plane_id) \
2535 REG_BIT(((plane_id) >= PLANE_5 ? 16 - PLANE_5 : 3 - PLANE_1) + (plane_id)) /* skl+ */
2536#define GEN8_PIPE_SCAN_LINE_EVENT REG_BIT(2)
2537#define GEN8_PIPE_VSYNC REG_BIT(1)
2538#define GEN8_PIPE_VBLANK REG_BIT(0)
2539
2540#define GEN8_DE_PIPE_IRQ_REGS(pipe) I915_IRQ_REGS(GEN8_DE_PIPE_IMR(pipe), \
2541 GEN8_DE_PIPE_IER(pipe), \
2542 GEN8_DE_PIPE_IIR(pipe))
2543
2544#define _HPD_PIN_DDI(hpd_pin) ((hpd_pin) - HPD_PORT_A)
2545#define _HPD_PIN_TC(hpd_pin) ((hpd_pin) - HPD_PORT_TC1)
2546
2547#define GEN8_DE_PORT_ISR _MMIO(0x44440)
2548#define GEN8_DE_PORT_IMR _MMIO(0x44444)
2549#define GEN8_DE_PORT_IIR _MMIO(0x44448)
2550#define GEN8_DE_PORT_IER _MMIO(0x4444c)
2551#define DSI1_NON_TE (1 << 31)
2552#define DSI0_NON_TE (1 << 30)
2553#define ICL_AUX_CHANNEL_E (1 << 29)
2554#define ICL_AUX_CHANNEL_F (1 << 28)
2555#define GEN9_AUX_CHANNEL_D (1 << 27)
2556#define GEN9_AUX_CHANNEL_C (1 << 26)
2557#define GEN9_AUX_CHANNEL_B (1 << 25)
2558#define DSI1_TE (1 << 24)
2559#define DSI0_TE (1 << 23)
2560#define GEN8_DE_PORT_HOTPLUG(hpd_pin) REG_BIT(3 + _HPD_PIN_DDI(hpd_pin))
2561#define BXT_DE_PORT_HOTPLUG_MASK (GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) | \
2562 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | \
2563 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C))
2564#define BDW_DE_PORT_HOTPLUG_MASK GEN8_DE_PORT_HOTPLUG(HPD_PORT_A)
2565#define BXT_DE_PORT_GMBUS (1 << 1)
2566#define GEN8_AUX_CHANNEL_A (1 << 0)
2567#define TGL_DE_PORT_AUX_USBC6 REG_BIT(13)
2568#define XELPD_DE_PORT_AUX_DDIE REG_BIT(13)
2569#define TGL_DE_PORT_AUX_USBC5 REG_BIT(12)
2570#define XELPD_DE_PORT_AUX_DDID REG_BIT(12)
2571#define TGL_DE_PORT_AUX_USBC4 REG_BIT(11)
2572#define TGL_DE_PORT_AUX_USBC3 REG_BIT(10)
2573#define TGL_DE_PORT_AUX_USBC2 REG_BIT(9)
2574#define TGL_DE_PORT_AUX_USBC1 REG_BIT(8)
2575#define TGL_DE_PORT_AUX_DDIC REG_BIT(2)
2576#define TGL_DE_PORT_AUX_DDIB REG_BIT(1)
2577#define TGL_DE_PORT_AUX_DDIA REG_BIT(0)
2578
2579#define GEN8_DE_PORT_IRQ_REGS I915_IRQ_REGS(GEN8_DE_PORT_IMR, \
2580 GEN8_DE_PORT_IER, \
2581 GEN8_DE_PORT_IIR)
2582
2583#define GEN8_DE_MISC_ISR _MMIO(0x44460)
2584#define GEN8_DE_MISC_IMR _MMIO(0x44464)
2585#define GEN8_DE_MISC_IIR _MMIO(0x44468)
2586#define GEN8_DE_MISC_IER _MMIO(0x4446c)
2587#define XELPDP_RM_TIMEOUT REG_BIT(29)
2588#define XELPDP_PMDEMAND_RSPTOUT_ERR REG_BIT(27)
2589#define GEN8_DE_MISC_GSE REG_BIT(27)
2590#define GEN8_DE_EDP_PSR REG_BIT(19)
2591#define XELPDP_PMDEMAND_RSP REG_BIT(3)
2592#define XE2LPD_DBUF_OVERLAP_DETECTED REG_BIT(1)
2593
2594#define GEN8_DE_MISC_IRQ_REGS I915_IRQ_REGS(GEN8_DE_MISC_IMR, \
2595 GEN8_DE_MISC_IER, \
2596 GEN8_DE_MISC_IIR)
2597
2598#define GEN8_PCU_ISR _MMIO(0x444e0)
2599#define GEN8_PCU_IMR _MMIO(0x444e4)
2600#define GEN8_PCU_IIR _MMIO(0x444e8)
2601#define GEN8_PCU_IER _MMIO(0x444ec)
2602
2603#define GEN8_PCU_IRQ_REGS I915_IRQ_REGS(GEN8_PCU_IMR, \
2604 GEN8_PCU_IER, \
2605 GEN8_PCU_IIR)
2606
2607#define GEN11_GU_MISC_ISR _MMIO(0x444f0)
2608#define GEN11_GU_MISC_IMR _MMIO(0x444f4)
2609#define GEN11_GU_MISC_IIR _MMIO(0x444f8)
2610#define GEN11_GU_MISC_IER _MMIO(0x444fc)
2611#define GEN11_GU_MISC_GSE (1 << 27)
2612
2613#define GEN11_GU_MISC_IRQ_REGS I915_IRQ_REGS(GEN11_GU_MISC_IMR, \
2614 GEN11_GU_MISC_IER, \
2615 GEN11_GU_MISC_IIR)
2616
2617#define GEN11_GFX_MSTR_IRQ _MMIO(0x190010)
2618#define GEN11_MASTER_IRQ (1 << 31)
2619#define GEN11_PCU_IRQ (1 << 30)
2620#define GEN11_GU_MISC_IRQ (1 << 29)
2621#define GEN11_DISPLAY_IRQ (1 << 16)
2622#define GEN11_GT_DW_IRQ(x) (1 << (x))
2623#define GEN11_GT_DW1_IRQ (1 << 1)
2624#define GEN11_GT_DW0_IRQ (1 << 0)
2625
2626#define DG1_MSTR_TILE_INTR _MMIO(0x190008)
2627#define DG1_MSTR_IRQ REG_BIT(31)
2628#define DG1_MSTR_TILE(t) REG_BIT(t)
2629
2630#define GEN11_DISPLAY_INT_CTL _MMIO(0x44200)
2631#define GEN11_DISPLAY_IRQ_ENABLE (1 << 31)
2632#define GEN11_AUDIO_CODEC_IRQ (1 << 24)
2633#define GEN11_DE_PCH_IRQ (1 << 23)
2634#define GEN11_DE_MISC_IRQ (1 << 22)
2635#define GEN11_DE_HPD_IRQ (1 << 21)
2636#define GEN11_DE_PORT_IRQ (1 << 20)
2637#define GEN11_DE_PIPE_C (1 << 18)
2638#define GEN11_DE_PIPE_B (1 << 17)
2639#define GEN11_DE_PIPE_A (1 << 16)
2640
2641#define GEN11_DE_HPD_ISR _MMIO(0x44470)
2642#define GEN11_DE_HPD_IMR _MMIO(0x44474)
2643#define GEN11_DE_HPD_IIR _MMIO(0x44478)
2644#define GEN11_DE_HPD_IER _MMIO(0x4447c)
2645#define GEN11_TC_HOTPLUG(hpd_pin) REG_BIT(16 + _HPD_PIN_TC(hpd_pin))
2646#define GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC_HOTPLUG(HPD_PORT_TC6) | \
2647 GEN11_TC_HOTPLUG(HPD_PORT_TC5) | \
2648 GEN11_TC_HOTPLUG(HPD_PORT_TC4) | \
2649 GEN11_TC_HOTPLUG(HPD_PORT_TC3) | \
2650 GEN11_TC_HOTPLUG(HPD_PORT_TC2) | \
2651 GEN11_TC_HOTPLUG(HPD_PORT_TC1))
2652#define GEN11_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin))
2653#define GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT_HOTPLUG(HPD_PORT_TC6) | \
2654 GEN11_TBT_HOTPLUG(HPD_PORT_TC5) | \
2655 GEN11_TBT_HOTPLUG(HPD_PORT_TC4) | \
2656 GEN11_TBT_HOTPLUG(HPD_PORT_TC3) | \
2657 GEN11_TBT_HOTPLUG(HPD_PORT_TC2) | \
2658 GEN11_TBT_HOTPLUG(HPD_PORT_TC1))
2659
2660#define GEN11_DE_HPD_IRQ_REGS I915_IRQ_REGS(GEN11_DE_HPD_IMR, \
2661 GEN11_DE_HPD_IER, \
2662 GEN11_DE_HPD_IIR)
2663
2664#define GEN11_TBT_HOTPLUG_CTL _MMIO(0x44030)
2665#define GEN11_TC_HOTPLUG_CTL _MMIO(0x44038)
2666#define GEN11_HOTPLUG_CTL_ENABLE(hpd_pin) (8 << (_HPD_PIN_TC(hpd_pin) * 4))
2667#define GEN11_HOTPLUG_CTL_LONG_DETECT(hpd_pin) (2 << (_HPD_PIN_TC(hpd_pin) * 4))
2668#define GEN11_HOTPLUG_CTL_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4))
2669#define GEN11_HOTPLUG_CTL_NO_DETECT(hpd_pin) (0 << (_HPD_PIN_TC(hpd_pin) * 4))
2670
2671#define PICAINTERRUPT_ISR _MMIO(0x16FE50)
2672#define PICAINTERRUPT_IMR _MMIO(0x16FE54)
2673#define PICAINTERRUPT_IIR _MMIO(0x16FE58)
2674#define PICAINTERRUPT_IER _MMIO(0x16FE5C)
2675#define XELPDP_DP_ALT_HOTPLUG(hpd_pin) REG_BIT(16 + _HPD_PIN_TC(hpd_pin))
2676#define XELPDP_DP_ALT_HOTPLUG_MASK REG_GENMASK(19, 16)
2677#define XELPDP_AUX_TC(hpd_pin) REG_BIT(8 + _HPD_PIN_TC(hpd_pin))
2678#define XELPDP_AUX_TC_MASK REG_GENMASK(11, 8)
2679#define XE2LPD_AUX_DDI(hpd_pin) REG_BIT(6 + _HPD_PIN_DDI(hpd_pin))
2680#define XE2LPD_AUX_DDI_MASK REG_GENMASK(7, 6)
2681#define XELPDP_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin))
2682#define XELPDP_TBT_HOTPLUG_MASK REG_GENMASK(3, 0)
2683
2684#define PICAINTERRUPT_IRQ_REGS I915_IRQ_REGS(PICAINTERRUPT_IMR, \
2685 PICAINTERRUPT_IER, \
2686 PICAINTERRUPT_IIR)
2687
2688#define XELPDP_PORT_HOTPLUG_CTL(hpd_pin) _MMIO(0x16F270 + (_HPD_PIN_TC(hpd_pin) * 0x200))
2689#define XELPDP_TBT_HOTPLUG_ENABLE REG_BIT(6)
2690#define XELPDP_TBT_HPD_LONG_DETECT REG_BIT(5)
2691#define XELPDP_TBT_HPD_SHORT_DETECT REG_BIT(4)
2692#define XELPDP_DP_ALT_HOTPLUG_ENABLE REG_BIT(2)
2693#define XELPDP_DP_ALT_HPD_LONG_DETECT REG_BIT(1)
2694#define XELPDP_DP_ALT_HPD_SHORT_DETECT REG_BIT(0)
2695
2696#define XELPDP_INITIATE_PMDEMAND_REQUEST(dword) _MMIO(0x45230 + 4 * (dword))
2697#define XELPDP_PMDEMAND_QCLK_GV_BW_MASK REG_GENMASK(31, 16)
2698#define XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK REG_GENMASK(14, 12)
2699#define XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK REG_GENMASK(11, 8)
2700#define XE3_PMDEMAND_PIPES_MASK REG_GENMASK(7, 4)
2701#define XELPDP_PMDEMAND_PIPES_MASK REG_GENMASK(7, 6)
2702#define XELPDP_PMDEMAND_DBUFS_MASK REG_GENMASK(5, 4)
2703#define XELPDP_PMDEMAND_PHYS_MASK REG_GENMASK(2, 0)
2704
2705#define XELPDP_PMDEMAND_REQ_ENABLE REG_BIT(31)
2706#define XELPDP_PMDEMAND_CDCLK_FREQ_MASK REG_GENMASK(30, 20)
2707#define XELPDP_PMDEMAND_DDICLK_FREQ_MASK REG_GENMASK(18, 8)
2708#define XELPDP_PMDEMAND_SCALERS_MASK REG_GENMASK(6, 4)
2709#define XELPDP_PMDEMAND_PLLS_MASK REG_GENMASK(2, 0)
2710
2711#define GEN12_DCPR_STATUS_1 _MMIO(0x46440)
2712#define XELPDP_PMDEMAND_INFLIGHT_STATUS REG_BIT(26)
2713
2714#define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004)
2715/* Required on all Ironlake and Sandybridge according to the B-Spec. */
2716#define ILK_ELPIN_409_SELECT REG_BIT(25)
2717#define ILK_DPARB_GATE REG_BIT(22)
2718#define ILK_VSDPFD_FULL REG_BIT(21)
2719
2720#define FUSE_STRAP _MMIO(0x42014)
2721#define ILK_INTERNAL_GRAPHICS_DISABLE REG_BIT(31)
2722#define ILK_INTERNAL_DISPLAY_DISABLE REG_BIT(30)
2723#define ILK_DISPLAY_DEBUG_DISABLE REG_BIT(29)
2724#define IVB_PIPE_C_DISABLE REG_BIT(28)
2725#define ILK_HDCP_DISABLE REG_BIT(25)
2726#define ILK_eDP_A_DISABLE REG_BIT(24)
2727#define HSW_CDCLK_LIMIT REG_BIT(24)
2728#define ILK_DESKTOP REG_BIT(23)
2729#define HSW_CPU_SSC_ENABLE REG_BIT(21)
2730
2731#define FUSE_STRAP3 _MMIO(0x42020)
2732#define HSW_REF_CLK_SELECT REG_BIT(1)
2733
2734#define ILK_DSPCLK_GATE_D _MMIO(0x42020)
2735#define ILK_VRHUNIT_CLOCK_GATE_DISABLE REG_BIT(28)
2736#define ILK_DPFCUNIT_CLOCK_GATE_DISABLE REG_BIT(9)
2737#define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE REG_BIT(8)
2738#define ILK_DPFDUNIT_CLOCK_GATE_ENABLE REG_BIT(7)
2739#define ILK_DPARBUNIT_CLOCK_GATE_ENABLE REG_BIT(5)
2740
2741#define IVB_CHICKEN3 _MMIO(0x4200c)
2742#define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE REG_BIT(5)
2743#define CHICKEN3_DGMG_DONE_FIX_DISABLE REG_BIT(2)
2744
2745#define CHICKEN_PAR1_1 _MMIO(0x42080)
2746#define IGNORE_KVMR_PIPE_A REG_BIT(23)
2747#define KBL_ARB_FILL_SPARE_22 REG_BIT(22)
2748#define DIS_RAM_BYPASS_PSR2_MAN_TRACK REG_BIT(16)
2749#define SKL_DE_COMPRESSED_HASH_MODE REG_BIT(15)
2750#define HSW_MASK_VBL_TO_PIPE_IN_SRD REG_BIT(15) /* hsw/bdw */
2751#define FORCE_ARB_IDLE_PLANES REG_BIT(14)
2752#define SKL_EDP_PSR_FIX_RDWRAP REG_BIT(3)
2753#define IGNORE_PSR2_HW_TRACKING REG_BIT(1)
2754
2755#define CHICKEN_PAR2_1 _MMIO(0x42090)
2756#define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT REG_BIT(14)
2757
2758#define CHICKEN_MISC_2 _MMIO(0x42084)
2759#define CHICKEN_MISC_DISABLE_DPT REG_BIT(30) /* adl,dg2 */
2760#define BMG_DARB_HALF_BLK_END_BURST REG_BIT(27)
2761#define KBL_ARB_FILL_SPARE_14 REG_BIT(14)
2762#define KBL_ARB_FILL_SPARE_13 REG_BIT(13)
2763#define GLK_CL2_PWR_DOWN REG_BIT(12)
2764#define GLK_CL1_PWR_DOWN REG_BIT(11)
2765#define GLK_CL0_PWR_DOWN REG_BIT(10)
2766
2767#define CHICKEN_MISC_3 _MMIO(0x42088)
2768#define DP_MST_DPT_DPTP_ALIGN_WA(trans) REG_BIT(9 + (trans) - TRANSCODER_A)
2769#define DP_MST_SHORT_HBLANK_WA(trans) REG_BIT(5 + (trans) - TRANSCODER_A)
2770#define DP_MST_FEC_BS_JITTER_WA(trans) REG_BIT(0 + (trans) - TRANSCODER_A)
2771
2772#define CHICKEN_MISC_4 _MMIO(0x4208c)
2773#define CHICKEN_FBC_STRIDE_OVERRIDE REG_BIT(13)
2774#define CHICKEN_FBC_STRIDE_MASK REG_GENMASK(12, 0)
2775#define CHICKEN_FBC_STRIDE(x) REG_FIELD_PREP(CHICKEN_FBC_STRIDE_MASK, (x))
2776
2777#define _CHICKEN_PIPESL_1_A 0x420b0
2778#define _CHICKEN_PIPESL_1_B 0x420b4
2779#define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
2780#define HSW_PRI_STRETCH_MAX_MASK REG_GENMASK(28, 27)
2781#define HSW_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 0)
2782#define HSW_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 1)
2783#define HSW_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 2)
2784#define HSW_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 3)
2785#define HSW_SPR_STRETCH_MAX_MASK REG_GENMASK(26, 25)
2786#define HSW_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 0)
2787#define HSW_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 1)
2788#define HSW_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 2)
2789#define HSW_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 3)
2790#define HSW_FBCQ_DIS REG_BIT(22)
2791#define HSW_UNMASK_VBL_TO_REGS_IN_SRD REG_BIT(15) /* hsw */
2792#define SKL_PSR_MASK_PLANE_FLIP REG_BIT(11) /* skl+ */
2793#define SKL_PLANE1_STRETCH_MAX_MASK REG_GENMASK(1, 0)
2794#define SKL_PLANE1_STRETCH_MAX_X8 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 0)
2795#define SKL_PLANE1_STRETCH_MAX_X4 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 1)
2796#define SKL_PLANE1_STRETCH_MAX_X2 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 2)
2797#define SKL_PLANE1_STRETCH_MAX_X1 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 3)
2798#define BDW_UNMASK_VBL_TO_REGS_IN_SRD REG_BIT(0) /* bdw */
2799
2800#define _CHICKEN_TRANS_A 0x420c0
2801#define _CHICKEN_TRANS_B 0x420c4
2802#define _CHICKEN_TRANS_C 0x420c8
2803#define _CHICKEN_TRANS_EDP 0x420cc
2804#define _CHICKEN_TRANS_D 0x420d8
2805#define CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \
2806 [TRANSCODER_EDP] = _CHICKEN_TRANS_EDP, \
2807 [TRANSCODER_A] = _CHICKEN_TRANS_A, \
2808 [TRANSCODER_B] = _CHICKEN_TRANS_B, \
2809 [TRANSCODER_C] = _CHICKEN_TRANS_C, \
2810 [TRANSCODER_D] = _CHICKEN_TRANS_D))
2811#define _MTL_CHICKEN_TRANS_A 0x604e0
2812#define _MTL_CHICKEN_TRANS_B 0x614e0
2813#define MTL_CHICKEN_TRANS(trans) _MMIO_TRANS((trans), \
2814 _MTL_CHICKEN_TRANS_A, \
2815 _MTL_CHICKEN_TRANS_B)
2816#define PIPE_VBLANK_WITH_DELAY REG_BIT(31) /* tgl+ */
2817#define SKL_UNMASK_VBL_TO_PIPE_IN_SRD REG_BIT(30) /* skl+ */
2818#define HSW_FRAME_START_DELAY_MASK REG_GENMASK(28, 27)
2819#define HSW_FRAME_START_DELAY(x) REG_FIELD_PREP(HSW_FRAME_START_DELAY_MASK, x)
2820#define VSC_DATA_SEL_SOFTWARE_CONTROL REG_BIT(25) /* GLK */
2821#define FECSTALL_DIS_DPTSTREAM_DPTTG REG_BIT(23)
2822#define DDI_TRAINING_OVERRIDE_ENABLE REG_BIT(19)
2823#define ADLP_1_BASED_X_GRANULARITY REG_BIT(18)
2824#define DDI_TRAINING_OVERRIDE_VALUE REG_BIT(18)
2825#define DDIE_TRAINING_OVERRIDE_ENABLE REG_BIT(17) /* CHICKEN_TRANS_A only */
2826#define DDIE_TRAINING_OVERRIDE_VALUE REG_BIT(16) /* CHICKEN_TRANS_A only */
2827#define PSR2_ADD_VERTICAL_LINE_COUNT REG_BIT(15)
2828#define DP_FEC_BS_JITTER_WA REG_BIT(15)
2829#define PSR2_VSC_ENABLE_PROG_HEADER REG_BIT(12)
2830#define DP_DSC_INSERT_SF_AT_EOL_WA REG_BIT(4)
2831#define HDCP_LINE_REKEY_DISABLE REG_BIT(0)
2832
2833#define DISP_ARB_CTL _MMIO(0x45000)
2834#define DISP_FBC_MEMORY_WAKE REG_BIT(31)
2835#define DISP_TILE_SURFACE_SWIZZLING REG_BIT(13)
2836#define DISP_FBC_WM_DIS REG_BIT(15)
2837
2838#define DISP_ARB_CTL2 _MMIO(0x45004)
2839#define DISP_DATA_PARTITION_5_6 REG_BIT(6)
2840#define DISP_IPC_ENABLE REG_BIT(3)
2841
2842#define GEN7_MSG_CTL _MMIO(0x45010)
2843#define WAIT_FOR_PCH_RESET_ACK (1 << 1)
2844#define WAIT_FOR_PCH_FLR_ACK (1 << 0)
2845
2846#define _BW_BUDDY0_CTL 0x45130
2847#define _BW_BUDDY1_CTL 0x45140
2848#define BW_BUDDY_CTL(x) _MMIO(_PICK_EVEN(x, \
2849 _BW_BUDDY0_CTL, \
2850 _BW_BUDDY1_CTL))
2851#define BW_BUDDY_DISABLE REG_BIT(31)
2852#define BW_BUDDY_TLB_REQ_TIMER_MASK REG_GENMASK(21, 16)
2853#define BW_BUDDY_TLB_REQ_TIMER(x) REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, x)
2854
2855#define _BW_BUDDY0_PAGE_MASK 0x45134
2856#define _BW_BUDDY1_PAGE_MASK 0x45144
2857#define BW_BUDDY_PAGE_MASK(x) _MMIO(_PICK_EVEN(x, \
2858 _BW_BUDDY0_PAGE_MASK, \
2859 _BW_BUDDY1_PAGE_MASK))
2860
2861#define HSW_NDE_RSTWRN_OPT _MMIO(0x46408)
2862#define MTL_RESET_PICA_HANDSHAKE_EN REG_BIT(6)
2863#define RESET_PCH_HANDSHAKE_ENABLE REG_BIT(4)
2864
2865#define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430)
2866#define LATENCY_REPORTING_REMOVED_PIPE_D REG_BIT(31)
2867#define SKL_SELECT_ALTERNATE_DC_EXIT REG_BIT(30)
2868#define LATENCY_REPORTING_REMOVED_PIPE_C REG_BIT(25)
2869#define LATENCY_REPORTING_REMOVED_PIPE_B REG_BIT(24)
2870#define LATENCY_REPORTING_REMOVED_PIPE_A REG_BIT(23)
2871#define ICL_DELAY_PMRSP REG_BIT(22)
2872#define DISABLE_FLR_SRC REG_BIT(15)
2873#define MASK_WAKEMEM REG_BIT(13)
2874#define DDI_CLOCK_REG_ACCESS REG_BIT(7)
2875
2876#define GEN11_CHICKEN_DCPR_2 _MMIO(0x46434)
2877#define DCPR_MASK_MAXLATENCY_MEMUP_CLR REG_BIT(27)
2878#define DCPR_MASK_LPMODE REG_BIT(26)
2879#define DCPR_SEND_RESP_IMM REG_BIT(25)
2880#define DCPR_CLEAR_MEMSTAT_DIS REG_BIT(24)
2881
2882#define XELPD_CHICKEN_DCPR_3 _MMIO(0x46438)
2883#define DMD_RSP_TIMEOUT_DISABLE REG_BIT(19)
2884
2885#define SKL_DFSM _MMIO(0x51000)
2886#define SKL_DFSM_DISPLAY_PM_DISABLE (1 << 27)
2887#define SKL_DFSM_DISPLAY_HDCP_DISABLE (1 << 25)
2888#define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23)
2889#define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23)
2890#define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
2891#define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23)
2892#define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23)
2893#define ICL_DFSM_DMC_DISABLE (1 << 23)
2894#define SKL_DFSM_PIPE_A_DISABLE (1 << 30)
2895#define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
2896#define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
2897#define TGL_DFSM_PIPE_D_DISABLE (1 << 22)
2898#define GLK_DFSM_DISPLAY_DSC_DISABLE (1 << 7)
2899#define XE2LPD_DFSM_DBUF_OVERLAP_DISABLE (1 << 3)
2900
2901#define XE2LPD_DE_CAP _MMIO(0x41100)
2902#define XE2LPD_DE_CAP_3DLUT_MASK REG_GENMASK(31, 30)
2903#define XE2LPD_DE_CAP_DSC_MASK REG_GENMASK(29, 28)
2904#define XE2LPD_DE_CAP_DSC_REMOVED 1
2905#define XE2LPD_DE_CAP_SCALER_MASK REG_GENMASK(27, 26)
2906#define XE2LPD_DE_CAP_SCALER_SINGLE 1
2907
2908#define SKL_DSSM _MMIO(0x51004)
2909#define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29)
2910#define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29)
2911#define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29)
2912#define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29)
2913
2914#define GMD_ID_DISPLAY _MMIO(0x510a0)
2915#define GMD_ID_ARCH_MASK REG_GENMASK(31, 22)
2916#define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14)
2917#define GMD_ID_STEP REG_GENMASK(5, 0)
2918
2919/*GEN11 chicken */
2920#define _PIPEA_CHICKEN 0x70038
2921#define _PIPEB_CHICKEN 0x71038
2922#define _PIPEC_CHICKEN 0x72038
2923#define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\
2924 _PIPEB_CHICKEN)
2925#define UNDERRUN_RECOVERY_DISABLE_ADLP REG_BIT(30)
2926#define UNDERRUN_RECOVERY_ENABLE_DG2 REG_BIT(30)
2927#define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU REG_BIT(15)
2928#define DG2_RENDER_CCSTAG_4_3_EN REG_BIT(12)
2929#define PER_PIXEL_ALPHA_BYPASS_EN REG_BIT(7)
2930
2931/* PCH */
2932
2933#define PCH_DISPLAY_BASE 0xc0000u
2934
2935/* south display engine interrupt: IBX */
2936#define SDE_AUDIO_POWER_D (1 << 27)
2937#define SDE_AUDIO_POWER_C (1 << 26)
2938#define SDE_AUDIO_POWER_B (1 << 25)
2939#define SDE_AUDIO_POWER_SHIFT (25)
2940#define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT)
2941#define SDE_GMBUS (1 << 24)
2942#define SDE_AUDIO_HDCP_TRANSB (1 << 23)
2943#define SDE_AUDIO_HDCP_TRANSA (1 << 22)
2944#define SDE_AUDIO_HDCP_MASK (3 << 22)
2945#define SDE_AUDIO_TRANSB (1 << 21)
2946#define SDE_AUDIO_TRANSA (1 << 20)
2947#define SDE_AUDIO_TRANS_MASK (3 << 20)
2948#define SDE_POISON (1 << 19)
2949/* 18 reserved */
2950#define SDE_FDI_RXB (1 << 17)
2951#define SDE_FDI_RXA (1 << 16)
2952#define SDE_FDI_MASK (3 << 16)
2953#define SDE_AUXD (1 << 15)
2954#define SDE_AUXC (1 << 14)
2955#define SDE_AUXB (1 << 13)
2956#define SDE_AUX_MASK (7 << 13)
2957/* 12 reserved */
2958#define SDE_CRT_HOTPLUG (1 << 11)
2959#define SDE_PORTD_HOTPLUG (1 << 10)
2960#define SDE_PORTC_HOTPLUG (1 << 9)
2961#define SDE_PORTB_HOTPLUG (1 << 8)
2962#define SDE_SDVOB_HOTPLUG (1 << 6)
2963#define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \
2964 SDE_SDVOB_HOTPLUG | \
2965 SDE_PORTB_HOTPLUG | \
2966 SDE_PORTC_HOTPLUG | \
2967 SDE_PORTD_HOTPLUG)
2968#define SDE_TRANSB_CRC_DONE (1 << 5)
2969#define SDE_TRANSB_CRC_ERR (1 << 4)
2970#define SDE_TRANSB_FIFO_UNDER (1 << 3)
2971#define SDE_TRANSA_CRC_DONE (1 << 2)
2972#define SDE_TRANSA_CRC_ERR (1 << 1)
2973#define SDE_TRANSA_FIFO_UNDER (1 << 0)
2974#define SDE_TRANS_MASK (0x3f)
2975
2976/* south display engine interrupt: CPT - CNP */
2977#define SDE_AUDIO_POWER_D_CPT (1 << 31)
2978#define SDE_AUDIO_POWER_C_CPT (1 << 30)
2979#define SDE_AUDIO_POWER_B_CPT (1 << 29)
2980#define SDE_AUDIO_POWER_SHIFT_CPT 29
2981#define SDE_AUDIO_POWER_MASK_CPT (7 << 29)
2982#define SDE_AUXD_CPT (1 << 27)
2983#define SDE_AUXC_CPT (1 << 26)
2984#define SDE_AUXB_CPT (1 << 25)
2985#define SDE_AUX_MASK_CPT (7 << 25)
2986#define SDE_PORTE_HOTPLUG_SPT (1 << 25)
2987#define SDE_PORTA_HOTPLUG_SPT (1 << 24)
2988#define SDE_PORTD_HOTPLUG_CPT (1 << 23)
2989#define SDE_PORTC_HOTPLUG_CPT (1 << 22)
2990#define SDE_PORTB_HOTPLUG_CPT (1 << 21)
2991#define SDE_CRT_HOTPLUG_CPT (1 << 19)
2992#define SDE_SDVOB_HOTPLUG_CPT (1 << 18)
2993#define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \
2994 SDE_SDVOB_HOTPLUG_CPT | \
2995 SDE_PORTD_HOTPLUG_CPT | \
2996 SDE_PORTC_HOTPLUG_CPT | \
2997 SDE_PORTB_HOTPLUG_CPT)
2998#define SDE_HOTPLUG_MASK_SPT (SDE_PORTE_HOTPLUG_SPT | \
2999 SDE_PORTD_HOTPLUG_CPT | \
3000 SDE_PORTC_HOTPLUG_CPT | \
3001 SDE_PORTB_HOTPLUG_CPT | \
3002 SDE_PORTA_HOTPLUG_SPT)
3003#define SDE_GMBUS_CPT (1 << 17)
3004#define SDE_ERROR_CPT (1 << 16)
3005#define SDE_AUDIO_CP_REQ_C_CPT (1 << 10)
3006#define SDE_AUDIO_CP_CHG_C_CPT (1 << 9)
3007#define SDE_FDI_RXC_CPT (1 << 8)
3008#define SDE_AUDIO_CP_REQ_B_CPT (1 << 6)
3009#define SDE_AUDIO_CP_CHG_B_CPT (1 << 5)
3010#define SDE_FDI_RXB_CPT (1 << 4)
3011#define SDE_AUDIO_CP_REQ_A_CPT (1 << 2)
3012#define SDE_AUDIO_CP_CHG_A_CPT (1 << 1)
3013#define SDE_FDI_RXA_CPT (1 << 0)
3014#define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \
3015 SDE_AUDIO_CP_REQ_B_CPT | \
3016 SDE_AUDIO_CP_REQ_A_CPT)
3017#define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \
3018 SDE_AUDIO_CP_CHG_B_CPT | \
3019 SDE_AUDIO_CP_CHG_A_CPT)
3020#define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \
3021 SDE_FDI_RXB_CPT | \
3022 SDE_FDI_RXA_CPT)
3023
3024/* south display engine interrupt: ICP/TGP/MTP */
3025#define SDE_PICAINTERRUPT REG_BIT(31)
3026#define SDE_GMBUS_ICP (1 << 23)
3027#define SDE_TC_HOTPLUG_ICP(hpd_pin) REG_BIT(24 + _HPD_PIN_TC(hpd_pin))
3028#define SDE_TC_HOTPLUG_DG2(hpd_pin) REG_BIT(25 + _HPD_PIN_TC(hpd_pin)) /* sigh */
3029#define SDE_DDI_HOTPLUG_ICP(hpd_pin) REG_BIT(16 + _HPD_PIN_DDI(hpd_pin))
3030#define SDE_DDI_HOTPLUG_MASK_ICP (SDE_DDI_HOTPLUG_ICP(HPD_PORT_D) | \
3031 SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
3032 SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \
3033 SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))
3034#define SDE_TC_HOTPLUG_MASK_ICP (SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6) | \
3035 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5) | \
3036 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \
3037 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \
3038 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \
3039 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1))
3040
3041#define SDEISR _MMIO(0xc4000)
3042#define SDEIMR _MMIO(0xc4004)
3043#define SDEIIR _MMIO(0xc4008)
3044#define SDEIER _MMIO(0xc400c)
3045
3046#define SDE_IRQ_REGS I915_IRQ_REGS(SDEIMR, \
3047 SDEIER, \
3048 SDEIIR)
3049
3050#define SERR_INT _MMIO(0xc4040)
3051#define SERR_INT_POISON (1 << 31)
3052#define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3))
3053
3054/* digital port hotplug */
3055#define PCH_PORT_HOTPLUG _MMIO(0xc4030) /* SHOTPLUG_CTL */
3056#define PORTA_HOTPLUG_ENABLE (1 << 28) /* LPT:LP+ & BXT */
3057#define BXT_DDIA_HPD_INVERT (1 << 27)
3058#define PORTA_HOTPLUG_STATUS_MASK (3 << 24) /* SPT+ & BXT */
3059#define PORTA_HOTPLUG_NO_DETECT (0 << 24) /* SPT+ & BXT */
3060#define PORTA_HOTPLUG_SHORT_DETECT (1 << 24) /* SPT+ & BXT */
3061#define PORTA_HOTPLUG_LONG_DETECT (2 << 24) /* SPT+ & BXT */
3062#define PORTD_HOTPLUG_ENABLE (1 << 20)
3063#define PORTD_PULSE_DURATION_2ms (0 << 18) /* pre-LPT */
3064#define PORTD_PULSE_DURATION_4_5ms (1 << 18) /* pre-LPT */
3065#define PORTD_PULSE_DURATION_6ms (2 << 18) /* pre-LPT */
3066#define PORTD_PULSE_DURATION_100ms (3 << 18) /* pre-LPT */
3067#define PORTD_PULSE_DURATION_MASK (3 << 18) /* pre-LPT */
3068#define PORTD_HOTPLUG_STATUS_MASK (3 << 16)
3069#define PORTD_HOTPLUG_NO_DETECT (0 << 16)
3070#define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
3071#define PORTD_HOTPLUG_LONG_DETECT (2 << 16)
3072#define PORTC_HOTPLUG_ENABLE (1 << 12)
3073#define BXT_DDIC_HPD_INVERT (1 << 11)
3074#define PORTC_PULSE_DURATION_2ms (0 << 10) /* pre-LPT */
3075#define PORTC_PULSE_DURATION_4_5ms (1 << 10) /* pre-LPT */
3076#define PORTC_PULSE_DURATION_6ms (2 << 10) /* pre-LPT */
3077#define PORTC_PULSE_DURATION_100ms (3 << 10) /* pre-LPT */
3078#define PORTC_PULSE_DURATION_MASK (3 << 10) /* pre-LPT */
3079#define PORTC_HOTPLUG_STATUS_MASK (3 << 8)
3080#define PORTC_HOTPLUG_NO_DETECT (0 << 8)
3081#define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
3082#define PORTC_HOTPLUG_LONG_DETECT (2 << 8)
3083#define PORTB_HOTPLUG_ENABLE (1 << 4)
3084#define BXT_DDIB_HPD_INVERT (1 << 3)
3085#define PORTB_PULSE_DURATION_2ms (0 << 2) /* pre-LPT */
3086#define PORTB_PULSE_DURATION_4_5ms (1 << 2) /* pre-LPT */
3087#define PORTB_PULSE_DURATION_6ms (2 << 2) /* pre-LPT */
3088#define PORTB_PULSE_DURATION_100ms (3 << 2) /* pre-LPT */
3089#define PORTB_PULSE_DURATION_MASK (3 << 2) /* pre-LPT */
3090#define PORTB_HOTPLUG_STATUS_MASK (3 << 0)
3091#define PORTB_HOTPLUG_NO_DETECT (0 << 0)
3092#define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
3093#define PORTB_HOTPLUG_LONG_DETECT (2 << 0)
3094#define BXT_DDI_HPD_INVERT_MASK (BXT_DDIA_HPD_INVERT | \
3095 BXT_DDIB_HPD_INVERT | \
3096 BXT_DDIC_HPD_INVERT)
3097
3098#define PCH_PORT_HOTPLUG2 _MMIO(0xc403C) /* SHOTPLUG_CTL2 SPT+ */
3099#define PORTE_HOTPLUG_ENABLE (1 << 4)
3100#define PORTE_HOTPLUG_STATUS_MASK (3 << 0)
3101#define PORTE_HOTPLUG_NO_DETECT (0 << 0)
3102#define PORTE_HOTPLUG_SHORT_DETECT (1 << 0)
3103#define PORTE_HOTPLUG_LONG_DETECT (2 << 0)
3104
3105/* This register is a reuse of PCH_PORT_HOTPLUG register. The
3106 * functionality covered in PCH_PORT_HOTPLUG is split into
3107 * SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC.
3108 */
3109
3110#define SHOTPLUG_CTL_DDI _MMIO(0xc4030)
3111#define SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin) (0x8 << (_HPD_PIN_DDI(hpd_pin) * 4))
3112#define SHOTPLUG_CTL_DDI_HPD_OUTPUT_DATA(hpd_pin) (0x4 << (_HPD_PIN_DDI(hpd_pin) * 4))
3113#define SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4))
3114#define SHOTPLUG_CTL_DDI_HPD_NO_DETECT(hpd_pin) (0x0 << (_HPD_PIN_DDI(hpd_pin) * 4))
3115#define SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(hpd_pin) (0x1 << (_HPD_PIN_DDI(hpd_pin) * 4))
3116#define SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(hpd_pin) (0x2 << (_HPD_PIN_DDI(hpd_pin) * 4))
3117#define SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4))
3118
3119#define SHOTPLUG_CTL_TC _MMIO(0xc4034)
3120#define ICP_TC_HPD_ENABLE(hpd_pin) (8 << (_HPD_PIN_TC(hpd_pin) * 4))
3121#define ICP_TC_HPD_LONG_DETECT(hpd_pin) (2 << (_HPD_PIN_TC(hpd_pin) * 4))
3122#define ICP_TC_HPD_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4))
3123
3124#define SHPD_FILTER_CNT _MMIO(0xc4038)
3125#define SHPD_FILTER_CNT_500_ADJ 0x001D9
3126#define SHPD_FILTER_CNT_250 0x000F8
3127
3128#define _PCH_DPLL_A 0xc6014
3129#define _PCH_DPLL_B 0xc6018
3130#define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
3131
3132#define _PCH_FPA0 0xc6040
3133#define _PCH_FPB0 0xc6048
3134#define PCH_FP0(pll) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0)
3135#define FP_CB_TUNE (0x3 << 22)
3136
3137#define _PCH_FPA1 0xc6044
3138#define _PCH_FPB1 0xc604c
3139#define PCH_FP1(pll) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1)
3140
3141#define PCH_DPLL_TEST _MMIO(0xc606c)
3142
3143#define PCH_DREF_CONTROL _MMIO(0xC6200)
3144#define DREF_CONTROL_MASK 0x7fc3
3145#define DREF_CPU_SOURCE_OUTPUT_DISABLE (0 << 13)
3146#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2 << 13)
3147#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3 << 13)
3148#define DREF_CPU_SOURCE_OUTPUT_MASK (3 << 13)
3149#define DREF_SSC_SOURCE_DISABLE (0 << 11)
3150#define DREF_SSC_SOURCE_ENABLE (2 << 11)
3151#define DREF_SSC_SOURCE_MASK (3 << 11)
3152#define DREF_NONSPREAD_SOURCE_DISABLE (0 << 9)
3153#define DREF_NONSPREAD_CK505_ENABLE (1 << 9)
3154#define DREF_NONSPREAD_SOURCE_ENABLE (2 << 9)
3155#define DREF_NONSPREAD_SOURCE_MASK (3 << 9)
3156#define DREF_SUPERSPREAD_SOURCE_DISABLE (0 << 7)
3157#define DREF_SUPERSPREAD_SOURCE_ENABLE (2 << 7)
3158#define DREF_SUPERSPREAD_SOURCE_MASK (3 << 7)
3159#define DREF_SSC4_DOWNSPREAD (0 << 6)
3160#define DREF_SSC4_CENTERSPREAD (1 << 6)
3161#define DREF_SSC1_DISABLE (0 << 1)
3162#define DREF_SSC1_ENABLE (1 << 1)
3163#define DREF_SSC4_DISABLE (0)
3164#define DREF_SSC4_ENABLE (1)
3165
3166#define PCH_RAWCLK_FREQ _MMIO(0xc6204)
3167#define FDL_TP1_TIMER_SHIFT 12
3168#define FDL_TP1_TIMER_MASK (3 << 12)
3169#define FDL_TP2_TIMER_SHIFT 10
3170#define FDL_TP2_TIMER_MASK (3 << 10)
3171#define RAWCLK_FREQ_MASK 0x3ff
3172#define CNP_RAWCLK_DIV_MASK (0x3ff << 16)
3173#define CNP_RAWCLK_DIV(div) ((div) << 16)
3174#define CNP_RAWCLK_FRAC_MASK (0xf << 26)
3175#define CNP_RAWCLK_DEN(den) ((den) << 26)
3176#define ICP_RAWCLK_NUM(num) ((num) << 11)
3177
3178#define PCH_DPLL_TMR_CFG _MMIO(0xc6208)
3179
3180#define PCH_SSC4_PARMS _MMIO(0xc6210)
3181#define PCH_SSC4_AUX_PARMS _MMIO(0xc6214)
3182
3183#define PCH_DPLL_SEL _MMIO(0xc7000)
3184#define TRANS_DPLLB_SEL(pipe) (1 << ((pipe) * 4))
3185#define TRANS_DPLLA_SEL(pipe) 0
3186#define TRANS_DPLL_ENABLE(pipe) (1 << ((pipe) * 4 + 3))
3187
3188/* transcoder */
3189
3190#define _PCH_TRANS_HTOTAL_A 0xe0000
3191#define _PCH_TRANS_HTOTAL_B 0xe1000
3192#define PCH_TRANS_HTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
3193#define TRANS_HTOTAL_SHIFT 16
3194#define TRANS_HACTIVE_SHIFT 0
3195
3196#define _PCH_TRANS_HBLANK_A 0xe0004
3197#define _PCH_TRANS_HBLANK_B 0xe1004
3198#define PCH_TRANS_HBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
3199#define TRANS_HBLANK_END_SHIFT 16
3200#define TRANS_HBLANK_START_SHIFT 0
3201
3202#define _PCH_TRANS_HSYNC_A 0xe0008
3203#define _PCH_TRANS_HSYNC_B 0xe1008
3204#define PCH_TRANS_HSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
3205#define TRANS_HSYNC_END_SHIFT 16
3206#define TRANS_HSYNC_START_SHIFT 0
3207
3208#define _PCH_TRANS_VTOTAL_A 0xe000c
3209#define _PCH_TRANS_VTOTAL_B 0xe100c
3210#define PCH_TRANS_VTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
3211#define TRANS_VTOTAL_SHIFT 16
3212#define TRANS_VACTIVE_SHIFT 0
3213
3214#define _PCH_TRANS_VBLANK_A 0xe0010
3215#define _PCH_TRANS_VBLANK_B 0xe1010
3216#define PCH_TRANS_VBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
3217#define TRANS_VBLANK_END_SHIFT 16
3218#define TRANS_VBLANK_START_SHIFT 0
3219
3220#define _PCH_TRANS_VSYNC_A 0xe0014
3221#define _PCH_TRANS_VSYNC_B 0xe1014
3222#define PCH_TRANS_VSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
3223#define TRANS_VSYNC_END_SHIFT 16
3224#define TRANS_VSYNC_START_SHIFT 0
3225
3226#define _PCH_TRANS_VSYNCSHIFT_A 0xe0028
3227#define _PCH_TRANS_VSYNCSHIFT_B 0xe1028
3228#define PCH_TRANS_VSYNCSHIFT(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B)
3229
3230#define _PCH_TRANSA_DATA_M1 0xe0030
3231#define _PCH_TRANSB_DATA_M1 0xe1030
3232#define PCH_TRANS_DATA_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
3233
3234#define _PCH_TRANSA_DATA_N1 0xe0034
3235#define _PCH_TRANSB_DATA_N1 0xe1034
3236#define PCH_TRANS_DATA_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
3237
3238#define _PCH_TRANSA_DATA_M2 0xe0038
3239#define _PCH_TRANSB_DATA_M2 0xe1038
3240#define PCH_TRANS_DATA_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
3241
3242#define _PCH_TRANSA_DATA_N2 0xe003c
3243#define _PCH_TRANSB_DATA_N2 0xe103c
3244#define PCH_TRANS_DATA_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
3245
3246#define _PCH_TRANSA_LINK_M1 0xe0040
3247#define _PCH_TRANSB_LINK_M1 0xe1040
3248#define PCH_TRANS_LINK_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
3249
3250#define _PCH_TRANSA_LINK_N1 0xe0044
3251#define _PCH_TRANSB_LINK_N1 0xe1044
3252#define PCH_TRANS_LINK_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
3253
3254#define _PCH_TRANSA_LINK_M2 0xe0048
3255#define _PCH_TRANSB_LINK_M2 0xe1048
3256#define PCH_TRANS_LINK_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
3257
3258#define _PCH_TRANSA_LINK_N2 0xe004c
3259#define _PCH_TRANSB_LINK_N2 0xe104c
3260#define PCH_TRANS_LINK_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
3261
3262/* Per-transcoder DIP controls (PCH) */
3263#define _VIDEO_DIP_CTL_A 0xe0200
3264#define _VIDEO_DIP_CTL_B 0xe1200
3265#define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
3266
3267#define _VIDEO_DIP_DATA_A 0xe0208
3268#define _VIDEO_DIP_DATA_B 0xe1208
3269#define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
3270
3271#define _VIDEO_DIP_GCP_A 0xe0210
3272#define _VIDEO_DIP_GCP_B 0xe1210
3273#define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
3274#define GCP_COLOR_INDICATION (1 << 2)
3275#define GCP_DEFAULT_PHASE_ENABLE (1 << 1)
3276#define GCP_AV_MUTE (1 << 0)
3277
3278/* Per-transcoder DIP controls (VLV) */
3279#define _VLV_VIDEO_DIP_CTL_A 0x60200
3280#define _VLV_VIDEO_DIP_CTL_B 0x61170
3281#define _CHV_VIDEO_DIP_CTL_C 0x611f0
3282#define VLV_TVIDEO_DIP_CTL(pipe) _MMIO_BASE_PIPE3(VLV_DISPLAY_BASE, (pipe), \
3283 _VLV_VIDEO_DIP_CTL_A, \
3284 _VLV_VIDEO_DIP_CTL_B, \
3285 _CHV_VIDEO_DIP_CTL_C)
3286
3287#define _VLV_VIDEO_DIP_DATA_A 0x60208
3288#define _VLV_VIDEO_DIP_DATA_B 0x61174
3289#define _CHV_VIDEO_DIP_DATA_C 0x611f4
3290#define VLV_TVIDEO_DIP_DATA(pipe) _MMIO_BASE_PIPE3(VLV_DISPLAY_BASE, (pipe), \
3291 _VLV_VIDEO_DIP_DATA_A, \
3292 _VLV_VIDEO_DIP_DATA_B, \
3293 _CHV_VIDEO_DIP_DATA_C)
3294
3295#define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A 0x60210
3296#define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B 0x61178
3297#define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C 0x611f8
3298#define VLV_TVIDEO_DIP_GCP(pipe) _MMIO_BASE_PIPE3(VLV_DISPLAY_BASE, (pipe), \
3299 _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \
3300 _VLV_VIDEO_DIP_GDCP_PAYLOAD_B, \
3301 _CHV_VIDEO_DIP_GDCP_PAYLOAD_C)
3302
3303/* Haswell DIP controls */
3304#define _HSW_VIDEO_DIP_CTL_A 0x60200
3305#define _HSW_VIDEO_DIP_CTL_B 0x61200
3306#define HSW_TVIDEO_DIP_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_CTL_A)
3307
3308#define _HSW_VIDEO_DIP_AVI_DATA_A 0x60220
3309#define _HSW_VIDEO_DIP_AVI_DATA_B 0x61220
3310#define HSW_TVIDEO_DIP_AVI_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4)
3311
3312#define _HSW_VIDEO_DIP_VS_DATA_A 0x60260
3313#define _HSW_VIDEO_DIP_VS_DATA_B 0x61260
3314#define HSW_TVIDEO_DIP_VS_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4)
3315
3316#define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0
3317#define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0
3318#define HSW_TVIDEO_DIP_SPD_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4)
3319
3320#define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0
3321#define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0
3322#define HSW_TVIDEO_DIP_GMP_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4)
3323
3324#define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320
3325#define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320
3326#define HSW_TVIDEO_DIP_VSC_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4)
3327
3328/*ADLP and later: */
3329#define _ADL_VIDEO_DIP_AS_DATA_A 0x60484
3330#define _ADL_VIDEO_DIP_AS_DATA_B 0x61484
3331#define ADL_TVIDEO_DIP_AS_SDP_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans,\
3332 _ADL_VIDEO_DIP_AS_DATA_A + (i) * 4)
3333
3334#define _GLK_VIDEO_DIP_DRM_DATA_A 0x60440
3335#define _GLK_VIDEO_DIP_DRM_DATA_B 0x61440
3336#define GLK_TVIDEO_DIP_DRM_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4)
3337
3338#define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240
3339#define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240
3340#define _HSW_VIDEO_DIP_VS_ECC_A 0x60280
3341#define _HSW_VIDEO_DIP_VS_ECC_B 0x61280
3342#define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0
3343#define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0
3344#define _HSW_VIDEO_DIP_GMP_ECC_A 0x60300
3345#define _HSW_VIDEO_DIP_GMP_ECC_B 0x61300
3346#define _HSW_VIDEO_DIP_VSC_ECC_A 0x60344
3347#define _HSW_VIDEO_DIP_VSC_ECC_B 0x61344
3348
3349#define _HSW_VIDEO_DIP_GCP_A 0x60210
3350#define _HSW_VIDEO_DIP_GCP_B 0x61210
3351#define HSW_TVIDEO_DIP_GCP(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_GCP_A)
3352
3353/* Icelake PPS_DATA and _ECC DIP Registers.
3354 * These are available for transcoders B,C and eDP.
3355 * Adding the _A so as to reuse the _MMIO_TRANS2
3356 * definition, with which it offsets to the right location.
3357 */
3358
3359#define _ICL_VIDEO_DIP_PPS_DATA_A 0x60350
3360#define _ICL_VIDEO_DIP_PPS_DATA_B 0x61350
3361#define ICL_VIDEO_DIP_PPS_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4)
3362
3363#define _ICL_VIDEO_DIP_PPS_ECC_A 0x603D4
3364#define _ICL_VIDEO_DIP_PPS_ECC_B 0x613D4
3365#define ICL_VIDEO_DIP_PPS_ECC(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4)
3366
3367#define _HSW_STEREO_3D_CTL_A 0x70020
3368#define _HSW_STEREO_3D_CTL_B 0x71020
3369#define HSW_STEREO_3D_CTL(dev_priv, trans) _MMIO_PIPE2(dev_priv, trans, _HSW_STEREO_3D_CTL_A)
3370#define S3D_ENABLE (1 << 31)
3371
3372#define _PCH_TRANSACONF 0xf0008
3373#define _PCH_TRANSBCONF 0xf1008
3374#define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
3375#define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */
3376#define TRANS_ENABLE REG_BIT(31)
3377#define TRANS_STATE_ENABLE REG_BIT(30)
3378#define TRANS_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* ibx */
3379#define TRANS_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_FRAME_START_DELAY_MASK, (x)) /* ibx: 0-3 */
3380#define TRANS_INTERLACE_MASK REG_GENMASK(23, 21)
3381#define TRANS_INTERLACE_PROGRESSIVE REG_FIELD_PREP(TRANS_INTERLACE_MASK, 0)
3382#define TRANS_INTERLACE_LEGACY_VSYNC_IBX REG_FIELD_PREP(TRANS_INTERLACE_MASK, 2) /* ibx */
3383#define TRANS_INTERLACE_INTERLACED REG_FIELD_PREP(TRANS_INTERLACE_MASK, 3)
3384#define TRANS_BPC_MASK REG_GENMASK(7, 5) /* ibx */
3385#define TRANS_BPC_8 REG_FIELD_PREP(TRANS_BPC_MASK, 0)
3386#define TRANS_BPC_10 REG_FIELD_PREP(TRANS_BPC_MASK, 1)
3387#define TRANS_BPC_6 REG_FIELD_PREP(TRANS_BPC_MASK, 2)
3388#define TRANS_BPC_12 REG_FIELD_PREP(TRANS_BPC_MASK, 3)
3389
3390#define _TRANSA_CHICKEN1 0xf0060
3391#define _TRANSB_CHICKEN1 0xf1060
3392#define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
3393#define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE REG_BIT(10)
3394#define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE REG_BIT(4)
3395
3396#define _TRANSA_CHICKEN2 0xf0064
3397#define _TRANSB_CHICKEN2 0xf1064
3398#define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
3399#define TRANS_CHICKEN2_TIMING_OVERRIDE REG_BIT(31)
3400#define TRANS_CHICKEN2_FDI_POLARITY_REVERSED REG_BIT(29)
3401#define TRANS_CHICKEN2_FRAME_START_DELAY_MASK REG_GENMASK(28, 27)
3402#define TRANS_CHICKEN2_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_CHICKEN2_FRAME_START_DELAY_MASK, (x)) /* 0-3 */
3403#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER REG_BIT(26)
3404#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH REG_BIT(25)
3405
3406#define SOUTH_CHICKEN1 _MMIO(0xc2000)
3407#define FDIA_PHASE_SYNC_SHIFT_OVR 19
3408#define FDIA_PHASE_SYNC_SHIFT_EN 18
3409#define INVERT_DDIE_HPD REG_BIT(28)
3410#define INVERT_DDID_HPD_MTP REG_BIT(27)
3411#define INVERT_TC4_HPD REG_BIT(26)
3412#define INVERT_TC3_HPD REG_BIT(25)
3413#define INVERT_TC2_HPD REG_BIT(24)
3414#define INVERT_TC1_HPD REG_BIT(23)
3415#define INVERT_DDID_HPD (1 << 18)
3416#define INVERT_DDIC_HPD (1 << 17)
3417#define INVERT_DDIB_HPD (1 << 16)
3418#define INVERT_DDIA_HPD (1 << 15)
3419#define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
3420#define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
3421#define FDI_BC_BIFURCATION_SELECT (1 << 12)
3422#define CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8)
3423#define CHASSIS_CLK_REQ_DURATION(x) ((x) << 8)
3424#define SBCLK_RUN_REFCLK_DIS (1 << 7)
3425#define ICP_SECOND_PPS_IO_SELECT REG_BIT(2)
3426#define SPT_PWM_GRANULARITY (1 << 0)
3427#define SOUTH_CHICKEN2 _MMIO(0xc2004)
3428#define FDI_MPHY_IOSFSB_RESET_STATUS (1 << 13)
3429#define FDI_MPHY_IOSFSB_RESET_CTL (1 << 12)
3430#define LPT_PWM_GRANULARITY (1 << 5)
3431#define DPLS_EDP_PPS_FIX_DIS (1 << 0)
3432
3433#define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020)
3434#define PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31)
3435#define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30)
3436#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29)
3437#define PCH_DPMGUNIT_CLOCK_GATE_DISABLE (1 << 15)
3438#define PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14)
3439#define CNP_PWM_CGE_GATING_DISABLE (1 << 13)
3440#define PCH_LP_PARTITION_LEVEL_DISABLE (1 << 12)
3441
3442#define PCH_DP_B _MMIO(0xe4100)
3443#define PCH_DP_C _MMIO(0xe4200)
3444#define PCH_DP_D _MMIO(0xe4300)
3445
3446/* CPT */
3447#define _TRANS_DP_CTL_A 0xe0300
3448#define _TRANS_DP_CTL_B 0xe1300
3449#define _TRANS_DP_CTL_C 0xe2300
3450#define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B)
3451#define TRANS_DP_OUTPUT_ENABLE REG_BIT(31)
3452#define TRANS_DP_PORT_SEL_MASK REG_GENMASK(30, 29)
3453#define TRANS_DP_PORT_SEL_NONE REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, 3)
3454#define TRANS_DP_PORT_SEL(port) REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, (port) - PORT_B)
3455#define TRANS_DP_AUDIO_ONLY REG_BIT(26)
3456#define TRANS_DP_ENH_FRAMING REG_BIT(18)
3457#define TRANS_DP_BPC_MASK REG_GENMASK(10, 9)
3458#define TRANS_DP_BPC_8 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 0)
3459#define TRANS_DP_BPC_10 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 1)
3460#define TRANS_DP_BPC_6 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 2)
3461#define TRANS_DP_BPC_12 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 3)
3462#define TRANS_DP_VSYNC_ACTIVE_HIGH REG_BIT(4)
3463#define TRANS_DP_HSYNC_ACTIVE_HIGH REG_BIT(3)
3464
3465#define _TRANS_DP2_CTL_A 0x600a0
3466#define _TRANS_DP2_CTL_B 0x610a0
3467#define _TRANS_DP2_CTL_C 0x620a0
3468#define _TRANS_DP2_CTL_D 0x630a0
3469#define TRANS_DP2_CTL(trans) _MMIO_TRANS(trans, _TRANS_DP2_CTL_A, _TRANS_DP2_CTL_B)
3470#define TRANS_DP2_128B132B_CHANNEL_CODING REG_BIT(31)
3471#define TRANS_DP2_PANEL_REPLAY_ENABLE REG_BIT(30)
3472#define TRANS_DP2_DEBUG_ENABLE REG_BIT(23)
3473
3474#define _TRANS_DP2_VFREQHIGH_A 0x600a4
3475#define _TRANS_DP2_VFREQHIGH_B 0x610a4
3476#define _TRANS_DP2_VFREQHIGH_C 0x620a4
3477#define _TRANS_DP2_VFREQHIGH_D 0x630a4
3478#define TRANS_DP2_VFREQHIGH(trans) _MMIO_TRANS(trans, _TRANS_DP2_VFREQHIGH_A, _TRANS_DP2_VFREQHIGH_B)
3479#define TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK REG_GENMASK(31, 8)
3480#define TRANS_DP2_VFREQ_PIXEL_CLOCK(clk_hz) REG_FIELD_PREP(TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK, (clk_hz))
3481
3482#define _TRANS_DP2_VFREQLOW_A 0x600a8
3483#define _TRANS_DP2_VFREQLOW_B 0x610a8
3484#define _TRANS_DP2_VFREQLOW_C 0x620a8
3485#define _TRANS_DP2_VFREQLOW_D 0x630a8
3486#define TRANS_DP2_VFREQLOW(trans) _MMIO_TRANS(trans, _TRANS_DP2_VFREQLOW_A, _TRANS_DP2_VFREQLOW_B)
3487
3488/* SNB eDP training params */
3489/* SNB A-stepping */
3490#define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22)
3491#define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22)
3492#define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22)
3493#define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22)
3494/* SNB B-stepping */
3495#define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0 << 22)
3496#define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1 << 22)
3497#define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a << 22)
3498#define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39 << 22)
3499#define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38 << 22)
3500#define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f << 22)
3501
3502/* IVB */
3503#define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 << 22)
3504#define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a << 22)
3505#define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f << 22)
3506#define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 << 22)
3507#define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 << 22)
3508#define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 << 22)
3509#define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e << 22)
3510
3511/* legacy values */
3512#define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 << 22)
3513#define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 << 22)
3514#define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 << 22)
3515#define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 << 22)
3516#define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 << 22)
3517
3518#define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f << 22)
3519
3520#define VLV_PMWGICZ _MMIO(0x1300a4)
3521
3522#define HSW_EDRAM_CAP _MMIO(0x120010)
3523#define EDRAM_ENABLED 0x1
3524#define EDRAM_NUM_BANKS(cap) (((cap) >> 1) & 0xf)
3525#define EDRAM_WAYS_IDX(cap) (((cap) >> 5) & 0x7)
3526#define EDRAM_SETS_IDX(cap) (((cap) >> 8) & 0x3)
3527
3528#define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C)
3529#define PIXEL_OVERLAP_CNT_MASK (3 << 30)
3530#define PIXEL_OVERLAP_CNT_SHIFT 30
3531
3532#define GEN6_PCODE_MAILBOX _MMIO(0x138124)
3533#define GEN6_PCODE_READY (1 << 31)
3534#define GEN6_PCODE_MB_PARAM2 REG_GENMASK(23, 16)
3535#define GEN6_PCODE_MB_PARAM1 REG_GENMASK(15, 8)
3536#define GEN6_PCODE_MB_COMMAND REG_GENMASK(7, 0)
3537#define GEN6_PCODE_ERROR_MASK 0xFF
3538#define GEN6_PCODE_SUCCESS 0x0
3539#define GEN6_PCODE_ILLEGAL_CMD 0x1
3540#define GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2
3541#define GEN6_PCODE_TIMEOUT 0x3
3542#define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF
3543#define GEN7_PCODE_TIMEOUT 0x2
3544#define GEN7_PCODE_ILLEGAL_DATA 0x3
3545#define GEN11_PCODE_ILLEGAL_SUBCOMMAND 0x4
3546#define GEN11_PCODE_LOCKED 0x6
3547#define GEN11_PCODE_REJECTED 0x11
3548#define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
3549#define GEN6_PCODE_WRITE_RC6VIDS 0x4
3550#define GEN6_PCODE_READ_RC6VIDS 0x5
3551#define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
3552#define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245)
3553#define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18
3554#define GEN9_PCODE_READ_MEM_LATENCY 0x6
3555#define GEN9_MEM_LATENCY_LEVEL_3_7_MASK REG_GENMASK(31, 24)
3556#define GEN9_MEM_LATENCY_LEVEL_2_6_MASK REG_GENMASK(23, 16)
3557#define GEN9_MEM_LATENCY_LEVEL_1_5_MASK REG_GENMASK(15, 8)
3558#define GEN9_MEM_LATENCY_LEVEL_0_4_MASK REG_GENMASK(7, 0)
3559#define SKL_PCODE_LOAD_HDCP_KEYS 0x5
3560#define SKL_PCODE_CDCLK_CONTROL 0x7
3561#define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3
3562#define SKL_CDCLK_READY_FOR_CHANGE 0x1
3563#define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
3564#define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
3565#define GEN6_READ_OC_PARAMS 0xc
3566#define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd
3567#define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8)
3568#define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8))
3569#define ADL_PCODE_MEM_SS_READ_PSF_GV_INFO ((0) | (0x2 << 8))
3570#define DISPLAY_TO_PCODE_CDCLK_MAX 0x28D
3571#define DISPLAY_TO_PCODE_VOLTAGE_MASK REG_GENMASK(1, 0)
3572#define DISPLAY_TO_PCODE_VOLTAGE_MAX DISPLAY_TO_PCODE_VOLTAGE_MASK
3573#define DISPLAY_TO_PCODE_CDCLK_VALID REG_BIT(27)
3574#define DISPLAY_TO_PCODE_PIPE_COUNT_VALID REG_BIT(31)
3575#define DISPLAY_TO_PCODE_CDCLK_MASK REG_GENMASK(25, 16)
3576#define DISPLAY_TO_PCODE_PIPE_COUNT_MASK REG_GENMASK(30, 28)
3577#define DISPLAY_TO_PCODE_CDCLK(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_CDCLK_MASK, (x))
3578#define DISPLAY_TO_PCODE_PIPE_COUNT(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_PIPE_COUNT_MASK, (x))
3579#define DISPLAY_TO_PCODE_VOLTAGE(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_VOLTAGE_MASK, (x))
3580#define DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, num_pipes, voltage_level) \
3581 ((DISPLAY_TO_PCODE_CDCLK(cdclk)) | \
3582 (DISPLAY_TO_PCODE_PIPE_COUNT(num_pipes)) | \
3583 (DISPLAY_TO_PCODE_VOLTAGE(voltage_level)))
3584#define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe
3585#define ICL_PCODE_REP_QGV_MASK REG_GENMASK(1, 0)
3586#define ICL_PCODE_REP_QGV_SAFE REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 0)
3587#define ICL_PCODE_REP_QGV_POLL REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 1)
3588#define ICL_PCODE_REP_QGV_REJECTED REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 2)
3589#define ADLS_PCODE_REP_PSF_MASK REG_GENMASK(3, 2)
3590#define ADLS_PCODE_REP_PSF_SAFE REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 0)
3591#define ADLS_PCODE_REP_PSF_POLL REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 1)
3592#define ADLS_PCODE_REP_PSF_REJECTED REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 2)
3593#define ICL_PCODE_REQ_QGV_PT_MASK REG_GENMASK(7, 0)
3594#define ICL_PCODE_REQ_QGV_PT(x) REG_FIELD_PREP(ICL_PCODE_REQ_QGV_PT_MASK, (x))
3595#define ADLS_PCODE_REQ_PSF_PT_MASK REG_GENMASK(10, 8)
3596#define ADLS_PCODE_REQ_PSF_PT(x) REG_FIELD_PREP(ADLS_PCODE_REQ_PSF_PT_MASK, (x))
3597#define GEN6_PCODE_READ_D_COMP 0x10
3598#define GEN6_PCODE_WRITE_D_COMP 0x11
3599#define ICL_PCODE_EXIT_TCCOLD 0x12
3600#define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
3601#define DISPLAY_IPS_CONTROL 0x19
3602#define TGL_PCODE_TCCOLD 0x26
3603#define TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED REG_BIT(0)
3604#define TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ 0
3605#define TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ REG_BIT(0)
3606 /* See also IPS_CTL */
3607#define IPS_PCODE_CONTROL (1 << 30)
3608#define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
3609#define GEN9_PCODE_SAGV_CONTROL 0x21
3610#define GEN9_SAGV_DISABLE 0x0
3611#define GEN9_SAGV_IS_DISABLED 0x1
3612#define GEN9_SAGV_ENABLE 0x3
3613#define DG1_PCODE_STATUS 0x7E
3614#define DG1_UNCORE_GET_INIT_STATUS 0x0
3615#define DG1_UNCORE_INIT_STATUS_COMPLETE 0x1
3616#define PCODE_POWER_SETUP 0x7C
3617#define POWER_SETUP_SUBCOMMAND_READ_I1 0x4
3618#define POWER_SETUP_SUBCOMMAND_WRITE_I1 0x5
3619#define POWER_SETUP_I1_WATTS REG_BIT(31)
3620#define POWER_SETUP_I1_SHIFT 6 /* 10.6 fixed point format */
3621#define POWER_SETUP_I1_DATA_MASK REG_GENMASK(15, 0)
3622#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23
3623#define XEHP_PCODE_FREQUENCY_CONFIG 0x6e /* pvc */
3624/* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
3625#define PCODE_MBOX_FC_SC_READ_FUSED_P0 0x0
3626#define PCODE_MBOX_FC_SC_READ_FUSED_PN 0x1
3627/* PCODE_MBOX_DOMAIN_* - mailbox domain IDs */
3628/* XEHP_PCODE_FREQUENCY_CONFIG param2 */
3629#define PCODE_MBOX_DOMAIN_NONE 0x0
3630#define PCODE_MBOX_DOMAIN_MEDIAFF 0x3
3631#define GEN6_PCODE_DATA _MMIO(0x138128)
3632#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
3633#define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
3634#define GEN6_PCODE_DATA1 _MMIO(0x13812C)
3635
3636#define MTL_PCODE_STOLEN_ACCESS _MMIO(0x138914)
3637#define STOLEN_ACCESS_ALLOWED 0x1
3638
3639/* IVYBRIDGE DPF */
3640#define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
3641#define GEN7_L3CDERRST1_ROW_MASK (0x7ff << 14)
3642#define GEN7_PARITY_ERROR_VALID (1 << 13)
3643#define GEN7_L3CDERRST1_BANK_MASK (3 << 11)
3644#define GEN7_L3CDERRST1_SUBBANK_MASK (7 << 8)
3645#define GEN7_PARITY_ERROR_ROW(reg) \
3646 (((reg) & GEN7_L3CDERRST1_ROW_MASK) >> 14)
3647#define GEN7_PARITY_ERROR_BANK(reg) \
3648 (((reg) & GEN7_L3CDERRST1_BANK_MASK) >> 11)
3649#define GEN7_PARITY_ERROR_SUBBANK(reg) \
3650 (((reg) & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
3651#define GEN7_L3CDERRST1_ENABLE (1 << 7)
3652
3653/* These are the 4 32-bit write offset registers for each stream
3654 * output buffer. It determines the offset from the
3655 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
3656 */
3657#define GEN7_SO_WRITE_OFFSET(n) _MMIO(0x5280 + (n) * 4)
3658
3659/*
3660 * HSW - ICL power wells
3661 *
3662 * Platforms have up to 3 power well control register sets, each set
3663 * controlling up to 16 power wells via a request/status HW flag tuple:
3664 * - main (HSW_PWR_WELL_CTL[1-4])
3665 * - AUX (ICL_PWR_WELL_CTL_AUX[1-4])
3666 * - DDI (ICL_PWR_WELL_CTL_DDI[1-4])
3667 * Each control register set consists of up to 4 registers used by different
3668 * sources that can request a power well to be enabled:
3669 * - BIOS (HSW_PWR_WELL_CTL1/ICL_PWR_WELL_CTL_AUX1/ICL_PWR_WELL_CTL_DDI1)
3670 * - DRIVER (HSW_PWR_WELL_CTL2/ICL_PWR_WELL_CTL_AUX2/ICL_PWR_WELL_CTL_DDI2)
3671 * - KVMR (HSW_PWR_WELL_CTL3) (only in the main register set)
3672 * - DEBUG (HSW_PWR_WELL_CTL4/ICL_PWR_WELL_CTL_AUX4/ICL_PWR_WELL_CTL_DDI4)
3673 */
3674#define HSW_PWR_WELL_CTL1 _MMIO(0x45400)
3675#define HSW_PWR_WELL_CTL2 _MMIO(0x45404)
3676#define HSW_PWR_WELL_CTL3 _MMIO(0x45408)
3677#define HSW_PWR_WELL_CTL4 _MMIO(0x4540C)
3678#define HSW_PWR_WELL_CTL_REQ(pw_idx) (0x2 << ((pw_idx) * 2))
3679#define HSW_PWR_WELL_CTL_STATE(pw_idx) (0x1 << ((pw_idx) * 2))
3680
3681/* HSW/BDW power well */
3682#define HSW_PW_CTL_IDX_GLOBAL 15
3683
3684/* SKL/BXT/GLK power wells */
3685#define SKL_PW_CTL_IDX_PW_2 15
3686#define SKL_PW_CTL_IDX_PW_1 14
3687#define GLK_PW_CTL_IDX_AUX_C 10
3688#define GLK_PW_CTL_IDX_AUX_B 9
3689#define GLK_PW_CTL_IDX_AUX_A 8
3690#define SKL_PW_CTL_IDX_DDI_D 4
3691#define SKL_PW_CTL_IDX_DDI_C 3
3692#define SKL_PW_CTL_IDX_DDI_B 2
3693#define SKL_PW_CTL_IDX_DDI_A_E 1
3694#define GLK_PW_CTL_IDX_DDI_A 1
3695#define SKL_PW_CTL_IDX_MISC_IO 0
3696
3697/* ICL/TGL - power wells */
3698#define TGL_PW_CTL_IDX_PW_5 4
3699#define ICL_PW_CTL_IDX_PW_4 3
3700#define ICL_PW_CTL_IDX_PW_3 2
3701#define ICL_PW_CTL_IDX_PW_2 1
3702#define ICL_PW_CTL_IDX_PW_1 0
3703
3704/* XE_LPD - power wells */
3705#define XELPD_PW_CTL_IDX_PW_D 8
3706#define XELPD_PW_CTL_IDX_PW_C 7
3707#define XELPD_PW_CTL_IDX_PW_B 6
3708#define XELPD_PW_CTL_IDX_PW_A 5
3709
3710#define ICL_PWR_WELL_CTL_AUX1 _MMIO(0x45440)
3711#define ICL_PWR_WELL_CTL_AUX2 _MMIO(0x45444)
3712#define ICL_PWR_WELL_CTL_AUX4 _MMIO(0x4544C)
3713#define TGL_PW_CTL_IDX_AUX_TBT6 14
3714#define TGL_PW_CTL_IDX_AUX_TBT5 13
3715#define TGL_PW_CTL_IDX_AUX_TBT4 12
3716#define ICL_PW_CTL_IDX_AUX_TBT4 11
3717#define TGL_PW_CTL_IDX_AUX_TBT3 11
3718#define ICL_PW_CTL_IDX_AUX_TBT3 10
3719#define TGL_PW_CTL_IDX_AUX_TBT2 10
3720#define ICL_PW_CTL_IDX_AUX_TBT2 9
3721#define TGL_PW_CTL_IDX_AUX_TBT1 9
3722#define ICL_PW_CTL_IDX_AUX_TBT1 8
3723#define TGL_PW_CTL_IDX_AUX_TC6 8
3724#define XELPD_PW_CTL_IDX_AUX_E 8
3725#define TGL_PW_CTL_IDX_AUX_TC5 7
3726#define XELPD_PW_CTL_IDX_AUX_D 7
3727#define TGL_PW_CTL_IDX_AUX_TC4 6
3728#define ICL_PW_CTL_IDX_AUX_F 5
3729#define TGL_PW_CTL_IDX_AUX_TC3 5
3730#define ICL_PW_CTL_IDX_AUX_E 4
3731#define TGL_PW_CTL_IDX_AUX_TC2 4
3732#define ICL_PW_CTL_IDX_AUX_D 3
3733#define TGL_PW_CTL_IDX_AUX_TC1 3
3734#define ICL_PW_CTL_IDX_AUX_C 2
3735#define ICL_PW_CTL_IDX_AUX_B 1
3736#define ICL_PW_CTL_IDX_AUX_A 0
3737
3738#define ICL_PWR_WELL_CTL_DDI1 _MMIO(0x45450)
3739#define ICL_PWR_WELL_CTL_DDI2 _MMIO(0x45454)
3740#define ICL_PWR_WELL_CTL_DDI4 _MMIO(0x4545C)
3741#define XELPD_PW_CTL_IDX_DDI_E 8
3742#define TGL_PW_CTL_IDX_DDI_TC6 8
3743#define XELPD_PW_CTL_IDX_DDI_D 7
3744#define TGL_PW_CTL_IDX_DDI_TC5 7
3745#define TGL_PW_CTL_IDX_DDI_TC4 6
3746#define ICL_PW_CTL_IDX_DDI_F 5
3747#define TGL_PW_CTL_IDX_DDI_TC3 5
3748#define ICL_PW_CTL_IDX_DDI_E 4
3749#define TGL_PW_CTL_IDX_DDI_TC2 4
3750#define ICL_PW_CTL_IDX_DDI_D 3
3751#define TGL_PW_CTL_IDX_DDI_TC1 3
3752#define ICL_PW_CTL_IDX_DDI_C 2
3753#define ICL_PW_CTL_IDX_DDI_B 1
3754#define ICL_PW_CTL_IDX_DDI_A 0
3755
3756/* HSW - power well misc debug registers */
3757#define HSW_PWR_WELL_CTL5 _MMIO(0x45410)
3758#define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1 << 31)
3759#define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1 << 20)
3760#define HSW_PWR_WELL_FORCE_ON (1 << 19)
3761#define HSW_PWR_WELL_CTL6 _MMIO(0x45414)
3762
3763/* SKL Fuse Status */
3764enum skl_power_gate {
3765 SKL_PG0,
3766 SKL_PG1,
3767 SKL_PG2,
3768 ICL_PG3,
3769 ICL_PG4,
3770};
3771
3772#define SKL_FUSE_STATUS _MMIO(0x42000)
3773#define SKL_FUSE_DOWNLOAD_STATUS (1 << 31)
3774/*
3775 * PG0 is HW controlled, so doesn't have a corresponding power well control knob
3776 * SKL_DISP_PW1_IDX..SKL_DISP_PW2_IDX -> PG1..PG2
3777 */
3778#define SKL_PW_CTL_IDX_TO_PG(pw_idx) \
3779 ((pw_idx) - SKL_PW_CTL_IDX_PW_1 + SKL_PG1)
3780/*
3781 * PG0 is HW controlled, so doesn't have a corresponding power well control knob
3782 * ICL_DISP_PW1_IDX..ICL_DISP_PW4_IDX -> PG1..PG4
3783 */
3784#define ICL_PW_CTL_IDX_TO_PG(pw_idx) \
3785 ((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1)
3786#define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg)))
3787
3788/* Per-pipe DDI Function Control */
3789#define _TRANS_DDI_FUNC_CTL_A 0x60400
3790#define _TRANS_DDI_FUNC_CTL_B 0x61400
3791#define _TRANS_DDI_FUNC_CTL_C 0x62400
3792#define _TRANS_DDI_FUNC_CTL_D 0x63400
3793#define _TRANS_DDI_FUNC_CTL_EDP 0x6F400
3794#define _TRANS_DDI_FUNC_CTL_DSI0 0x6b400
3795#define _TRANS_DDI_FUNC_CTL_DSI1 0x6bc00
3796#define TRANS_DDI_FUNC_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _TRANS_DDI_FUNC_CTL_A)
3797
3798#define TRANS_DDI_FUNC_ENABLE (1 << 31)
3799/* Those bits are ignored by pipe EDP since it can only connect to DDI A */
3800#define TRANS_DDI_PORT_SHIFT 28
3801#define TGL_TRANS_DDI_PORT_SHIFT 27
3802#define TRANS_DDI_PORT_MASK (7 << TRANS_DDI_PORT_SHIFT)
3803#define TGL_TRANS_DDI_PORT_MASK (0xf << TGL_TRANS_DDI_PORT_SHIFT)
3804#define TRANS_DDI_SELECT_PORT(x) ((x) << TRANS_DDI_PORT_SHIFT)
3805#define TGL_TRANS_DDI_SELECT_PORT(x) (((x) + 1) << TGL_TRANS_DDI_PORT_SHIFT)
3806#define TRANS_DDI_MODE_SELECT_MASK (7 << 24)
3807#define TRANS_DDI_MODE_SELECT_HDMI (0 << 24)
3808#define TRANS_DDI_MODE_SELECT_DVI (1 << 24)
3809#define TRANS_DDI_MODE_SELECT_DP_SST (2 << 24)
3810#define TRANS_DDI_MODE_SELECT_DP_MST (3 << 24)
3811#define TRANS_DDI_MODE_SELECT_FDI_OR_128B132B (4 << 24)
3812#define TRANS_DDI_BPC_MASK (7 << 20)
3813#define TRANS_DDI_BPC_8 (0 << 20)
3814#define TRANS_DDI_BPC_10 (1 << 20)
3815#define TRANS_DDI_BPC_6 (2 << 20)
3816#define TRANS_DDI_BPC_12 (3 << 20)
3817#define TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK REG_GENMASK(19, 18)
3818#define TRANS_DDI_PORT_SYNC_MASTER_SELECT(x) REG_FIELD_PREP(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, (x))
3819#define TRANS_DDI_PVSYNC (1 << 17)
3820#define TRANS_DDI_PHSYNC (1 << 16)
3821#define TRANS_DDI_PORT_SYNC_ENABLE REG_BIT(15)
3822#define TRANS_DDI_EDP_INPUT_MASK (7 << 12)
3823#define TRANS_DDI_EDP_INPUT_A_ON (0 << 12)
3824#define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12)
3825#define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12)
3826#define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12)
3827#define TRANS_DDI_EDP_INPUT_D_ONOFF (7 << 12)
3828#define TRANS_DDI_HDCP_LINE_REKEY_DISABLE REG_BIT(12)
3829#define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(11, 10)
3830#define TRANS_DDI_MST_TRANSPORT_SELECT(trans) \
3831 REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, trans)
3832#define TRANS_DDI_HDCP_SIGNALLING (1 << 9)
3833#define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1 << 8)
3834#define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7)
3835#define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1 << 6)
3836#define TRANS_DDI_HDCP_SELECT REG_BIT(5)
3837#define TRANS_DDI_BFI_ENABLE (1 << 4)
3838#define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1 << 4)
3839#define TRANS_DDI_PORT_WIDTH_MASK REG_GENMASK(3, 1)
3840#define TRANS_DDI_PORT_WIDTH(width) REG_FIELD_PREP(TRANS_DDI_PORT_WIDTH_MASK, (width) - 1)
3841#define TRANS_DDI_HDMI_SCRAMBLING (1 << 0)
3842#define TRANS_DDI_HDMI_SCRAMBLING_MASK (TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE \
3843 | TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \
3844 | TRANS_DDI_HDMI_SCRAMBLING)
3845
3846#define _TRANS_DDI_FUNC_CTL2_A 0x60404
3847#define _TRANS_DDI_FUNC_CTL2_B 0x61404
3848#define _TRANS_DDI_FUNC_CTL2_C 0x62404
3849#define _TRANS_DDI_FUNC_CTL2_EDP 0x6f404
3850#define _TRANS_DDI_FUNC_CTL2_DSI0 0x6b404
3851#define _TRANS_DDI_FUNC_CTL2_DSI1 0x6bc04
3852#define TRANS_DDI_FUNC_CTL2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _TRANS_DDI_FUNC_CTL2_A)
3853#define PORT_SYNC_MODE_ENABLE REG_BIT(4)
3854#define PORT_SYNC_MODE_MASTER_SELECT_MASK REG_GENMASK(2, 0)
3855#define PORT_SYNC_MODE_MASTER_SELECT(x) REG_FIELD_PREP(PORT_SYNC_MODE_MASTER_SELECT_MASK, (x))
3856
3857#define TRANS_CMTG_CHICKEN _MMIO(0x6fa90)
3858#define DISABLE_DPT_CLK_GATING REG_BIT(1)
3859
3860/* DisplayPort Transport Control */
3861#define _DP_TP_CTL_A 0x64040
3862#define _DP_TP_CTL_B 0x64140
3863#define _TGL_DP_TP_CTL_A 0x60540
3864#define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
3865#define TGL_DP_TP_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, (tran), _TGL_DP_TP_CTL_A)
3866#define DP_TP_CTL_ENABLE (1 << 31)
3867#define DP_TP_CTL_FEC_ENABLE (1 << 30)
3868#define DP_TP_CTL_MODE_SST (0 << 27)
3869#define DP_TP_CTL_MODE_MST (1 << 27)
3870#define DP_TP_CTL_FORCE_ACT (1 << 25)
3871#define DP_TP_CTL_TRAIN_PAT4_SEL_MASK (3 << 19)
3872#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4A (0 << 19)
3873#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4B (1 << 19)
3874#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4C (2 << 19)
3875#define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18)
3876#define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15)
3877#define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8)
3878#define DP_TP_CTL_LINK_TRAIN_PAT1 (0 << 8)
3879#define DP_TP_CTL_LINK_TRAIN_PAT2 (1 << 8)
3880#define DP_TP_CTL_LINK_TRAIN_PAT3 (4 << 8)
3881#define DP_TP_CTL_LINK_TRAIN_PAT4 (5 << 8)
3882#define DP_TP_CTL_LINK_TRAIN_IDLE (2 << 8)
3883#define DP_TP_CTL_LINK_TRAIN_NORMAL (3 << 8)
3884#define DP_TP_CTL_SCRAMBLE_DISABLE (1 << 7)
3885
3886/* DisplayPort Transport Status */
3887#define _DP_TP_STATUS_A 0x64044
3888#define _DP_TP_STATUS_B 0x64144
3889#define _TGL_DP_TP_STATUS_A 0x60544
3890#define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)
3891#define TGL_DP_TP_STATUS(dev_priv, tran) _MMIO_TRANS2(dev_priv, (tran), _TGL_DP_TP_STATUS_A)
3892#define DP_TP_STATUS_FEC_ENABLE_LIVE (1 << 28)
3893#define DP_TP_STATUS_IDLE_DONE (1 << 25)
3894#define DP_TP_STATUS_ACT_SENT (1 << 24)
3895#define DP_TP_STATUS_MODE_STATUS_MST (1 << 23)
3896#define DP_TP_STATUS_AUTOTRAIN_DONE (1 << 12)
3897#define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8)
3898#define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4)
3899#define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0)
3900
3901/* DDI Buffer Control */
3902#define _DDI_BUF_CTL_A 0x64000
3903#define _DDI_BUF_CTL_B 0x64100
3904/* Known as DDI_CTL_DE in MTL+ */
3905#define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B)
3906#define DDI_BUF_CTL_ENABLE (1 << 31)
3907#define XE2LPD_DDI_BUF_D2D_LINK_ENABLE REG_BIT(29)
3908#define XE2LPD_DDI_BUF_D2D_LINK_STATE REG_BIT(28)
3909#define DDI_BUF_TRANS_SELECT(n) ((n) << 24)
3910#define DDI_BUF_EMP_MASK (0xf << 24)
3911#define DDI_BUF_PHY_LINK_RATE(r) ((r) << 20)
3912#define DDI_BUF_PORT_DATA_MASK REG_GENMASK(19, 18)
3913#define DDI_BUF_PORT_DATA_10BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 0)
3914#define DDI_BUF_PORT_DATA_20BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 1)
3915#define DDI_BUF_PORT_DATA_40BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 2)
3916#define DDI_BUF_PORT_REVERSAL (1 << 16)
3917#define DDI_BUF_IS_IDLE (1 << 7)
3918#define DDI_BUF_CTL_TC_PHY_OWNERSHIP REG_BIT(6)
3919#define DDI_A_4_LANES (1 << 4)
3920#define DDI_PORT_WIDTH(width) (((width) == 3 ? 4 : ((width) - 1)) << 1)
3921#define DDI_PORT_WIDTH_MASK (7 << 1)
3922#define DDI_PORT_WIDTH_SHIFT 1
3923#define DDI_INIT_DISPLAY_DETECTED (1 << 0)
3924
3925/* DDI Buffer Translations */
3926#define _DDI_BUF_TRANS_A 0x64E00
3927#define _DDI_BUF_TRANS_B 0x64E60
3928#define DDI_BUF_TRANS_LO(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8)
3929#define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31)
3930#define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
3931
3932/* DDI DP Compliance Control */
3933#define _DDI_DP_COMP_CTL_A 0x605F0
3934#define _DDI_DP_COMP_CTL_B 0x615F0
3935#define DDI_DP_COMP_CTL(pipe) _MMIO_PIPE(pipe, _DDI_DP_COMP_CTL_A, _DDI_DP_COMP_CTL_B)
3936#define DDI_DP_COMP_CTL_ENABLE (1 << 31)
3937#define DDI_DP_COMP_CTL_D10_2 (0 << 28)
3938#define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28)
3939#define DDI_DP_COMP_CTL_PRBS7 (2 << 28)
3940#define DDI_DP_COMP_CTL_CUSTOM80 (3 << 28)
3941#define DDI_DP_COMP_CTL_HBR2 (4 << 28)
3942#define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28)
3943#define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0)
3944
3945/* DDI DP Compliance Pattern */
3946#define _DDI_DP_COMP_PAT_A 0x605F4
3947#define _DDI_DP_COMP_PAT_B 0x615F4
3948#define DDI_DP_COMP_PAT(pipe, i) _MMIO(_PIPE(pipe, _DDI_DP_COMP_PAT_A, _DDI_DP_COMP_PAT_B) + (i) * 4)
3949
3950/* Sideband Interface (SBI) is programmed indirectly, via
3951 * SBI_ADDR, which contains the register offset; and SBI_DATA,
3952 * which contains the payload */
3953#define SBI_ADDR _MMIO(0xC6000)
3954#define SBI_DATA _MMIO(0xC6004)
3955#define SBI_CTL_STAT _MMIO(0xC6008)
3956#define SBI_CTL_DEST_ICLK (0x0 << 16)
3957#define SBI_CTL_DEST_MPHY (0x1 << 16)
3958#define SBI_CTL_OP_IORD (0x2 << 8)
3959#define SBI_CTL_OP_IOWR (0x3 << 8)
3960#define SBI_CTL_OP_CRRD (0x6 << 8)
3961#define SBI_CTL_OP_CRWR (0x7 << 8)
3962#define SBI_RESPONSE_FAIL (0x1 << 1)
3963#define SBI_RESPONSE_SUCCESS (0x0 << 1)
3964#define SBI_BUSY (0x1 << 0)
3965#define SBI_READY (0x0 << 0)
3966
3967/* SBI offsets */
3968#define SBI_SSCDIVINTPHASE 0x0200
3969#define SBI_SSCDIVINTPHASE6 0x0600
3970#define SBI_SSCDIVINTPHASE_DIVSEL_SHIFT 1
3971#define SBI_SSCDIVINTPHASE_DIVSEL_MASK (0x7f << 1)
3972#define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x) << 1)
3973#define SBI_SSCDIVINTPHASE_INCVAL_SHIFT 8
3974#define SBI_SSCDIVINTPHASE_INCVAL_MASK (0x7f << 8)
3975#define SBI_SSCDIVINTPHASE_INCVAL(x) ((x) << 8)
3976#define SBI_SSCDIVINTPHASE_DIR(x) ((x) << 15)
3977#define SBI_SSCDIVINTPHASE_PROPAGATE (1 << 0)
3978#define SBI_SSCDITHPHASE 0x0204
3979#define SBI_SSCCTL 0x020c
3980#define SBI_SSCCTL6 0x060C
3981#define SBI_SSCCTL_PATHALT (1 << 3)
3982#define SBI_SSCCTL_DISABLE (1 << 0)
3983#define SBI_SSCAUXDIV6 0x0610
3984#define SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT 4
3985#define SBI_SSCAUXDIV_FINALDIV2SEL_MASK (1 << 4)
3986#define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x) << 4)
3987#define SBI_DBUFF0 0x2a00
3988#define SBI_GEN0 0x1f00
3989#define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1 << 0)
3990
3991/* LPT PIXCLK_GATE */
3992#define PIXCLK_GATE _MMIO(0xC6020)
3993#define PIXCLK_GATE_UNGATE (1 << 0)
3994#define PIXCLK_GATE_GATE (0 << 0)
3995
3996/* SPLL */
3997#define SPLL_CTL _MMIO(0x46020)
3998#define SPLL_PLL_ENABLE (1 << 31)
3999#define SPLL_REF_BCLK (0 << 28)
4000#define SPLL_REF_MUXED_SSC (1 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */
4001#define SPLL_REF_NON_SSC_HSW (2 << 28)
4002#define SPLL_REF_PCH_SSC_BDW (2 << 28)
4003#define SPLL_REF_LCPLL (3 << 28)
4004#define SPLL_REF_MASK (3 << 28)
4005#define SPLL_FREQ_810MHz (0 << 26)
4006#define SPLL_FREQ_1350MHz (1 << 26)
4007#define SPLL_FREQ_2700MHz (2 << 26)
4008#define SPLL_FREQ_MASK (3 << 26)
4009
4010/* WRPLL */
4011#define _WRPLL_CTL1 0x46040
4012#define _WRPLL_CTL2 0x46060
4013#define WRPLL_CTL(pll) _MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2)
4014#define WRPLL_PLL_ENABLE (1 << 31)
4015#define WRPLL_REF_BCLK (0 << 28)
4016#define WRPLL_REF_PCH_SSC (1 << 28)
4017#define WRPLL_REF_MUXED_SSC_BDW (2 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */
4018#define WRPLL_REF_SPECIAL_HSW (2 << 28) /* muxed SSC (ULT), non-SSC (non-ULT) */
4019#define WRPLL_REF_LCPLL (3 << 28)
4020#define WRPLL_REF_MASK (3 << 28)
4021/* WRPLL divider programming */
4022#define WRPLL_DIVIDER_REFERENCE(x) ((x) << 0)
4023#define WRPLL_DIVIDER_REF_MASK (0xff)
4024#define WRPLL_DIVIDER_POST(x) ((x) << 8)
4025#define WRPLL_DIVIDER_POST_MASK (0x3f << 8)
4026#define WRPLL_DIVIDER_POST_SHIFT 8
4027#define WRPLL_DIVIDER_FEEDBACK(x) ((x) << 16)
4028#define WRPLL_DIVIDER_FB_SHIFT 16
4029#define WRPLL_DIVIDER_FB_MASK (0xff << 16)
4030
4031/* Port clock selection */
4032#define _PORT_CLK_SEL_A 0x46100
4033#define _PORT_CLK_SEL_B 0x46104
4034#define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B)
4035#define PORT_CLK_SEL_MASK REG_GENMASK(31, 29)
4036#define PORT_CLK_SEL_LCPLL_2700 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 0)
4037#define PORT_CLK_SEL_LCPLL_1350 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 1)
4038#define PORT_CLK_SEL_LCPLL_810 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 2)
4039#define PORT_CLK_SEL_SPLL REG_FIELD_PREP(PORT_CLK_SEL_MASK, 3)
4040#define PORT_CLK_SEL_WRPLL(pll) REG_FIELD_PREP(PORT_CLK_SEL_MASK, 4 + (pll))
4041#define PORT_CLK_SEL_WRPLL1 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 4)
4042#define PORT_CLK_SEL_WRPLL2 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 5)
4043#define PORT_CLK_SEL_NONE REG_FIELD_PREP(PORT_CLK_SEL_MASK, 7)
4044
4045/* On ICL+ this is the same as PORT_CLK_SEL, but all bits change. */
4046#define DDI_CLK_SEL(port) PORT_CLK_SEL(port)
4047#define DDI_CLK_SEL_MASK REG_GENMASK(31, 28)
4048#define DDI_CLK_SEL_NONE REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x0)
4049#define DDI_CLK_SEL_MG REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x8)
4050#define DDI_CLK_SEL_TBT_162 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xC)
4051#define DDI_CLK_SEL_TBT_270 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xD)
4052#define DDI_CLK_SEL_TBT_540 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xE)
4053#define DDI_CLK_SEL_TBT_810 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xF)
4054
4055/* Transcoder clock selection */
4056#define _TRANS_CLK_SEL_A 0x46140
4057#define _TRANS_CLK_SEL_B 0x46144
4058#define TRANS_CLK_SEL(tran) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B)
4059/* For each transcoder, we need to select the corresponding port clock */
4060#define TRANS_CLK_SEL_DISABLED (0x0 << 29)
4061#define TRANS_CLK_SEL_PORT(x) (((x) + 1) << 29)
4062#define TGL_TRANS_CLK_SEL_DISABLED (0x0 << 28)
4063#define TGL_TRANS_CLK_SEL_PORT(x) (((x) + 1) << 28)
4064
4065
4066#define CDCLK_FREQ _MMIO(0x46200)
4067
4068#define _TRANSA_MSA_MISC 0x60410
4069#define _TRANSB_MSA_MISC 0x61410
4070#define _TRANSC_MSA_MISC 0x62410
4071#define _TRANS_EDP_MSA_MISC 0x6f410
4072#define TRANS_MSA_MISC(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _TRANSA_MSA_MISC)
4073/* See DP_MSA_MISC_* for the bit definitions */
4074
4075#define _TRANS_A_SET_CONTEXT_LATENCY 0x6007C
4076#define _TRANS_B_SET_CONTEXT_LATENCY 0x6107C
4077#define _TRANS_C_SET_CONTEXT_LATENCY 0x6207C
4078#define _TRANS_D_SET_CONTEXT_LATENCY 0x6307C
4079#define TRANS_SET_CONTEXT_LATENCY(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _TRANS_A_SET_CONTEXT_LATENCY)
4080#define TRANS_SET_CONTEXT_LATENCY_MASK REG_GENMASK(15, 0)
4081#define TRANS_SET_CONTEXT_LATENCY_VALUE(x) REG_FIELD_PREP(TRANS_SET_CONTEXT_LATENCY_MASK, (x))
4082
4083/* LCPLL Control */
4084#define LCPLL_CTL _MMIO(0x130040)
4085#define LCPLL_PLL_DISABLE (1 << 31)
4086#define LCPLL_PLL_LOCK (1 << 30)
4087#define LCPLL_REF_NON_SSC (0 << 28)
4088#define LCPLL_REF_BCLK (2 << 28)
4089#define LCPLL_REF_PCH_SSC (3 << 28)
4090#define LCPLL_REF_MASK (3 << 28)
4091#define LCPLL_CLK_FREQ_MASK (3 << 26)
4092#define LCPLL_CLK_FREQ_450 (0 << 26)
4093#define LCPLL_CLK_FREQ_54O_BDW (1 << 26)
4094#define LCPLL_CLK_FREQ_337_5_BDW (2 << 26)
4095#define LCPLL_CLK_FREQ_675_BDW (3 << 26)
4096#define LCPLL_CD_CLOCK_DISABLE (1 << 25)
4097#define LCPLL_ROOT_CD_CLOCK_DISABLE (1 << 24)
4098#define LCPLL_CD2X_CLOCK_DISABLE (1 << 23)
4099#define LCPLL_POWER_DOWN_ALLOW (1 << 22)
4100#define LCPLL_CD_SOURCE_FCLK (1 << 21)
4101#define LCPLL_CD_SOURCE_FCLK_DONE (1 << 19)
4102
4103/*
4104 * SKL Clocks
4105 */
4106
4107/* CDCLK_CTL */
4108#define CDCLK_CTL _MMIO(0x46000)
4109#define CDCLK_FREQ_SEL_MASK REG_GENMASK(27, 26)
4110#define CDCLK_FREQ_450_432 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 0)
4111#define CDCLK_FREQ_540 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 1)
4112#define CDCLK_FREQ_337_308 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 2)
4113#define CDCLK_FREQ_675_617 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 3)
4114#define MDCLK_SOURCE_SEL_MASK REG_GENMASK(25, 25)
4115#define MDCLK_SOURCE_SEL_CD2XCLK REG_FIELD_PREP(MDCLK_SOURCE_SEL_MASK, 0)
4116#define MDCLK_SOURCE_SEL_CDCLK_PLL REG_FIELD_PREP(MDCLK_SOURCE_SEL_MASK, 1)
4117#define BXT_CDCLK_CD2X_DIV_SEL_MASK REG_GENMASK(23, 22)
4118#define BXT_CDCLK_CD2X_DIV_SEL_1 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 0)
4119#define BXT_CDCLK_CD2X_DIV_SEL_1_5 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 1)
4120#define BXT_CDCLK_CD2X_DIV_SEL_2 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 2)
4121#define BXT_CDCLK_CD2X_DIV_SEL_4 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 3)
4122#define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe) << 20)
4123#define CDCLK_DIVMUX_CD_OVERRIDE (1 << 19)
4124#define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3)
4125#define ICL_CDCLK_CD2X_PIPE(pipe) (_PICK(pipe, 0, 2, 6) << 19)
4126#define ICL_CDCLK_CD2X_PIPE_NONE (7 << 19)
4127#define TGL_CDCLK_CD2X_PIPE(pipe) BXT_CDCLK_CD2X_PIPE(pipe)
4128#define TGL_CDCLK_CD2X_PIPE_NONE ICL_CDCLK_CD2X_PIPE_NONE
4129#define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1 << 16)
4130#define CDCLK_FREQ_DECIMAL_MASK (0x7ff)
4131
4132/* CDCLK_SQUASH_CTL */
4133#define CDCLK_SQUASH_CTL _MMIO(0x46008)
4134#define CDCLK_SQUASH_ENABLE REG_BIT(31)
4135#define CDCLK_SQUASH_WINDOW_SIZE_MASK REG_GENMASK(27, 24)
4136#define CDCLK_SQUASH_WINDOW_SIZE(x) REG_FIELD_PREP(CDCLK_SQUASH_WINDOW_SIZE_MASK, (x))
4137#define CDCLK_SQUASH_WAVEFORM_MASK REG_GENMASK(15, 0)
4138#define CDCLK_SQUASH_WAVEFORM(x) REG_FIELD_PREP(CDCLK_SQUASH_WAVEFORM_MASK, (x))
4139
4140/* LCPLL_CTL */
4141#define LCPLL1_CTL _MMIO(0x46010)
4142#define LCPLL2_CTL _MMIO(0x46014)
4143#define LCPLL_PLL_ENABLE (1 << 31)
4144
4145/* DPLL control1 */
4146#define DPLL_CTRL1 _MMIO(0x6C058)
4147#define DPLL_CTRL1_HDMI_MODE(id) (1 << ((id) * 6 + 5))
4148#define DPLL_CTRL1_SSC(id) (1 << ((id) * 6 + 4))
4149#define DPLL_CTRL1_LINK_RATE_MASK(id) (7 << ((id) * 6 + 1))
4150#define DPLL_CTRL1_LINK_RATE_SHIFT(id) ((id) * 6 + 1)
4151#define DPLL_CTRL1_LINK_RATE(linkrate, id) ((linkrate) << ((id) * 6 + 1))
4152#define DPLL_CTRL1_OVERRIDE(id) (1 << ((id) * 6))
4153#define DPLL_CTRL1_LINK_RATE_2700 0
4154#define DPLL_CTRL1_LINK_RATE_1350 1
4155#define DPLL_CTRL1_LINK_RATE_810 2
4156#define DPLL_CTRL1_LINK_RATE_1620 3
4157#define DPLL_CTRL1_LINK_RATE_1080 4
4158#define DPLL_CTRL1_LINK_RATE_2160 5
4159
4160/* DPLL control2 */
4161#define DPLL_CTRL2 _MMIO(0x6C05C)
4162#define DPLL_CTRL2_DDI_CLK_OFF(port) (1 << ((port) + 15))
4163#define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3 << ((port) * 3 + 1))
4164#define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port) * 3 + 1)
4165#define DPLL_CTRL2_DDI_CLK_SEL(clk, port) ((clk) << ((port) * 3 + 1))
4166#define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1 << ((port) * 3))
4167
4168/* DPLL Status */
4169#define DPLL_STATUS _MMIO(0x6C060)
4170#define DPLL_LOCK(id) (1 << ((id) * 8))
4171
4172/* DPLL cfg */
4173#define _DPLL1_CFGCR1 0x6C040
4174#define _DPLL2_CFGCR1 0x6C048
4175#define _DPLL3_CFGCR1 0x6C050
4176#define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1)
4177#define DPLL_CFGCR1_FREQ_ENABLE (1 << 31)
4178#define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff << 9)
4179#define DPLL_CFGCR1_DCO_FRACTION(x) ((x) << 9)
4180#define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff)
4181
4182#define _DPLL1_CFGCR2 0x6C044
4183#define _DPLL2_CFGCR2 0x6C04C
4184#define _DPLL3_CFGCR2 0x6C054
4185#define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2)
4186#define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff << 8)
4187#define DPLL_CFGCR2_QDIV_RATIO(x) ((x) << 8)
4188#define DPLL_CFGCR2_QDIV_MODE(x) ((x) << 7)
4189#define DPLL_CFGCR2_KDIV_MASK (3 << 5)
4190#define DPLL_CFGCR2_KDIV(x) ((x) << 5)
4191#define DPLL_CFGCR2_KDIV_5 (0 << 5)
4192#define DPLL_CFGCR2_KDIV_2 (1 << 5)
4193#define DPLL_CFGCR2_KDIV_3 (2 << 5)
4194#define DPLL_CFGCR2_KDIV_1 (3 << 5)
4195#define DPLL_CFGCR2_PDIV_MASK (7 << 2)
4196#define DPLL_CFGCR2_PDIV(x) ((x) << 2)
4197#define DPLL_CFGCR2_PDIV_1 (0 << 2)
4198#define DPLL_CFGCR2_PDIV_2 (1 << 2)
4199#define DPLL_CFGCR2_PDIV_3 (2 << 2)
4200#define DPLL_CFGCR2_PDIV_7 (4 << 2)
4201#define DPLL_CFGCR2_PDIV_7_INVALID (5 << 2)
4202#define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3)
4203
4204/* ICL Clocks */
4205#define ICL_DPCLKA_CFGCR0 _MMIO(0x164280)
4206#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24, 4, 5))
4207#define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10)
4208#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < TC_PORT_4 ? \
4209 (tc_port) + 12 : \
4210 (tc_port) - TC_PORT_4 + 21))
4211#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2)
4212#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
4213#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
4214#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) _PICK(phy, 0, 2, 4, 27)
4215#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) \
4216 (3 << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
4217#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) \
4218 ((pll) << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
4219
4220/*
4221 * DG1 Clocks
4222 * First registers controls the first A and B, while the second register
4223 * controls the phy C and D. The bits on these registers are the
4224 * same, but refer to different phys
4225 */
4226#define _DG1_DPCLKA_CFGCR0 0x164280
4227#define _DG1_DPCLKA1_CFGCR0 0x16C280
4228#define _DG1_DPCLKA_PHY_IDX(phy) ((phy) % 2)
4229#define _DG1_DPCLKA_PLL_IDX(pll) ((pll) % 2)
4230#define DG1_DPCLKA_CFGCR0(phy) _MMIO_PHY((phy) / 2, \
4231 _DG1_DPCLKA_CFGCR0, \
4232 _DG1_DPCLKA1_CFGCR0)
4233#define DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT(_DG1_DPCLKA_PHY_IDX(phy) + 10)
4234#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) (_DG1_DPCLKA_PHY_IDX(phy) * 2)
4235#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) (_DG1_DPCLKA_PLL_IDX(pll) << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
4236#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (0x3 << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
4237
4238/* ADLS Clocks */
4239#define _ADLS_DPCLKA_CFGCR0 0x164280
4240#define _ADLS_DPCLKA_CFGCR1 0x1642BC
4241#define ADLS_DPCLKA_CFGCR(phy) _MMIO_PHY((phy) / 3, \
4242 _ADLS_DPCLKA_CFGCR0, \
4243 _ADLS_DPCLKA_CFGCR1)
4244#define ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy) (((phy) % 3) * 2)
4245/* ADLS DPCLKA_CFGCR0 DDI mask */
4246#define ADLS_DPCLKA_DDII_SEL_MASK REG_GENMASK(5, 4)
4247#define ADLS_DPCLKA_DDIB_SEL_MASK REG_GENMASK(3, 2)
4248#define ADLS_DPCLKA_DDIA_SEL_MASK REG_GENMASK(1, 0)
4249/* ADLS DPCLKA_CFGCR1 DDI mask */
4250#define ADLS_DPCLKA_DDIK_SEL_MASK REG_GENMASK(3, 2)
4251#define ADLS_DPCLKA_DDIJ_SEL_MASK REG_GENMASK(1, 0)
4252#define ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy) _PICK((phy), \
4253 ADLS_DPCLKA_DDIA_SEL_MASK, \
4254 ADLS_DPCLKA_DDIB_SEL_MASK, \
4255 ADLS_DPCLKA_DDII_SEL_MASK, \
4256 ADLS_DPCLKA_DDIJ_SEL_MASK, \
4257 ADLS_DPCLKA_DDIK_SEL_MASK)
4258
4259/* ICL PLL */
4260#define _DPLL0_ENABLE 0x46010
4261#define _DPLL1_ENABLE 0x46014
4262#define _ADLS_DPLL2_ENABLE 0x46018
4263#define _ADLS_DPLL3_ENABLE 0x46030
4264#define PLL_ENABLE REG_BIT(31)
4265#define PLL_LOCK REG_BIT(30)
4266#define PLL_POWER_ENABLE REG_BIT(27)
4267#define PLL_POWER_STATE REG_BIT(26)
4268#define ICL_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 3, \
4269 _DPLL0_ENABLE, _DPLL1_ENABLE, \
4270 _ADLS_DPLL3_ENABLE, _ADLS_DPLL3_ENABLE))
4271
4272#define _DG2_PLL3_ENABLE 0x4601C
4273
4274#define DG2_PLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 3, \
4275 _DPLL0_ENABLE, _DPLL1_ENABLE, \
4276 _DG2_PLL3_ENABLE, _DG2_PLL3_ENABLE))
4277
4278#define TBT_PLL_ENABLE _MMIO(0x46020)
4279
4280#define _MG_PLL1_ENABLE 0x46030
4281#define _MG_PLL2_ENABLE 0x46034
4282#define _MG_PLL3_ENABLE 0x46038
4283#define _MG_PLL4_ENABLE 0x4603C
4284/* Bits are the same as _DPLL0_ENABLE */
4285#define MG_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \
4286 _MG_PLL2_ENABLE)
4287
4288/* DG1 PLL */
4289#define DG1_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
4290 _DPLL0_ENABLE, _DPLL1_ENABLE, \
4291 _MG_PLL1_ENABLE, _MG_PLL2_ENABLE))
4292
4293/* ADL-P Type C PLL */
4294#define PORTTC1_PLL_ENABLE 0x46038
4295#define PORTTC2_PLL_ENABLE 0x46040
4296#define ADLP_PORTTC_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), \
4297 PORTTC1_PLL_ENABLE, \
4298 PORTTC2_PLL_ENABLE)
4299
4300#define _ICL_DPLL0_CFGCR0 0x164000
4301#define _ICL_DPLL1_CFGCR0 0x164080
4302#define ICL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR0, \
4303 _ICL_DPLL1_CFGCR0)
4304#define DPLL_CFGCR0_HDMI_MODE (1 << 30)
4305#define DPLL_CFGCR0_SSC_ENABLE (1 << 29)
4306#define DPLL_CFGCR0_SSC_ENABLE_ICL (1 << 25)
4307#define DPLL_CFGCR0_LINK_RATE_MASK (0xf << 25)
4308#define DPLL_CFGCR0_LINK_RATE_2700 (0 << 25)
4309#define DPLL_CFGCR0_LINK_RATE_1350 (1 << 25)
4310#define DPLL_CFGCR0_LINK_RATE_810 (2 << 25)
4311#define DPLL_CFGCR0_LINK_RATE_1620 (3 << 25)
4312#define DPLL_CFGCR0_LINK_RATE_1080 (4 << 25)
4313#define DPLL_CFGCR0_LINK_RATE_2160 (5 << 25)
4314#define DPLL_CFGCR0_LINK_RATE_3240 (6 << 25)
4315#define DPLL_CFGCR0_LINK_RATE_4050 (7 << 25)
4316#define DPLL_CFGCR0_DCO_FRACTION_MASK (0x7fff << 10)
4317#define DPLL_CFGCR0_DCO_FRACTION_SHIFT (10)
4318#define DPLL_CFGCR0_DCO_FRACTION(x) ((x) << 10)
4319#define DPLL_CFGCR0_DCO_INTEGER_MASK (0x3ff)
4320
4321#define _ICL_DPLL0_CFGCR1 0x164004
4322#define _ICL_DPLL1_CFGCR1 0x164084
4323#define ICL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \
4324 _ICL_DPLL1_CFGCR1)
4325#define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10)
4326#define DPLL_CFGCR1_QDIV_RATIO_SHIFT (10)
4327#define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10)
4328#define DPLL_CFGCR1_QDIV_MODE_SHIFT (9)
4329#define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9)
4330#define DPLL_CFGCR1_KDIV_MASK (7 << 6)
4331#define DPLL_CFGCR1_KDIV_SHIFT (6)
4332#define DPLL_CFGCR1_KDIV(x) ((x) << 6)
4333#define DPLL_CFGCR1_KDIV_1 (1 << 6)
4334#define DPLL_CFGCR1_KDIV_2 (2 << 6)
4335#define DPLL_CFGCR1_KDIV_3 (4 << 6)
4336#define DPLL_CFGCR1_PDIV_MASK (0xf << 2)
4337#define DPLL_CFGCR1_PDIV_SHIFT (2)
4338#define DPLL_CFGCR1_PDIV(x) ((x) << 2)
4339#define DPLL_CFGCR1_PDIV_2 (1 << 2)
4340#define DPLL_CFGCR1_PDIV_3 (2 << 2)
4341#define DPLL_CFGCR1_PDIV_5 (4 << 2)
4342#define DPLL_CFGCR1_PDIV_7 (8 << 2)
4343#define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0)
4344#define DPLL_CFGCR1_CENTRAL_FREQ_8400 (3 << 0)
4345#define TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL (0 << 0)
4346
4347#define _TGL_DPLL0_CFGCR0 0x164284
4348#define _TGL_DPLL1_CFGCR0 0x16428C
4349#define _TGL_TBTPLL_CFGCR0 0x16429C
4350#define TGL_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
4351 _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \
4352 _TGL_TBTPLL_CFGCR0, _TGL_TBTPLL_CFGCR0))
4353#define RKL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR0, \
4354 _TGL_DPLL1_CFGCR0)
4355
4356#define _TGL_DPLL0_DIV0 0x164B00
4357#define _TGL_DPLL1_DIV0 0x164C00
4358#define TGL_DPLL0_DIV0(pll) _MMIO_PLL(pll, _TGL_DPLL0_DIV0, _TGL_DPLL1_DIV0)
4359#define TGL_DPLL0_DIV0_AFC_STARTUP_MASK REG_GENMASK(27, 25)
4360#define TGL_DPLL0_DIV0_AFC_STARTUP(val) REG_FIELD_PREP(TGL_DPLL0_DIV0_AFC_STARTUP_MASK, (val))
4361
4362#define _TGL_DPLL0_CFGCR1 0x164288
4363#define _TGL_DPLL1_CFGCR1 0x164290
4364#define _TGL_TBTPLL_CFGCR1 0x1642A0
4365#define TGL_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
4366 _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \
4367 _TGL_TBTPLL_CFGCR1, _TGL_TBTPLL_CFGCR1))
4368#define RKL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \
4369 _TGL_DPLL1_CFGCR1)
4370
4371#define _DG1_DPLL2_CFGCR0 0x16C284
4372#define _DG1_DPLL3_CFGCR0 0x16C28C
4373#define DG1_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
4374 _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \
4375 _DG1_DPLL2_CFGCR0, _DG1_DPLL3_CFGCR0))
4376
4377#define _DG1_DPLL2_CFGCR1 0x16C288
4378#define _DG1_DPLL3_CFGCR1 0x16C290
4379#define DG1_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
4380 _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \
4381 _DG1_DPLL2_CFGCR1, _DG1_DPLL3_CFGCR1))
4382
4383/* For ADL-S DPLL4_CFGCR0/1 are used to control DPLL2 */
4384#define _ADLS_DPLL4_CFGCR0 0x164294
4385#define _ADLS_DPLL3_CFGCR0 0x1642C0
4386#define ADLS_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
4387 _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \
4388 _ADLS_DPLL4_CFGCR0, _ADLS_DPLL3_CFGCR0))
4389
4390#define _ADLS_DPLL4_CFGCR1 0x164298
4391#define _ADLS_DPLL3_CFGCR1 0x1642C4
4392#define ADLS_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
4393 _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \
4394 _ADLS_DPLL4_CFGCR1, _ADLS_DPLL3_CFGCR1))
4395
4396/* BXT display engine PLL */
4397#define BXT_DE_PLL_CTL _MMIO(0x6d000)
4398#define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */
4399#define BXT_DE_PLL_RATIO_MASK 0xff
4400
4401#define BXT_DE_PLL_ENABLE _MMIO(0x46070)
4402#define BXT_DE_PLL_PLL_ENABLE (1 << 31)
4403#define BXT_DE_PLL_LOCK (1 << 30)
4404#define BXT_DE_PLL_FREQ_REQ (1 << 23)
4405#define BXT_DE_PLL_FREQ_REQ_ACK (1 << 22)
4406#define ICL_CDCLK_PLL_RATIO(x) (x)
4407#define ICL_CDCLK_PLL_RATIO_MASK 0xff
4408
4409/* GEN9 DC */
4410#define DC_STATE_EN _MMIO(0x45504)
4411#define DC_STATE_DISABLE 0
4412#define DC_STATE_EN_DC3CO REG_BIT(30)
4413#define DC_STATE_DC3CO_STATUS REG_BIT(29)
4414#define HOLD_PHY_CLKREQ_PG1_LATCH REG_BIT(21)
4415#define HOLD_PHY_PG1_LATCH REG_BIT(20)
4416#define DC_STATE_EN_UPTO_DC5 (1 << 0)
4417#define DC_STATE_EN_DC9 (1 << 3)
4418#define DC_STATE_EN_UPTO_DC6 (2 << 0)
4419#define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3
4420
4421#define DC_STATE_DEBUG _MMIO(0x45520)
4422#define DC_STATE_DEBUG_MASK_CORES (1 << 0)
4423#define DC_STATE_DEBUG_MASK_MEMORY_UP (1 << 1)
4424
4425#define D_COMP_BDW _MMIO(0x138144)
4426
4427/* Pipe WM_LINETIME - watermark line time */
4428#define _WM_LINETIME_A 0x45270
4429#define _WM_LINETIME_B 0x45274
4430#define WM_LINETIME(pipe) _MMIO_PIPE(pipe, _WM_LINETIME_A, _WM_LINETIME_B)
4431#define HSW_LINETIME_MASK REG_GENMASK(8, 0)
4432#define HSW_LINETIME(x) REG_FIELD_PREP(HSW_LINETIME_MASK, (x))
4433#define HSW_IPS_LINETIME_MASK REG_GENMASK(24, 16)
4434#define HSW_IPS_LINETIME(x) REG_FIELD_PREP(HSW_IPS_LINETIME_MASK, (x))
4435
4436/* SFUSE_STRAP */
4437#define SFUSE_STRAP _MMIO(0xc2014)
4438#define SFUSE_STRAP_FUSE_LOCK (1 << 13)
4439#define SFUSE_STRAP_RAW_FREQUENCY (1 << 8)
4440#define SFUSE_STRAP_DISPLAY_DISABLED (1 << 7)
4441#define SFUSE_STRAP_CRT_DISABLED (1 << 6)
4442#define SFUSE_STRAP_DDIF_DETECTED (1 << 3)
4443#define SFUSE_STRAP_DDIB_DETECTED (1 << 2)
4444#define SFUSE_STRAP_DDIC_DETECTED (1 << 1)
4445#define SFUSE_STRAP_DDID_DETECTED (1 << 0)
4446
4447#define WM_MISC _MMIO(0x45260)
4448#define WM_MISC_DATA_PARTITION_5_6 (1 << 0)
4449
4450#define WM_DBG _MMIO(0x45280)
4451#define WM_DBG_DISALLOW_MULTIPLE_LP (1 << 0)
4452#define WM_DBG_DISALLOW_MAXFIFO (1 << 1)
4453#define WM_DBG_DISALLOW_SPRITE (1 << 2)
4454
4455/* Gen4+ Timestamp and Pipe Frame time stamp registers */
4456#define GEN4_TIMESTAMP _MMIO(0x2358)
4457#define ILK_TIMESTAMP_HI _MMIO(0x70070)
4458#define IVB_TIMESTAMP_CTR _MMIO(0x44070)
4459
4460#define GEN9_TIMESTAMP_OVERRIDE _MMIO(0x44074)
4461#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT 0
4462#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK 0x3ff
4463#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT 12
4464#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK (0xf << 12)
4465
4466/* g4x+, except vlv/chv! */
4467#define _PIPE_FRMTMSTMP_A 0x70048
4468#define _PIPE_FRMTMSTMP_B 0x71048
4469#define PIPE_FRMTMSTMP(pipe) \
4470 _MMIO_PIPE(pipe, _PIPE_FRMTMSTMP_A, _PIPE_FRMTMSTMP_B)
4471
4472/* g4x+, except vlv/chv! */
4473#define _PIPE_FLIPTMSTMP_A 0x7004C
4474#define _PIPE_FLIPTMSTMP_B 0x7104C
4475#define PIPE_FLIPTMSTMP(pipe) \
4476 _MMIO_PIPE(pipe, _PIPE_FLIPTMSTMP_A, _PIPE_FLIPTMSTMP_B)
4477
4478/* tgl+ */
4479#define _PIPE_FLIPDONETMSTMP_A 0x70054
4480#define _PIPE_FLIPDONETMSTMP_B 0x71054
4481#define PIPE_FLIPDONETIMSTMP(pipe) \
4482 _MMIO_PIPE(pipe, _PIPE_FLIPDONETMSTMP_A, _PIPE_FLIPDONETMSTMP_B)
4483
4484#define _VLV_PIPE_MSA_MISC_A 0x70048
4485#define VLV_PIPE_MSA_MISC(pipe) \
4486 _MMIO_PIPE2(dev_priv, pipe, _VLV_PIPE_MSA_MISC_A)
4487#define VLV_MSA_MISC1_HW_ENABLE REG_BIT(31)
4488#define VLV_MSA_MISC1_SW_S3D_MASK REG_GENMASK(2, 0) /* MSA MISC1 3:1 */
4489
4490#define GGC _MMIO(0x108040)
4491#define GMS_MASK REG_GENMASK(15, 8)
4492#define GGMS_MASK REG_GENMASK(7, 6)
4493
4494#define GEN6_GSMBASE _MMIO(0x108100)
4495#define GEN6_DSMBASE _MMIO(0x1080C0)
4496#define GEN6_BDSM_MASK REG_GENMASK64(31, 20)
4497#define GEN11_BDSM_MASK REG_GENMASK64(63, 20)
4498
4499#define XEHP_CLOCK_GATE_DIS _MMIO(0x101014)
4500#define SGSI_SIDECLK_DIS REG_BIT(17)
4501#define SGGI_DIS REG_BIT(15)
4502#define SGR_DIS REG_BIT(13)
4503
4504#define _ICL_PHY_MISC_A 0x64C00
4505#define _ICL_PHY_MISC_B 0x64C04
4506#define _DG2_PHY_MISC_TC1 0x64C14 /* TC1="PHY E" but offset as if "PHY F" */
4507#define ICL_PHY_MISC(port) _MMIO_PORT(port, _ICL_PHY_MISC_A, _ICL_PHY_MISC_B)
4508#define DG2_PHY_MISC(port) ((port) == PHY_E ? _MMIO(_DG2_PHY_MISC_TC1) : \
4509 ICL_PHY_MISC(port))
4510#define ICL_PHY_MISC_MUX_DDID (1 << 28)
4511#define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23)
4512#define DG2_PHY_DP_TX_ACK_MASK REG_GENMASK(23, 20)
4513
4514#define PORT_TX_DFLEXDPSP(fia) _MMIO_FIA((fia), 0x008A0)
4515#define MODULAR_FIA_MASK (1 << 4)
4516#define TC_LIVE_STATE_TBT(idx) (1 << ((idx) * 8 + 6))
4517#define TC_LIVE_STATE_TC(idx) (1 << ((idx) * 8 + 5))
4518#define DP_LANE_ASSIGNMENT_SHIFT(idx) ((idx) * 8)
4519#define DP_LANE_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 8))
4520#define DP_LANE_ASSIGNMENT(idx, x) ((x) << ((idx) * 8))
4521
4522#define PORT_TX_DFLEXDPPMS(fia) _MMIO_FIA((fia), 0x00890)
4523#define DP_PHY_MODE_STATUS_COMPLETED(idx) (1 << (idx))
4524
4525#define PORT_TX_DFLEXDPCSSS(fia) _MMIO_FIA((fia), 0x00894)
4526#define DP_PHY_MODE_STATUS_NOT_SAFE(idx) (1 << (idx))
4527
4528#define PORT_TX_DFLEXPA1(fia) _MMIO_FIA((fia), 0x00880)
4529#define DP_PIN_ASSIGNMENT_SHIFT(idx) ((idx) * 4)
4530#define DP_PIN_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 4))
4531#define DP_PIN_ASSIGNMENT(idx, x) ((x) << ((idx) * 4))
4532
4533#define _TCSS_DDI_STATUS_1 0x161500
4534#define _TCSS_DDI_STATUS_2 0x161504
4535#define TCSS_DDI_STATUS(tc) _MMIO(_PICK_EVEN(tc, \
4536 _TCSS_DDI_STATUS_1, \
4537 _TCSS_DDI_STATUS_2))
4538#define TCSS_DDI_STATUS_PIN_ASSIGNMENT_MASK REG_GENMASK(28, 25)
4539#define TCSS_DDI_STATUS_READY REG_BIT(2)
4540#define TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT REG_BIT(1)
4541#define TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT REG_BIT(0)
4542
4543#define PRIMARY_SPI_TRIGGER _MMIO(0x102040)
4544#define PRIMARY_SPI_ADDRESS _MMIO(0x102080)
4545#define PRIMARY_SPI_REGIONID _MMIO(0x102084)
4546#define SPI_STATIC_REGIONS _MMIO(0x102090)
4547#define OPTIONROM_SPI_REGIONID_MASK REG_GENMASK(7, 0)
4548#define OROM_OFFSET _MMIO(0x1020c0)
4549#define OROM_OFFSET_MASK REG_GENMASK(20, 16)
4550
4551#define CLKREQ_POLICY _MMIO(0x101038)
4552#define CLKREQ_POLICY_MEM_UP_OVRD REG_BIT(1)
4553
4554#define CLKGATE_DIS_MISC _MMIO(0x46534)
4555#define CLKGATE_DIS_MISC_DMASC_GATING_DIS REG_BIT(21)
4556
4557#define _MTL_CLKGATE_DIS_TRANS_A 0x604E8
4558#define _MTL_CLKGATE_DIS_TRANS_B 0x614E8
4559#define MTL_CLKGATE_DIS_TRANS(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _MTL_CLKGATE_DIS_TRANS_A)
4560#define MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS REG_BIT(7)
4561
4562#define MTL_MEM_SS_INFO_GLOBAL _MMIO(0x45700)
4563#define MTL_N_OF_ENABLED_QGV_POINTS_MASK REG_GENMASK(11, 8)
4564#define MTL_N_OF_POPULATED_CH_MASK REG_GENMASK(7, 4)
4565#define MTL_DDR_TYPE_MASK REG_GENMASK(3, 0)
4566
4567#define MTL_MEM_SS_INFO_QGV_POINT_OFFSET 0x45710
4568#define MTL_MEM_SS_INFO_QGV_POINT_LOW(point) _MMIO(MTL_MEM_SS_INFO_QGV_POINT_OFFSET + (point) * 8)
4569#define MTL_TRCD_MASK REG_GENMASK(31, 24)
4570#define MTL_TRP_MASK REG_GENMASK(23, 16)
4571#define MTL_DCLK_MASK REG_GENMASK(15, 0)
4572
4573#define MTL_MEM_SS_INFO_QGV_POINT_HIGH(point) _MMIO(MTL_MEM_SS_INFO_QGV_POINT_OFFSET + (point) * 8 + 4)
4574#define MTL_TRAS_MASK REG_GENMASK(16, 8)
4575#define MTL_TRDPRE_MASK REG_GENMASK(7, 0)
4576
4577#define MTL_MEDIA_GSI_BASE 0x380000
4578
4579#endif /* _I915_REG_H_ */