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1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27#include <linux/dmi.h>
28#include <linux/i2c.h>
29#include <linux/slab.h>
30
31#include <drm/drm_atomic_helper.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_edid.h>
34#include <drm/drm_probe_helper.h>
35
36#include "i915_drv.h"
37#include "i915_irq.h"
38#include "i915_reg.h"
39#include "intel_connector.h"
40#include "intel_crt.h"
41#include "intel_crtc.h"
42#include "intel_ddi.h"
43#include "intel_ddi_buf_trans.h"
44#include "intel_de.h"
45#include "intel_display_driver.h"
46#include "intel_display_types.h"
47#include "intel_fdi.h"
48#include "intel_fdi_regs.h"
49#include "intel_fifo_underrun.h"
50#include "intel_gmbus.h"
51#include "intel_hotplug.h"
52#include "intel_hotplug_irq.h"
53#include "intel_load_detect.h"
54#include "intel_pch_display.h"
55#include "intel_pch_refclk.h"
56
57/* Here's the desired hotplug mode */
58#define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \
59 ADPA_CRT_HOTPLUG_WARMUP_10MS | \
60 ADPA_CRT_HOTPLUG_SAMPLE_4S | \
61 ADPA_CRT_HOTPLUG_VOLTAGE_50 | \
62 ADPA_CRT_HOTPLUG_VOLREF_325MV | \
63 ADPA_CRT_HOTPLUG_ENABLE)
64
65struct intel_crt {
66 struct intel_encoder base;
67 /* DPMS state is stored in the connector, which we need in the
68 * encoder's enable/disable callbacks */
69 struct intel_connector *connector;
70 bool force_hotplug_required;
71 i915_reg_t adpa_reg;
72};
73
74static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder)
75{
76 return container_of(encoder, struct intel_crt, base);
77}
78
79static struct intel_crt *intel_attached_crt(struct intel_connector *connector)
80{
81 return intel_encoder_to_crt(intel_attached_encoder(connector));
82}
83
84bool intel_crt_port_enabled(struct intel_display *display,
85 i915_reg_t adpa_reg, enum pipe *pipe)
86{
87 struct drm_i915_private *dev_priv = to_i915(display->drm);
88 u32 val;
89
90 val = intel_de_read(display, adpa_reg);
91
92 /* asserts want to know the pipe even if the port is disabled */
93 if (HAS_PCH_CPT(dev_priv))
94 *pipe = (val & ADPA_PIPE_SEL_MASK_CPT) >> ADPA_PIPE_SEL_SHIFT_CPT;
95 else
96 *pipe = (val & ADPA_PIPE_SEL_MASK) >> ADPA_PIPE_SEL_SHIFT;
97
98 return val & ADPA_DAC_ENABLE;
99}
100
101static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
102 enum pipe *pipe)
103{
104 struct intel_display *display = to_intel_display(encoder);
105 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
106 struct intel_crt *crt = intel_encoder_to_crt(encoder);
107 intel_wakeref_t wakeref;
108 bool ret;
109
110 wakeref = intel_display_power_get_if_enabled(dev_priv,
111 encoder->power_domain);
112 if (!wakeref)
113 return false;
114
115 ret = intel_crt_port_enabled(display, crt->adpa_reg, pipe);
116
117 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
118
119 return ret;
120}
121
122static unsigned int intel_crt_get_flags(struct intel_encoder *encoder)
123{
124 struct intel_display *display = to_intel_display(encoder);
125 struct intel_crt *crt = intel_encoder_to_crt(encoder);
126 u32 tmp, flags = 0;
127
128 tmp = intel_de_read(display, crt->adpa_reg);
129
130 if (tmp & ADPA_HSYNC_ACTIVE_HIGH)
131 flags |= DRM_MODE_FLAG_PHSYNC;
132 else
133 flags |= DRM_MODE_FLAG_NHSYNC;
134
135 if (tmp & ADPA_VSYNC_ACTIVE_HIGH)
136 flags |= DRM_MODE_FLAG_PVSYNC;
137 else
138 flags |= DRM_MODE_FLAG_NVSYNC;
139
140 return flags;
141}
142
143static void intel_crt_get_config(struct intel_encoder *encoder,
144 struct intel_crtc_state *pipe_config)
145{
146 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
147
148 pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder);
149
150 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock;
151}
152
153static void hsw_crt_get_config(struct intel_encoder *encoder,
154 struct intel_crtc_state *pipe_config)
155{
156 lpt_pch_get_config(pipe_config);
157
158 hsw_ddi_get_config(encoder, pipe_config);
159
160 pipe_config->hw.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
161 DRM_MODE_FLAG_NHSYNC |
162 DRM_MODE_FLAG_PVSYNC |
163 DRM_MODE_FLAG_NVSYNC);
164 pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder);
165}
166
167/* Note: The caller is required to filter out dpms modes not supported by the
168 * platform. */
169static void intel_crt_set_dpms(struct intel_encoder *encoder,
170 const struct intel_crtc_state *crtc_state,
171 int mode)
172{
173 struct intel_display *display = to_intel_display(encoder);
174 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
175 struct intel_crt *crt = intel_encoder_to_crt(encoder);
176 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
177 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
178 u32 adpa;
179
180 if (DISPLAY_VER(display) >= 5)
181 adpa = ADPA_HOTPLUG_BITS;
182 else
183 adpa = 0;
184
185 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
186 adpa |= ADPA_HSYNC_ACTIVE_HIGH;
187 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
188 adpa |= ADPA_VSYNC_ACTIVE_HIGH;
189
190 /* For CPT allow 3 pipe config, for others just use A or B */
191 if (HAS_PCH_LPT(dev_priv))
192 ; /* Those bits don't exist here */
193 else if (HAS_PCH_CPT(dev_priv))
194 adpa |= ADPA_PIPE_SEL_CPT(crtc->pipe);
195 else
196 adpa |= ADPA_PIPE_SEL(crtc->pipe);
197
198 if (!HAS_PCH_SPLIT(dev_priv))
199 intel_de_write(display, BCLRPAT(display, crtc->pipe), 0);
200
201 switch (mode) {
202 case DRM_MODE_DPMS_ON:
203 adpa |= ADPA_DAC_ENABLE;
204 break;
205 case DRM_MODE_DPMS_STANDBY:
206 adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
207 break;
208 case DRM_MODE_DPMS_SUSPEND:
209 adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
210 break;
211 case DRM_MODE_DPMS_OFF:
212 adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
213 break;
214 }
215
216 intel_de_write(display, crt->adpa_reg, adpa);
217}
218
219static void intel_disable_crt(struct intel_atomic_state *state,
220 struct intel_encoder *encoder,
221 const struct intel_crtc_state *old_crtc_state,
222 const struct drm_connector_state *old_conn_state)
223{
224 intel_crt_set_dpms(encoder, old_crtc_state, DRM_MODE_DPMS_OFF);
225}
226
227static void pch_disable_crt(struct intel_atomic_state *state,
228 struct intel_encoder *encoder,
229 const struct intel_crtc_state *old_crtc_state,
230 const struct drm_connector_state *old_conn_state)
231{
232}
233
234static void pch_post_disable_crt(struct intel_atomic_state *state,
235 struct intel_encoder *encoder,
236 const struct intel_crtc_state *old_crtc_state,
237 const struct drm_connector_state *old_conn_state)
238{
239 intel_disable_crt(state, encoder, old_crtc_state, old_conn_state);
240}
241
242static void hsw_disable_crt(struct intel_atomic_state *state,
243 struct intel_encoder *encoder,
244 const struct intel_crtc_state *old_crtc_state,
245 const struct drm_connector_state *old_conn_state)
246{
247 struct intel_display *display = to_intel_display(encoder);
248 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
249
250 drm_WARN_ON(display->drm, !old_crtc_state->has_pch_encoder);
251
252 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
253}
254
255static void hsw_post_disable_crt(struct intel_atomic_state *state,
256 struct intel_encoder *encoder,
257 const struct intel_crtc_state *old_crtc_state,
258 const struct drm_connector_state *old_conn_state)
259{
260 struct intel_display *display = to_intel_display(encoder);
261 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
262 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
263
264 intel_crtc_vblank_off(old_crtc_state);
265
266 intel_disable_transcoder(old_crtc_state);
267
268 intel_ddi_disable_transcoder_func(old_crtc_state);
269
270 ilk_pfit_disable(old_crtc_state);
271
272 intel_ddi_disable_transcoder_clock(old_crtc_state);
273
274 pch_post_disable_crt(state, encoder, old_crtc_state, old_conn_state);
275
276 lpt_pch_disable(state, crtc);
277
278 hsw_fdi_disable(encoder);
279
280 drm_WARN_ON(display->drm, !old_crtc_state->has_pch_encoder);
281
282 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
283}
284
285static void hsw_pre_pll_enable_crt(struct intel_atomic_state *state,
286 struct intel_encoder *encoder,
287 const struct intel_crtc_state *crtc_state,
288 const struct drm_connector_state *conn_state)
289{
290 struct intel_display *display = to_intel_display(encoder);
291 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
292
293 drm_WARN_ON(display->drm, !crtc_state->has_pch_encoder);
294
295 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
296}
297
298static void hsw_pre_enable_crt(struct intel_atomic_state *state,
299 struct intel_encoder *encoder,
300 const struct intel_crtc_state *crtc_state,
301 const struct drm_connector_state *conn_state)
302{
303 struct intel_display *display = to_intel_display(encoder);
304 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
305 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
306 enum pipe pipe = crtc->pipe;
307
308 drm_WARN_ON(display->drm, !crtc_state->has_pch_encoder);
309
310 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
311
312 hsw_fdi_link_train(encoder, crtc_state);
313
314 intel_ddi_enable_transcoder_clock(encoder, crtc_state);
315}
316
317static void hsw_enable_crt(struct intel_atomic_state *state,
318 struct intel_encoder *encoder,
319 const struct intel_crtc_state *crtc_state,
320 const struct drm_connector_state *conn_state)
321{
322 struct intel_display *display = to_intel_display(encoder);
323 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
324 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
325 enum pipe pipe = crtc->pipe;
326
327 drm_WARN_ON(display->drm, !crtc_state->has_pch_encoder);
328
329 intel_ddi_enable_transcoder_func(encoder, crtc_state);
330
331 intel_enable_transcoder(crtc_state);
332
333 lpt_pch_enable(state, crtc);
334
335 intel_crtc_vblank_on(crtc_state);
336
337 intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON);
338
339 intel_crtc_wait_for_next_vblank(crtc);
340 intel_crtc_wait_for_next_vblank(crtc);
341 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
342 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
343}
344
345static void intel_enable_crt(struct intel_atomic_state *state,
346 struct intel_encoder *encoder,
347 const struct intel_crtc_state *crtc_state,
348 const struct drm_connector_state *conn_state)
349{
350 intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON);
351}
352
353static enum drm_mode_status
354intel_crt_mode_valid(struct drm_connector *connector,
355 struct drm_display_mode *mode)
356{
357 struct intel_display *display = to_intel_display(connector->dev);
358 struct drm_device *dev = connector->dev;
359 struct drm_i915_private *dev_priv = to_i915(dev);
360 int max_dotclk = display->cdclk.max_dotclk_freq;
361 enum drm_mode_status status;
362 int max_clock;
363
364 status = intel_cpu_transcoder_mode_valid(dev_priv, mode);
365 if (status != MODE_OK)
366 return status;
367
368 if (mode->clock < 25000)
369 return MODE_CLOCK_LOW;
370
371 if (HAS_PCH_LPT(dev_priv))
372 max_clock = 180000;
373 else if (IS_VALLEYVIEW(dev_priv))
374 /*
375 * 270 MHz due to current DPLL limits,
376 * DAC limit supposedly 355 MHz.
377 */
378 max_clock = 270000;
379 else if (IS_DISPLAY_VER(display, 3, 4))
380 max_clock = 400000;
381 else
382 max_clock = 350000;
383 if (mode->clock > max_clock)
384 return MODE_CLOCK_HIGH;
385
386 if (mode->clock > max_dotclk)
387 return MODE_CLOCK_HIGH;
388
389 /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
390 if (HAS_PCH_LPT(dev_priv) &&
391 ilk_get_lanes_required(mode->clock, 270000, 24) > 2)
392 return MODE_CLOCK_HIGH;
393
394 /* HSW/BDW FDI limited to 4k */
395 if (mode->hdisplay > 4096)
396 return MODE_H_ILLEGAL;
397
398 return MODE_OK;
399}
400
401static int intel_crt_compute_config(struct intel_encoder *encoder,
402 struct intel_crtc_state *pipe_config,
403 struct drm_connector_state *conn_state)
404{
405 struct drm_display_mode *adjusted_mode =
406 &pipe_config->hw.adjusted_mode;
407
408 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
409 return -EINVAL;
410
411 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
412 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
413
414 return 0;
415}
416
417static int pch_crt_compute_config(struct intel_encoder *encoder,
418 struct intel_crtc_state *pipe_config,
419 struct drm_connector_state *conn_state)
420{
421 struct drm_display_mode *adjusted_mode =
422 &pipe_config->hw.adjusted_mode;
423
424 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
425 return -EINVAL;
426
427 pipe_config->has_pch_encoder = true;
428 if (!intel_fdi_compute_pipe_bpp(pipe_config))
429 return -EINVAL;
430
431 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
432
433 return 0;
434}
435
436static int hsw_crt_compute_config(struct intel_encoder *encoder,
437 struct intel_crtc_state *pipe_config,
438 struct drm_connector_state *conn_state)
439{
440 struct intel_display *display = to_intel_display(encoder);
441 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
442 struct drm_display_mode *adjusted_mode =
443 &pipe_config->hw.adjusted_mode;
444
445 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
446 return -EINVAL;
447
448 /* HSW/BDW FDI limited to 4k */
449 if (adjusted_mode->crtc_hdisplay > 4096 ||
450 adjusted_mode->crtc_hblank_start > 4096)
451 return -EINVAL;
452
453 pipe_config->has_pch_encoder = true;
454 if (!intel_fdi_compute_pipe_bpp(pipe_config))
455 return -EINVAL;
456
457 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
458
459 /* LPT FDI RX only supports 8bpc. */
460 if (HAS_PCH_LPT(dev_priv)) {
461 /* TODO: Check crtc_state->max_link_bpp_x16 instead of bw_constrained */
462 if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) {
463 drm_dbg_kms(display->drm,
464 "LPT only supports 24bpp\n");
465 return -EINVAL;
466 }
467
468 pipe_config->pipe_bpp = 24;
469 }
470
471 /* FDI must always be 2.7 GHz */
472 pipe_config->port_clock = 135000 * 2;
473
474 pipe_config->enhanced_framing = true;
475
476 adjusted_mode->crtc_clock = lpt_iclkip(pipe_config);
477
478 return 0;
479}
480
481static bool ilk_crt_detect_hotplug(struct drm_connector *connector)
482{
483 struct intel_display *display = to_intel_display(connector->dev);
484 struct drm_device *dev = connector->dev;
485 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
486 struct drm_i915_private *dev_priv = to_i915(dev);
487 u32 adpa;
488 bool ret;
489
490 /* The first time through, trigger an explicit detection cycle */
491 if (crt->force_hotplug_required) {
492 bool turn_off_dac = HAS_PCH_SPLIT(dev_priv);
493 u32 save_adpa;
494
495 crt->force_hotplug_required = false;
496
497 save_adpa = adpa = intel_de_read(display, crt->adpa_reg);
498 drm_dbg_kms(display->drm,
499 "trigger hotplug detect cycle: adpa=0x%x\n", adpa);
500
501 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
502 if (turn_off_dac)
503 adpa &= ~ADPA_DAC_ENABLE;
504
505 intel_de_write(display, crt->adpa_reg, adpa);
506
507 if (intel_de_wait_for_clear(display,
508 crt->adpa_reg,
509 ADPA_CRT_HOTPLUG_FORCE_TRIGGER,
510 1000))
511 drm_dbg_kms(display->drm,
512 "timed out waiting for FORCE_TRIGGER");
513
514 if (turn_off_dac) {
515 intel_de_write(display, crt->adpa_reg, save_adpa);
516 intel_de_posting_read(display, crt->adpa_reg);
517 }
518 }
519
520 /* Check the status to see if both blue and green are on now */
521 adpa = intel_de_read(display, crt->adpa_reg);
522 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
523 ret = true;
524 else
525 ret = false;
526 drm_dbg_kms(display->drm, "ironlake hotplug adpa=0x%x, result %d\n",
527 adpa, ret);
528
529 return ret;
530}
531
532static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
533{
534 struct intel_display *display = to_intel_display(connector->dev);
535 struct drm_device *dev = connector->dev;
536 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
537 struct drm_i915_private *dev_priv = to_i915(dev);
538 bool reenable_hpd;
539 u32 adpa;
540 bool ret;
541 u32 save_adpa;
542
543 /*
544 * Doing a force trigger causes a hpd interrupt to get sent, which can
545 * get us stuck in a loop if we're polling:
546 * - We enable power wells and reset the ADPA
547 * - output_poll_exec does force probe on VGA, triggering a hpd
548 * - HPD handler waits for poll to unlock dev->mode_config.mutex
549 * - output_poll_exec shuts off the ADPA, unlocks
550 * dev->mode_config.mutex
551 * - HPD handler runs, resets ADPA and brings us back to the start
552 *
553 * Just disable HPD interrupts here to prevent this
554 */
555 reenable_hpd = intel_hpd_disable(dev_priv, crt->base.hpd_pin);
556
557 save_adpa = adpa = intel_de_read(display, crt->adpa_reg);
558 drm_dbg_kms(display->drm,
559 "trigger hotplug detect cycle: adpa=0x%x\n", adpa);
560
561 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
562
563 intel_de_write(display, crt->adpa_reg, adpa);
564
565 if (intel_de_wait_for_clear(display, crt->adpa_reg,
566 ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 1000)) {
567 drm_dbg_kms(display->drm,
568 "timed out waiting for FORCE_TRIGGER");
569 intel_de_write(display, crt->adpa_reg, save_adpa);
570 }
571
572 /* Check the status to see if both blue and green are on now */
573 adpa = intel_de_read(display, crt->adpa_reg);
574 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
575 ret = true;
576 else
577 ret = false;
578
579 drm_dbg_kms(display->drm,
580 "valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
581
582 if (reenable_hpd)
583 intel_hpd_enable(dev_priv, crt->base.hpd_pin);
584
585 return ret;
586}
587
588static bool intel_crt_detect_hotplug(struct drm_connector *connector)
589{
590 struct intel_display *display = to_intel_display(connector->dev);
591 struct drm_device *dev = connector->dev;
592 struct drm_i915_private *dev_priv = to_i915(dev);
593 u32 stat;
594 bool ret = false;
595 int i, tries = 0;
596
597 if (HAS_PCH_SPLIT(dev_priv))
598 return ilk_crt_detect_hotplug(connector);
599
600 if (IS_VALLEYVIEW(dev_priv))
601 return valleyview_crt_detect_hotplug(connector);
602
603 /*
604 * On 4 series desktop, CRT detect sequence need to be done twice
605 * to get a reliable result.
606 */
607
608 if (IS_G45(dev_priv))
609 tries = 2;
610 else
611 tries = 1;
612
613 for (i = 0; i < tries ; i++) {
614 /* turn on the FORCE_DETECT */
615 i915_hotplug_interrupt_update(dev_priv,
616 CRT_HOTPLUG_FORCE_DETECT,
617 CRT_HOTPLUG_FORCE_DETECT);
618 /* wait for FORCE_DETECT to go off */
619 if (intel_de_wait_for_clear(display, PORT_HOTPLUG_EN(display),
620 CRT_HOTPLUG_FORCE_DETECT, 1000))
621 drm_dbg_kms(display->drm,
622 "timed out waiting for FORCE_DETECT to go off");
623 }
624
625 stat = intel_de_read(display, PORT_HOTPLUG_STAT(display));
626 if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
627 ret = true;
628
629 /* clear the interrupt we just generated, if any */
630 intel_de_write(display, PORT_HOTPLUG_STAT(display),
631 CRT_HOTPLUG_INT_STATUS);
632
633 i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0);
634
635 return ret;
636}
637
638static const struct drm_edid *intel_crt_get_edid(struct drm_connector *connector,
639 struct i2c_adapter *ddc)
640{
641 const struct drm_edid *drm_edid;
642
643 drm_edid = drm_edid_read_ddc(connector, ddc);
644
645 if (!drm_edid && !intel_gmbus_is_forced_bit(ddc)) {
646 drm_dbg_kms(connector->dev,
647 "CRT GMBUS EDID read failed, retry using GPIO bit-banging\n");
648 intel_gmbus_force_bit(ddc, true);
649 drm_edid = drm_edid_read_ddc(connector, ddc);
650 intel_gmbus_force_bit(ddc, false);
651 }
652
653 return drm_edid;
654}
655
656/* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */
657static int intel_crt_ddc_get_modes(struct drm_connector *connector,
658 struct i2c_adapter *ddc)
659{
660 const struct drm_edid *drm_edid;
661 int ret;
662
663 drm_edid = intel_crt_get_edid(connector, ddc);
664 if (!drm_edid)
665 return 0;
666
667 ret = intel_connector_update_modes(connector, drm_edid);
668
669 drm_edid_free(drm_edid);
670
671 return ret;
672}
673
674static bool intel_crt_detect_ddc(struct drm_connector *connector)
675{
676 struct intel_display *display = to_intel_display(connector->dev);
677 const struct drm_edid *drm_edid;
678 bool ret = false;
679
680 drm_edid = intel_crt_get_edid(connector, connector->ddc);
681
682 if (drm_edid) {
683 /*
684 * This may be a DVI-I connector with a shared DDC
685 * link between analog and digital outputs, so we
686 * have to check the EDID input spec of the attached device.
687 */
688 if (drm_edid_is_digital(drm_edid)) {
689 drm_dbg_kms(display->drm,
690 "CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
691 } else {
692 drm_dbg_kms(display->drm,
693 "CRT detected via DDC:0x50 [EDID]\n");
694 ret = true;
695 }
696 } else {
697 drm_dbg_kms(display->drm,
698 "CRT not detected via DDC:0x50 [no valid EDID found]\n");
699 }
700
701 drm_edid_free(drm_edid);
702
703 return ret;
704}
705
706static enum drm_connector_status
707intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
708{
709 struct intel_display *display = to_intel_display(&crt->base);
710 enum transcoder cpu_transcoder = (enum transcoder)pipe;
711 u32 save_bclrpat;
712 u32 save_vtotal;
713 u32 vtotal, vactive;
714 u32 vsample;
715 u32 vblank, vblank_start, vblank_end;
716 u32 dsl;
717 u8 st00;
718 enum drm_connector_status status;
719
720 drm_dbg_kms(display->drm, "starting load-detect on CRT\n");
721
722 save_bclrpat = intel_de_read(display,
723 BCLRPAT(display, cpu_transcoder));
724 save_vtotal = intel_de_read(display,
725 TRANS_VTOTAL(display, cpu_transcoder));
726 vblank = intel_de_read(display,
727 TRANS_VBLANK(display, cpu_transcoder));
728
729 vtotal = REG_FIELD_GET(VTOTAL_MASK, save_vtotal) + 1;
730 vactive = REG_FIELD_GET(VACTIVE_MASK, save_vtotal) + 1;
731
732 vblank_start = REG_FIELD_GET(VBLANK_START_MASK, vblank) + 1;
733 vblank_end = REG_FIELD_GET(VBLANK_END_MASK, vblank) + 1;
734
735 /* Set the border color to purple. */
736 intel_de_write(display, BCLRPAT(display, cpu_transcoder), 0x500050);
737
738 if (DISPLAY_VER(display) != 2) {
739 u32 transconf = intel_de_read(display,
740 TRANSCONF(display, cpu_transcoder));
741
742 intel_de_write(display, TRANSCONF(display, cpu_transcoder),
743 transconf | TRANSCONF_FORCE_BORDER);
744 intel_de_posting_read(display,
745 TRANSCONF(display, cpu_transcoder));
746 /* Wait for next Vblank to substitue
747 * border color for Color info */
748 intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(display, pipe));
749 st00 = intel_de_read8(display, _VGA_MSR_WRITE);
750 status = ((st00 & (1 << 4)) != 0) ?
751 connector_status_connected :
752 connector_status_disconnected;
753
754 intel_de_write(display, TRANSCONF(display, cpu_transcoder),
755 transconf);
756 } else {
757 bool restore_vblank = false;
758 int count, detect;
759
760 /*
761 * If there isn't any border, add some.
762 * Yes, this will flicker
763 */
764 if (vblank_start <= vactive && vblank_end >= vtotal) {
765 u32 vsync = intel_de_read(display,
766 TRANS_VSYNC(display, cpu_transcoder));
767 u32 vsync_start = REG_FIELD_GET(VSYNC_START_MASK, vsync) + 1;
768
769 vblank_start = vsync_start;
770 intel_de_write(display,
771 TRANS_VBLANK(display, cpu_transcoder),
772 VBLANK_START(vblank_start - 1) |
773 VBLANK_END(vblank_end - 1));
774 restore_vblank = true;
775 }
776 /* sample in the vertical border, selecting the larger one */
777 if (vblank_start - vactive >= vtotal - vblank_end)
778 vsample = (vblank_start + vactive) >> 1;
779 else
780 vsample = (vtotal + vblank_end) >> 1;
781
782 /*
783 * Wait for the border to be displayed
784 */
785 while (intel_de_read(display, PIPEDSL(display, pipe)) >= vactive)
786 ;
787 while ((dsl = intel_de_read(display, PIPEDSL(display, pipe))) <= vsample)
788 ;
789 /*
790 * Watch ST00 for an entire scanline
791 */
792 detect = 0;
793 count = 0;
794 do {
795 count++;
796 /* Read the ST00 VGA status register */
797 st00 = intel_de_read8(display, _VGA_MSR_WRITE);
798 if (st00 & (1 << 4))
799 detect++;
800 } while ((intel_de_read(display, PIPEDSL(display, pipe)) == dsl));
801
802 /* restore vblank if necessary */
803 if (restore_vblank)
804 intel_de_write(display,
805 TRANS_VBLANK(display, cpu_transcoder),
806 vblank);
807 /*
808 * If more than 3/4 of the scanline detected a monitor,
809 * then it is assumed to be present. This works even on i830,
810 * where there isn't any way to force the border color across
811 * the screen
812 */
813 status = detect * 4 > count * 3 ?
814 connector_status_connected :
815 connector_status_disconnected;
816 }
817
818 /* Restore previous settings */
819 intel_de_write(display, BCLRPAT(display, cpu_transcoder),
820 save_bclrpat);
821
822 return status;
823}
824
825static int intel_spurious_crt_detect_dmi_callback(const struct dmi_system_id *id)
826{
827 DRM_DEBUG_DRIVER("Skipping CRT detection for %s\n", id->ident);
828 return 1;
829}
830
831static const struct dmi_system_id intel_spurious_crt_detect[] = {
832 {
833 .callback = intel_spurious_crt_detect_dmi_callback,
834 .ident = "ACER ZGB",
835 .matches = {
836 DMI_MATCH(DMI_SYS_VENDOR, "ACER"),
837 DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"),
838 },
839 },
840 {
841 .callback = intel_spurious_crt_detect_dmi_callback,
842 .ident = "Intel DZ77BH-55K",
843 .matches = {
844 DMI_MATCH(DMI_BOARD_VENDOR, "Intel Corporation"),
845 DMI_MATCH(DMI_BOARD_NAME, "DZ77BH-55K"),
846 },
847 },
848 { }
849};
850
851static int
852intel_crt_detect(struct drm_connector *connector,
853 struct drm_modeset_acquire_ctx *ctx,
854 bool force)
855{
856 struct intel_display *display = to_intel_display(connector->dev);
857 struct drm_i915_private *dev_priv = to_i915(connector->dev);
858 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
859 struct intel_encoder *intel_encoder = &crt->base;
860 struct drm_atomic_state *state;
861 intel_wakeref_t wakeref;
862 int status;
863
864 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] force=%d\n",
865 connector->base.id, connector->name,
866 force);
867
868 if (!intel_display_device_enabled(dev_priv))
869 return connector_status_disconnected;
870
871 if (!intel_display_driver_check_access(dev_priv))
872 return connector->status;
873
874 if (display->params.load_detect_test) {
875 wakeref = intel_display_power_get(dev_priv,
876 intel_encoder->power_domain);
877 goto load_detect;
878 }
879
880 /* Skip machines without VGA that falsely report hotplug events */
881 if (dmi_check_system(intel_spurious_crt_detect))
882 return connector_status_disconnected;
883
884 wakeref = intel_display_power_get(dev_priv,
885 intel_encoder->power_domain);
886
887 if (I915_HAS_HOTPLUG(display)) {
888 /* We can not rely on the HPD pin always being correctly wired
889 * up, for example many KVM do not pass it through, and so
890 * only trust an assertion that the monitor is connected.
891 */
892 if (intel_crt_detect_hotplug(connector)) {
893 drm_dbg_kms(display->drm,
894 "CRT detected via hotplug\n");
895 status = connector_status_connected;
896 goto out;
897 } else
898 drm_dbg_kms(display->drm,
899 "CRT not detected via hotplug\n");
900 }
901
902 if (intel_crt_detect_ddc(connector)) {
903 status = connector_status_connected;
904 goto out;
905 }
906
907 /* Load detection is broken on HPD capable machines. Whoever wants a
908 * broken monitor (without edid) to work behind a broken kvm (that fails
909 * to have the right resistors for HP detection) needs to fix this up.
910 * For now just bail out. */
911 if (I915_HAS_HOTPLUG(display)) {
912 status = connector_status_disconnected;
913 goto out;
914 }
915
916load_detect:
917 if (!force) {
918 status = connector->status;
919 goto out;
920 }
921
922 /* for pre-945g platforms use load detect */
923 state = intel_load_detect_get_pipe(connector, ctx);
924 if (IS_ERR(state)) {
925 status = PTR_ERR(state);
926 } else if (!state) {
927 status = connector_status_unknown;
928 } else {
929 if (intel_crt_detect_ddc(connector))
930 status = connector_status_connected;
931 else if (DISPLAY_VER(display) < 4)
932 status = intel_crt_load_detect(crt,
933 to_intel_crtc(connector->state->crtc)->pipe);
934 else if (display->params.load_detect_test)
935 status = connector_status_disconnected;
936 else
937 status = connector_status_unknown;
938 intel_load_detect_release_pipe(connector, state, ctx);
939 }
940
941out:
942 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
943
944 return status;
945}
946
947static int intel_crt_get_modes(struct drm_connector *connector)
948{
949 struct intel_display *display = to_intel_display(connector->dev);
950 struct drm_device *dev = connector->dev;
951 struct drm_i915_private *dev_priv = to_i915(dev);
952 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
953 struct intel_encoder *intel_encoder = &crt->base;
954 intel_wakeref_t wakeref;
955 struct i2c_adapter *ddc;
956 int ret;
957
958 if (!intel_display_driver_check_access(dev_priv))
959 return drm_edid_connector_add_modes(connector);
960
961 wakeref = intel_display_power_get(dev_priv,
962 intel_encoder->power_domain);
963
964 ret = intel_crt_ddc_get_modes(connector, connector->ddc);
965 if (ret || !IS_G4X(dev_priv))
966 goto out;
967
968 /* Try to probe digital port for output in DVI-I -> VGA mode. */
969 ddc = intel_gmbus_get_adapter(display, GMBUS_PIN_DPB);
970 ret = intel_crt_ddc_get_modes(connector, ddc);
971
972out:
973 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
974
975 return ret;
976}
977
978void intel_crt_reset(struct drm_encoder *encoder)
979{
980 struct intel_display *display = to_intel_display(encoder->dev);
981 struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder));
982
983 if (DISPLAY_VER(display) >= 5) {
984 u32 adpa;
985
986 adpa = intel_de_read(display, crt->adpa_reg);
987 adpa &= ~ADPA_CRT_HOTPLUG_MASK;
988 adpa |= ADPA_HOTPLUG_BITS;
989 intel_de_write(display, crt->adpa_reg, adpa);
990 intel_de_posting_read(display, crt->adpa_reg);
991
992 drm_dbg_kms(display->drm, "crt adpa set to 0x%x\n", adpa);
993 crt->force_hotplug_required = true;
994 }
995
996}
997
998/*
999 * Routines for controlling stuff on the analog port
1000 */
1001
1002static const struct drm_connector_funcs intel_crt_connector_funcs = {
1003 .fill_modes = drm_helper_probe_single_connector_modes,
1004 .late_register = intel_connector_register,
1005 .early_unregister = intel_connector_unregister,
1006 .destroy = intel_connector_destroy,
1007 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1008 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1009};
1010
1011static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
1012 .detect_ctx = intel_crt_detect,
1013 .mode_valid = intel_crt_mode_valid,
1014 .get_modes = intel_crt_get_modes,
1015};
1016
1017static const struct drm_encoder_funcs intel_crt_enc_funcs = {
1018 .reset = intel_crt_reset,
1019 .destroy = intel_encoder_destroy,
1020};
1021
1022void intel_crt_init(struct intel_display *display)
1023{
1024 struct drm_i915_private *dev_priv = to_i915(display->drm);
1025 struct drm_connector *connector;
1026 struct intel_crt *crt;
1027 struct intel_connector *intel_connector;
1028 i915_reg_t adpa_reg;
1029 u8 ddc_pin;
1030 u32 adpa;
1031
1032 if (HAS_PCH_SPLIT(dev_priv))
1033 adpa_reg = PCH_ADPA;
1034 else if (IS_VALLEYVIEW(dev_priv))
1035 adpa_reg = VLV_ADPA;
1036 else
1037 adpa_reg = ADPA;
1038
1039 adpa = intel_de_read(display, adpa_reg);
1040 if ((adpa & ADPA_DAC_ENABLE) == 0) {
1041 /*
1042 * On some machines (some IVB at least) CRT can be
1043 * fused off, but there's no known fuse bit to
1044 * indicate that. On these machine the ADPA register
1045 * works normally, except the DAC enable bit won't
1046 * take. So the only way to tell is attempt to enable
1047 * it and see what happens.
1048 */
1049 intel_de_write(display, adpa_reg,
1050 adpa | ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
1051 if ((intel_de_read(display, adpa_reg) & ADPA_DAC_ENABLE) == 0)
1052 return;
1053 intel_de_write(display, adpa_reg, adpa);
1054 }
1055
1056 crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
1057 if (!crt)
1058 return;
1059
1060 intel_connector = intel_connector_alloc();
1061 if (!intel_connector) {
1062 kfree(crt);
1063 return;
1064 }
1065
1066 ddc_pin = display->vbt.crt_ddc_pin;
1067
1068 connector = &intel_connector->base;
1069 crt->connector = intel_connector;
1070 drm_connector_init_with_ddc(display->drm, connector,
1071 &intel_crt_connector_funcs,
1072 DRM_MODE_CONNECTOR_VGA,
1073 intel_gmbus_get_adapter(display, ddc_pin));
1074
1075 drm_encoder_init(display->drm, &crt->base.base, &intel_crt_enc_funcs,
1076 DRM_MODE_ENCODER_DAC, "CRT");
1077
1078 intel_connector_attach_encoder(intel_connector, &crt->base);
1079
1080 crt->base.type = INTEL_OUTPUT_ANALOG;
1081 crt->base.cloneable = BIT(INTEL_OUTPUT_DVO) | BIT(INTEL_OUTPUT_HDMI);
1082 if (IS_I830(dev_priv))
1083 crt->base.pipe_mask = BIT(PIPE_A);
1084 else
1085 crt->base.pipe_mask = ~0;
1086
1087 if (DISPLAY_VER(display) != 2)
1088 connector->interlace_allowed = true;
1089
1090 crt->adpa_reg = adpa_reg;
1091
1092 crt->base.power_domain = POWER_DOMAIN_PORT_CRT;
1093
1094 if (I915_HAS_HOTPLUG(display) &&
1095 !dmi_check_system(intel_spurious_crt_detect)) {
1096 crt->base.hpd_pin = HPD_CRT;
1097 crt->base.hotplug = intel_encoder_hotplug;
1098 intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
1099 } else {
1100 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
1101 }
1102 intel_connector->base.polled = intel_connector->polled;
1103
1104 if (HAS_DDI(display)) {
1105 assert_port_valid(dev_priv, PORT_E);
1106
1107 crt->base.port = PORT_E;
1108 crt->base.get_config = hsw_crt_get_config;
1109 crt->base.get_hw_state = intel_ddi_get_hw_state;
1110 crt->base.compute_config = hsw_crt_compute_config;
1111 crt->base.pre_pll_enable = hsw_pre_pll_enable_crt;
1112 crt->base.pre_enable = hsw_pre_enable_crt;
1113 crt->base.enable = hsw_enable_crt;
1114 crt->base.disable = hsw_disable_crt;
1115 crt->base.post_disable = hsw_post_disable_crt;
1116 crt->base.enable_clock = hsw_ddi_enable_clock;
1117 crt->base.disable_clock = hsw_ddi_disable_clock;
1118 crt->base.is_clock_enabled = hsw_ddi_is_clock_enabled;
1119
1120 intel_ddi_buf_trans_init(&crt->base);
1121 } else {
1122 if (HAS_PCH_SPLIT(dev_priv)) {
1123 crt->base.compute_config = pch_crt_compute_config;
1124 crt->base.disable = pch_disable_crt;
1125 crt->base.post_disable = pch_post_disable_crt;
1126 } else {
1127 crt->base.compute_config = intel_crt_compute_config;
1128 crt->base.disable = intel_disable_crt;
1129 }
1130 crt->base.port = PORT_NONE;
1131 crt->base.get_config = intel_crt_get_config;
1132 crt->base.get_hw_state = intel_crt_get_hw_state;
1133 crt->base.enable = intel_enable_crt;
1134 }
1135 intel_connector->get_hw_state = intel_connector_get_hw_state;
1136
1137 drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
1138
1139 /*
1140 * TODO: find a proper way to discover whether we need to set the the
1141 * polarity and link reversal bits or not, instead of relying on the
1142 * BIOS.
1143 */
1144 if (HAS_PCH_LPT(dev_priv)) {
1145 u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
1146 FDI_RX_LINK_REVERSAL_OVERRIDE;
1147
1148 display->fdi.rx_config = intel_de_read(display,
1149 FDI_RX_CTL(PIPE_A)) & fdi_config;
1150 }
1151
1152 intel_crt_reset(&crt->base.base);
1153}