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1/*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24#include <linux/component.h>
25#include <linux/kernel.h>
26
27#include <drm/drm_edid.h>
28#include <drm/drm_eld.h>
29#include <drm/drm_fixed.h>
30#include <drm/intel/i915_component.h>
31
32#include "i915_drv.h"
33#include "intel_atomic.h"
34#include "intel_audio.h"
35#include "intel_audio_regs.h"
36#include "intel_cdclk.h"
37#include "intel_crtc.h"
38#include "intel_de.h"
39#include "intel_display_types.h"
40#include "intel_lpe_audio.h"
41
42/**
43 * DOC: High Definition Audio over HDMI and Display Port
44 *
45 * The graphics and audio drivers together support High Definition Audio over
46 * HDMI and Display Port. The audio programming sequences are divided into audio
47 * codec and controller enable and disable sequences. The graphics driver
48 * handles the audio codec sequences, while the audio driver handles the audio
49 * controller sequences.
50 *
51 * The disable sequences must be performed before disabling the transcoder or
52 * port. The enable sequences may only be performed after enabling the
53 * transcoder and port, and after completed link training. Therefore the audio
54 * enable/disable sequences are part of the modeset sequence.
55 *
56 * The codec and controller sequences could be done either parallel or serial,
57 * but generally the ELDV/PD change in the codec sequence indicates to the audio
58 * driver that the controller sequence should start. Indeed, most of the
59 * co-operation between the graphics and audio drivers is handled via audio
60 * related registers. (The notable exception is the power management, not
61 * covered here.)
62 *
63 * The struct &i915_audio_component is used to interact between the graphics
64 * and audio drivers. The struct &i915_audio_component_ops @ops in it is
65 * defined in graphics driver and called in audio driver. The
66 * struct &i915_audio_component_audio_ops @audio_ops is called from i915 driver.
67 */
68
69struct intel_audio_funcs {
70 void (*audio_codec_enable)(struct intel_encoder *encoder,
71 const struct intel_crtc_state *crtc_state,
72 const struct drm_connector_state *conn_state);
73 void (*audio_codec_disable)(struct intel_encoder *encoder,
74 const struct intel_crtc_state *old_crtc_state,
75 const struct drm_connector_state *old_conn_state);
76 void (*audio_codec_get_config)(struct intel_encoder *encoder,
77 struct intel_crtc_state *crtc_state);
78};
79
80struct hdmi_aud_ncts {
81 int sample_rate;
82 int clock;
83 int n;
84 int cts;
85};
86
87static const struct {
88 int clock;
89 u32 config;
90} hdmi_audio_clock[] = {
91 { 25175, AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
92 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
93 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
94 { 27027, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
95 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
96 { 54054, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
97 { 74176, AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
98 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
99 { 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
100 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
101 { 296703, AUD_CONFIG_PIXEL_CLOCK_HDMI_296703 },
102 { 297000, AUD_CONFIG_PIXEL_CLOCK_HDMI_297000 },
103 { 593407, AUD_CONFIG_PIXEL_CLOCK_HDMI_593407 },
104 { 594000, AUD_CONFIG_PIXEL_CLOCK_HDMI_594000 },
105};
106
107/* HDMI N/CTS table */
108#define TMDS_297M 297000
109#define TMDS_296M 296703
110#define TMDS_594M 594000
111#define TMDS_593M 593407
112
113static const struct hdmi_aud_ncts hdmi_aud_ncts_24bpp[] = {
114 { 32000, TMDS_296M, 5824, 421875 },
115 { 32000, TMDS_297M, 3072, 222750 },
116 { 32000, TMDS_593M, 5824, 843750 },
117 { 32000, TMDS_594M, 3072, 445500 },
118 { 44100, TMDS_296M, 4459, 234375 },
119 { 44100, TMDS_297M, 4704, 247500 },
120 { 44100, TMDS_593M, 8918, 937500 },
121 { 44100, TMDS_594M, 9408, 990000 },
122 { 88200, TMDS_296M, 8918, 234375 },
123 { 88200, TMDS_297M, 9408, 247500 },
124 { 88200, TMDS_593M, 17836, 937500 },
125 { 88200, TMDS_594M, 18816, 990000 },
126 { 176400, TMDS_296M, 17836, 234375 },
127 { 176400, TMDS_297M, 18816, 247500 },
128 { 176400, TMDS_593M, 35672, 937500 },
129 { 176400, TMDS_594M, 37632, 990000 },
130 { 48000, TMDS_296M, 5824, 281250 },
131 { 48000, TMDS_297M, 5120, 247500 },
132 { 48000, TMDS_593M, 5824, 562500 },
133 { 48000, TMDS_594M, 6144, 594000 },
134 { 96000, TMDS_296M, 11648, 281250 },
135 { 96000, TMDS_297M, 10240, 247500 },
136 { 96000, TMDS_593M, 11648, 562500 },
137 { 96000, TMDS_594M, 12288, 594000 },
138 { 192000, TMDS_296M, 23296, 281250 },
139 { 192000, TMDS_297M, 20480, 247500 },
140 { 192000, TMDS_593M, 23296, 562500 },
141 { 192000, TMDS_594M, 24576, 594000 },
142};
143
144/* Appendix C - N & CTS values for deep color from HDMI 2.0 spec*/
145/* HDMI N/CTS table for 10 bit deep color(30 bpp)*/
146#define TMDS_371M 371250
147#define TMDS_370M 370878
148
149static const struct hdmi_aud_ncts hdmi_aud_ncts_30bpp[] = {
150 { 32000, TMDS_370M, 5824, 527344 },
151 { 32000, TMDS_371M, 6144, 556875 },
152 { 44100, TMDS_370M, 8918, 585938 },
153 { 44100, TMDS_371M, 4704, 309375 },
154 { 88200, TMDS_370M, 17836, 585938 },
155 { 88200, TMDS_371M, 9408, 309375 },
156 { 176400, TMDS_370M, 35672, 585938 },
157 { 176400, TMDS_371M, 18816, 309375 },
158 { 48000, TMDS_370M, 11648, 703125 },
159 { 48000, TMDS_371M, 5120, 309375 },
160 { 96000, TMDS_370M, 23296, 703125 },
161 { 96000, TMDS_371M, 10240, 309375 },
162 { 192000, TMDS_370M, 46592, 703125 },
163 { 192000, TMDS_371M, 20480, 309375 },
164};
165
166/* HDMI N/CTS table for 12 bit deep color(36 bpp)*/
167#define TMDS_445_5M 445500
168#define TMDS_445M 445054
169
170static const struct hdmi_aud_ncts hdmi_aud_ncts_36bpp[] = {
171 { 32000, TMDS_445M, 5824, 632813 },
172 { 32000, TMDS_445_5M, 4096, 445500 },
173 { 44100, TMDS_445M, 8918, 703125 },
174 { 44100, TMDS_445_5M, 4704, 371250 },
175 { 88200, TMDS_445M, 17836, 703125 },
176 { 88200, TMDS_445_5M, 9408, 371250 },
177 { 176400, TMDS_445M, 35672, 703125 },
178 { 176400, TMDS_445_5M, 18816, 371250 },
179 { 48000, TMDS_445M, 5824, 421875 },
180 { 48000, TMDS_445_5M, 5120, 371250 },
181 { 96000, TMDS_445M, 11648, 421875 },
182 { 96000, TMDS_445_5M, 10240, 371250 },
183 { 192000, TMDS_445M, 23296, 421875 },
184 { 192000, TMDS_445_5M, 20480, 371250 },
185};
186
187/*
188 * WA_14020863754: Implement Audio Workaround
189 * Corner case with Min Hblank Fix can cause audio hang
190 */
191static bool needs_wa_14020863754(struct drm_i915_private *i915)
192{
193 return (DISPLAY_VER(i915) == 20 || IS_BATTLEMAGE(i915));
194}
195
196/* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
197static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_state)
198{
199 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
200 const struct drm_display_mode *adjusted_mode =
201 &crtc_state->hw.adjusted_mode;
202 int i;
203
204 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
205 if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock)
206 break;
207 }
208
209 if (DISPLAY_VER(i915) < 12 && adjusted_mode->crtc_clock > 148500)
210 i = ARRAY_SIZE(hdmi_audio_clock);
211
212 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
213 drm_dbg_kms(&i915->drm,
214 "HDMI audio pixel clock setting for %d not found, falling back to defaults\n",
215 adjusted_mode->crtc_clock);
216 i = 1;
217 }
218
219 drm_dbg_kms(&i915->drm,
220 "Configuring HDMI audio for pixel clock %d (0x%08x)\n",
221 hdmi_audio_clock[i].clock,
222 hdmi_audio_clock[i].config);
223
224 return hdmi_audio_clock[i].config;
225}
226
227static int audio_config_hdmi_get_n(const struct intel_crtc_state *crtc_state,
228 int rate)
229{
230 const struct hdmi_aud_ncts *hdmi_ncts_table;
231 int i, size;
232
233 if (crtc_state->pipe_bpp == 36) {
234 hdmi_ncts_table = hdmi_aud_ncts_36bpp;
235 size = ARRAY_SIZE(hdmi_aud_ncts_36bpp);
236 } else if (crtc_state->pipe_bpp == 30) {
237 hdmi_ncts_table = hdmi_aud_ncts_30bpp;
238 size = ARRAY_SIZE(hdmi_aud_ncts_30bpp);
239 } else {
240 hdmi_ncts_table = hdmi_aud_ncts_24bpp;
241 size = ARRAY_SIZE(hdmi_aud_ncts_24bpp);
242 }
243
244 for (i = 0; i < size; i++) {
245 if (rate == hdmi_ncts_table[i].sample_rate &&
246 crtc_state->port_clock == hdmi_ncts_table[i].clock) {
247 return hdmi_ncts_table[i].n;
248 }
249 }
250 return 0;
251}
252
253/* ELD buffer size in dwords */
254static int g4x_eld_buffer_size(struct drm_i915_private *i915)
255{
256 u32 tmp;
257
258 tmp = intel_de_read(i915, G4X_AUD_CNTL_ST);
259
260 return REG_FIELD_GET(G4X_ELD_BUFFER_SIZE_MASK, tmp);
261}
262
263static void g4x_audio_codec_get_config(struct intel_encoder *encoder,
264 struct intel_crtc_state *crtc_state)
265{
266 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
267 u32 *eld = (u32 *)crtc_state->eld;
268 int eld_buffer_size, len, i;
269 u32 tmp;
270
271 tmp = intel_de_read(i915, G4X_AUD_CNTL_ST);
272 if ((tmp & G4X_ELD_VALID) == 0)
273 return;
274
275 intel_de_rmw(i915, G4X_AUD_CNTL_ST, G4X_ELD_ADDRESS_MASK, 0);
276
277 eld_buffer_size = g4x_eld_buffer_size(i915);
278 len = min_t(int, sizeof(crtc_state->eld) / 4, eld_buffer_size);
279
280 for (i = 0; i < len; i++)
281 eld[i] = intel_de_read(i915, G4X_HDMIW_HDMIEDID);
282}
283
284static void g4x_audio_codec_disable(struct intel_encoder *encoder,
285 const struct intel_crtc_state *old_crtc_state,
286 const struct drm_connector_state *old_conn_state)
287{
288 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
289 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
290
291 /* Invalidate ELD */
292 intel_de_rmw(i915, G4X_AUD_CNTL_ST,
293 G4X_ELD_VALID, 0);
294
295 intel_crtc_wait_for_next_vblank(crtc);
296 intel_crtc_wait_for_next_vblank(crtc);
297}
298
299static void g4x_audio_codec_enable(struct intel_encoder *encoder,
300 const struct intel_crtc_state *crtc_state,
301 const struct drm_connector_state *conn_state)
302{
303 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
304 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
305 const u32 *eld = (const u32 *)crtc_state->eld;
306 int eld_buffer_size, len, i;
307
308 intel_crtc_wait_for_next_vblank(crtc);
309
310 intel_de_rmw(i915, G4X_AUD_CNTL_ST,
311 G4X_ELD_VALID | G4X_ELD_ADDRESS_MASK, 0);
312
313 eld_buffer_size = g4x_eld_buffer_size(i915);
314 len = min(drm_eld_size(crtc_state->eld) / 4, eld_buffer_size);
315
316 for (i = 0; i < len; i++)
317 intel_de_write(i915, G4X_HDMIW_HDMIEDID, eld[i]);
318 for (; i < eld_buffer_size; i++)
319 intel_de_write(i915, G4X_HDMIW_HDMIEDID, 0);
320
321 drm_WARN_ON(&i915->drm,
322 (intel_de_read(i915, G4X_AUD_CNTL_ST) & G4X_ELD_ADDRESS_MASK) != 0);
323
324 intel_de_rmw(i915, G4X_AUD_CNTL_ST,
325 0, G4X_ELD_VALID);
326}
327
328static void
329hsw_dp_audio_config_update(struct intel_encoder *encoder,
330 const struct intel_crtc_state *crtc_state)
331{
332 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
333 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
334
335 /* Enable time stamps. Let HW calculate Maud/Naud values */
336 intel_de_rmw(i915, HSW_AUD_CFG(cpu_transcoder),
337 AUD_CONFIG_N_VALUE_INDEX |
338 AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK |
339 AUD_CONFIG_UPPER_N_MASK |
340 AUD_CONFIG_LOWER_N_MASK |
341 AUD_CONFIG_N_PROG_ENABLE,
342 AUD_CONFIG_N_VALUE_INDEX);
343
344}
345
346static void
347hsw_hdmi_audio_config_update(struct intel_encoder *encoder,
348 const struct intel_crtc_state *crtc_state)
349{
350 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
351 struct i915_audio_component *acomp = i915->display.audio.component;
352 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
353 enum port port = encoder->port;
354 int n, rate;
355 u32 tmp;
356
357 rate = acomp ? acomp->aud_sample_rate[port] : 0;
358
359 tmp = intel_de_read(i915, HSW_AUD_CFG(cpu_transcoder));
360 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
361 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
362 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
363 tmp |= audio_config_hdmi_pixel_clock(crtc_state);
364
365 n = audio_config_hdmi_get_n(crtc_state, rate);
366 if (n != 0) {
367 drm_dbg_kms(&i915->drm, "using N %d\n", n);
368
369 tmp &= ~AUD_CONFIG_N_MASK;
370 tmp |= AUD_CONFIG_N(n);
371 tmp |= AUD_CONFIG_N_PROG_ENABLE;
372 } else {
373 drm_dbg_kms(&i915->drm, "using automatic N\n");
374 }
375
376 intel_de_write(i915, HSW_AUD_CFG(cpu_transcoder), tmp);
377
378 /*
379 * Let's disable "Enable CTS or M Prog bit"
380 * and let HW calculate the value
381 */
382 tmp = intel_de_read(i915, HSW_AUD_M_CTS_ENABLE(cpu_transcoder));
383 tmp &= ~AUD_M_CTS_M_PROG_ENABLE;
384 tmp &= ~AUD_M_CTS_M_VALUE_INDEX;
385 intel_de_write(i915, HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp);
386}
387
388static void
389hsw_audio_config_update(struct intel_encoder *encoder,
390 const struct intel_crtc_state *crtc_state)
391{
392 if (intel_crtc_has_dp_encoder(crtc_state))
393 hsw_dp_audio_config_update(encoder, crtc_state);
394 else
395 hsw_hdmi_audio_config_update(encoder, crtc_state);
396}
397
398static void hsw_audio_codec_disable(struct intel_encoder *encoder,
399 const struct intel_crtc_state *old_crtc_state,
400 const struct drm_connector_state *old_conn_state)
401{
402 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
403 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
404 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
405
406 mutex_lock(&i915->display.audio.mutex);
407
408 /* Disable timestamps */
409 intel_de_rmw(i915, HSW_AUD_CFG(cpu_transcoder),
410 AUD_CONFIG_N_VALUE_INDEX |
411 AUD_CONFIG_UPPER_N_MASK |
412 AUD_CONFIG_LOWER_N_MASK,
413 AUD_CONFIG_N_PROG_ENABLE |
414 (intel_crtc_has_dp_encoder(old_crtc_state) ?
415 AUD_CONFIG_N_VALUE_INDEX : 0));
416
417 /* Invalidate ELD */
418 intel_de_rmw(i915, HSW_AUD_PIN_ELD_CP_VLD,
419 AUDIO_ELD_VALID(cpu_transcoder), 0);
420
421 intel_crtc_wait_for_next_vblank(crtc);
422 intel_crtc_wait_for_next_vblank(crtc);
423
424 /* Disable audio presence detect */
425 intel_de_rmw(i915, HSW_AUD_PIN_ELD_CP_VLD,
426 AUDIO_OUTPUT_ENABLE(cpu_transcoder), 0);
427
428 if (needs_wa_14020863754(i915))
429 intel_de_rmw(i915, AUD_CHICKENBIT_REG3, DACBE_DISABLE_MIN_HBLANK_FIX, 0);
430
431 mutex_unlock(&i915->display.audio.mutex);
432}
433
434static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder,
435 const struct intel_crtc_state *crtc_state)
436{
437 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
438 unsigned int link_clks_available, link_clks_required;
439 unsigned int tu_data, tu_line, link_clks_active;
440 unsigned int h_active, h_total, hblank_delta, pixel_clk;
441 unsigned int fec_coeff, cdclk, vdsc_bppx16;
442 unsigned int link_clk, lanes;
443 unsigned int hblank_rise;
444
445 h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay;
446 h_total = crtc_state->hw.adjusted_mode.crtc_htotal;
447 pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock;
448 vdsc_bppx16 = crtc_state->dsc.compressed_bpp_x16;
449 cdclk = i915->display.cdclk.hw.cdclk;
450 /* fec= 0.972261, using rounding multiplier of 1000000 */
451 fec_coeff = 972261;
452 link_clk = crtc_state->port_clock;
453 lanes = crtc_state->lane_count;
454
455 drm_dbg_kms(&i915->drm,
456 "h_active = %u link_clk = %u : lanes = %u vdsc_bpp = " FXP_Q4_FMT " cdclk = %u\n",
457 h_active, link_clk, lanes, FXP_Q4_ARGS(vdsc_bppx16), cdclk);
458
459 if (WARN_ON(!link_clk || !pixel_clk || !lanes || !vdsc_bppx16 || !cdclk))
460 return 0;
461
462 link_clks_available = (h_total - h_active) * link_clk / pixel_clk - 28;
463 link_clks_required = DIV_ROUND_UP(192000 * h_total, 1000 * pixel_clk) * (48 / lanes + 2);
464
465 if (link_clks_available > link_clks_required)
466 hblank_delta = 32;
467 else
468 hblank_delta = DIV64_U64_ROUND_UP(mul_u32_u32(5 * (link_clk + cdclk), pixel_clk),
469 mul_u32_u32(link_clk, cdclk));
470
471 tu_data = div64_u64(mul_u32_u32(pixel_clk * vdsc_bppx16 * 8, 1000000),
472 mul_u32_u32(link_clk * lanes * 16, fec_coeff));
473 tu_line = div64_u64(h_active * mul_u32_u32(link_clk, fec_coeff),
474 mul_u32_u32(64 * pixel_clk, 1000000));
475 link_clks_active = (tu_line - 1) * 64 + tu_data;
476
477 hblank_rise = (link_clks_active + 6 * DIV_ROUND_UP(link_clks_active, 250) + 4) * pixel_clk / link_clk;
478
479 return h_active - hblank_rise + hblank_delta;
480}
481
482static unsigned int calc_samples_room(const struct intel_crtc_state *crtc_state)
483{
484 unsigned int h_active, h_total, pixel_clk;
485 unsigned int link_clk, lanes;
486
487 h_active = crtc_state->hw.adjusted_mode.hdisplay;
488 h_total = crtc_state->hw.adjusted_mode.htotal;
489 pixel_clk = crtc_state->hw.adjusted_mode.clock;
490 link_clk = crtc_state->port_clock;
491 lanes = crtc_state->lane_count;
492
493 return ((h_total - h_active) * link_clk - 12 * pixel_clk) /
494 (pixel_clk * (48 / lanes + 2));
495}
496
497static void enable_audio_dsc_wa(struct intel_encoder *encoder,
498 const struct intel_crtc_state *crtc_state)
499{
500 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
501 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
502 unsigned int hblank_early_prog, samples_room;
503 unsigned int val;
504
505 if (DISPLAY_VER(i915) < 11)
506 return;
507
508 val = intel_de_read(i915, AUD_CONFIG_BE);
509
510 if (DISPLAY_VER(i915) == 11)
511 val |= HBLANK_EARLY_ENABLE_ICL(cpu_transcoder);
512 else if (DISPLAY_VER(i915) >= 12)
513 val |= HBLANK_EARLY_ENABLE_TGL(cpu_transcoder);
514
515 if (crtc_state->dsc.compression_enable &&
516 crtc_state->hw.adjusted_mode.hdisplay >= 3840 &&
517 crtc_state->hw.adjusted_mode.vdisplay >= 2160) {
518 /* Get hblank early enable value required */
519 val &= ~HBLANK_START_COUNT_MASK(cpu_transcoder);
520 hblank_early_prog = calc_hblank_early_prog(encoder, crtc_state);
521 if (hblank_early_prog < 32)
522 val |= HBLANK_START_COUNT(cpu_transcoder, HBLANK_START_COUNT_32);
523 else if (hblank_early_prog < 64)
524 val |= HBLANK_START_COUNT(cpu_transcoder, HBLANK_START_COUNT_64);
525 else if (hblank_early_prog < 96)
526 val |= HBLANK_START_COUNT(cpu_transcoder, HBLANK_START_COUNT_96);
527 else
528 val |= HBLANK_START_COUNT(cpu_transcoder, HBLANK_START_COUNT_128);
529
530 /* Get samples room value required */
531 val &= ~NUMBER_SAMPLES_PER_LINE_MASK(cpu_transcoder);
532 samples_room = calc_samples_room(crtc_state);
533 if (samples_room < 3)
534 val |= NUMBER_SAMPLES_PER_LINE(cpu_transcoder, samples_room);
535 else /* Program 0 i.e "All Samples available in buffer" */
536 val |= NUMBER_SAMPLES_PER_LINE(cpu_transcoder, 0x0);
537 }
538
539 intel_de_write(i915, AUD_CONFIG_BE, val);
540}
541
542static void hsw_audio_codec_enable(struct intel_encoder *encoder,
543 const struct intel_crtc_state *crtc_state,
544 const struct drm_connector_state *conn_state)
545{
546 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
547 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
548 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
549
550 mutex_lock(&i915->display.audio.mutex);
551
552 /* Enable Audio WA for 4k DSC usecases */
553 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP))
554 enable_audio_dsc_wa(encoder, crtc_state);
555
556 if (needs_wa_14020863754(i915))
557 intel_de_rmw(i915, AUD_CHICKENBIT_REG3, 0, DACBE_DISABLE_MIN_HBLANK_FIX);
558
559 /* Enable audio presence detect */
560 intel_de_rmw(i915, HSW_AUD_PIN_ELD_CP_VLD,
561 0, AUDIO_OUTPUT_ENABLE(cpu_transcoder));
562
563 intel_crtc_wait_for_next_vblank(crtc);
564
565 /* Invalidate ELD */
566 intel_de_rmw(i915, HSW_AUD_PIN_ELD_CP_VLD,
567 AUDIO_ELD_VALID(cpu_transcoder), 0);
568
569 /*
570 * The audio componenent is used to convey the ELD
571 * instead using of the hardware ELD buffer.
572 */
573
574 /* Enable timestamps */
575 hsw_audio_config_update(encoder, crtc_state);
576
577 mutex_unlock(&i915->display.audio.mutex);
578}
579
580struct ibx_audio_regs {
581 i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2;
582};
583
584static void ibx_audio_regs_init(struct drm_i915_private *i915,
585 enum pipe pipe,
586 struct ibx_audio_regs *regs)
587{
588 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
589 regs->hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
590 regs->aud_config = VLV_AUD_CFG(pipe);
591 regs->aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
592 regs->aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
593 } else if (HAS_PCH_CPT(i915)) {
594 regs->hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
595 regs->aud_config = CPT_AUD_CFG(pipe);
596 regs->aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
597 regs->aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
598 } else if (HAS_PCH_IBX(i915)) {
599 regs->hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
600 regs->aud_config = IBX_AUD_CFG(pipe);
601 regs->aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
602 regs->aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
603 }
604}
605
606static void ibx_audio_codec_disable(struct intel_encoder *encoder,
607 const struct intel_crtc_state *old_crtc_state,
608 const struct drm_connector_state *old_conn_state)
609{
610 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
611 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
612 enum port port = encoder->port;
613 enum pipe pipe = crtc->pipe;
614 struct ibx_audio_regs regs;
615
616 if (drm_WARN_ON(&i915->drm, port == PORT_A))
617 return;
618
619 ibx_audio_regs_init(i915, pipe, ®s);
620
621 mutex_lock(&i915->display.audio.mutex);
622
623 /* Disable timestamps */
624 intel_de_rmw(i915, regs.aud_config,
625 AUD_CONFIG_N_VALUE_INDEX |
626 AUD_CONFIG_UPPER_N_MASK |
627 AUD_CONFIG_LOWER_N_MASK,
628 AUD_CONFIG_N_PROG_ENABLE |
629 (intel_crtc_has_dp_encoder(old_crtc_state) ?
630 AUD_CONFIG_N_VALUE_INDEX : 0));
631
632 /* Invalidate ELD */
633 intel_de_rmw(i915, regs.aud_cntrl_st2,
634 IBX_ELD_VALID(port), 0);
635
636 mutex_unlock(&i915->display.audio.mutex);
637
638 intel_crtc_wait_for_next_vblank(crtc);
639 intel_crtc_wait_for_next_vblank(crtc);
640}
641
642static void ibx_audio_codec_enable(struct intel_encoder *encoder,
643 const struct intel_crtc_state *crtc_state,
644 const struct drm_connector_state *conn_state)
645{
646 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
647 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
648 enum port port = encoder->port;
649 enum pipe pipe = crtc->pipe;
650 struct ibx_audio_regs regs;
651
652 if (drm_WARN_ON(&i915->drm, port == PORT_A))
653 return;
654
655 intel_crtc_wait_for_next_vblank(crtc);
656
657 ibx_audio_regs_init(i915, pipe, ®s);
658
659 mutex_lock(&i915->display.audio.mutex);
660
661 /* Invalidate ELD */
662 intel_de_rmw(i915, regs.aud_cntrl_st2,
663 IBX_ELD_VALID(port), 0);
664
665 /*
666 * The audio componenent is used to convey the ELD
667 * instead using of the hardware ELD buffer.
668 */
669
670 /* Enable timestamps */
671 intel_de_rmw(i915, regs.aud_config,
672 AUD_CONFIG_N_VALUE_INDEX |
673 AUD_CONFIG_N_PROG_ENABLE |
674 AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK,
675 (intel_crtc_has_dp_encoder(crtc_state) ?
676 AUD_CONFIG_N_VALUE_INDEX :
677 audio_config_hdmi_pixel_clock(crtc_state)));
678
679 mutex_unlock(&i915->display.audio.mutex);
680}
681
682void intel_audio_sdp_split_update(const struct intel_crtc_state *crtc_state)
683{
684 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
685 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
686 enum transcoder trans = crtc_state->cpu_transcoder;
687
688 if (HAS_DP20(i915))
689 intel_de_rmw(i915, AUD_DP_2DOT0_CTRL(trans), AUD_ENABLE_SDP_SPLIT,
690 crtc_state->sdp_split_enable ? AUD_ENABLE_SDP_SPLIT : 0);
691}
692
693bool intel_audio_compute_config(struct intel_encoder *encoder,
694 struct intel_crtc_state *crtc_state,
695 struct drm_connector_state *conn_state)
696{
697 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
698 struct drm_connector *connector = conn_state->connector;
699 const struct drm_display_mode *adjusted_mode =
700 &crtc_state->hw.adjusted_mode;
701
702 if (!connector->eld[0]) {
703 drm_dbg_kms(&i915->drm,
704 "Bogus ELD on [CONNECTOR:%d:%s]\n",
705 connector->base.id, connector->name);
706 return false;
707 }
708
709 BUILD_BUG_ON(sizeof(crtc_state->eld) != sizeof(connector->eld));
710 memcpy(crtc_state->eld, connector->eld, sizeof(crtc_state->eld));
711
712 crtc_state->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
713
714 return true;
715}
716
717/**
718 * intel_audio_codec_enable - Enable the audio codec for HD audio
719 * @encoder: encoder on which to enable audio
720 * @crtc_state: pointer to the current crtc state.
721 * @conn_state: pointer to the current connector state.
722 *
723 * The enable sequences may only be performed after enabling the transcoder and
724 * port, and after completed link training.
725 */
726void intel_audio_codec_enable(struct intel_encoder *encoder,
727 const struct intel_crtc_state *crtc_state,
728 const struct drm_connector_state *conn_state)
729{
730 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
731 struct i915_audio_component *acomp = i915->display.audio.component;
732 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
733 struct intel_connector *connector = to_intel_connector(conn_state->connector);
734 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
735 struct intel_audio_state *audio_state;
736 enum port port = encoder->port;
737
738 if (!crtc_state->has_audio)
739 return;
740
741 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s][ENCODER:%d:%s] Enable audio codec on [CRTC:%d:%s], %u bytes ELD\n",
742 connector->base.base.id, connector->base.name,
743 encoder->base.base.id, encoder->base.name,
744 crtc->base.base.id, crtc->base.name,
745 drm_eld_size(crtc_state->eld));
746
747 if (i915->display.funcs.audio)
748 i915->display.funcs.audio->audio_codec_enable(encoder,
749 crtc_state,
750 conn_state);
751
752 mutex_lock(&i915->display.audio.mutex);
753
754 audio_state = &i915->display.audio.state[cpu_transcoder];
755
756 audio_state->encoder = encoder;
757 BUILD_BUG_ON(sizeof(audio_state->eld) != sizeof(crtc_state->eld));
758 memcpy(audio_state->eld, crtc_state->eld, sizeof(audio_state->eld));
759
760 mutex_unlock(&i915->display.audio.mutex);
761
762 if (acomp && acomp->base.audio_ops &&
763 acomp->base.audio_ops->pin_eld_notify) {
764 /* audio drivers expect cpu_transcoder = -1 to indicate Non-MST cases */
765 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
766 cpu_transcoder = -1;
767 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr,
768 (int)port, (int)cpu_transcoder);
769 }
770
771 intel_lpe_audio_notify(i915, cpu_transcoder, port, crtc_state->eld,
772 crtc_state->port_clock,
773 intel_crtc_has_dp_encoder(crtc_state));
774}
775
776/**
777 * intel_audio_codec_disable - Disable the audio codec for HD audio
778 * @encoder: encoder on which to disable audio
779 * @old_crtc_state: pointer to the old crtc state.
780 * @old_conn_state: pointer to the old connector state.
781 *
782 * The disable sequences must be performed before disabling the transcoder or
783 * port.
784 */
785void intel_audio_codec_disable(struct intel_encoder *encoder,
786 const struct intel_crtc_state *old_crtc_state,
787 const struct drm_connector_state *old_conn_state)
788{
789 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
790 struct i915_audio_component *acomp = i915->display.audio.component;
791 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
792 struct intel_connector *connector = to_intel_connector(old_conn_state->connector);
793 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
794 struct intel_audio_state *audio_state;
795 enum port port = encoder->port;
796
797 if (!old_crtc_state->has_audio)
798 return;
799
800 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s][ENCODER:%d:%s] Disable audio codec on [CRTC:%d:%s]\n",
801 connector->base.base.id, connector->base.name,
802 encoder->base.base.id, encoder->base.name,
803 crtc->base.base.id, crtc->base.name);
804
805 if (i915->display.funcs.audio)
806 i915->display.funcs.audio->audio_codec_disable(encoder,
807 old_crtc_state,
808 old_conn_state);
809
810 mutex_lock(&i915->display.audio.mutex);
811
812 audio_state = &i915->display.audio.state[cpu_transcoder];
813
814 audio_state->encoder = NULL;
815 memset(audio_state->eld, 0, sizeof(audio_state->eld));
816
817 mutex_unlock(&i915->display.audio.mutex);
818
819 if (acomp && acomp->base.audio_ops &&
820 acomp->base.audio_ops->pin_eld_notify) {
821 /* audio drivers expect cpu_transcoder = -1 to indicate Non-MST cases */
822 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST))
823 cpu_transcoder = -1;
824 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr,
825 (int)port, (int)cpu_transcoder);
826 }
827
828 intel_lpe_audio_notify(i915, cpu_transcoder, port, NULL, 0, false);
829}
830
831static void intel_acomp_get_config(struct intel_encoder *encoder,
832 struct intel_crtc_state *crtc_state)
833{
834 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
835 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
836 struct intel_audio_state *audio_state;
837
838 mutex_lock(&i915->display.audio.mutex);
839
840 audio_state = &i915->display.audio.state[cpu_transcoder];
841
842 if (audio_state->encoder)
843 memcpy(crtc_state->eld, audio_state->eld, sizeof(audio_state->eld));
844
845 mutex_unlock(&i915->display.audio.mutex);
846}
847
848void intel_audio_codec_get_config(struct intel_encoder *encoder,
849 struct intel_crtc_state *crtc_state)
850{
851 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
852
853 if (!crtc_state->has_audio)
854 return;
855
856 if (i915->display.funcs.audio)
857 i915->display.funcs.audio->audio_codec_get_config(encoder, crtc_state);
858}
859
860static const struct intel_audio_funcs g4x_audio_funcs = {
861 .audio_codec_enable = g4x_audio_codec_enable,
862 .audio_codec_disable = g4x_audio_codec_disable,
863 .audio_codec_get_config = g4x_audio_codec_get_config,
864};
865
866static const struct intel_audio_funcs ibx_audio_funcs = {
867 .audio_codec_enable = ibx_audio_codec_enable,
868 .audio_codec_disable = ibx_audio_codec_disable,
869 .audio_codec_get_config = intel_acomp_get_config,
870};
871
872static const struct intel_audio_funcs hsw_audio_funcs = {
873 .audio_codec_enable = hsw_audio_codec_enable,
874 .audio_codec_disable = hsw_audio_codec_disable,
875 .audio_codec_get_config = intel_acomp_get_config,
876};
877
878/**
879 * intel_audio_hooks_init - Set up chip specific audio hooks
880 * @i915: device private
881 */
882void intel_audio_hooks_init(struct drm_i915_private *i915)
883{
884 if (IS_G4X(i915))
885 i915->display.funcs.audio = &g4x_audio_funcs;
886 else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915) ||
887 HAS_PCH_CPT(i915) || HAS_PCH_IBX(i915))
888 i915->display.funcs.audio = &ibx_audio_funcs;
889 else if (IS_HASWELL(i915) || DISPLAY_VER(i915) >= 8)
890 i915->display.funcs.audio = &hsw_audio_funcs;
891}
892
893struct aud_ts_cdclk_m_n {
894 u8 m;
895 u16 n;
896};
897
898void intel_audio_cdclk_change_pre(struct drm_i915_private *i915)
899{
900 if (DISPLAY_VER(i915) >= 13)
901 intel_de_rmw(i915, AUD_TS_CDCLK_M, AUD_TS_CDCLK_M_EN, 0);
902}
903
904static void get_aud_ts_cdclk_m_n(int refclk, int cdclk, struct aud_ts_cdclk_m_n *aud_ts)
905{
906 aud_ts->m = 60;
907 aud_ts->n = cdclk * aud_ts->m / 24000;
908}
909
910void intel_audio_cdclk_change_post(struct drm_i915_private *i915)
911{
912 struct aud_ts_cdclk_m_n aud_ts;
913
914 if (DISPLAY_VER(i915) >= 13) {
915 get_aud_ts_cdclk_m_n(i915->display.cdclk.hw.ref, i915->display.cdclk.hw.cdclk, &aud_ts);
916
917 intel_de_write(i915, AUD_TS_CDCLK_N, aud_ts.n);
918 intel_de_write(i915, AUD_TS_CDCLK_M, aud_ts.m | AUD_TS_CDCLK_M_EN);
919 drm_dbg_kms(&i915->drm, "aud_ts_cdclk set to M=%u, N=%u\n", aud_ts.m, aud_ts.n);
920 }
921}
922
923static int glk_force_audio_cdclk_commit(struct intel_atomic_state *state,
924 struct intel_crtc *crtc,
925 bool enable)
926{
927 struct intel_cdclk_state *cdclk_state;
928 int ret;
929
930 /* need to hold at least one crtc lock for the global state */
931 ret = drm_modeset_lock(&crtc->base.mutex, state->base.acquire_ctx);
932 if (ret)
933 return ret;
934
935 cdclk_state = intel_atomic_get_cdclk_state(state);
936 if (IS_ERR(cdclk_state))
937 return PTR_ERR(cdclk_state);
938
939 cdclk_state->force_min_cdclk = enable ? 2 * 96000 : 0;
940
941 return drm_atomic_commit(&state->base);
942}
943
944static void glk_force_audio_cdclk(struct drm_i915_private *i915,
945 bool enable)
946{
947 struct drm_modeset_acquire_ctx ctx;
948 struct drm_atomic_state *state;
949 struct intel_crtc *crtc;
950 int ret;
951
952 crtc = intel_first_crtc(i915);
953 if (!crtc)
954 return;
955
956 drm_modeset_acquire_init(&ctx, 0);
957 state = drm_atomic_state_alloc(&i915->drm);
958 if (drm_WARN_ON(&i915->drm, !state))
959 return;
960
961 state->acquire_ctx = &ctx;
962 to_intel_atomic_state(state)->internal = true;
963
964retry:
965 ret = glk_force_audio_cdclk_commit(to_intel_atomic_state(state), crtc,
966 enable);
967 if (ret == -EDEADLK) {
968 drm_atomic_state_clear(state);
969 drm_modeset_backoff(&ctx);
970 goto retry;
971 }
972
973 drm_WARN_ON(&i915->drm, ret);
974
975 drm_atomic_state_put(state);
976
977 drm_modeset_drop_locks(&ctx);
978 drm_modeset_acquire_fini(&ctx);
979}
980
981static unsigned long i915_audio_component_get_power(struct device *kdev)
982{
983 struct intel_display *display = to_intel_display(kdev);
984 struct drm_i915_private *i915 = to_i915(display->drm);
985 intel_wakeref_t wakeref;
986
987 /* Catch potential impedance mismatches before they occur! */
988 BUILD_BUG_ON(sizeof(intel_wakeref_t) > sizeof(unsigned long));
989
990 wakeref = intel_display_power_get(i915, POWER_DOMAIN_AUDIO_PLAYBACK);
991
992 if (i915->display.audio.power_refcount++ == 0) {
993 if (DISPLAY_VER(i915) >= 9) {
994 intel_de_write(i915, AUD_FREQ_CNTRL,
995 i915->display.audio.freq_cntrl);
996 drm_dbg_kms(&i915->drm,
997 "restored AUD_FREQ_CNTRL to 0x%x\n",
998 i915->display.audio.freq_cntrl);
999 }
1000
1001 /* Force CDCLK to 2*BCLK as long as we need audio powered. */
1002 if (IS_GEMINILAKE(i915))
1003 glk_force_audio_cdclk(i915, true);
1004
1005 if (DISPLAY_VER(i915) >= 10)
1006 intel_de_rmw(i915, AUD_PIN_BUF_CTL,
1007 0, AUD_PIN_BUF_ENABLE);
1008 }
1009
1010 return (unsigned long)wakeref;
1011}
1012
1013static void i915_audio_component_put_power(struct device *kdev,
1014 unsigned long cookie)
1015{
1016 struct intel_display *display = to_intel_display(kdev);
1017 struct drm_i915_private *i915 = to_i915(display->drm);
1018 intel_wakeref_t wakeref = (intel_wakeref_t)cookie;
1019
1020 /* Stop forcing CDCLK to 2*BCLK if no need for audio to be powered. */
1021 if (--i915->display.audio.power_refcount == 0)
1022 if (IS_GEMINILAKE(i915))
1023 glk_force_audio_cdclk(i915, false);
1024
1025 intel_display_power_put(i915, POWER_DOMAIN_AUDIO_PLAYBACK, wakeref);
1026}
1027
1028static void i915_audio_component_codec_wake_override(struct device *kdev,
1029 bool enable)
1030{
1031 struct intel_display *display = to_intel_display(kdev);
1032 struct drm_i915_private *i915 = to_i915(display->drm);
1033 unsigned long cookie;
1034
1035 if (DISPLAY_VER(i915) < 9)
1036 return;
1037
1038 cookie = i915_audio_component_get_power(kdev);
1039
1040 /*
1041 * Enable/disable generating the codec wake signal, overriding the
1042 * internal logic to generate the codec wake to controller.
1043 */
1044 intel_de_rmw(i915, HSW_AUD_CHICKENBIT,
1045 SKL_AUD_CODEC_WAKE_SIGNAL, 0);
1046 usleep_range(1000, 1500);
1047
1048 if (enable) {
1049 intel_de_rmw(i915, HSW_AUD_CHICKENBIT,
1050 0, SKL_AUD_CODEC_WAKE_SIGNAL);
1051 usleep_range(1000, 1500);
1052 }
1053
1054 i915_audio_component_put_power(kdev, cookie);
1055}
1056
1057/* Get CDCLK in kHz */
1058static int i915_audio_component_get_cdclk_freq(struct device *kdev)
1059{
1060 struct intel_display *display = to_intel_display(kdev);
1061 struct drm_i915_private *i915 = to_i915(display->drm);
1062
1063 if (drm_WARN_ON_ONCE(&i915->drm, !HAS_DDI(i915)))
1064 return -ENODEV;
1065
1066 return i915->display.cdclk.hw.cdclk;
1067}
1068
1069/*
1070 * get the intel audio state according to the parameter port and cpu_transcoder
1071 * MST & (cpu_transcoder >= 0): return the audio.state[cpu_transcoder].encoder],
1072 * when port is matched
1073 * MST & (cpu_transcoder < 0): this is invalid
1074 * Non-MST & (cpu_transcoder >= 0): only cpu_transcoder = 0 (the first device entry)
1075 * will get the right intel_encoder with port matched
1076 * Non-MST & (cpu_transcoder < 0): get the right intel_encoder with port matched
1077 */
1078static struct intel_audio_state *find_audio_state(struct drm_i915_private *i915,
1079 int port, int cpu_transcoder)
1080{
1081 /* MST */
1082 if (cpu_transcoder >= 0) {
1083 struct intel_audio_state *audio_state;
1084 struct intel_encoder *encoder;
1085
1086 if (drm_WARN_ON(&i915->drm,
1087 cpu_transcoder >= ARRAY_SIZE(i915->display.audio.state)))
1088 return NULL;
1089
1090 audio_state = &i915->display.audio.state[cpu_transcoder];
1091 encoder = audio_state->encoder;
1092
1093 if (encoder && encoder->port == port &&
1094 encoder->type == INTEL_OUTPUT_DP_MST)
1095 return audio_state;
1096 }
1097
1098 /* Non-MST */
1099 if (cpu_transcoder > 0)
1100 return NULL;
1101
1102 for_each_cpu_transcoder(i915, cpu_transcoder) {
1103 struct intel_audio_state *audio_state;
1104 struct intel_encoder *encoder;
1105
1106 audio_state = &i915->display.audio.state[cpu_transcoder];
1107 encoder = audio_state->encoder;
1108
1109 if (encoder && encoder->port == port &&
1110 encoder->type != INTEL_OUTPUT_DP_MST)
1111 return audio_state;
1112 }
1113
1114 return NULL;
1115}
1116
1117static int i915_audio_component_sync_audio_rate(struct device *kdev, int port,
1118 int cpu_transcoder, int rate)
1119{
1120 struct intel_display *display = to_intel_display(kdev);
1121 struct drm_i915_private *i915 = to_i915(display->drm);
1122 struct i915_audio_component *acomp = i915->display.audio.component;
1123 const struct intel_audio_state *audio_state;
1124 struct intel_encoder *encoder;
1125 struct intel_crtc *crtc;
1126 unsigned long cookie;
1127 int err = 0;
1128
1129 if (!HAS_DDI(i915))
1130 return 0;
1131
1132 cookie = i915_audio_component_get_power(kdev);
1133 mutex_lock(&i915->display.audio.mutex);
1134
1135 audio_state = find_audio_state(i915, port, cpu_transcoder);
1136 if (!audio_state) {
1137 drm_dbg_kms(&i915->drm, "Not valid for port %c\n", port_name(port));
1138 err = -ENODEV;
1139 goto unlock;
1140 }
1141
1142 encoder = audio_state->encoder;
1143
1144 /* FIXME stop using the legacy crtc pointer */
1145 crtc = to_intel_crtc(encoder->base.crtc);
1146
1147 /* port must be valid now, otherwise the cpu_transcoder will be invalid */
1148 acomp->aud_sample_rate[port] = rate;
1149
1150 /* FIXME get rid of the crtc->config stuff */
1151 hsw_audio_config_update(encoder, crtc->config);
1152
1153 unlock:
1154 mutex_unlock(&i915->display.audio.mutex);
1155 i915_audio_component_put_power(kdev, cookie);
1156 return err;
1157}
1158
1159static int i915_audio_component_get_eld(struct device *kdev, int port,
1160 int cpu_transcoder, bool *enabled,
1161 unsigned char *buf, int max_bytes)
1162{
1163 struct intel_display *display = to_intel_display(kdev);
1164 struct drm_i915_private *i915 = to_i915(display->drm);
1165 const struct intel_audio_state *audio_state;
1166 int ret = 0;
1167
1168 mutex_lock(&i915->display.audio.mutex);
1169
1170 audio_state = find_audio_state(i915, port, cpu_transcoder);
1171 if (!audio_state) {
1172 drm_dbg_kms(&i915->drm, "Not valid for port %c\n", port_name(port));
1173 mutex_unlock(&i915->display.audio.mutex);
1174 return -EINVAL;
1175 }
1176
1177 *enabled = audio_state->encoder != NULL;
1178 if (*enabled) {
1179 const u8 *eld = audio_state->eld;
1180
1181 ret = drm_eld_size(eld);
1182 memcpy(buf, eld, min(max_bytes, ret));
1183 }
1184
1185 mutex_unlock(&i915->display.audio.mutex);
1186 return ret;
1187}
1188
1189static const struct drm_audio_component_ops i915_audio_component_ops = {
1190 .owner = THIS_MODULE,
1191 .get_power = i915_audio_component_get_power,
1192 .put_power = i915_audio_component_put_power,
1193 .codec_wake_override = i915_audio_component_codec_wake_override,
1194 .get_cdclk_freq = i915_audio_component_get_cdclk_freq,
1195 .sync_audio_rate = i915_audio_component_sync_audio_rate,
1196 .get_eld = i915_audio_component_get_eld,
1197};
1198
1199static int i915_audio_component_bind(struct device *drv_kdev,
1200 struct device *hda_kdev, void *data)
1201{
1202 struct intel_display *display = to_intel_display(drv_kdev);
1203 struct drm_i915_private *i915 = to_i915(display->drm);
1204 struct i915_audio_component *acomp = data;
1205 int i;
1206
1207 if (drm_WARN_ON(&i915->drm, acomp->base.ops || acomp->base.dev))
1208 return -EEXIST;
1209
1210 if (drm_WARN_ON(&i915->drm,
1211 !device_link_add(hda_kdev, drv_kdev,
1212 DL_FLAG_STATELESS)))
1213 return -ENOMEM;
1214
1215 drm_modeset_lock_all(&i915->drm);
1216 acomp->base.ops = &i915_audio_component_ops;
1217 acomp->base.dev = drv_kdev;
1218 BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS);
1219 for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++)
1220 acomp->aud_sample_rate[i] = 0;
1221 i915->display.audio.component = acomp;
1222 drm_modeset_unlock_all(&i915->drm);
1223
1224 return 0;
1225}
1226
1227static void i915_audio_component_unbind(struct device *drv_kdev,
1228 struct device *hda_kdev, void *data)
1229{
1230 struct intel_display *display = to_intel_display(drv_kdev);
1231 struct drm_i915_private *i915 = to_i915(display->drm);
1232 struct i915_audio_component *acomp = data;
1233
1234 drm_modeset_lock_all(&i915->drm);
1235 acomp->base.ops = NULL;
1236 acomp->base.dev = NULL;
1237 i915->display.audio.component = NULL;
1238 drm_modeset_unlock_all(&i915->drm);
1239
1240 device_link_remove(hda_kdev, drv_kdev);
1241
1242 if (i915->display.audio.power_refcount)
1243 drm_err(&i915->drm, "audio power refcount %d after unbind\n",
1244 i915->display.audio.power_refcount);
1245}
1246
1247static const struct component_ops i915_audio_component_bind_ops = {
1248 .bind = i915_audio_component_bind,
1249 .unbind = i915_audio_component_unbind,
1250};
1251
1252#define AUD_FREQ_TMODE_SHIFT 14
1253#define AUD_FREQ_4T 0
1254#define AUD_FREQ_8T (2 << AUD_FREQ_TMODE_SHIFT)
1255#define AUD_FREQ_PULLCLKS(x) (((x) & 0x3) << 11)
1256#define AUD_FREQ_BCLK_96M BIT(4)
1257
1258#define AUD_FREQ_GEN12 (AUD_FREQ_8T | AUD_FREQ_PULLCLKS(0) | AUD_FREQ_BCLK_96M)
1259#define AUD_FREQ_TGL_BROKEN (AUD_FREQ_8T | AUD_FREQ_PULLCLKS(2) | AUD_FREQ_BCLK_96M)
1260
1261/**
1262 * i915_audio_component_init - initialize and register the audio component
1263 * @i915: i915 device instance
1264 *
1265 * This will register with the component framework a child component which
1266 * will bind dynamically to the snd_hda_intel driver's corresponding master
1267 * component when the latter is registered. During binding the child
1268 * initializes an instance of struct i915_audio_component which it receives
1269 * from the master. The master can then start to use the interface defined by
1270 * this struct. Each side can break the binding at any point by deregistering
1271 * its own component after which each side's component unbind callback is
1272 * called.
1273 *
1274 * We ignore any error during registration and continue with reduced
1275 * functionality (i.e. without HDMI audio).
1276 */
1277static void i915_audio_component_init(struct drm_i915_private *i915)
1278{
1279 u32 aud_freq, aud_freq_init;
1280
1281 if (DISPLAY_VER(i915) >= 9) {
1282 aud_freq_init = intel_de_read(i915, AUD_FREQ_CNTRL);
1283
1284 if (DISPLAY_VER(i915) >= 12)
1285 aud_freq = AUD_FREQ_GEN12;
1286 else
1287 aud_freq = aud_freq_init;
1288
1289 /* use BIOS provided value for TGL and RKL unless it is a known bad value */
1290 if ((IS_TIGERLAKE(i915) || IS_ROCKETLAKE(i915)) &&
1291 aud_freq_init != AUD_FREQ_TGL_BROKEN)
1292 aud_freq = aud_freq_init;
1293
1294 drm_dbg_kms(&i915->drm, "use AUD_FREQ_CNTRL of 0x%x (init value 0x%x)\n",
1295 aud_freq, aud_freq_init);
1296
1297 i915->display.audio.freq_cntrl = aud_freq;
1298 }
1299
1300 /* init with current cdclk */
1301 intel_audio_cdclk_change_post(i915);
1302}
1303
1304static void i915_audio_component_register(struct drm_i915_private *i915)
1305{
1306 int ret;
1307
1308 ret = component_add_typed(i915->drm.dev,
1309 &i915_audio_component_bind_ops,
1310 I915_COMPONENT_AUDIO);
1311 if (ret < 0) {
1312 drm_err(&i915->drm,
1313 "failed to add audio component (%d)\n", ret);
1314 /* continue with reduced functionality */
1315 return;
1316 }
1317
1318 i915->display.audio.component_registered = true;
1319}
1320
1321/**
1322 * i915_audio_component_cleanup - deregister the audio component
1323 * @i915: i915 device instance
1324 *
1325 * Deregisters the audio component, breaking any existing binding to the
1326 * corresponding snd_hda_intel driver's master component.
1327 */
1328static void i915_audio_component_cleanup(struct drm_i915_private *i915)
1329{
1330 if (!i915->display.audio.component_registered)
1331 return;
1332
1333 component_del(i915->drm.dev, &i915_audio_component_bind_ops);
1334 i915->display.audio.component_registered = false;
1335}
1336
1337/**
1338 * intel_audio_init() - Initialize the audio driver either using
1339 * component framework or using lpe audio bridge
1340 * @i915: the i915 drm device private data
1341 *
1342 */
1343void intel_audio_init(struct drm_i915_private *i915)
1344{
1345 if (intel_lpe_audio_init(i915) < 0)
1346 i915_audio_component_init(i915);
1347}
1348
1349void intel_audio_register(struct drm_i915_private *i915)
1350{
1351 if (!i915->display.audio.lpe.platdev)
1352 i915_audio_component_register(i915);
1353}
1354
1355/**
1356 * intel_audio_deinit() - deinitialize the audio driver
1357 * @i915: the i915 drm device private data
1358 *
1359 */
1360void intel_audio_deinit(struct drm_i915_private *i915)
1361{
1362 if (i915->display.audio.lpe.platdev != NULL)
1363 intel_lpe_audio_teardown(i915);
1364 else
1365 i915_audio_component_cleanup(i915);
1366}