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1/*
2 * linux/arch/arm/plat-pxa/gpio.c
3 *
4 * Generic PXA GPIO handling
5 *
6 * Author: Nicolas Pitre
7 * Created: Jun 15, 2001
8 * Copyright: MontaVista Software Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14#include <linux/module.h>
15#include <linux/clk.h>
16#include <linux/err.h>
17#include <linux/gpio.h>
18#include <linux/gpio-pxa.h>
19#include <linux/init.h>
20#include <linux/interrupt.h>
21#include <linux/irq.h>
22#include <linux/irqdomain.h>
23#include <linux/irqchip/chained_irq.h>
24#include <linux/io.h>
25#include <linux/of.h>
26#include <linux/of_device.h>
27#include <linux/pinctrl/consumer.h>
28#include <linux/platform_device.h>
29#include <linux/syscore_ops.h>
30#include <linux/slab.h>
31
32/*
33 * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with
34 * one set of registers. The register offsets are organized below:
35 *
36 * GPLR GPDR GPSR GPCR GRER GFER GEDR
37 * BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048
38 * BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C
39 * BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050
40 *
41 * BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148
42 * BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C
43 * BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150
44 *
45 * BANK 6 - 0x0200 0x020C 0x0218 0x0224 0x0230 0x023C 0x0248
46 *
47 * NOTE:
48 * BANK 3 is only available on PXA27x and later processors.
49 * BANK 4 and 5 are only available on PXA935, PXA1928
50 * BANK 6 is only available on PXA1928
51 */
52
53#define GPLR_OFFSET 0x00
54#define GPDR_OFFSET 0x0C
55#define GPSR_OFFSET 0x18
56#define GPCR_OFFSET 0x24
57#define GRER_OFFSET 0x30
58#define GFER_OFFSET 0x3C
59#define GEDR_OFFSET 0x48
60#define GAFR_OFFSET 0x54
61#define ED_MASK_OFFSET 0x9C /* GPIO edge detection for AP side */
62
63#define BANK_OFF(n) (((n) / 3) << 8) + (((n) % 3) << 2)
64
65int pxa_last_gpio;
66static int irq_base;
67
68struct pxa_gpio_bank {
69 void __iomem *regbase;
70 unsigned long irq_mask;
71 unsigned long irq_edge_rise;
72 unsigned long irq_edge_fall;
73
74#ifdef CONFIG_PM
75 unsigned long saved_gplr;
76 unsigned long saved_gpdr;
77 unsigned long saved_grer;
78 unsigned long saved_gfer;
79#endif
80};
81
82struct pxa_gpio_chip {
83 struct device *dev;
84 struct gpio_chip chip;
85 struct pxa_gpio_bank *banks;
86 struct irq_domain *irqdomain;
87
88 int irq0;
89 int irq1;
90 int (*set_wake)(unsigned int gpio, unsigned int on);
91};
92
93enum pxa_gpio_type {
94 PXA25X_GPIO = 0,
95 PXA26X_GPIO,
96 PXA27X_GPIO,
97 PXA3XX_GPIO,
98 PXA93X_GPIO,
99 MMP_GPIO = 0x10,
100 MMP2_GPIO,
101 PXA1928_GPIO,
102};
103
104struct pxa_gpio_id {
105 enum pxa_gpio_type type;
106 int gpio_nums;
107};
108
109static DEFINE_SPINLOCK(gpio_lock);
110static struct pxa_gpio_chip *pxa_gpio_chip;
111static enum pxa_gpio_type gpio_type;
112
113static struct pxa_gpio_id pxa25x_id = {
114 .type = PXA25X_GPIO,
115 .gpio_nums = 85,
116};
117
118static struct pxa_gpio_id pxa26x_id = {
119 .type = PXA26X_GPIO,
120 .gpio_nums = 90,
121};
122
123static struct pxa_gpio_id pxa27x_id = {
124 .type = PXA27X_GPIO,
125 .gpio_nums = 121,
126};
127
128static struct pxa_gpio_id pxa3xx_id = {
129 .type = PXA3XX_GPIO,
130 .gpio_nums = 128,
131};
132
133static struct pxa_gpio_id pxa93x_id = {
134 .type = PXA93X_GPIO,
135 .gpio_nums = 192,
136};
137
138static struct pxa_gpio_id mmp_id = {
139 .type = MMP_GPIO,
140 .gpio_nums = 128,
141};
142
143static struct pxa_gpio_id mmp2_id = {
144 .type = MMP2_GPIO,
145 .gpio_nums = 192,
146};
147
148static struct pxa_gpio_id pxa1928_id = {
149 .type = PXA1928_GPIO,
150 .gpio_nums = 224,
151};
152
153#define for_each_gpio_bank(i, b, pc) \
154 for (i = 0, b = pc->banks; i <= pxa_last_gpio; i += 32, b++)
155
156static inline struct pxa_gpio_chip *chip_to_pxachip(struct gpio_chip *c)
157{
158 struct pxa_gpio_chip *pxa_chip = gpiochip_get_data(c);
159
160 return pxa_chip;
161}
162
163static inline void __iomem *gpio_bank_base(struct gpio_chip *c, int gpio)
164{
165 struct pxa_gpio_chip *p = gpiochip_get_data(c);
166 struct pxa_gpio_bank *bank = p->banks + (gpio / 32);
167
168 return bank->regbase;
169}
170
171static inline struct pxa_gpio_bank *gpio_to_pxabank(struct gpio_chip *c,
172 unsigned gpio)
173{
174 return chip_to_pxachip(c)->banks + gpio / 32;
175}
176
177static inline int gpio_is_pxa_type(int type)
178{
179 return (type & MMP_GPIO) == 0;
180}
181
182static inline int gpio_is_mmp_type(int type)
183{
184 return (type & MMP_GPIO) != 0;
185}
186
187/* GPIO86/87/88/89 on PXA26x have their direction bits in PXA_GPDR(2 inverted,
188 * as well as their Alternate Function value being '1' for GPIO in GAFRx.
189 */
190static inline int __gpio_is_inverted(int gpio)
191{
192 if ((gpio_type == PXA26X_GPIO) && (gpio > 85))
193 return 1;
194 return 0;
195}
196
197/*
198 * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate
199 * function of a GPIO, and GPDRx cannot be altered once configured. It
200 * is attributed as "occupied" here (I know this terminology isn't
201 * accurate, you are welcome to propose a better one :-)
202 */
203static inline int __gpio_is_occupied(struct pxa_gpio_chip *pchip, unsigned gpio)
204{
205 void __iomem *base;
206 unsigned long gafr = 0, gpdr = 0;
207 int ret, af = 0, dir = 0;
208
209 base = gpio_bank_base(&pchip->chip, gpio);
210 gpdr = readl_relaxed(base + GPDR_OFFSET);
211
212 switch (gpio_type) {
213 case PXA25X_GPIO:
214 case PXA26X_GPIO:
215 case PXA27X_GPIO:
216 gafr = readl_relaxed(base + GAFR_OFFSET);
217 af = (gafr >> ((gpio & 0xf) * 2)) & 0x3;
218 dir = gpdr & GPIO_bit(gpio);
219
220 if (__gpio_is_inverted(gpio))
221 ret = (af != 1) || (dir == 0);
222 else
223 ret = (af != 0) || (dir != 0);
224 break;
225 default:
226 ret = gpdr & GPIO_bit(gpio);
227 break;
228 }
229 return ret;
230}
231
232int pxa_irq_to_gpio(int irq)
233{
234 struct pxa_gpio_chip *pchip = pxa_gpio_chip;
235 int irq_gpio0;
236
237 irq_gpio0 = irq_find_mapping(pchip->irqdomain, 0);
238 if (irq_gpio0 > 0)
239 return irq - irq_gpio0;
240
241 return irq_gpio0;
242}
243
244static int pxa_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
245{
246 struct pxa_gpio_chip *pchip = chip_to_pxachip(chip);
247
248 return irq_find_mapping(pchip->irqdomain, offset);
249}
250
251static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
252{
253 void __iomem *base = gpio_bank_base(chip, offset);
254 uint32_t value, mask = GPIO_bit(offset);
255 unsigned long flags;
256 int ret;
257
258 ret = pinctrl_gpio_direction_input(chip->base + offset);
259 if (!ret)
260 return 0;
261
262 spin_lock_irqsave(&gpio_lock, flags);
263
264 value = readl_relaxed(base + GPDR_OFFSET);
265 if (__gpio_is_inverted(chip->base + offset))
266 value |= mask;
267 else
268 value &= ~mask;
269 writel_relaxed(value, base + GPDR_OFFSET);
270
271 spin_unlock_irqrestore(&gpio_lock, flags);
272 return 0;
273}
274
275static int pxa_gpio_direction_output(struct gpio_chip *chip,
276 unsigned offset, int value)
277{
278 void __iomem *base = gpio_bank_base(chip, offset);
279 uint32_t tmp, mask = GPIO_bit(offset);
280 unsigned long flags;
281 int ret;
282
283 writel_relaxed(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET));
284
285 ret = pinctrl_gpio_direction_output(chip->base + offset);
286 if (ret)
287 return ret;
288
289 spin_lock_irqsave(&gpio_lock, flags);
290
291 tmp = readl_relaxed(base + GPDR_OFFSET);
292 if (__gpio_is_inverted(chip->base + offset))
293 tmp &= ~mask;
294 else
295 tmp |= mask;
296 writel_relaxed(tmp, base + GPDR_OFFSET);
297
298 spin_unlock_irqrestore(&gpio_lock, flags);
299 return 0;
300}
301
302static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset)
303{
304 void __iomem *base = gpio_bank_base(chip, offset);
305 u32 gplr = readl_relaxed(base + GPLR_OFFSET);
306
307 return !!(gplr & GPIO_bit(offset));
308}
309
310static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
311{
312 void __iomem *base = gpio_bank_base(chip, offset);
313
314 writel_relaxed(GPIO_bit(offset),
315 base + (value ? GPSR_OFFSET : GPCR_OFFSET));
316}
317
318#ifdef CONFIG_OF_GPIO
319static int pxa_gpio_of_xlate(struct gpio_chip *gc,
320 const struct of_phandle_args *gpiospec,
321 u32 *flags)
322{
323 if (gpiospec->args[0] > pxa_last_gpio)
324 return -EINVAL;
325
326 if (flags)
327 *flags = gpiospec->args[1];
328
329 return gpiospec->args[0];
330}
331#endif
332
333static int pxa_gpio_request(struct gpio_chip *chip, unsigned int offset)
334{
335 return pinctrl_request_gpio(chip->base + offset);
336}
337
338static void pxa_gpio_free(struct gpio_chip *chip, unsigned int offset)
339{
340 pinctrl_free_gpio(chip->base + offset);
341}
342
343static int pxa_init_gpio_chip(struct pxa_gpio_chip *pchip, int ngpio,
344 struct device_node *np, void __iomem *regbase)
345{
346 int i, gpio, nbanks = DIV_ROUND_UP(ngpio, 32);
347 struct pxa_gpio_bank *bank;
348
349 pchip->banks = devm_kcalloc(pchip->dev, nbanks, sizeof(*pchip->banks),
350 GFP_KERNEL);
351 if (!pchip->banks)
352 return -ENOMEM;
353
354 pchip->chip.label = "gpio-pxa";
355 pchip->chip.direction_input = pxa_gpio_direction_input;
356 pchip->chip.direction_output = pxa_gpio_direction_output;
357 pchip->chip.get = pxa_gpio_get;
358 pchip->chip.set = pxa_gpio_set;
359 pchip->chip.to_irq = pxa_gpio_to_irq;
360 pchip->chip.ngpio = ngpio;
361 pchip->chip.request = pxa_gpio_request;
362 pchip->chip.free = pxa_gpio_free;
363#ifdef CONFIG_OF_GPIO
364 pchip->chip.of_node = np;
365 pchip->chip.of_xlate = pxa_gpio_of_xlate;
366 pchip->chip.of_gpio_n_cells = 2;
367#endif
368
369 for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) {
370 bank = pchip->banks + i;
371 bank->regbase = regbase + BANK_OFF(i);
372 }
373
374 return gpiochip_add_data(&pchip->chip, pchip);
375}
376
377/* Update only those GRERx and GFERx edge detection register bits if those
378 * bits are set in c->irq_mask
379 */
380static inline void update_edge_detect(struct pxa_gpio_bank *c)
381{
382 uint32_t grer, gfer;
383
384 grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~c->irq_mask;
385 gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~c->irq_mask;
386 grer |= c->irq_edge_rise & c->irq_mask;
387 gfer |= c->irq_edge_fall & c->irq_mask;
388 writel_relaxed(grer, c->regbase + GRER_OFFSET);
389 writel_relaxed(gfer, c->regbase + GFER_OFFSET);
390}
391
392static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type)
393{
394 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
395 unsigned int gpio = irqd_to_hwirq(d);
396 struct pxa_gpio_bank *c = gpio_to_pxabank(&pchip->chip, gpio);
397 unsigned long gpdr, mask = GPIO_bit(gpio);
398
399 if (type == IRQ_TYPE_PROBE) {
400 /* Don't mess with enabled GPIOs using preconfigured edges or
401 * GPIOs set to alternate function or to output during probe
402 */
403 if ((c->irq_edge_rise | c->irq_edge_fall) & GPIO_bit(gpio))
404 return 0;
405
406 if (__gpio_is_occupied(pchip, gpio))
407 return 0;
408
409 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
410 }
411
412 gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
413
414 if (__gpio_is_inverted(gpio))
415 writel_relaxed(gpdr | mask, c->regbase + GPDR_OFFSET);
416 else
417 writel_relaxed(gpdr & ~mask, c->regbase + GPDR_OFFSET);
418
419 if (type & IRQ_TYPE_EDGE_RISING)
420 c->irq_edge_rise |= mask;
421 else
422 c->irq_edge_rise &= ~mask;
423
424 if (type & IRQ_TYPE_EDGE_FALLING)
425 c->irq_edge_fall |= mask;
426 else
427 c->irq_edge_fall &= ~mask;
428
429 update_edge_detect(c);
430
431 pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, d->irq, gpio,
432 ((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""),
433 ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : ""));
434 return 0;
435}
436
437static irqreturn_t pxa_gpio_demux_handler(int in_irq, void *d)
438{
439 int loop, gpio, n, handled = 0;
440 unsigned long gedr;
441 struct pxa_gpio_chip *pchip = d;
442 struct pxa_gpio_bank *c;
443
444 do {
445 loop = 0;
446 for_each_gpio_bank(gpio, c, pchip) {
447 gedr = readl_relaxed(c->regbase + GEDR_OFFSET);
448 gedr = gedr & c->irq_mask;
449 writel_relaxed(gedr, c->regbase + GEDR_OFFSET);
450
451 for_each_set_bit(n, &gedr, BITS_PER_LONG) {
452 loop = 1;
453
454 generic_handle_irq(gpio_to_irq(gpio + n));
455 }
456 }
457 handled += loop;
458 } while (loop);
459
460 return handled ? IRQ_HANDLED : IRQ_NONE;
461}
462
463static irqreturn_t pxa_gpio_direct_handler(int in_irq, void *d)
464{
465 struct pxa_gpio_chip *pchip = d;
466
467 if (in_irq == pchip->irq0) {
468 generic_handle_irq(gpio_to_irq(0));
469 } else if (in_irq == pchip->irq1) {
470 generic_handle_irq(gpio_to_irq(1));
471 } else {
472 pr_err("%s() unknown irq %d\n", __func__, in_irq);
473 return IRQ_NONE;
474 }
475 return IRQ_HANDLED;
476}
477
478static void pxa_ack_muxed_gpio(struct irq_data *d)
479{
480 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
481 unsigned int gpio = irqd_to_hwirq(d);
482 void __iomem *base = gpio_bank_base(&pchip->chip, gpio);
483
484 writel_relaxed(GPIO_bit(gpio), base + GEDR_OFFSET);
485}
486
487static void pxa_mask_muxed_gpio(struct irq_data *d)
488{
489 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
490 unsigned int gpio = irqd_to_hwirq(d);
491 struct pxa_gpio_bank *b = gpio_to_pxabank(&pchip->chip, gpio);
492 void __iomem *base = gpio_bank_base(&pchip->chip, gpio);
493 uint32_t grer, gfer;
494
495 b->irq_mask &= ~GPIO_bit(gpio);
496
497 grer = readl_relaxed(base + GRER_OFFSET) & ~GPIO_bit(gpio);
498 gfer = readl_relaxed(base + GFER_OFFSET) & ~GPIO_bit(gpio);
499 writel_relaxed(grer, base + GRER_OFFSET);
500 writel_relaxed(gfer, base + GFER_OFFSET);
501}
502
503static int pxa_gpio_set_wake(struct irq_data *d, unsigned int on)
504{
505 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
506 unsigned int gpio = irqd_to_hwirq(d);
507
508 if (pchip->set_wake)
509 return pchip->set_wake(gpio, on);
510 else
511 return 0;
512}
513
514static void pxa_unmask_muxed_gpio(struct irq_data *d)
515{
516 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
517 unsigned int gpio = irqd_to_hwirq(d);
518 struct pxa_gpio_bank *c = gpio_to_pxabank(&pchip->chip, gpio);
519
520 c->irq_mask |= GPIO_bit(gpio);
521 update_edge_detect(c);
522}
523
524static struct irq_chip pxa_muxed_gpio_chip = {
525 .name = "GPIO",
526 .irq_ack = pxa_ack_muxed_gpio,
527 .irq_mask = pxa_mask_muxed_gpio,
528 .irq_unmask = pxa_unmask_muxed_gpio,
529 .irq_set_type = pxa_gpio_irq_type,
530 .irq_set_wake = pxa_gpio_set_wake,
531};
532
533static int pxa_gpio_nums(struct platform_device *pdev)
534{
535 const struct platform_device_id *id = platform_get_device_id(pdev);
536 struct pxa_gpio_id *pxa_id = (struct pxa_gpio_id *)id->driver_data;
537 int count = 0;
538
539 switch (pxa_id->type) {
540 case PXA25X_GPIO:
541 case PXA26X_GPIO:
542 case PXA27X_GPIO:
543 case PXA3XX_GPIO:
544 case PXA93X_GPIO:
545 case MMP_GPIO:
546 case MMP2_GPIO:
547 case PXA1928_GPIO:
548 gpio_type = pxa_id->type;
549 count = pxa_id->gpio_nums - 1;
550 break;
551 default:
552 count = -EINVAL;
553 break;
554 }
555 return count;
556}
557
558static int pxa_irq_domain_map(struct irq_domain *d, unsigned int irq,
559 irq_hw_number_t hw)
560{
561 irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
562 handle_edge_irq);
563 irq_set_chip_data(irq, d->host_data);
564 irq_set_noprobe(irq);
565 return 0;
566}
567
568const struct irq_domain_ops pxa_irq_domain_ops = {
569 .map = pxa_irq_domain_map,
570 .xlate = irq_domain_xlate_twocell,
571};
572
573#ifdef CONFIG_OF
574static const struct of_device_id pxa_gpio_dt_ids[] = {
575 { .compatible = "intel,pxa25x-gpio", .data = &pxa25x_id, },
576 { .compatible = "intel,pxa26x-gpio", .data = &pxa26x_id, },
577 { .compatible = "intel,pxa27x-gpio", .data = &pxa27x_id, },
578 { .compatible = "intel,pxa3xx-gpio", .data = &pxa3xx_id, },
579 { .compatible = "marvell,pxa93x-gpio", .data = &pxa93x_id, },
580 { .compatible = "marvell,mmp-gpio", .data = &mmp_id, },
581 { .compatible = "marvell,mmp2-gpio", .data = &mmp2_id, },
582 { .compatible = "marvell,pxa1928-gpio", .data = &pxa1928_id, },
583 {}
584};
585
586static int pxa_gpio_probe_dt(struct platform_device *pdev,
587 struct pxa_gpio_chip *pchip)
588{
589 int nr_gpios;
590 const struct of_device_id *of_id =
591 of_match_device(pxa_gpio_dt_ids, &pdev->dev);
592 const struct pxa_gpio_id *gpio_id;
593
594 if (!of_id || !of_id->data) {
595 dev_err(&pdev->dev, "Failed to find gpio controller\n");
596 return -EFAULT;
597 }
598 gpio_id = of_id->data;
599 gpio_type = gpio_id->type;
600
601 nr_gpios = gpio_id->gpio_nums;
602 pxa_last_gpio = nr_gpios - 1;
603
604 irq_base = irq_alloc_descs(-1, 0, nr_gpios, 0);
605 if (irq_base < 0) {
606 dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n");
607 return irq_base;
608 }
609 return irq_base;
610}
611#else
612#define pxa_gpio_probe_dt(pdev, pchip) (-1)
613#endif
614
615static int pxa_gpio_probe(struct platform_device *pdev)
616{
617 struct pxa_gpio_chip *pchip;
618 struct pxa_gpio_bank *c;
619 struct resource *res;
620 struct clk *clk;
621 struct pxa_gpio_platform_data *info;
622 void __iomem *gpio_reg_base;
623 int gpio, ret;
624 int irq0 = 0, irq1 = 0, irq_mux, gpio_offset = 0;
625
626 pchip = devm_kzalloc(&pdev->dev, sizeof(*pchip), GFP_KERNEL);
627 if (!pchip)
628 return -ENOMEM;
629 pchip->dev = &pdev->dev;
630
631 info = dev_get_platdata(&pdev->dev);
632 if (info) {
633 irq_base = info->irq_base;
634 if (irq_base <= 0)
635 return -EINVAL;
636 pxa_last_gpio = pxa_gpio_nums(pdev);
637 pchip->set_wake = info->gpio_set_wake;
638 } else {
639 irq_base = pxa_gpio_probe_dt(pdev, pchip);
640 if (irq_base < 0)
641 return -EINVAL;
642 }
643
644 if (!pxa_last_gpio)
645 return -EINVAL;
646
647 pchip->irqdomain = irq_domain_add_legacy(pdev->dev.of_node,
648 pxa_last_gpio + 1, irq_base,
649 0, &pxa_irq_domain_ops, pchip);
650 if (!pchip->irqdomain)
651 return -ENOMEM;
652
653 irq0 = platform_get_irq_byname(pdev, "gpio0");
654 irq1 = platform_get_irq_byname(pdev, "gpio1");
655 irq_mux = platform_get_irq_byname(pdev, "gpio_mux");
656 if ((irq0 > 0 && irq1 <= 0) || (irq0 <= 0 && irq1 > 0)
657 || (irq_mux <= 0))
658 return -EINVAL;
659
660 pchip->irq0 = irq0;
661 pchip->irq1 = irq1;
662 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
663 gpio_reg_base = devm_ioremap(&pdev->dev, res->start,
664 resource_size(res));
665 if (!gpio_reg_base)
666 return -EINVAL;
667
668 if (irq0 > 0)
669 gpio_offset = 2;
670
671 clk = clk_get(&pdev->dev, NULL);
672 if (IS_ERR(clk)) {
673 dev_err(&pdev->dev, "Error %ld to get gpio clock\n",
674 PTR_ERR(clk));
675 return PTR_ERR(clk);
676 }
677 ret = clk_prepare_enable(clk);
678 if (ret) {
679 clk_put(clk);
680 return ret;
681 }
682
683 /* Initialize GPIO chips */
684 ret = pxa_init_gpio_chip(pchip, pxa_last_gpio + 1, pdev->dev.of_node,
685 gpio_reg_base);
686 if (ret) {
687 clk_put(clk);
688 return ret;
689 }
690
691 /* clear all GPIO edge detects */
692 for_each_gpio_bank(gpio, c, pchip) {
693 writel_relaxed(0, c->regbase + GFER_OFFSET);
694 writel_relaxed(0, c->regbase + GRER_OFFSET);
695 writel_relaxed(~0, c->regbase + GEDR_OFFSET);
696 /* unmask GPIO edge detect for AP side */
697 if (gpio_is_mmp_type(gpio_type))
698 writel_relaxed(~0, c->regbase + ED_MASK_OFFSET);
699 }
700
701 if (irq0 > 0) {
702 ret = devm_request_irq(&pdev->dev,
703 irq0, pxa_gpio_direct_handler, 0,
704 "gpio-0", pchip);
705 if (ret)
706 dev_err(&pdev->dev, "request of gpio0 irq failed: %d\n",
707 ret);
708 }
709 if (irq1 > 0) {
710 ret = devm_request_irq(&pdev->dev,
711 irq1, pxa_gpio_direct_handler, 0,
712 "gpio-1", pchip);
713 if (ret)
714 dev_err(&pdev->dev, "request of gpio1 irq failed: %d\n",
715 ret);
716 }
717 ret = devm_request_irq(&pdev->dev,
718 irq_mux, pxa_gpio_demux_handler, 0,
719 "gpio-mux", pchip);
720 if (ret)
721 dev_err(&pdev->dev, "request of gpio-mux irq failed: %d\n",
722 ret);
723
724 pxa_gpio_chip = pchip;
725
726 return 0;
727}
728
729static const struct platform_device_id gpio_id_table[] = {
730 { "pxa25x-gpio", (unsigned long)&pxa25x_id },
731 { "pxa26x-gpio", (unsigned long)&pxa26x_id },
732 { "pxa27x-gpio", (unsigned long)&pxa27x_id },
733 { "pxa3xx-gpio", (unsigned long)&pxa3xx_id },
734 { "pxa93x-gpio", (unsigned long)&pxa93x_id },
735 { "mmp-gpio", (unsigned long)&mmp_id },
736 { "mmp2-gpio", (unsigned long)&mmp2_id },
737 { "pxa1928-gpio", (unsigned long)&pxa1928_id },
738 { },
739};
740
741static struct platform_driver pxa_gpio_driver = {
742 .probe = pxa_gpio_probe,
743 .driver = {
744 .name = "pxa-gpio",
745 .of_match_table = of_match_ptr(pxa_gpio_dt_ids),
746 },
747 .id_table = gpio_id_table,
748};
749
750static int __init pxa_gpio_legacy_init(void)
751{
752 if (of_have_populated_dt())
753 return 0;
754
755 return platform_driver_register(&pxa_gpio_driver);
756}
757postcore_initcall(pxa_gpio_legacy_init);
758
759static int __init pxa_gpio_dt_init(void)
760{
761 if (of_have_populated_dt())
762 return platform_driver_register(&pxa_gpio_driver);
763
764 return 0;
765}
766device_initcall(pxa_gpio_dt_init);
767
768#ifdef CONFIG_PM
769static int pxa_gpio_suspend(void)
770{
771 struct pxa_gpio_chip *pchip = pxa_gpio_chip;
772 struct pxa_gpio_bank *c;
773 int gpio;
774
775 for_each_gpio_bank(gpio, c, pchip) {
776 c->saved_gplr = readl_relaxed(c->regbase + GPLR_OFFSET);
777 c->saved_gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
778 c->saved_grer = readl_relaxed(c->regbase + GRER_OFFSET);
779 c->saved_gfer = readl_relaxed(c->regbase + GFER_OFFSET);
780
781 /* Clear GPIO transition detect bits */
782 writel_relaxed(0xffffffff, c->regbase + GEDR_OFFSET);
783 }
784 return 0;
785}
786
787static void pxa_gpio_resume(void)
788{
789 struct pxa_gpio_chip *pchip = pxa_gpio_chip;
790 struct pxa_gpio_bank *c;
791 int gpio;
792
793 for_each_gpio_bank(gpio, c, pchip) {
794 /* restore level with set/clear */
795 writel_relaxed(c->saved_gplr, c->regbase + GPSR_OFFSET);
796 writel_relaxed(~c->saved_gplr, c->regbase + GPCR_OFFSET);
797
798 writel_relaxed(c->saved_grer, c->regbase + GRER_OFFSET);
799 writel_relaxed(c->saved_gfer, c->regbase + GFER_OFFSET);
800 writel_relaxed(c->saved_gpdr, c->regbase + GPDR_OFFSET);
801 }
802}
803#else
804#define pxa_gpio_suspend NULL
805#define pxa_gpio_resume NULL
806#endif
807
808struct syscore_ops pxa_gpio_syscore_ops = {
809 .suspend = pxa_gpio_suspend,
810 .resume = pxa_gpio_resume,
811};
812
813static int __init pxa_gpio_sysinit(void)
814{
815 register_syscore_ops(&pxa_gpio_syscore_ops);
816 return 0;
817}
818postcore_initcall(pxa_gpio_sysinit);
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * linux/arch/arm/plat-pxa/gpio.c
4 *
5 * Generic PXA GPIO handling
6 *
7 * Author: Nicolas Pitre
8 * Created: Jun 15, 2001
9 * Copyright: MontaVista Software Inc.
10 */
11#include <linux/module.h>
12#include <linux/clk.h>
13#include <linux/err.h>
14#include <linux/gpio/driver.h>
15#include <linux/gpio-pxa.h>
16#include <linux/init.h>
17#include <linux/interrupt.h>
18#include <linux/irq.h>
19#include <linux/irqdomain.h>
20#include <linux/irqchip/chained_irq.h>
21#include <linux/io.h>
22#include <linux/of.h>
23#include <linux/pinctrl/consumer.h>
24#include <linux/platform_device.h>
25#include <linux/syscore_ops.h>
26#include <linux/slab.h>
27
28/*
29 * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with
30 * one set of registers. The register offsets are organized below:
31 *
32 * GPLR GPDR GPSR GPCR GRER GFER GEDR
33 * BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048
34 * BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C
35 * BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050
36 *
37 * BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148
38 * BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C
39 * BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150
40 *
41 * BANK 6 - 0x0200 0x020C 0x0218 0x0224 0x0230 0x023C 0x0248
42 *
43 * NOTE:
44 * BANK 3 is only available on PXA27x and later processors.
45 * BANK 4 and 5 are only available on PXA935, PXA1928
46 * BANK 6 is only available on PXA1928
47 */
48
49#define GPLR_OFFSET 0x00
50#define GPDR_OFFSET 0x0C
51#define GPSR_OFFSET 0x18
52#define GPCR_OFFSET 0x24
53#define GRER_OFFSET 0x30
54#define GFER_OFFSET 0x3C
55#define GEDR_OFFSET 0x48
56#define GAFR_OFFSET 0x54
57#define ED_MASK_OFFSET 0x9C /* GPIO edge detection for AP side */
58
59#define BANK_OFF(n) (((n) / 3) << 8) + (((n) % 3) << 2)
60
61int pxa_last_gpio;
62static int irq_base;
63
64struct pxa_gpio_bank {
65 void __iomem *regbase;
66 unsigned long irq_mask;
67 unsigned long irq_edge_rise;
68 unsigned long irq_edge_fall;
69
70#ifdef CONFIG_PM
71 unsigned long saved_gplr;
72 unsigned long saved_gpdr;
73 unsigned long saved_grer;
74 unsigned long saved_gfer;
75#endif
76};
77
78struct pxa_gpio_chip {
79 struct device *dev;
80 struct gpio_chip chip;
81 struct pxa_gpio_bank *banks;
82 struct irq_domain *irqdomain;
83
84 int irq0;
85 int irq1;
86 int (*set_wake)(unsigned int gpio, unsigned int on);
87};
88
89enum pxa_gpio_type {
90 PXA25X_GPIO = 0,
91 PXA26X_GPIO,
92 PXA27X_GPIO,
93 PXA3XX_GPIO,
94 PXA93X_GPIO,
95 MMP_GPIO = 0x10,
96 MMP2_GPIO,
97 PXA1928_GPIO,
98};
99
100struct pxa_gpio_id {
101 enum pxa_gpio_type type;
102 int gpio_nums;
103};
104
105static DEFINE_SPINLOCK(gpio_lock);
106static struct pxa_gpio_chip *pxa_gpio_chip;
107static enum pxa_gpio_type gpio_type;
108
109static struct pxa_gpio_id pxa25x_id = {
110 .type = PXA25X_GPIO,
111 .gpio_nums = 85,
112};
113
114static struct pxa_gpio_id pxa26x_id = {
115 .type = PXA26X_GPIO,
116 .gpio_nums = 90,
117};
118
119static struct pxa_gpio_id pxa27x_id = {
120 .type = PXA27X_GPIO,
121 .gpio_nums = 121,
122};
123
124static struct pxa_gpio_id pxa3xx_id = {
125 .type = PXA3XX_GPIO,
126 .gpio_nums = 128,
127};
128
129static struct pxa_gpio_id pxa93x_id = {
130 .type = PXA93X_GPIO,
131 .gpio_nums = 192,
132};
133
134static struct pxa_gpio_id mmp_id = {
135 .type = MMP_GPIO,
136 .gpio_nums = 128,
137};
138
139static struct pxa_gpio_id mmp2_id = {
140 .type = MMP2_GPIO,
141 .gpio_nums = 192,
142};
143
144static struct pxa_gpio_id pxa1928_id = {
145 .type = PXA1928_GPIO,
146 .gpio_nums = 224,
147};
148
149#define for_each_gpio_bank(i, b, pc) \
150 for (i = 0, b = pc->banks; i <= pxa_last_gpio; i += 32, b++)
151
152static inline struct pxa_gpio_chip *chip_to_pxachip(struct gpio_chip *c)
153{
154 struct pxa_gpio_chip *pxa_chip = gpiochip_get_data(c);
155
156 return pxa_chip;
157}
158
159static inline void __iomem *gpio_bank_base(struct gpio_chip *c, int gpio)
160{
161 struct pxa_gpio_chip *p = gpiochip_get_data(c);
162 struct pxa_gpio_bank *bank = p->banks + (gpio / 32);
163
164 return bank->regbase;
165}
166
167static inline struct pxa_gpio_bank *gpio_to_pxabank(struct gpio_chip *c,
168 unsigned gpio)
169{
170 return chip_to_pxachip(c)->banks + gpio / 32;
171}
172
173static inline int gpio_is_mmp_type(int type)
174{
175 return (type & MMP_GPIO) != 0;
176}
177
178/* GPIO86/87/88/89 on PXA26x have their direction bits in PXA_GPDR(2 inverted,
179 * as well as their Alternate Function value being '1' for GPIO in GAFRx.
180 */
181static inline int __gpio_is_inverted(int gpio)
182{
183 if ((gpio_type == PXA26X_GPIO) && (gpio > 85))
184 return 1;
185 return 0;
186}
187
188/*
189 * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate
190 * function of a GPIO, and GPDRx cannot be altered once configured. It
191 * is attributed as "occupied" here (I know this terminology isn't
192 * accurate, you are welcome to propose a better one :-)
193 */
194static inline int __gpio_is_occupied(struct pxa_gpio_chip *pchip, unsigned gpio)
195{
196 void __iomem *base;
197 unsigned long gafr = 0, gpdr = 0;
198 int ret, af = 0, dir = 0;
199
200 base = gpio_bank_base(&pchip->chip, gpio);
201 gpdr = readl_relaxed(base + GPDR_OFFSET);
202
203 switch (gpio_type) {
204 case PXA25X_GPIO:
205 case PXA26X_GPIO:
206 case PXA27X_GPIO:
207 gafr = readl_relaxed(base + GAFR_OFFSET);
208 af = (gafr >> ((gpio & 0xf) * 2)) & 0x3;
209 dir = gpdr & GPIO_bit(gpio);
210
211 if (__gpio_is_inverted(gpio))
212 ret = (af != 1) || (dir == 0);
213 else
214 ret = (af != 0) || (dir != 0);
215 break;
216 default:
217 ret = gpdr & GPIO_bit(gpio);
218 break;
219 }
220 return ret;
221}
222
223int pxa_irq_to_gpio(int irq)
224{
225 struct pxa_gpio_chip *pchip = pxa_gpio_chip;
226 int irq_gpio0;
227
228 irq_gpio0 = irq_find_mapping(pchip->irqdomain, 0);
229 if (irq_gpio0 > 0)
230 return irq - irq_gpio0;
231
232 return irq_gpio0;
233}
234
235static bool pxa_gpio_has_pinctrl(void)
236{
237 switch (gpio_type) {
238 case PXA3XX_GPIO:
239 case MMP2_GPIO:
240 case MMP_GPIO:
241 return false;
242
243 default:
244 return true;
245 }
246}
247
248static int pxa_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
249{
250 struct pxa_gpio_chip *pchip = chip_to_pxachip(chip);
251
252 return irq_find_mapping(pchip->irqdomain, offset);
253}
254
255static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
256{
257 void __iomem *base = gpio_bank_base(chip, offset);
258 uint32_t value, mask = GPIO_bit(offset);
259 unsigned long flags;
260 int ret;
261
262 if (pxa_gpio_has_pinctrl()) {
263 ret = pinctrl_gpio_direction_input(chip, offset);
264 if (ret)
265 return ret;
266 }
267
268 spin_lock_irqsave(&gpio_lock, flags);
269
270 value = readl_relaxed(base + GPDR_OFFSET);
271 if (__gpio_is_inverted(chip->base + offset))
272 value |= mask;
273 else
274 value &= ~mask;
275 writel_relaxed(value, base + GPDR_OFFSET);
276
277 spin_unlock_irqrestore(&gpio_lock, flags);
278 return 0;
279}
280
281static int pxa_gpio_direction_output(struct gpio_chip *chip,
282 unsigned offset, int value)
283{
284 void __iomem *base = gpio_bank_base(chip, offset);
285 uint32_t tmp, mask = GPIO_bit(offset);
286 unsigned long flags;
287 int ret;
288
289 writel_relaxed(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET));
290
291 if (pxa_gpio_has_pinctrl()) {
292 ret = pinctrl_gpio_direction_output(chip, offset);
293 if (ret)
294 return ret;
295 }
296
297 spin_lock_irqsave(&gpio_lock, flags);
298
299 tmp = readl_relaxed(base + GPDR_OFFSET);
300 if (__gpio_is_inverted(chip->base + offset))
301 tmp &= ~mask;
302 else
303 tmp |= mask;
304 writel_relaxed(tmp, base + GPDR_OFFSET);
305
306 spin_unlock_irqrestore(&gpio_lock, flags);
307 return 0;
308}
309
310static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset)
311{
312 void __iomem *base = gpio_bank_base(chip, offset);
313 u32 gplr = readl_relaxed(base + GPLR_OFFSET);
314
315 return !!(gplr & GPIO_bit(offset));
316}
317
318static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
319{
320 void __iomem *base = gpio_bank_base(chip, offset);
321
322 writel_relaxed(GPIO_bit(offset),
323 base + (value ? GPSR_OFFSET : GPCR_OFFSET));
324}
325
326#ifdef CONFIG_OF_GPIO
327static int pxa_gpio_of_xlate(struct gpio_chip *gc,
328 const struct of_phandle_args *gpiospec,
329 u32 *flags)
330{
331 if (gpiospec->args[0] > pxa_last_gpio)
332 return -EINVAL;
333
334 if (flags)
335 *flags = gpiospec->args[1];
336
337 return gpiospec->args[0];
338}
339#endif
340
341static int pxa_init_gpio_chip(struct pxa_gpio_chip *pchip, int ngpio, void __iomem *regbase)
342{
343 int i, gpio, nbanks = DIV_ROUND_UP(ngpio, 32);
344 struct pxa_gpio_bank *bank;
345
346 pchip->banks = devm_kcalloc(pchip->dev, nbanks, sizeof(*pchip->banks),
347 GFP_KERNEL);
348 if (!pchip->banks)
349 return -ENOMEM;
350
351 pchip->chip.parent = pchip->dev;
352 pchip->chip.label = "gpio-pxa";
353 pchip->chip.direction_input = pxa_gpio_direction_input;
354 pchip->chip.direction_output = pxa_gpio_direction_output;
355 pchip->chip.get = pxa_gpio_get;
356 pchip->chip.set = pxa_gpio_set;
357 pchip->chip.to_irq = pxa_gpio_to_irq;
358 pchip->chip.ngpio = ngpio;
359 pchip->chip.request = gpiochip_generic_request;
360 pchip->chip.free = gpiochip_generic_free;
361
362#ifdef CONFIG_OF_GPIO
363 pchip->chip.of_xlate = pxa_gpio_of_xlate;
364 pchip->chip.of_gpio_n_cells = 2;
365#endif
366
367 for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) {
368 bank = pchip->banks + i;
369 bank->regbase = regbase + BANK_OFF(i);
370 }
371
372 return gpiochip_add_data(&pchip->chip, pchip);
373}
374
375/* Update only those GRERx and GFERx edge detection register bits if those
376 * bits are set in c->irq_mask
377 */
378static inline void update_edge_detect(struct pxa_gpio_bank *c)
379{
380 uint32_t grer, gfer;
381
382 grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~c->irq_mask;
383 gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~c->irq_mask;
384 grer |= c->irq_edge_rise & c->irq_mask;
385 gfer |= c->irq_edge_fall & c->irq_mask;
386 writel_relaxed(grer, c->regbase + GRER_OFFSET);
387 writel_relaxed(gfer, c->regbase + GFER_OFFSET);
388}
389
390static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type)
391{
392 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
393 unsigned int gpio = irqd_to_hwirq(d);
394 struct pxa_gpio_bank *c = gpio_to_pxabank(&pchip->chip, gpio);
395 unsigned long gpdr, mask = GPIO_bit(gpio);
396
397 if (type == IRQ_TYPE_PROBE) {
398 /* Don't mess with enabled GPIOs using preconfigured edges or
399 * GPIOs set to alternate function or to output during probe
400 */
401 if ((c->irq_edge_rise | c->irq_edge_fall) & GPIO_bit(gpio))
402 return 0;
403
404 if (__gpio_is_occupied(pchip, gpio))
405 return 0;
406
407 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
408 }
409
410 gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
411
412 if (__gpio_is_inverted(gpio))
413 writel_relaxed(gpdr | mask, c->regbase + GPDR_OFFSET);
414 else
415 writel_relaxed(gpdr & ~mask, c->regbase + GPDR_OFFSET);
416
417 if (type & IRQ_TYPE_EDGE_RISING)
418 c->irq_edge_rise |= mask;
419 else
420 c->irq_edge_rise &= ~mask;
421
422 if (type & IRQ_TYPE_EDGE_FALLING)
423 c->irq_edge_fall |= mask;
424 else
425 c->irq_edge_fall &= ~mask;
426
427 update_edge_detect(c);
428
429 pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, d->irq, gpio,
430 ((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""),
431 ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : ""));
432 return 0;
433}
434
435static irqreturn_t pxa_gpio_demux_handler(int in_irq, void *d)
436{
437 int loop, gpio, n, handled = 0;
438 unsigned long gedr;
439 struct pxa_gpio_chip *pchip = d;
440 struct pxa_gpio_bank *c;
441
442 do {
443 loop = 0;
444 for_each_gpio_bank(gpio, c, pchip) {
445 gedr = readl_relaxed(c->regbase + GEDR_OFFSET);
446 gedr = gedr & c->irq_mask;
447 writel_relaxed(gedr, c->regbase + GEDR_OFFSET);
448
449 for_each_set_bit(n, &gedr, BITS_PER_LONG) {
450 loop = 1;
451
452 generic_handle_domain_irq(pchip->irqdomain,
453 gpio + n);
454 }
455 }
456 handled += loop;
457 } while (loop);
458
459 return handled ? IRQ_HANDLED : IRQ_NONE;
460}
461
462static irqreturn_t pxa_gpio_direct_handler(int in_irq, void *d)
463{
464 struct pxa_gpio_chip *pchip = d;
465
466 if (in_irq == pchip->irq0) {
467 generic_handle_domain_irq(pchip->irqdomain, 0);
468 } else if (in_irq == pchip->irq1) {
469 generic_handle_domain_irq(pchip->irqdomain, 1);
470 } else {
471 pr_err("%s() unknown irq %d\n", __func__, in_irq);
472 return IRQ_NONE;
473 }
474 return IRQ_HANDLED;
475}
476
477static void pxa_ack_muxed_gpio(struct irq_data *d)
478{
479 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
480 unsigned int gpio = irqd_to_hwirq(d);
481 void __iomem *base = gpio_bank_base(&pchip->chip, gpio);
482
483 writel_relaxed(GPIO_bit(gpio), base + GEDR_OFFSET);
484}
485
486static void pxa_mask_muxed_gpio(struct irq_data *d)
487{
488 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
489 unsigned int gpio = irqd_to_hwirq(d);
490 struct pxa_gpio_bank *b = gpio_to_pxabank(&pchip->chip, gpio);
491 void __iomem *base = gpio_bank_base(&pchip->chip, gpio);
492 uint32_t grer, gfer;
493
494 b->irq_mask &= ~GPIO_bit(gpio);
495
496 grer = readl_relaxed(base + GRER_OFFSET) & ~GPIO_bit(gpio);
497 gfer = readl_relaxed(base + GFER_OFFSET) & ~GPIO_bit(gpio);
498 writel_relaxed(grer, base + GRER_OFFSET);
499 writel_relaxed(gfer, base + GFER_OFFSET);
500}
501
502static int pxa_gpio_set_wake(struct irq_data *d, unsigned int on)
503{
504 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
505 unsigned int gpio = irqd_to_hwirq(d);
506
507 if (pchip->set_wake)
508 return pchip->set_wake(gpio, on);
509 else
510 return 0;
511}
512
513static void pxa_unmask_muxed_gpio(struct irq_data *d)
514{
515 struct pxa_gpio_chip *pchip = irq_data_get_irq_chip_data(d);
516 unsigned int gpio = irqd_to_hwirq(d);
517 struct pxa_gpio_bank *c = gpio_to_pxabank(&pchip->chip, gpio);
518
519 c->irq_mask |= GPIO_bit(gpio);
520 update_edge_detect(c);
521}
522
523static struct irq_chip pxa_muxed_gpio_chip = {
524 .name = "GPIO",
525 .irq_ack = pxa_ack_muxed_gpio,
526 .irq_mask = pxa_mask_muxed_gpio,
527 .irq_unmask = pxa_unmask_muxed_gpio,
528 .irq_set_type = pxa_gpio_irq_type,
529 .irq_set_wake = pxa_gpio_set_wake,
530};
531
532static int pxa_gpio_nums(struct platform_device *pdev)
533{
534 const struct platform_device_id *id = platform_get_device_id(pdev);
535 struct pxa_gpio_id *pxa_id = (struct pxa_gpio_id *)id->driver_data;
536 int count = 0;
537
538 switch (pxa_id->type) {
539 case PXA25X_GPIO:
540 case PXA26X_GPIO:
541 case PXA27X_GPIO:
542 case PXA3XX_GPIO:
543 case PXA93X_GPIO:
544 case MMP_GPIO:
545 case MMP2_GPIO:
546 case PXA1928_GPIO:
547 gpio_type = pxa_id->type;
548 count = pxa_id->gpio_nums - 1;
549 break;
550 default:
551 count = -EINVAL;
552 break;
553 }
554 return count;
555}
556
557static int pxa_irq_domain_map(struct irq_domain *d, unsigned int irq,
558 irq_hw_number_t hw)
559{
560 irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
561 handle_edge_irq);
562 irq_set_chip_data(irq, d->host_data);
563 irq_set_noprobe(irq);
564 return 0;
565}
566
567static const struct irq_domain_ops pxa_irq_domain_ops = {
568 .map = pxa_irq_domain_map,
569 .xlate = irq_domain_xlate_twocell,
570};
571
572#ifdef CONFIG_OF
573static const struct of_device_id pxa_gpio_dt_ids[] = {
574 { .compatible = "intel,pxa25x-gpio", .data = &pxa25x_id, },
575 { .compatible = "intel,pxa26x-gpio", .data = &pxa26x_id, },
576 { .compatible = "intel,pxa27x-gpio", .data = &pxa27x_id, },
577 { .compatible = "intel,pxa3xx-gpio", .data = &pxa3xx_id, },
578 { .compatible = "marvell,pxa93x-gpio", .data = &pxa93x_id, },
579 { .compatible = "marvell,mmp-gpio", .data = &mmp_id, },
580 { .compatible = "marvell,mmp2-gpio", .data = &mmp2_id, },
581 { .compatible = "marvell,pxa1928-gpio", .data = &pxa1928_id, },
582 {}
583};
584
585static int pxa_gpio_probe_dt(struct platform_device *pdev,
586 struct pxa_gpio_chip *pchip)
587{
588 int nr_gpios;
589 const struct pxa_gpio_id *gpio_id;
590
591 gpio_id = of_device_get_match_data(&pdev->dev);
592 gpio_type = gpio_id->type;
593
594 nr_gpios = gpio_id->gpio_nums;
595 pxa_last_gpio = nr_gpios - 1;
596
597 irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, nr_gpios, 0);
598 if (irq_base < 0) {
599 dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n");
600 return irq_base;
601 }
602 return irq_base;
603}
604#else
605#define pxa_gpio_probe_dt(pdev, pchip) (-1)
606#endif
607
608static int pxa_gpio_probe(struct platform_device *pdev)
609{
610 struct pxa_gpio_chip *pchip;
611 struct pxa_gpio_bank *c;
612 struct clk *clk;
613 struct pxa_gpio_platform_data *info;
614 void __iomem *gpio_reg_base;
615 int gpio, ret;
616 int irq0 = 0, irq1 = 0, irq_mux;
617
618 pchip = devm_kzalloc(&pdev->dev, sizeof(*pchip), GFP_KERNEL);
619 if (!pchip)
620 return -ENOMEM;
621 pchip->dev = &pdev->dev;
622
623 info = dev_get_platdata(&pdev->dev);
624 if (info) {
625 irq_base = info->irq_base;
626 if (irq_base <= 0)
627 return -EINVAL;
628 pxa_last_gpio = pxa_gpio_nums(pdev);
629 pchip->set_wake = info->gpio_set_wake;
630 } else {
631 irq_base = pxa_gpio_probe_dt(pdev, pchip);
632 if (irq_base < 0)
633 return -EINVAL;
634 }
635
636 if (!pxa_last_gpio)
637 return -EINVAL;
638
639 pchip->irqdomain = irq_domain_add_legacy(pdev->dev.of_node,
640 pxa_last_gpio + 1, irq_base,
641 0, &pxa_irq_domain_ops, pchip);
642 if (!pchip->irqdomain)
643 return -ENOMEM;
644
645 irq0 = platform_get_irq_byname_optional(pdev, "gpio0");
646 irq1 = platform_get_irq_byname_optional(pdev, "gpio1");
647 irq_mux = platform_get_irq_byname(pdev, "gpio_mux");
648 if ((irq0 > 0 && irq1 <= 0) || (irq0 <= 0 && irq1 > 0)
649 || (irq_mux <= 0))
650 return -EINVAL;
651
652 pchip->irq0 = irq0;
653 pchip->irq1 = irq1;
654
655 gpio_reg_base = devm_platform_ioremap_resource(pdev, 0);
656 if (IS_ERR(gpio_reg_base))
657 return PTR_ERR(gpio_reg_base);
658
659 clk = devm_clk_get_enabled(&pdev->dev, NULL);
660 if (IS_ERR(clk)) {
661 dev_err(&pdev->dev, "Error %ld to get gpio clock\n",
662 PTR_ERR(clk));
663 return PTR_ERR(clk);
664 }
665
666 /* Initialize GPIO chips */
667 ret = pxa_init_gpio_chip(pchip, pxa_last_gpio + 1, gpio_reg_base);
668 if (ret)
669 return ret;
670
671 /* clear all GPIO edge detects */
672 for_each_gpio_bank(gpio, c, pchip) {
673 writel_relaxed(0, c->regbase + GFER_OFFSET);
674 writel_relaxed(0, c->regbase + GRER_OFFSET);
675 writel_relaxed(~0, c->regbase + GEDR_OFFSET);
676 /* unmask GPIO edge detect for AP side */
677 if (gpio_is_mmp_type(gpio_type))
678 writel_relaxed(~0, c->regbase + ED_MASK_OFFSET);
679 }
680
681 if (irq0 > 0) {
682 ret = devm_request_irq(&pdev->dev,
683 irq0, pxa_gpio_direct_handler, 0,
684 "gpio-0", pchip);
685 if (ret)
686 dev_err(&pdev->dev, "request of gpio0 irq failed: %d\n",
687 ret);
688 }
689 if (irq1 > 0) {
690 ret = devm_request_irq(&pdev->dev,
691 irq1, pxa_gpio_direct_handler, 0,
692 "gpio-1", pchip);
693 if (ret)
694 dev_err(&pdev->dev, "request of gpio1 irq failed: %d\n",
695 ret);
696 }
697 ret = devm_request_irq(&pdev->dev,
698 irq_mux, pxa_gpio_demux_handler, 0,
699 "gpio-mux", pchip);
700 if (ret)
701 dev_err(&pdev->dev, "request of gpio-mux irq failed: %d\n",
702 ret);
703
704 pxa_gpio_chip = pchip;
705
706 return 0;
707}
708
709static const struct platform_device_id gpio_id_table[] = {
710 { "pxa25x-gpio", (unsigned long)&pxa25x_id },
711 { "pxa26x-gpio", (unsigned long)&pxa26x_id },
712 { "pxa27x-gpio", (unsigned long)&pxa27x_id },
713 { "pxa3xx-gpio", (unsigned long)&pxa3xx_id },
714 { "pxa93x-gpio", (unsigned long)&pxa93x_id },
715 { "mmp-gpio", (unsigned long)&mmp_id },
716 { "mmp2-gpio", (unsigned long)&mmp2_id },
717 { "pxa1928-gpio", (unsigned long)&pxa1928_id },
718 { },
719};
720
721static struct platform_driver pxa_gpio_driver = {
722 .probe = pxa_gpio_probe,
723 .driver = {
724 .name = "pxa-gpio",
725 .of_match_table = of_match_ptr(pxa_gpio_dt_ids),
726 },
727 .id_table = gpio_id_table,
728};
729
730static int __init pxa_gpio_legacy_init(void)
731{
732 if (of_have_populated_dt())
733 return 0;
734
735 return platform_driver_register(&pxa_gpio_driver);
736}
737postcore_initcall(pxa_gpio_legacy_init);
738
739static int __init pxa_gpio_dt_init(void)
740{
741 if (of_have_populated_dt())
742 return platform_driver_register(&pxa_gpio_driver);
743
744 return 0;
745}
746device_initcall(pxa_gpio_dt_init);
747
748#ifdef CONFIG_PM
749static int pxa_gpio_suspend(void)
750{
751 struct pxa_gpio_chip *pchip = pxa_gpio_chip;
752 struct pxa_gpio_bank *c;
753 int gpio;
754
755 if (!pchip)
756 return 0;
757
758 for_each_gpio_bank(gpio, c, pchip) {
759 c->saved_gplr = readl_relaxed(c->regbase + GPLR_OFFSET);
760 c->saved_gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
761 c->saved_grer = readl_relaxed(c->regbase + GRER_OFFSET);
762 c->saved_gfer = readl_relaxed(c->regbase + GFER_OFFSET);
763
764 /* Clear GPIO transition detect bits */
765 writel_relaxed(0xffffffff, c->regbase + GEDR_OFFSET);
766 }
767 return 0;
768}
769
770static void pxa_gpio_resume(void)
771{
772 struct pxa_gpio_chip *pchip = pxa_gpio_chip;
773 struct pxa_gpio_bank *c;
774 int gpio;
775
776 if (!pchip)
777 return;
778
779 for_each_gpio_bank(gpio, c, pchip) {
780 /* restore level with set/clear */
781 writel_relaxed(c->saved_gplr, c->regbase + GPSR_OFFSET);
782 writel_relaxed(~c->saved_gplr, c->regbase + GPCR_OFFSET);
783
784 writel_relaxed(c->saved_grer, c->regbase + GRER_OFFSET);
785 writel_relaxed(c->saved_gfer, c->regbase + GFER_OFFSET);
786 writel_relaxed(c->saved_gpdr, c->regbase + GPDR_OFFSET);
787 }
788}
789#else
790#define pxa_gpio_suspend NULL
791#define pxa_gpio_resume NULL
792#endif
793
794static struct syscore_ops pxa_gpio_syscore_ops = {
795 .suspend = pxa_gpio_suspend,
796 .resume = pxa_gpio_resume,
797};
798
799static int __init pxa_gpio_sysinit(void)
800{
801 register_syscore_ops(&pxa_gpio_syscore_ops);
802 return 0;
803}
804postcore_initcall(pxa_gpio_sysinit);