1/*
 2 * Based on arch/arm/mm/proc-macros.S
 3 *
 4 * Copyright (C) 2012 ARM Ltd.
 5 *
 6 * This program is free software; you can redistribute it and/or modify
 7 * it under the terms of the GNU General Public License version 2 as
 8 * published by the Free Software Foundation.
 9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#include <asm/asm-offsets.h>
20#include <asm/thread_info.h>
21
22/*
23 * vma_vm_mm - get mm pointer from vma pointer (vma->vm_mm)
24 */
25	.macro	vma_vm_mm, rd, rn
26	ldr	\rd, [\rn, #VMA_VM_MM]
27	.endm
28
29/*
30 * mmid - get context id from mm pointer (mm->context.id)
31 */
32	.macro	mmid, rd, rn
33	ldr	\rd, [\rn, #MM_CONTEXT_ID]
34	.endm
35
36/*
37 * dcache_line_size - get the minimum D-cache line size from the CTR register.
38 */
39	.macro	dcache_line_size, reg, tmp
40	mrs	\tmp, ctr_el0			// read CTR
41	ubfm	\tmp, \tmp, #16, #19		// cache line size encoding
42	mov	\reg, #4			// bytes per word
43	lsl	\reg, \reg, \tmp		// actual cache line size
44	.endm
45
46/*
47 * icache_line_size - get the minimum I-cache line size from the CTR register.
48 */
49	.macro	icache_line_size, reg, tmp
50	mrs	\tmp, ctr_el0			// read CTR
51	and	\tmp, \tmp, #0xf		// cache line size encoding
52	mov	\reg, #4			// bytes per word
53	lsl	\reg, \reg, \tmp		// actual cache line size
54	.endm
55
56/*
57 * tcr_set_idmap_t0sz - update TCR.T0SZ so that we can load the ID map
58 */
59	.macro	tcr_set_idmap_t0sz, valreg, tmpreg
60#ifndef CONFIG_ARM64_VA_BITS_48
61	ldr_l	\tmpreg, idmap_t0sz
62	bfi	\valreg, \tmpreg, #TCR_T0SZ_OFFSET, #TCR_TxSZ_WIDTH
63#endif
64	.endm
65
66/*
67 * Macro to perform a data cache maintenance for the interval
68 * [kaddr, kaddr + size)
69 *
70 * 	op:		operation passed to dc instruction
71 * 	domain:		domain used in dsb instruciton
72 * 	kaddr:		starting virtual address of the region
73 * 	size:		size of the region
74 * 	Corrupts: 	kaddr, size, tmp1, tmp2
75 */
76	.macro dcache_by_line_op op, domain, kaddr, size, tmp1, tmp2
77	dcache_line_size \tmp1, \tmp2
78	add	\size, \kaddr, \size
79	sub	\tmp2, \tmp1, #1
80	bic	\kaddr, \kaddr, \tmp2
819998:	dc	\op, \kaddr
82	add	\kaddr, \kaddr, \tmp1
83	cmp	\kaddr, \size
84	b.lo	9998b
85	dsb	\domain
86	.endm
87
88/*
89 * reset_pmuserenr_el0 - reset PMUSERENR_EL0 if PMUv3 present
90 */
91	.macro	reset_pmuserenr_el0, tmpreg
92	mrs	\tmpreg, id_aa64dfr0_el1	// Check ID_AA64DFR0_EL1 PMUVer
93	sbfx	\tmpreg, \tmpreg, #8, #4
94	cmp	\tmpreg, #1			// Skip if no PMU present
95	b.lt	9000f
96	msr	pmuserenr_el0, xzr		// Disable PMU access from EL0
979000:
98	.endm