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1/*
2 * FP/SIMD context switching and fault handling
3 *
4 * Copyright (C) 2012 ARM Ltd.
5 * Author: Catalin Marinas <catalin.marinas@arm.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include <linux/cpu.h>
21#include <linux/cpu_pm.h>
22#include <linux/kernel.h>
23#include <linux/init.h>
24#include <linux/sched.h>
25#include <linux/signal.h>
26#include <linux/hardirq.h>
27
28#include <asm/fpsimd.h>
29#include <asm/cputype.h>
30
31#define FPEXC_IOF (1 << 0)
32#define FPEXC_DZF (1 << 1)
33#define FPEXC_OFF (1 << 2)
34#define FPEXC_UFF (1 << 3)
35#define FPEXC_IXF (1 << 4)
36#define FPEXC_IDF (1 << 7)
37
38/*
39 * In order to reduce the number of times the FPSIMD state is needlessly saved
40 * and restored, we need to keep track of two things:
41 * (a) for each task, we need to remember which CPU was the last one to have
42 * the task's FPSIMD state loaded into its FPSIMD registers;
43 * (b) for each CPU, we need to remember which task's userland FPSIMD state has
44 * been loaded into its FPSIMD registers most recently, or whether it has
45 * been used to perform kernel mode NEON in the meantime.
46 *
47 * For (a), we add a 'cpu' field to struct fpsimd_state, which gets updated to
48 * the id of the current CPU every time the state is loaded onto a CPU. For (b),
49 * we add the per-cpu variable 'fpsimd_last_state' (below), which contains the
50 * address of the userland FPSIMD state of the task that was loaded onto the CPU
51 * the most recently, or NULL if kernel mode NEON has been performed after that.
52 *
53 * With this in place, we no longer have to restore the next FPSIMD state right
54 * when switching between tasks. Instead, we can defer this check to userland
55 * resume, at which time we verify whether the CPU's fpsimd_last_state and the
56 * task's fpsimd_state.cpu are still mutually in sync. If this is the case, we
57 * can omit the FPSIMD restore.
58 *
59 * As an optimization, we use the thread_info flag TIF_FOREIGN_FPSTATE to
60 * indicate whether or not the userland FPSIMD state of the current task is
61 * present in the registers. The flag is set unless the FPSIMD registers of this
62 * CPU currently contain the most recent userland FPSIMD state of the current
63 * task.
64 *
65 * For a certain task, the sequence may look something like this:
66 * - the task gets scheduled in; if both the task's fpsimd_state.cpu field
67 * contains the id of the current CPU, and the CPU's fpsimd_last_state per-cpu
68 * variable points to the task's fpsimd_state, the TIF_FOREIGN_FPSTATE flag is
69 * cleared, otherwise it is set;
70 *
71 * - the task returns to userland; if TIF_FOREIGN_FPSTATE is set, the task's
72 * userland FPSIMD state is copied from memory to the registers, the task's
73 * fpsimd_state.cpu field is set to the id of the current CPU, the current
74 * CPU's fpsimd_last_state pointer is set to this task's fpsimd_state and the
75 * TIF_FOREIGN_FPSTATE flag is cleared;
76 *
77 * - the task executes an ordinary syscall; upon return to userland, the
78 * TIF_FOREIGN_FPSTATE flag will still be cleared, so no FPSIMD state is
79 * restored;
80 *
81 * - the task executes a syscall which executes some NEON instructions; this is
82 * preceded by a call to kernel_neon_begin(), which copies the task's FPSIMD
83 * register contents to memory, clears the fpsimd_last_state per-cpu variable
84 * and sets the TIF_FOREIGN_FPSTATE flag;
85 *
86 * - the task gets preempted after kernel_neon_end() is called; as we have not
87 * returned from the 2nd syscall yet, TIF_FOREIGN_FPSTATE is still set so
88 * whatever is in the FPSIMD registers is not saved to memory, but discarded.
89 */
90static DEFINE_PER_CPU(struct fpsimd_state *, fpsimd_last_state);
91
92/*
93 * Trapped FP/ASIMD access.
94 */
95void do_fpsimd_acc(unsigned int esr, struct pt_regs *regs)
96{
97 /* TODO: implement lazy context saving/restoring */
98 WARN_ON(1);
99}
100
101/*
102 * Raise a SIGFPE for the current process.
103 */
104void do_fpsimd_exc(unsigned int esr, struct pt_regs *regs)
105{
106 siginfo_t info;
107 unsigned int si_code = 0;
108
109 if (esr & FPEXC_IOF)
110 si_code = FPE_FLTINV;
111 else if (esr & FPEXC_DZF)
112 si_code = FPE_FLTDIV;
113 else if (esr & FPEXC_OFF)
114 si_code = FPE_FLTOVF;
115 else if (esr & FPEXC_UFF)
116 si_code = FPE_FLTUND;
117 else if (esr & FPEXC_IXF)
118 si_code = FPE_FLTRES;
119
120 memset(&info, 0, sizeof(info));
121 info.si_signo = SIGFPE;
122 info.si_code = si_code;
123 info.si_addr = (void __user *)instruction_pointer(regs);
124
125 send_sig_info(SIGFPE, &info, current);
126}
127
128void fpsimd_thread_switch(struct task_struct *next)
129{
130 /*
131 * Save the current FPSIMD state to memory, but only if whatever is in
132 * the registers is in fact the most recent userland FPSIMD state of
133 * 'current'.
134 */
135 if (current->mm && !test_thread_flag(TIF_FOREIGN_FPSTATE))
136 fpsimd_save_state(¤t->thread.fpsimd_state);
137
138 if (next->mm) {
139 /*
140 * If we are switching to a task whose most recent userland
141 * FPSIMD state is already in the registers of *this* cpu,
142 * we can skip loading the state from memory. Otherwise, set
143 * the TIF_FOREIGN_FPSTATE flag so the state will be loaded
144 * upon the next return to userland.
145 */
146 struct fpsimd_state *st = &next->thread.fpsimd_state;
147
148 if (__this_cpu_read(fpsimd_last_state) == st
149 && st->cpu == smp_processor_id())
150 clear_ti_thread_flag(task_thread_info(next),
151 TIF_FOREIGN_FPSTATE);
152 else
153 set_ti_thread_flag(task_thread_info(next),
154 TIF_FOREIGN_FPSTATE);
155 }
156}
157
158void fpsimd_flush_thread(void)
159{
160 memset(¤t->thread.fpsimd_state, 0, sizeof(struct fpsimd_state));
161 fpsimd_flush_task_state(current);
162 set_thread_flag(TIF_FOREIGN_FPSTATE);
163}
164
165/*
166 * Save the userland FPSIMD state of 'current' to memory, but only if the state
167 * currently held in the registers does in fact belong to 'current'
168 */
169void fpsimd_preserve_current_state(void)
170{
171 preempt_disable();
172 if (!test_thread_flag(TIF_FOREIGN_FPSTATE))
173 fpsimd_save_state(¤t->thread.fpsimd_state);
174 preempt_enable();
175}
176
177/*
178 * Load the userland FPSIMD state of 'current' from memory, but only if the
179 * FPSIMD state already held in the registers is /not/ the most recent FPSIMD
180 * state of 'current'
181 */
182void fpsimd_restore_current_state(void)
183{
184 preempt_disable();
185 if (test_and_clear_thread_flag(TIF_FOREIGN_FPSTATE)) {
186 struct fpsimd_state *st = ¤t->thread.fpsimd_state;
187
188 fpsimd_load_state(st);
189 this_cpu_write(fpsimd_last_state, st);
190 st->cpu = smp_processor_id();
191 }
192 preempt_enable();
193}
194
195/*
196 * Load an updated userland FPSIMD state for 'current' from memory and set the
197 * flag that indicates that the FPSIMD register contents are the most recent
198 * FPSIMD state of 'current'
199 */
200void fpsimd_update_current_state(struct fpsimd_state *state)
201{
202 preempt_disable();
203 fpsimd_load_state(state);
204 if (test_and_clear_thread_flag(TIF_FOREIGN_FPSTATE)) {
205 struct fpsimd_state *st = ¤t->thread.fpsimd_state;
206
207 this_cpu_write(fpsimd_last_state, st);
208 st->cpu = smp_processor_id();
209 }
210 preempt_enable();
211}
212
213/*
214 * Invalidate live CPU copies of task t's FPSIMD state
215 */
216void fpsimd_flush_task_state(struct task_struct *t)
217{
218 t->thread.fpsimd_state.cpu = NR_CPUS;
219}
220
221#ifdef CONFIG_KERNEL_MODE_NEON
222
223static DEFINE_PER_CPU(struct fpsimd_partial_state, hardirq_fpsimdstate);
224static DEFINE_PER_CPU(struct fpsimd_partial_state, softirq_fpsimdstate);
225
226/*
227 * Kernel-side NEON support functions
228 */
229void kernel_neon_begin_partial(u32 num_regs)
230{
231 if (in_interrupt()) {
232 struct fpsimd_partial_state *s = this_cpu_ptr(
233 in_irq() ? &hardirq_fpsimdstate : &softirq_fpsimdstate);
234
235 BUG_ON(num_regs > 32);
236 fpsimd_save_partial_state(s, roundup(num_regs, 2));
237 } else {
238 /*
239 * Save the userland FPSIMD state if we have one and if we
240 * haven't done so already. Clear fpsimd_last_state to indicate
241 * that there is no longer userland FPSIMD state in the
242 * registers.
243 */
244 preempt_disable();
245 if (current->mm &&
246 !test_and_set_thread_flag(TIF_FOREIGN_FPSTATE))
247 fpsimd_save_state(¤t->thread.fpsimd_state);
248 this_cpu_write(fpsimd_last_state, NULL);
249 }
250}
251EXPORT_SYMBOL(kernel_neon_begin_partial);
252
253void kernel_neon_end(void)
254{
255 if (in_interrupt()) {
256 struct fpsimd_partial_state *s = this_cpu_ptr(
257 in_irq() ? &hardirq_fpsimdstate : &softirq_fpsimdstate);
258 fpsimd_load_partial_state(s);
259 } else {
260 preempt_enable();
261 }
262}
263EXPORT_SYMBOL(kernel_neon_end);
264
265#endif /* CONFIG_KERNEL_MODE_NEON */
266
267#ifdef CONFIG_CPU_PM
268static int fpsimd_cpu_pm_notifier(struct notifier_block *self,
269 unsigned long cmd, void *v)
270{
271 switch (cmd) {
272 case CPU_PM_ENTER:
273 if (current->mm && !test_thread_flag(TIF_FOREIGN_FPSTATE))
274 fpsimd_save_state(¤t->thread.fpsimd_state);
275 this_cpu_write(fpsimd_last_state, NULL);
276 break;
277 case CPU_PM_EXIT:
278 if (current->mm)
279 set_thread_flag(TIF_FOREIGN_FPSTATE);
280 break;
281 case CPU_PM_ENTER_FAILED:
282 default:
283 return NOTIFY_DONE;
284 }
285 return NOTIFY_OK;
286}
287
288static struct notifier_block fpsimd_cpu_pm_notifier_block = {
289 .notifier_call = fpsimd_cpu_pm_notifier,
290};
291
292static void __init fpsimd_pm_init(void)
293{
294 cpu_pm_register_notifier(&fpsimd_cpu_pm_notifier_block);
295}
296
297#else
298static inline void fpsimd_pm_init(void) { }
299#endif /* CONFIG_CPU_PM */
300
301#ifdef CONFIG_HOTPLUG_CPU
302static int fpsimd_cpu_hotplug_notifier(struct notifier_block *nfb,
303 unsigned long action,
304 void *hcpu)
305{
306 unsigned int cpu = (long)hcpu;
307
308 switch (action) {
309 case CPU_DEAD:
310 case CPU_DEAD_FROZEN:
311 per_cpu(fpsimd_last_state, cpu) = NULL;
312 break;
313 }
314 return NOTIFY_OK;
315}
316
317static struct notifier_block fpsimd_cpu_hotplug_notifier_block = {
318 .notifier_call = fpsimd_cpu_hotplug_notifier,
319};
320
321static inline void fpsimd_hotplug_init(void)
322{
323 register_cpu_notifier(&fpsimd_cpu_hotplug_notifier_block);
324}
325
326#else
327static inline void fpsimd_hotplug_init(void) { }
328#endif
329
330/*
331 * FP/SIMD support code initialisation.
332 */
333static int __init fpsimd_init(void)
334{
335 if (elf_hwcap & HWCAP_FP) {
336 fpsimd_pm_init();
337 fpsimd_hotplug_init();
338 } else {
339 pr_notice("Floating-point is not implemented\n");
340 }
341
342 if (!(elf_hwcap & HWCAP_ASIMD))
343 pr_notice("Advanced SIMD is not implemented\n");
344
345 return 0;
346}
347late_initcall(fpsimd_init);
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * FP/SIMD context switching and fault handling
4 *
5 * Copyright (C) 2012 ARM Ltd.
6 * Author: Catalin Marinas <catalin.marinas@arm.com>
7 */
8
9#include <linux/bitmap.h>
10#include <linux/bitops.h>
11#include <linux/bottom_half.h>
12#include <linux/bug.h>
13#include <linux/cache.h>
14#include <linux/compat.h>
15#include <linux/compiler.h>
16#include <linux/cpu.h>
17#include <linux/cpu_pm.h>
18#include <linux/ctype.h>
19#include <linux/kernel.h>
20#include <linux/linkage.h>
21#include <linux/irqflags.h>
22#include <linux/init.h>
23#include <linux/percpu.h>
24#include <linux/prctl.h>
25#include <linux/preempt.h>
26#include <linux/ptrace.h>
27#include <linux/sched/signal.h>
28#include <linux/sched/task_stack.h>
29#include <linux/signal.h>
30#include <linux/slab.h>
31#include <linux/stddef.h>
32#include <linux/sysctl.h>
33#include <linux/swab.h>
34
35#include <asm/esr.h>
36#include <asm/exception.h>
37#include <asm/fpsimd.h>
38#include <asm/cpufeature.h>
39#include <asm/cputype.h>
40#include <asm/neon.h>
41#include <asm/processor.h>
42#include <asm/simd.h>
43#include <asm/sigcontext.h>
44#include <asm/sysreg.h>
45#include <asm/traps.h>
46#include <asm/virt.h>
47
48#define FPEXC_IOF (1 << 0)
49#define FPEXC_DZF (1 << 1)
50#define FPEXC_OFF (1 << 2)
51#define FPEXC_UFF (1 << 3)
52#define FPEXC_IXF (1 << 4)
53#define FPEXC_IDF (1 << 7)
54
55/*
56 * (Note: in this discussion, statements about FPSIMD apply equally to SVE.)
57 *
58 * In order to reduce the number of times the FPSIMD state is needlessly saved
59 * and restored, we need to keep track of two things:
60 * (a) for each task, we need to remember which CPU was the last one to have
61 * the task's FPSIMD state loaded into its FPSIMD registers;
62 * (b) for each CPU, we need to remember which task's userland FPSIMD state has
63 * been loaded into its FPSIMD registers most recently, or whether it has
64 * been used to perform kernel mode NEON in the meantime.
65 *
66 * For (a), we add a fpsimd_cpu field to thread_struct, which gets updated to
67 * the id of the current CPU every time the state is loaded onto a CPU. For (b),
68 * we add the per-cpu variable 'fpsimd_last_state' (below), which contains the
69 * address of the userland FPSIMD state of the task that was loaded onto the CPU
70 * the most recently, or NULL if kernel mode NEON has been performed after that.
71 *
72 * With this in place, we no longer have to restore the next FPSIMD state right
73 * when switching between tasks. Instead, we can defer this check to userland
74 * resume, at which time we verify whether the CPU's fpsimd_last_state and the
75 * task's fpsimd_cpu are still mutually in sync. If this is the case, we
76 * can omit the FPSIMD restore.
77 *
78 * As an optimization, we use the thread_info flag TIF_FOREIGN_FPSTATE to
79 * indicate whether or not the userland FPSIMD state of the current task is
80 * present in the registers. The flag is set unless the FPSIMD registers of this
81 * CPU currently contain the most recent userland FPSIMD state of the current
82 * task. If the task is behaving as a VMM, then this is will be managed by
83 * KVM which will clear it to indicate that the vcpu FPSIMD state is currently
84 * loaded on the CPU, allowing the state to be saved if a FPSIMD-aware
85 * softirq kicks in. Upon vcpu_put(), KVM will save the vcpu FP state and
86 * flag the register state as invalid.
87 *
88 * In order to allow softirq handlers to use FPSIMD, kernel_neon_begin() may be
89 * called from softirq context, which will save the task's FPSIMD context back
90 * to task_struct. To prevent this from racing with the manipulation of the
91 * task's FPSIMD state from task context and thereby corrupting the state, it
92 * is necessary to protect any manipulation of a task's fpsimd_state or
93 * TIF_FOREIGN_FPSTATE flag with get_cpu_fpsimd_context(), which will suspend
94 * softirq servicing entirely until put_cpu_fpsimd_context() is called.
95 *
96 * For a certain task, the sequence may look something like this:
97 * - the task gets scheduled in; if both the task's fpsimd_cpu field
98 * contains the id of the current CPU, and the CPU's fpsimd_last_state per-cpu
99 * variable points to the task's fpsimd_state, the TIF_FOREIGN_FPSTATE flag is
100 * cleared, otherwise it is set;
101 *
102 * - the task returns to userland; if TIF_FOREIGN_FPSTATE is set, the task's
103 * userland FPSIMD state is copied from memory to the registers, the task's
104 * fpsimd_cpu field is set to the id of the current CPU, the current
105 * CPU's fpsimd_last_state pointer is set to this task's fpsimd_state and the
106 * TIF_FOREIGN_FPSTATE flag is cleared;
107 *
108 * - the task executes an ordinary syscall; upon return to userland, the
109 * TIF_FOREIGN_FPSTATE flag will still be cleared, so no FPSIMD state is
110 * restored;
111 *
112 * - the task executes a syscall which executes some NEON instructions; this is
113 * preceded by a call to kernel_neon_begin(), which copies the task's FPSIMD
114 * register contents to memory, clears the fpsimd_last_state per-cpu variable
115 * and sets the TIF_FOREIGN_FPSTATE flag;
116 *
117 * - the task gets preempted after kernel_neon_end() is called; as we have not
118 * returned from the 2nd syscall yet, TIF_FOREIGN_FPSTATE is still set so
119 * whatever is in the FPSIMD registers is not saved to memory, but discarded.
120 */
121
122static DEFINE_PER_CPU(struct cpu_fp_state, fpsimd_last_state);
123
124__ro_after_init struct vl_info vl_info[ARM64_VEC_MAX] = {
125#ifdef CONFIG_ARM64_SVE
126 [ARM64_VEC_SVE] = {
127 .type = ARM64_VEC_SVE,
128 .name = "SVE",
129 .min_vl = SVE_VL_MIN,
130 .max_vl = SVE_VL_MIN,
131 .max_virtualisable_vl = SVE_VL_MIN,
132 },
133#endif
134#ifdef CONFIG_ARM64_SME
135 [ARM64_VEC_SME] = {
136 .type = ARM64_VEC_SME,
137 .name = "SME",
138 },
139#endif
140};
141
142static unsigned int vec_vl_inherit_flag(enum vec_type type)
143{
144 switch (type) {
145 case ARM64_VEC_SVE:
146 return TIF_SVE_VL_INHERIT;
147 case ARM64_VEC_SME:
148 return TIF_SME_VL_INHERIT;
149 default:
150 WARN_ON_ONCE(1);
151 return 0;
152 }
153}
154
155struct vl_config {
156 int __default_vl; /* Default VL for tasks */
157};
158
159static struct vl_config vl_config[ARM64_VEC_MAX];
160
161static inline int get_default_vl(enum vec_type type)
162{
163 return READ_ONCE(vl_config[type].__default_vl);
164}
165
166#ifdef CONFIG_ARM64_SVE
167
168static inline int get_sve_default_vl(void)
169{
170 return get_default_vl(ARM64_VEC_SVE);
171}
172
173static inline void set_default_vl(enum vec_type type, int val)
174{
175 WRITE_ONCE(vl_config[type].__default_vl, val);
176}
177
178static inline void set_sve_default_vl(int val)
179{
180 set_default_vl(ARM64_VEC_SVE, val);
181}
182
183static void __percpu *efi_sve_state;
184
185#else /* ! CONFIG_ARM64_SVE */
186
187/* Dummy declaration for code that will be optimised out: */
188extern void __percpu *efi_sve_state;
189
190#endif /* ! CONFIG_ARM64_SVE */
191
192#ifdef CONFIG_ARM64_SME
193
194static int get_sme_default_vl(void)
195{
196 return get_default_vl(ARM64_VEC_SME);
197}
198
199static void set_sme_default_vl(int val)
200{
201 set_default_vl(ARM64_VEC_SME, val);
202}
203
204static void sme_free(struct task_struct *);
205
206#else
207
208static inline void sme_free(struct task_struct *t) { }
209
210#endif
211
212static void fpsimd_bind_task_to_cpu(void);
213
214/*
215 * Claim ownership of the CPU FPSIMD context for use by the calling context.
216 *
217 * The caller may freely manipulate the FPSIMD context metadata until
218 * put_cpu_fpsimd_context() is called.
219 *
220 * On RT kernels local_bh_disable() is not sufficient because it only
221 * serializes soft interrupt related sections via a local lock, but stays
222 * preemptible. Disabling preemption is the right choice here as bottom
223 * half processing is always in thread context on RT kernels so it
224 * implicitly prevents bottom half processing as well.
225 */
226static void get_cpu_fpsimd_context(void)
227{
228 if (!IS_ENABLED(CONFIG_PREEMPT_RT))
229 local_bh_disable();
230 else
231 preempt_disable();
232}
233
234/*
235 * Release the CPU FPSIMD context.
236 *
237 * Must be called from a context in which get_cpu_fpsimd_context() was
238 * previously called, with no call to put_cpu_fpsimd_context() in the
239 * meantime.
240 */
241static void put_cpu_fpsimd_context(void)
242{
243 if (!IS_ENABLED(CONFIG_PREEMPT_RT))
244 local_bh_enable();
245 else
246 preempt_enable();
247}
248
249unsigned int task_get_vl(const struct task_struct *task, enum vec_type type)
250{
251 return task->thread.vl[type];
252}
253
254void task_set_vl(struct task_struct *task, enum vec_type type,
255 unsigned long vl)
256{
257 task->thread.vl[type] = vl;
258}
259
260unsigned int task_get_vl_onexec(const struct task_struct *task,
261 enum vec_type type)
262{
263 return task->thread.vl_onexec[type];
264}
265
266void task_set_vl_onexec(struct task_struct *task, enum vec_type type,
267 unsigned long vl)
268{
269 task->thread.vl_onexec[type] = vl;
270}
271
272/*
273 * TIF_SME controls whether a task can use SME without trapping while
274 * in userspace, when TIF_SME is set then we must have storage
275 * allocated in sve_state and sme_state to store the contents of both ZA
276 * and the SVE registers for both streaming and non-streaming modes.
277 *
278 * If both SVCR.ZA and SVCR.SM are disabled then at any point we
279 * may disable TIF_SME and reenable traps.
280 */
281
282
283/*
284 * TIF_SVE controls whether a task can use SVE without trapping while
285 * in userspace, and also (together with TIF_SME) the way a task's
286 * FPSIMD/SVE state is stored in thread_struct.
287 *
288 * The kernel uses this flag to track whether a user task is actively
289 * using SVE, and therefore whether full SVE register state needs to
290 * be tracked. If not, the cheaper FPSIMD context handling code can
291 * be used instead of the more costly SVE equivalents.
292 *
293 * * TIF_SVE or SVCR.SM set:
294 *
295 * The task can execute SVE instructions while in userspace without
296 * trapping to the kernel.
297 *
298 * During any syscall, the kernel may optionally clear TIF_SVE and
299 * discard the vector state except for the FPSIMD subset.
300 *
301 * * TIF_SVE clear:
302 *
303 * An attempt by the user task to execute an SVE instruction causes
304 * do_sve_acc() to be called, which does some preparation and then
305 * sets TIF_SVE.
306 *
307 * During any syscall, the kernel may optionally clear TIF_SVE and
308 * discard the vector state except for the FPSIMD subset.
309 *
310 * The data will be stored in one of two formats:
311 *
312 * * FPSIMD only - FP_STATE_FPSIMD:
313 *
314 * When the FPSIMD only state stored task->thread.fp_type is set to
315 * FP_STATE_FPSIMD, the FPSIMD registers V0-V31 are encoded in
316 * task->thread.uw.fpsimd_state; bits [max : 128] for each of Z0-Z31 are
317 * logically zero but not stored anywhere; P0-P15 and FFR are not
318 * stored and have unspecified values from userspace's point of
319 * view. For hygiene purposes, the kernel zeroes them on next use,
320 * but userspace is discouraged from relying on this.
321 *
322 * task->thread.sve_state does not need to be non-NULL, valid or any
323 * particular size: it must not be dereferenced and any data stored
324 * there should be considered stale and not referenced.
325 *
326 * * SVE state - FP_STATE_SVE:
327 *
328 * When the full SVE state is stored task->thread.fp_type is set to
329 * FP_STATE_SVE and Z0-Z31 (incorporating Vn in bits[127:0] or the
330 * corresponding Zn), P0-P15 and FFR are encoded in in
331 * task->thread.sve_state, formatted appropriately for vector
332 * length task->thread.sve_vl or, if SVCR.SM is set,
333 * task->thread.sme_vl. The storage for the vector registers in
334 * task->thread.uw.fpsimd_state should be ignored.
335 *
336 * task->thread.sve_state must point to a valid buffer at least
337 * sve_state_size(task) bytes in size. The data stored in
338 * task->thread.uw.fpsimd_state.vregs should be considered stale
339 * and not referenced.
340 *
341 * * FPSR and FPCR are always stored in task->thread.uw.fpsimd_state
342 * irrespective of whether TIF_SVE is clear or set, since these are
343 * not vector length dependent.
344 */
345
346/*
347 * Update current's FPSIMD/SVE registers from thread_struct.
348 *
349 * This function should be called only when the FPSIMD/SVE state in
350 * thread_struct is known to be up to date, when preparing to enter
351 * userspace.
352 */
353static void task_fpsimd_load(void)
354{
355 bool restore_sve_regs = false;
356 bool restore_ffr;
357
358 WARN_ON(!system_supports_fpsimd());
359 WARN_ON(preemptible());
360 WARN_ON(test_thread_flag(TIF_KERNEL_FPSTATE));
361
362 if (system_supports_fpmr())
363 write_sysreg_s(current->thread.uw.fpmr, SYS_FPMR);
364
365 if (system_supports_sve() || system_supports_sme()) {
366 switch (current->thread.fp_type) {
367 case FP_STATE_FPSIMD:
368 /* Stop tracking SVE for this task until next use. */
369 if (test_and_clear_thread_flag(TIF_SVE))
370 sve_user_disable();
371 break;
372 case FP_STATE_SVE:
373 if (!thread_sm_enabled(¤t->thread) &&
374 !WARN_ON_ONCE(!test_and_set_thread_flag(TIF_SVE)))
375 sve_user_enable();
376
377 if (test_thread_flag(TIF_SVE))
378 sve_set_vq(sve_vq_from_vl(task_get_sve_vl(current)) - 1);
379
380 restore_sve_regs = true;
381 restore_ffr = true;
382 break;
383 default:
384 /*
385 * This indicates either a bug in
386 * fpsimd_save_user_state() or memory corruption, we
387 * should always record an explicit format
388 * when we save. We always at least have the
389 * memory allocated for FPSIMD registers so
390 * try that and hope for the best.
391 */
392 WARN_ON_ONCE(1);
393 clear_thread_flag(TIF_SVE);
394 break;
395 }
396 }
397
398 /* Restore SME, override SVE register configuration if needed */
399 if (system_supports_sme()) {
400 unsigned long sme_vl = task_get_sme_vl(current);
401
402 /* Ensure VL is set up for restoring data */
403 if (test_thread_flag(TIF_SME))
404 sme_set_vq(sve_vq_from_vl(sme_vl) - 1);
405
406 write_sysreg_s(current->thread.svcr, SYS_SVCR);
407
408 if (thread_za_enabled(¤t->thread))
409 sme_load_state(current->thread.sme_state,
410 system_supports_sme2());
411
412 if (thread_sm_enabled(¤t->thread))
413 restore_ffr = system_supports_fa64();
414 }
415
416 if (restore_sve_regs) {
417 WARN_ON_ONCE(current->thread.fp_type != FP_STATE_SVE);
418 sve_load_state(sve_pffr(¤t->thread),
419 ¤t->thread.uw.fpsimd_state.fpsr,
420 restore_ffr);
421 } else {
422 WARN_ON_ONCE(current->thread.fp_type != FP_STATE_FPSIMD);
423 fpsimd_load_state(¤t->thread.uw.fpsimd_state);
424 }
425}
426
427/*
428 * Ensure FPSIMD/SVE storage in memory for the loaded context is up to
429 * date with respect to the CPU registers. Note carefully that the
430 * current context is the context last bound to the CPU stored in
431 * last, if KVM is involved this may be the guest VM context rather
432 * than the host thread for the VM pointed to by current. This means
433 * that we must always reference the state storage via last rather
434 * than via current, if we are saving KVM state then it will have
435 * ensured that the type of registers to save is set in last->to_save.
436 */
437static void fpsimd_save_user_state(void)
438{
439 struct cpu_fp_state const *last =
440 this_cpu_ptr(&fpsimd_last_state);
441 /* set by fpsimd_bind_task_to_cpu() or fpsimd_bind_state_to_cpu() */
442 bool save_sve_regs = false;
443 bool save_ffr;
444 unsigned int vl;
445
446 WARN_ON(!system_supports_fpsimd());
447 WARN_ON(preemptible());
448
449 if (test_thread_flag(TIF_FOREIGN_FPSTATE))
450 return;
451
452 if (system_supports_fpmr())
453 *(last->fpmr) = read_sysreg_s(SYS_FPMR);
454
455 /*
456 * If a task is in a syscall the ABI allows us to only
457 * preserve the state shared with FPSIMD so don't bother
458 * saving the full SVE state in that case.
459 */
460 if ((last->to_save == FP_STATE_CURRENT && test_thread_flag(TIF_SVE) &&
461 !in_syscall(current_pt_regs())) ||
462 last->to_save == FP_STATE_SVE) {
463 save_sve_regs = true;
464 save_ffr = true;
465 vl = last->sve_vl;
466 }
467
468 if (system_supports_sme()) {
469 u64 *svcr = last->svcr;
470
471 *svcr = read_sysreg_s(SYS_SVCR);
472
473 if (*svcr & SVCR_ZA_MASK)
474 sme_save_state(last->sme_state,
475 system_supports_sme2());
476
477 /* If we are in streaming mode override regular SVE. */
478 if (*svcr & SVCR_SM_MASK) {
479 save_sve_regs = true;
480 save_ffr = system_supports_fa64();
481 vl = last->sme_vl;
482 }
483 }
484
485 if (IS_ENABLED(CONFIG_ARM64_SVE) && save_sve_regs) {
486 /* Get the configured VL from RDVL, will account for SM */
487 if (WARN_ON(sve_get_vl() != vl)) {
488 /*
489 * Can't save the user regs, so current would
490 * re-enter user with corrupt state.
491 * There's no way to recover, so kill it:
492 */
493 force_signal_inject(SIGKILL, SI_KERNEL, 0, 0);
494 return;
495 }
496
497 sve_save_state((char *)last->sve_state +
498 sve_ffr_offset(vl),
499 &last->st->fpsr, save_ffr);
500 *last->fp_type = FP_STATE_SVE;
501 } else {
502 fpsimd_save_state(last->st);
503 *last->fp_type = FP_STATE_FPSIMD;
504 }
505}
506
507/*
508 * All vector length selection from userspace comes through here.
509 * We're on a slow path, so some sanity-checks are included.
510 * If things go wrong there's a bug somewhere, but try to fall back to a
511 * safe choice.
512 */
513static unsigned int find_supported_vector_length(enum vec_type type,
514 unsigned int vl)
515{
516 struct vl_info *info = &vl_info[type];
517 int bit;
518 int max_vl = info->max_vl;
519
520 if (WARN_ON(!sve_vl_valid(vl)))
521 vl = info->min_vl;
522
523 if (WARN_ON(!sve_vl_valid(max_vl)))
524 max_vl = info->min_vl;
525
526 if (vl > max_vl)
527 vl = max_vl;
528 if (vl < info->min_vl)
529 vl = info->min_vl;
530
531 bit = find_next_bit(info->vq_map, SVE_VQ_MAX,
532 __vq_to_bit(sve_vq_from_vl(vl)));
533 return sve_vl_from_vq(__bit_to_vq(bit));
534}
535
536#if defined(CONFIG_ARM64_SVE) && defined(CONFIG_SYSCTL)
537
538static int vec_proc_do_default_vl(const struct ctl_table *table, int write,
539 void *buffer, size_t *lenp, loff_t *ppos)
540{
541 struct vl_info *info = table->extra1;
542 enum vec_type type = info->type;
543 int ret;
544 int vl = get_default_vl(type);
545 struct ctl_table tmp_table = {
546 .data = &vl,
547 .maxlen = sizeof(vl),
548 };
549
550 ret = proc_dointvec(&tmp_table, write, buffer, lenp, ppos);
551 if (ret || !write)
552 return ret;
553
554 /* Writing -1 has the special meaning "set to max": */
555 if (vl == -1)
556 vl = info->max_vl;
557
558 if (!sve_vl_valid(vl))
559 return -EINVAL;
560
561 set_default_vl(type, find_supported_vector_length(type, vl));
562 return 0;
563}
564
565static struct ctl_table sve_default_vl_table[] = {
566 {
567 .procname = "sve_default_vector_length",
568 .mode = 0644,
569 .proc_handler = vec_proc_do_default_vl,
570 .extra1 = &vl_info[ARM64_VEC_SVE],
571 },
572};
573
574static int __init sve_sysctl_init(void)
575{
576 if (system_supports_sve())
577 if (!register_sysctl("abi", sve_default_vl_table))
578 return -EINVAL;
579
580 return 0;
581}
582
583#else /* ! (CONFIG_ARM64_SVE && CONFIG_SYSCTL) */
584static int __init sve_sysctl_init(void) { return 0; }
585#endif /* ! (CONFIG_ARM64_SVE && CONFIG_SYSCTL) */
586
587#if defined(CONFIG_ARM64_SME) && defined(CONFIG_SYSCTL)
588static struct ctl_table sme_default_vl_table[] = {
589 {
590 .procname = "sme_default_vector_length",
591 .mode = 0644,
592 .proc_handler = vec_proc_do_default_vl,
593 .extra1 = &vl_info[ARM64_VEC_SME],
594 },
595};
596
597static int __init sme_sysctl_init(void)
598{
599 if (system_supports_sme())
600 if (!register_sysctl("abi", sme_default_vl_table))
601 return -EINVAL;
602
603 return 0;
604}
605
606#else /* ! (CONFIG_ARM64_SME && CONFIG_SYSCTL) */
607static int __init sme_sysctl_init(void) { return 0; }
608#endif /* ! (CONFIG_ARM64_SME && CONFIG_SYSCTL) */
609
610#define ZREG(sve_state, vq, n) ((char *)(sve_state) + \
611 (SVE_SIG_ZREG_OFFSET(vq, n) - SVE_SIG_REGS_OFFSET))
612
613#ifdef CONFIG_CPU_BIG_ENDIAN
614static __uint128_t arm64_cpu_to_le128(__uint128_t x)
615{
616 u64 a = swab64(x);
617 u64 b = swab64(x >> 64);
618
619 return ((__uint128_t)a << 64) | b;
620}
621#else
622static __uint128_t arm64_cpu_to_le128(__uint128_t x)
623{
624 return x;
625}
626#endif
627
628#define arm64_le128_to_cpu(x) arm64_cpu_to_le128(x)
629
630static void __fpsimd_to_sve(void *sst, struct user_fpsimd_state const *fst,
631 unsigned int vq)
632{
633 unsigned int i;
634 __uint128_t *p;
635
636 for (i = 0; i < SVE_NUM_ZREGS; ++i) {
637 p = (__uint128_t *)ZREG(sst, vq, i);
638 *p = arm64_cpu_to_le128(fst->vregs[i]);
639 }
640}
641
642/*
643 * Transfer the FPSIMD state in task->thread.uw.fpsimd_state to
644 * task->thread.sve_state.
645 *
646 * Task can be a non-runnable task, or current. In the latter case,
647 * the caller must have ownership of the cpu FPSIMD context before calling
648 * this function.
649 * task->thread.sve_state must point to at least sve_state_size(task)
650 * bytes of allocated kernel memory.
651 * task->thread.uw.fpsimd_state must be up to date before calling this
652 * function.
653 */
654static void fpsimd_to_sve(struct task_struct *task)
655{
656 unsigned int vq;
657 void *sst = task->thread.sve_state;
658 struct user_fpsimd_state const *fst = &task->thread.uw.fpsimd_state;
659
660 if (!system_supports_sve() && !system_supports_sme())
661 return;
662
663 vq = sve_vq_from_vl(thread_get_cur_vl(&task->thread));
664 __fpsimd_to_sve(sst, fst, vq);
665}
666
667/*
668 * Transfer the SVE state in task->thread.sve_state to
669 * task->thread.uw.fpsimd_state.
670 *
671 * Task can be a non-runnable task, or current. In the latter case,
672 * the caller must have ownership of the cpu FPSIMD context before calling
673 * this function.
674 * task->thread.sve_state must point to at least sve_state_size(task)
675 * bytes of allocated kernel memory.
676 * task->thread.sve_state must be up to date before calling this function.
677 */
678static void sve_to_fpsimd(struct task_struct *task)
679{
680 unsigned int vq, vl;
681 void const *sst = task->thread.sve_state;
682 struct user_fpsimd_state *fst = &task->thread.uw.fpsimd_state;
683 unsigned int i;
684 __uint128_t const *p;
685
686 if (!system_supports_sve() && !system_supports_sme())
687 return;
688
689 vl = thread_get_cur_vl(&task->thread);
690 vq = sve_vq_from_vl(vl);
691 for (i = 0; i < SVE_NUM_ZREGS; ++i) {
692 p = (__uint128_t const *)ZREG(sst, vq, i);
693 fst->vregs[i] = arm64_le128_to_cpu(*p);
694 }
695}
696
697void cpu_enable_fpmr(const struct arm64_cpu_capabilities *__always_unused p)
698{
699 write_sysreg_s(read_sysreg_s(SYS_SCTLR_EL1) | SCTLR_EL1_EnFPM_MASK,
700 SYS_SCTLR_EL1);
701}
702
703#ifdef CONFIG_ARM64_SVE
704/*
705 * Call __sve_free() directly only if you know task can't be scheduled
706 * or preempted.
707 */
708static void __sve_free(struct task_struct *task)
709{
710 kfree(task->thread.sve_state);
711 task->thread.sve_state = NULL;
712}
713
714static void sve_free(struct task_struct *task)
715{
716 WARN_ON(test_tsk_thread_flag(task, TIF_SVE));
717
718 __sve_free(task);
719}
720
721/*
722 * Return how many bytes of memory are required to store the full SVE
723 * state for task, given task's currently configured vector length.
724 */
725size_t sve_state_size(struct task_struct const *task)
726{
727 unsigned int vl = 0;
728
729 if (system_supports_sve())
730 vl = task_get_sve_vl(task);
731 if (system_supports_sme())
732 vl = max(vl, task_get_sme_vl(task));
733
734 return SVE_SIG_REGS_SIZE(sve_vq_from_vl(vl));
735}
736
737/*
738 * Ensure that task->thread.sve_state is allocated and sufficiently large.
739 *
740 * This function should be used only in preparation for replacing
741 * task->thread.sve_state with new data. The memory is always zeroed
742 * here to prevent stale data from showing through: this is done in
743 * the interest of testability and predictability: except in the
744 * do_sve_acc() case, there is no ABI requirement to hide stale data
745 * written previously be task.
746 */
747void sve_alloc(struct task_struct *task, bool flush)
748{
749 if (task->thread.sve_state) {
750 if (flush)
751 memset(task->thread.sve_state, 0,
752 sve_state_size(task));
753 return;
754 }
755
756 /* This is a small allocation (maximum ~8KB) and Should Not Fail. */
757 task->thread.sve_state =
758 kzalloc(sve_state_size(task), GFP_KERNEL);
759}
760
761
762/*
763 * Force the FPSIMD state shared with SVE to be updated in the SVE state
764 * even if the SVE state is the current active state.
765 *
766 * This should only be called by ptrace. task must be non-runnable.
767 * task->thread.sve_state must point to at least sve_state_size(task)
768 * bytes of allocated kernel memory.
769 */
770void fpsimd_force_sync_to_sve(struct task_struct *task)
771{
772 fpsimd_to_sve(task);
773}
774
775/*
776 * Ensure that task->thread.sve_state is up to date with respect to
777 * the user task, irrespective of when SVE is in use or not.
778 *
779 * This should only be called by ptrace. task must be non-runnable.
780 * task->thread.sve_state must point to at least sve_state_size(task)
781 * bytes of allocated kernel memory.
782 */
783void fpsimd_sync_to_sve(struct task_struct *task)
784{
785 if (!test_tsk_thread_flag(task, TIF_SVE) &&
786 !thread_sm_enabled(&task->thread))
787 fpsimd_to_sve(task);
788}
789
790/*
791 * Ensure that task->thread.uw.fpsimd_state is up to date with respect to
792 * the user task, irrespective of whether SVE is in use or not.
793 *
794 * This should only be called by ptrace. task must be non-runnable.
795 * task->thread.sve_state must point to at least sve_state_size(task)
796 * bytes of allocated kernel memory.
797 */
798void sve_sync_to_fpsimd(struct task_struct *task)
799{
800 if (task->thread.fp_type == FP_STATE_SVE)
801 sve_to_fpsimd(task);
802}
803
804/*
805 * Ensure that task->thread.sve_state is up to date with respect to
806 * the task->thread.uw.fpsimd_state.
807 *
808 * This should only be called by ptrace to merge new FPSIMD register
809 * values into a task for which SVE is currently active.
810 * task must be non-runnable.
811 * task->thread.sve_state must point to at least sve_state_size(task)
812 * bytes of allocated kernel memory.
813 * task->thread.uw.fpsimd_state must already have been initialised with
814 * the new FPSIMD register values to be merged in.
815 */
816void sve_sync_from_fpsimd_zeropad(struct task_struct *task)
817{
818 unsigned int vq;
819 void *sst = task->thread.sve_state;
820 struct user_fpsimd_state const *fst = &task->thread.uw.fpsimd_state;
821
822 if (!test_tsk_thread_flag(task, TIF_SVE) &&
823 !thread_sm_enabled(&task->thread))
824 return;
825
826 vq = sve_vq_from_vl(thread_get_cur_vl(&task->thread));
827
828 memset(sst, 0, SVE_SIG_REGS_SIZE(vq));
829 __fpsimd_to_sve(sst, fst, vq);
830}
831
832int vec_set_vector_length(struct task_struct *task, enum vec_type type,
833 unsigned long vl, unsigned long flags)
834{
835 bool free_sme = false;
836
837 if (flags & ~(unsigned long)(PR_SVE_VL_INHERIT |
838 PR_SVE_SET_VL_ONEXEC))
839 return -EINVAL;
840
841 if (!sve_vl_valid(vl))
842 return -EINVAL;
843
844 /*
845 * Clamp to the maximum vector length that VL-agnostic code
846 * can work with. A flag may be assigned in the future to
847 * allow setting of larger vector lengths without confusing
848 * older software.
849 */
850 if (vl > VL_ARCH_MAX)
851 vl = VL_ARCH_MAX;
852
853 vl = find_supported_vector_length(type, vl);
854
855 if (flags & (PR_SVE_VL_INHERIT |
856 PR_SVE_SET_VL_ONEXEC))
857 task_set_vl_onexec(task, type, vl);
858 else
859 /* Reset VL to system default on next exec: */
860 task_set_vl_onexec(task, type, 0);
861
862 /* Only actually set the VL if not deferred: */
863 if (flags & PR_SVE_SET_VL_ONEXEC)
864 goto out;
865
866 if (vl == task_get_vl(task, type))
867 goto out;
868
869 /*
870 * To ensure the FPSIMD bits of the SVE vector registers are preserved,
871 * write any live register state back to task_struct, and convert to a
872 * regular FPSIMD thread.
873 */
874 if (task == current) {
875 get_cpu_fpsimd_context();
876
877 fpsimd_save_user_state();
878 }
879
880 fpsimd_flush_task_state(task);
881 if (test_and_clear_tsk_thread_flag(task, TIF_SVE) ||
882 thread_sm_enabled(&task->thread)) {
883 sve_to_fpsimd(task);
884 task->thread.fp_type = FP_STATE_FPSIMD;
885 }
886
887 if (system_supports_sme()) {
888 if (type == ARM64_VEC_SME ||
889 !(task->thread.svcr & (SVCR_SM_MASK | SVCR_ZA_MASK))) {
890 /*
891 * We are changing the SME VL or weren't using
892 * SME anyway, discard the state and force a
893 * reallocation.
894 */
895 task->thread.svcr &= ~(SVCR_SM_MASK |
896 SVCR_ZA_MASK);
897 clear_tsk_thread_flag(task, TIF_SME);
898 free_sme = true;
899 }
900 }
901
902 if (task == current)
903 put_cpu_fpsimd_context();
904
905 task_set_vl(task, type, vl);
906
907 /*
908 * Free the changed states if they are not in use, SME will be
909 * reallocated to the correct size on next use and we just
910 * allocate SVE now in case it is needed for use in streaming
911 * mode.
912 */
913 sve_free(task);
914 sve_alloc(task, true);
915
916 if (free_sme)
917 sme_free(task);
918
919out:
920 update_tsk_thread_flag(task, vec_vl_inherit_flag(type),
921 flags & PR_SVE_VL_INHERIT);
922
923 return 0;
924}
925
926/*
927 * Encode the current vector length and flags for return.
928 * This is only required for prctl(): ptrace has separate fields.
929 * SVE and SME use the same bits for _ONEXEC and _INHERIT.
930 *
931 * flags are as for vec_set_vector_length().
932 */
933static int vec_prctl_status(enum vec_type type, unsigned long flags)
934{
935 int ret;
936
937 if (flags & PR_SVE_SET_VL_ONEXEC)
938 ret = task_get_vl_onexec(current, type);
939 else
940 ret = task_get_vl(current, type);
941
942 if (test_thread_flag(vec_vl_inherit_flag(type)))
943 ret |= PR_SVE_VL_INHERIT;
944
945 return ret;
946}
947
948/* PR_SVE_SET_VL */
949int sve_set_current_vl(unsigned long arg)
950{
951 unsigned long vl, flags;
952 int ret;
953
954 vl = arg & PR_SVE_VL_LEN_MASK;
955 flags = arg & ~vl;
956
957 if (!system_supports_sve() || is_compat_task())
958 return -EINVAL;
959
960 ret = vec_set_vector_length(current, ARM64_VEC_SVE, vl, flags);
961 if (ret)
962 return ret;
963
964 return vec_prctl_status(ARM64_VEC_SVE, flags);
965}
966
967/* PR_SVE_GET_VL */
968int sve_get_current_vl(void)
969{
970 if (!system_supports_sve() || is_compat_task())
971 return -EINVAL;
972
973 return vec_prctl_status(ARM64_VEC_SVE, 0);
974}
975
976#ifdef CONFIG_ARM64_SME
977/* PR_SME_SET_VL */
978int sme_set_current_vl(unsigned long arg)
979{
980 unsigned long vl, flags;
981 int ret;
982
983 vl = arg & PR_SME_VL_LEN_MASK;
984 flags = arg & ~vl;
985
986 if (!system_supports_sme() || is_compat_task())
987 return -EINVAL;
988
989 ret = vec_set_vector_length(current, ARM64_VEC_SME, vl, flags);
990 if (ret)
991 return ret;
992
993 return vec_prctl_status(ARM64_VEC_SME, flags);
994}
995
996/* PR_SME_GET_VL */
997int sme_get_current_vl(void)
998{
999 if (!system_supports_sme() || is_compat_task())
1000 return -EINVAL;
1001
1002 return vec_prctl_status(ARM64_VEC_SME, 0);
1003}
1004#endif /* CONFIG_ARM64_SME */
1005
1006static void vec_probe_vqs(struct vl_info *info,
1007 DECLARE_BITMAP(map, SVE_VQ_MAX))
1008{
1009 unsigned int vq, vl;
1010
1011 bitmap_zero(map, SVE_VQ_MAX);
1012
1013 for (vq = SVE_VQ_MAX; vq >= SVE_VQ_MIN; --vq) {
1014 write_vl(info->type, vq - 1); /* self-syncing */
1015
1016 switch (info->type) {
1017 case ARM64_VEC_SVE:
1018 vl = sve_get_vl();
1019 break;
1020 case ARM64_VEC_SME:
1021 vl = sme_get_vl();
1022 break;
1023 default:
1024 vl = 0;
1025 break;
1026 }
1027
1028 /* Minimum VL identified? */
1029 if (sve_vq_from_vl(vl) > vq)
1030 break;
1031
1032 vq = sve_vq_from_vl(vl); /* skip intervening lengths */
1033 set_bit(__vq_to_bit(vq), map);
1034 }
1035}
1036
1037/*
1038 * Initialise the set of known supported VQs for the boot CPU.
1039 * This is called during kernel boot, before secondary CPUs are brought up.
1040 */
1041void __init vec_init_vq_map(enum vec_type type)
1042{
1043 struct vl_info *info = &vl_info[type];
1044 vec_probe_vqs(info, info->vq_map);
1045 bitmap_copy(info->vq_partial_map, info->vq_map, SVE_VQ_MAX);
1046}
1047
1048/*
1049 * If we haven't committed to the set of supported VQs yet, filter out
1050 * those not supported by the current CPU.
1051 * This function is called during the bring-up of early secondary CPUs only.
1052 */
1053void vec_update_vq_map(enum vec_type type)
1054{
1055 struct vl_info *info = &vl_info[type];
1056 DECLARE_BITMAP(tmp_map, SVE_VQ_MAX);
1057
1058 vec_probe_vqs(info, tmp_map);
1059 bitmap_and(info->vq_map, info->vq_map, tmp_map, SVE_VQ_MAX);
1060 bitmap_or(info->vq_partial_map, info->vq_partial_map, tmp_map,
1061 SVE_VQ_MAX);
1062}
1063
1064/*
1065 * Check whether the current CPU supports all VQs in the committed set.
1066 * This function is called during the bring-up of late secondary CPUs only.
1067 */
1068int vec_verify_vq_map(enum vec_type type)
1069{
1070 struct vl_info *info = &vl_info[type];
1071 DECLARE_BITMAP(tmp_map, SVE_VQ_MAX);
1072 unsigned long b;
1073
1074 vec_probe_vqs(info, tmp_map);
1075
1076 bitmap_complement(tmp_map, tmp_map, SVE_VQ_MAX);
1077 if (bitmap_intersects(tmp_map, info->vq_map, SVE_VQ_MAX)) {
1078 pr_warn("%s: cpu%d: Required vector length(s) missing\n",
1079 info->name, smp_processor_id());
1080 return -EINVAL;
1081 }
1082
1083 if (!IS_ENABLED(CONFIG_KVM) || !is_hyp_mode_available())
1084 return 0;
1085
1086 /*
1087 * For KVM, it is necessary to ensure that this CPU doesn't
1088 * support any vector length that guests may have probed as
1089 * unsupported.
1090 */
1091
1092 /* Recover the set of supported VQs: */
1093 bitmap_complement(tmp_map, tmp_map, SVE_VQ_MAX);
1094 /* Find VQs supported that are not globally supported: */
1095 bitmap_andnot(tmp_map, tmp_map, info->vq_map, SVE_VQ_MAX);
1096
1097 /* Find the lowest such VQ, if any: */
1098 b = find_last_bit(tmp_map, SVE_VQ_MAX);
1099 if (b >= SVE_VQ_MAX)
1100 return 0; /* no mismatches */
1101
1102 /*
1103 * Mismatches above sve_max_virtualisable_vl are fine, since
1104 * no guest is allowed to configure ZCR_EL2.LEN to exceed this:
1105 */
1106 if (sve_vl_from_vq(__bit_to_vq(b)) <= info->max_virtualisable_vl) {
1107 pr_warn("%s: cpu%d: Unsupported vector length(s) present\n",
1108 info->name, smp_processor_id());
1109 return -EINVAL;
1110 }
1111
1112 return 0;
1113}
1114
1115static void __init sve_efi_setup(void)
1116{
1117 int max_vl = 0;
1118 int i;
1119
1120 if (!IS_ENABLED(CONFIG_EFI))
1121 return;
1122
1123 for (i = 0; i < ARRAY_SIZE(vl_info); i++)
1124 max_vl = max(vl_info[i].max_vl, max_vl);
1125
1126 /*
1127 * alloc_percpu() warns and prints a backtrace if this goes wrong.
1128 * This is evidence of a crippled system and we are returning void,
1129 * so no attempt is made to handle this situation here.
1130 */
1131 if (!sve_vl_valid(max_vl))
1132 goto fail;
1133
1134 efi_sve_state = __alloc_percpu(
1135 SVE_SIG_REGS_SIZE(sve_vq_from_vl(max_vl)), SVE_VQ_BYTES);
1136 if (!efi_sve_state)
1137 goto fail;
1138
1139 return;
1140
1141fail:
1142 panic("Cannot allocate percpu memory for EFI SVE save/restore");
1143}
1144
1145void cpu_enable_sve(const struct arm64_cpu_capabilities *__always_unused p)
1146{
1147 write_sysreg(read_sysreg(CPACR_EL1) | CPACR_EL1_ZEN_EL1EN, CPACR_EL1);
1148 isb();
1149
1150 write_sysreg_s(0, SYS_ZCR_EL1);
1151}
1152
1153void __init sve_setup(void)
1154{
1155 struct vl_info *info = &vl_info[ARM64_VEC_SVE];
1156 DECLARE_BITMAP(tmp_map, SVE_VQ_MAX);
1157 unsigned long b;
1158 int max_bit;
1159
1160 if (!system_supports_sve())
1161 return;
1162
1163 /*
1164 * The SVE architecture mandates support for 128-bit vectors,
1165 * so sve_vq_map must have at least SVE_VQ_MIN set.
1166 * If something went wrong, at least try to patch it up:
1167 */
1168 if (WARN_ON(!test_bit(__vq_to_bit(SVE_VQ_MIN), info->vq_map)))
1169 set_bit(__vq_to_bit(SVE_VQ_MIN), info->vq_map);
1170
1171 max_bit = find_first_bit(info->vq_map, SVE_VQ_MAX);
1172 info->max_vl = sve_vl_from_vq(__bit_to_vq(max_bit));
1173
1174 /*
1175 * For the default VL, pick the maximum supported value <= 64.
1176 * VL == 64 is guaranteed not to grow the signal frame.
1177 */
1178 set_sve_default_vl(find_supported_vector_length(ARM64_VEC_SVE, 64));
1179
1180 bitmap_andnot(tmp_map, info->vq_partial_map, info->vq_map,
1181 SVE_VQ_MAX);
1182
1183 b = find_last_bit(tmp_map, SVE_VQ_MAX);
1184 if (b >= SVE_VQ_MAX)
1185 /* No non-virtualisable VLs found */
1186 info->max_virtualisable_vl = SVE_VQ_MAX;
1187 else if (WARN_ON(b == SVE_VQ_MAX - 1))
1188 /* No virtualisable VLs? This is architecturally forbidden. */
1189 info->max_virtualisable_vl = SVE_VQ_MIN;
1190 else /* b + 1 < SVE_VQ_MAX */
1191 info->max_virtualisable_vl = sve_vl_from_vq(__bit_to_vq(b + 1));
1192
1193 if (info->max_virtualisable_vl > info->max_vl)
1194 info->max_virtualisable_vl = info->max_vl;
1195
1196 pr_info("%s: maximum available vector length %u bytes per vector\n",
1197 info->name, info->max_vl);
1198 pr_info("%s: default vector length %u bytes per vector\n",
1199 info->name, get_sve_default_vl());
1200
1201 /* KVM decides whether to support mismatched systems. Just warn here: */
1202 if (sve_max_virtualisable_vl() < sve_max_vl())
1203 pr_warn("%s: unvirtualisable vector lengths present\n",
1204 info->name);
1205
1206 sve_efi_setup();
1207}
1208
1209/*
1210 * Called from the put_task_struct() path, which cannot get here
1211 * unless dead_task is really dead and not schedulable.
1212 */
1213void fpsimd_release_task(struct task_struct *dead_task)
1214{
1215 __sve_free(dead_task);
1216 sme_free(dead_task);
1217}
1218
1219#endif /* CONFIG_ARM64_SVE */
1220
1221#ifdef CONFIG_ARM64_SME
1222
1223/*
1224 * Ensure that task->thread.sme_state is allocated and sufficiently large.
1225 *
1226 * This function should be used only in preparation for replacing
1227 * task->thread.sme_state with new data. The memory is always zeroed
1228 * here to prevent stale data from showing through: this is done in
1229 * the interest of testability and predictability, the architecture
1230 * guarantees that when ZA is enabled it will be zeroed.
1231 */
1232void sme_alloc(struct task_struct *task, bool flush)
1233{
1234 if (task->thread.sme_state) {
1235 if (flush)
1236 memset(task->thread.sme_state, 0,
1237 sme_state_size(task));
1238 return;
1239 }
1240
1241 /* This could potentially be up to 64K. */
1242 task->thread.sme_state =
1243 kzalloc(sme_state_size(task), GFP_KERNEL);
1244}
1245
1246static void sme_free(struct task_struct *task)
1247{
1248 kfree(task->thread.sme_state);
1249 task->thread.sme_state = NULL;
1250}
1251
1252void cpu_enable_sme(const struct arm64_cpu_capabilities *__always_unused p)
1253{
1254 /* Set priority for all PEs to architecturally defined minimum */
1255 write_sysreg_s(read_sysreg_s(SYS_SMPRI_EL1) & ~SMPRI_EL1_PRIORITY_MASK,
1256 SYS_SMPRI_EL1);
1257
1258 /* Allow SME in kernel */
1259 write_sysreg(read_sysreg(CPACR_EL1) | CPACR_EL1_SMEN_EL1EN, CPACR_EL1);
1260 isb();
1261
1262 /* Ensure all bits in SMCR are set to known values */
1263 write_sysreg_s(0, SYS_SMCR_EL1);
1264
1265 /* Allow EL0 to access TPIDR2 */
1266 write_sysreg(read_sysreg(SCTLR_EL1) | SCTLR_ELx_ENTP2, SCTLR_EL1);
1267 isb();
1268}
1269
1270void cpu_enable_sme2(const struct arm64_cpu_capabilities *__always_unused p)
1271{
1272 /* This must be enabled after SME */
1273 BUILD_BUG_ON(ARM64_SME2 <= ARM64_SME);
1274
1275 /* Allow use of ZT0 */
1276 write_sysreg_s(read_sysreg_s(SYS_SMCR_EL1) | SMCR_ELx_EZT0_MASK,
1277 SYS_SMCR_EL1);
1278}
1279
1280void cpu_enable_fa64(const struct arm64_cpu_capabilities *__always_unused p)
1281{
1282 /* This must be enabled after SME */
1283 BUILD_BUG_ON(ARM64_SME_FA64 <= ARM64_SME);
1284
1285 /* Allow use of FA64 */
1286 write_sysreg_s(read_sysreg_s(SYS_SMCR_EL1) | SMCR_ELx_FA64_MASK,
1287 SYS_SMCR_EL1);
1288}
1289
1290void __init sme_setup(void)
1291{
1292 struct vl_info *info = &vl_info[ARM64_VEC_SME];
1293 int min_bit, max_bit;
1294
1295 if (!system_supports_sme())
1296 return;
1297
1298 /*
1299 * SME doesn't require any particular vector length be
1300 * supported but it does require at least one. We should have
1301 * disabled the feature entirely while bringing up CPUs but
1302 * let's double check here. The bitmap is SVE_VQ_MAP sized for
1303 * sharing with SVE.
1304 */
1305 WARN_ON(bitmap_empty(info->vq_map, SVE_VQ_MAX));
1306
1307 min_bit = find_last_bit(info->vq_map, SVE_VQ_MAX);
1308 info->min_vl = sve_vl_from_vq(__bit_to_vq(min_bit));
1309
1310 max_bit = find_first_bit(info->vq_map, SVE_VQ_MAX);
1311 info->max_vl = sve_vl_from_vq(__bit_to_vq(max_bit));
1312
1313 WARN_ON(info->min_vl > info->max_vl);
1314
1315 /*
1316 * For the default VL, pick the maximum supported value <= 32
1317 * (256 bits) if there is one since this is guaranteed not to
1318 * grow the signal frame when in streaming mode, otherwise the
1319 * minimum available VL will be used.
1320 */
1321 set_sme_default_vl(find_supported_vector_length(ARM64_VEC_SME, 32));
1322
1323 pr_info("SME: minimum available vector length %u bytes per vector\n",
1324 info->min_vl);
1325 pr_info("SME: maximum available vector length %u bytes per vector\n",
1326 info->max_vl);
1327 pr_info("SME: default vector length %u bytes per vector\n",
1328 get_sme_default_vl());
1329}
1330
1331void sme_suspend_exit(void)
1332{
1333 u64 smcr = 0;
1334
1335 if (!system_supports_sme())
1336 return;
1337
1338 if (system_supports_fa64())
1339 smcr |= SMCR_ELx_FA64;
1340 if (system_supports_sme2())
1341 smcr |= SMCR_ELx_EZT0;
1342
1343 write_sysreg_s(smcr, SYS_SMCR_EL1);
1344 write_sysreg_s(0, SYS_SMPRI_EL1);
1345}
1346
1347#endif /* CONFIG_ARM64_SME */
1348
1349static void sve_init_regs(void)
1350{
1351 /*
1352 * Convert the FPSIMD state to SVE, zeroing all the state that
1353 * is not shared with FPSIMD. If (as is likely) the current
1354 * state is live in the registers then do this there and
1355 * update our metadata for the current task including
1356 * disabling the trap, otherwise update our in-memory copy.
1357 * We are guaranteed to not be in streaming mode, we can only
1358 * take a SVE trap when not in streaming mode and we can't be
1359 * in streaming mode when taking a SME trap.
1360 */
1361 if (!test_thread_flag(TIF_FOREIGN_FPSTATE)) {
1362 unsigned long vq_minus_one =
1363 sve_vq_from_vl(task_get_sve_vl(current)) - 1;
1364 sve_set_vq(vq_minus_one);
1365 sve_flush_live(true, vq_minus_one);
1366 fpsimd_bind_task_to_cpu();
1367 } else {
1368 fpsimd_to_sve(current);
1369 current->thread.fp_type = FP_STATE_SVE;
1370 fpsimd_flush_task_state(current);
1371 }
1372}
1373
1374/*
1375 * Trapped SVE access
1376 *
1377 * Storage is allocated for the full SVE state, the current FPSIMD
1378 * register contents are migrated across, and the access trap is
1379 * disabled.
1380 *
1381 * TIF_SVE should be clear on entry: otherwise, fpsimd_restore_current_state()
1382 * would have disabled the SVE access trap for userspace during
1383 * ret_to_user, making an SVE access trap impossible in that case.
1384 */
1385void do_sve_acc(unsigned long esr, struct pt_regs *regs)
1386{
1387 /* Even if we chose not to use SVE, the hardware could still trap: */
1388 if (unlikely(!system_supports_sve()) || WARN_ON(is_compat_task())) {
1389 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0);
1390 return;
1391 }
1392
1393 sve_alloc(current, true);
1394 if (!current->thread.sve_state) {
1395 force_sig(SIGKILL);
1396 return;
1397 }
1398
1399 get_cpu_fpsimd_context();
1400
1401 if (test_and_set_thread_flag(TIF_SVE))
1402 WARN_ON(1); /* SVE access shouldn't have trapped */
1403
1404 /*
1405 * Even if the task can have used streaming mode we can only
1406 * generate SVE access traps in normal SVE mode and
1407 * transitioning out of streaming mode may discard any
1408 * streaming mode state. Always clear the high bits to avoid
1409 * any potential errors tracking what is properly initialised.
1410 */
1411 sve_init_regs();
1412
1413 put_cpu_fpsimd_context();
1414}
1415
1416/*
1417 * Trapped SME access
1418 *
1419 * Storage is allocated for the full SVE and SME state, the current
1420 * FPSIMD register contents are migrated to SVE if SVE is not already
1421 * active, and the access trap is disabled.
1422 *
1423 * TIF_SME should be clear on entry: otherwise, fpsimd_restore_current_state()
1424 * would have disabled the SME access trap for userspace during
1425 * ret_to_user, making an SME access trap impossible in that case.
1426 */
1427void do_sme_acc(unsigned long esr, struct pt_regs *regs)
1428{
1429 /* Even if we chose not to use SME, the hardware could still trap: */
1430 if (unlikely(!system_supports_sme()) || WARN_ON(is_compat_task())) {
1431 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0);
1432 return;
1433 }
1434
1435 /*
1436 * If this not a trap due to SME being disabled then something
1437 * is being used in the wrong mode, report as SIGILL.
1438 */
1439 if (ESR_ELx_ISS(esr) != ESR_ELx_SME_ISS_SME_DISABLED) {
1440 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0);
1441 return;
1442 }
1443
1444 sve_alloc(current, false);
1445 sme_alloc(current, true);
1446 if (!current->thread.sve_state || !current->thread.sme_state) {
1447 force_sig(SIGKILL);
1448 return;
1449 }
1450
1451 get_cpu_fpsimd_context();
1452
1453 /* With TIF_SME userspace shouldn't generate any traps */
1454 if (test_and_set_thread_flag(TIF_SME))
1455 WARN_ON(1);
1456
1457 if (!test_thread_flag(TIF_FOREIGN_FPSTATE)) {
1458 unsigned long vq_minus_one =
1459 sve_vq_from_vl(task_get_sme_vl(current)) - 1;
1460 sme_set_vq(vq_minus_one);
1461
1462 fpsimd_bind_task_to_cpu();
1463 }
1464
1465 put_cpu_fpsimd_context();
1466}
1467
1468/*
1469 * Trapped FP/ASIMD access.
1470 */
1471void do_fpsimd_acc(unsigned long esr, struct pt_regs *regs)
1472{
1473 /* Even if we chose not to use FPSIMD, the hardware could still trap: */
1474 if (!system_supports_fpsimd()) {
1475 force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0);
1476 return;
1477 }
1478
1479 /*
1480 * When FPSIMD is enabled, we should never take a trap unless something
1481 * has gone very wrong.
1482 */
1483 BUG();
1484}
1485
1486/*
1487 * Raise a SIGFPE for the current process.
1488 */
1489void do_fpsimd_exc(unsigned long esr, struct pt_regs *regs)
1490{
1491 unsigned int si_code = FPE_FLTUNK;
1492
1493 if (esr & ESR_ELx_FP_EXC_TFV) {
1494 if (esr & FPEXC_IOF)
1495 si_code = FPE_FLTINV;
1496 else if (esr & FPEXC_DZF)
1497 si_code = FPE_FLTDIV;
1498 else if (esr & FPEXC_OFF)
1499 si_code = FPE_FLTOVF;
1500 else if (esr & FPEXC_UFF)
1501 si_code = FPE_FLTUND;
1502 else if (esr & FPEXC_IXF)
1503 si_code = FPE_FLTRES;
1504 }
1505
1506 send_sig_fault(SIGFPE, si_code,
1507 (void __user *)instruction_pointer(regs),
1508 current);
1509}
1510
1511static void fpsimd_load_kernel_state(struct task_struct *task)
1512{
1513 struct cpu_fp_state *last = this_cpu_ptr(&fpsimd_last_state);
1514
1515 /*
1516 * Elide the load if this CPU holds the most recent kernel mode
1517 * FPSIMD context of the current task.
1518 */
1519 if (last->st == &task->thread.kernel_fpsimd_state &&
1520 task->thread.kernel_fpsimd_cpu == smp_processor_id())
1521 return;
1522
1523 fpsimd_load_state(&task->thread.kernel_fpsimd_state);
1524}
1525
1526static void fpsimd_save_kernel_state(struct task_struct *task)
1527{
1528 struct cpu_fp_state cpu_fp_state = {
1529 .st = &task->thread.kernel_fpsimd_state,
1530 .to_save = FP_STATE_FPSIMD,
1531 };
1532
1533 fpsimd_save_state(&task->thread.kernel_fpsimd_state);
1534 fpsimd_bind_state_to_cpu(&cpu_fp_state);
1535
1536 task->thread.kernel_fpsimd_cpu = smp_processor_id();
1537}
1538
1539/*
1540 * Invalidate any task's FPSIMD state that is present on this cpu.
1541 * The FPSIMD context should be acquired with get_cpu_fpsimd_context()
1542 * before calling this function.
1543 */
1544static void fpsimd_flush_cpu_state(void)
1545{
1546 WARN_ON(!system_supports_fpsimd());
1547 __this_cpu_write(fpsimd_last_state.st, NULL);
1548
1549 /*
1550 * Leaving streaming mode enabled will cause issues for any kernel
1551 * NEON and leaving streaming mode or ZA enabled may increase power
1552 * consumption.
1553 */
1554 if (system_supports_sme())
1555 sme_smstop();
1556
1557 set_thread_flag(TIF_FOREIGN_FPSTATE);
1558}
1559
1560void fpsimd_thread_switch(struct task_struct *next)
1561{
1562 bool wrong_task, wrong_cpu;
1563
1564 if (!system_supports_fpsimd())
1565 return;
1566
1567 WARN_ON_ONCE(!irqs_disabled());
1568
1569 /* Save unsaved fpsimd state, if any: */
1570 if (test_thread_flag(TIF_KERNEL_FPSTATE))
1571 fpsimd_save_kernel_state(current);
1572 else
1573 fpsimd_save_user_state();
1574
1575 if (test_tsk_thread_flag(next, TIF_KERNEL_FPSTATE)) {
1576 fpsimd_load_kernel_state(next);
1577 fpsimd_flush_cpu_state();
1578 } else {
1579 /*
1580 * Fix up TIF_FOREIGN_FPSTATE to correctly describe next's
1581 * state. For kernel threads, FPSIMD registers are never
1582 * loaded with user mode FPSIMD state and so wrong_task and
1583 * wrong_cpu will always be true.
1584 */
1585 wrong_task = __this_cpu_read(fpsimd_last_state.st) !=
1586 &next->thread.uw.fpsimd_state;
1587 wrong_cpu = next->thread.fpsimd_cpu != smp_processor_id();
1588
1589 update_tsk_thread_flag(next, TIF_FOREIGN_FPSTATE,
1590 wrong_task || wrong_cpu);
1591 }
1592}
1593
1594static void fpsimd_flush_thread_vl(enum vec_type type)
1595{
1596 int vl, supported_vl;
1597
1598 /*
1599 * Reset the task vector length as required. This is where we
1600 * ensure that all user tasks have a valid vector length
1601 * configured: no kernel task can become a user task without
1602 * an exec and hence a call to this function. By the time the
1603 * first call to this function is made, all early hardware
1604 * probing is complete, so __sve_default_vl should be valid.
1605 * If a bug causes this to go wrong, we make some noise and
1606 * try to fudge thread.sve_vl to a safe value here.
1607 */
1608 vl = task_get_vl_onexec(current, type);
1609 if (!vl)
1610 vl = get_default_vl(type);
1611
1612 if (WARN_ON(!sve_vl_valid(vl)))
1613 vl = vl_info[type].min_vl;
1614
1615 supported_vl = find_supported_vector_length(type, vl);
1616 if (WARN_ON(supported_vl != vl))
1617 vl = supported_vl;
1618
1619 task_set_vl(current, type, vl);
1620
1621 /*
1622 * If the task is not set to inherit, ensure that the vector
1623 * length will be reset by a subsequent exec:
1624 */
1625 if (!test_thread_flag(vec_vl_inherit_flag(type)))
1626 task_set_vl_onexec(current, type, 0);
1627}
1628
1629void fpsimd_flush_thread(void)
1630{
1631 void *sve_state = NULL;
1632 void *sme_state = NULL;
1633
1634 if (!system_supports_fpsimd())
1635 return;
1636
1637 get_cpu_fpsimd_context();
1638
1639 fpsimd_flush_task_state(current);
1640 memset(¤t->thread.uw.fpsimd_state, 0,
1641 sizeof(current->thread.uw.fpsimd_state));
1642
1643 if (system_supports_sve()) {
1644 clear_thread_flag(TIF_SVE);
1645
1646 /* Defer kfree() while in atomic context */
1647 sve_state = current->thread.sve_state;
1648 current->thread.sve_state = NULL;
1649
1650 fpsimd_flush_thread_vl(ARM64_VEC_SVE);
1651 }
1652
1653 if (system_supports_sme()) {
1654 clear_thread_flag(TIF_SME);
1655
1656 /* Defer kfree() while in atomic context */
1657 sme_state = current->thread.sme_state;
1658 current->thread.sme_state = NULL;
1659
1660 fpsimd_flush_thread_vl(ARM64_VEC_SME);
1661 current->thread.svcr = 0;
1662 }
1663
1664 current->thread.fp_type = FP_STATE_FPSIMD;
1665
1666 put_cpu_fpsimd_context();
1667 kfree(sve_state);
1668 kfree(sme_state);
1669}
1670
1671/*
1672 * Save the userland FPSIMD state of 'current' to memory, but only if the state
1673 * currently held in the registers does in fact belong to 'current'
1674 */
1675void fpsimd_preserve_current_state(void)
1676{
1677 if (!system_supports_fpsimd())
1678 return;
1679
1680 get_cpu_fpsimd_context();
1681 fpsimd_save_user_state();
1682 put_cpu_fpsimd_context();
1683}
1684
1685/*
1686 * Like fpsimd_preserve_current_state(), but ensure that
1687 * current->thread.uw.fpsimd_state is updated so that it can be copied to
1688 * the signal frame.
1689 */
1690void fpsimd_signal_preserve_current_state(void)
1691{
1692 fpsimd_preserve_current_state();
1693 if (current->thread.fp_type == FP_STATE_SVE)
1694 sve_to_fpsimd(current);
1695}
1696
1697/*
1698 * Called by KVM when entering the guest.
1699 */
1700void fpsimd_kvm_prepare(void)
1701{
1702 if (!system_supports_sve())
1703 return;
1704
1705 /*
1706 * KVM does not save host SVE state since we can only enter
1707 * the guest from a syscall so the ABI means that only the
1708 * non-saved SVE state needs to be saved. If we have left
1709 * SVE enabled for performance reasons then update the task
1710 * state to be FPSIMD only.
1711 */
1712 get_cpu_fpsimd_context();
1713
1714 if (test_and_clear_thread_flag(TIF_SVE)) {
1715 sve_to_fpsimd(current);
1716 current->thread.fp_type = FP_STATE_FPSIMD;
1717 }
1718
1719 put_cpu_fpsimd_context();
1720}
1721
1722/*
1723 * Associate current's FPSIMD context with this cpu
1724 * The caller must have ownership of the cpu FPSIMD context before calling
1725 * this function.
1726 */
1727static void fpsimd_bind_task_to_cpu(void)
1728{
1729 struct cpu_fp_state *last = this_cpu_ptr(&fpsimd_last_state);
1730
1731 WARN_ON(!system_supports_fpsimd());
1732 last->st = ¤t->thread.uw.fpsimd_state;
1733 last->sve_state = current->thread.sve_state;
1734 last->sme_state = current->thread.sme_state;
1735 last->sve_vl = task_get_sve_vl(current);
1736 last->sme_vl = task_get_sme_vl(current);
1737 last->svcr = ¤t->thread.svcr;
1738 last->fpmr = ¤t->thread.uw.fpmr;
1739 last->fp_type = ¤t->thread.fp_type;
1740 last->to_save = FP_STATE_CURRENT;
1741 current->thread.fpsimd_cpu = smp_processor_id();
1742
1743 /*
1744 * Toggle SVE and SME trapping for userspace if needed, these
1745 * are serialsied by ret_to_user().
1746 */
1747 if (system_supports_sme()) {
1748 if (test_thread_flag(TIF_SME))
1749 sme_user_enable();
1750 else
1751 sme_user_disable();
1752 }
1753
1754 if (system_supports_sve()) {
1755 if (test_thread_flag(TIF_SVE))
1756 sve_user_enable();
1757 else
1758 sve_user_disable();
1759 }
1760}
1761
1762void fpsimd_bind_state_to_cpu(struct cpu_fp_state *state)
1763{
1764 struct cpu_fp_state *last = this_cpu_ptr(&fpsimd_last_state);
1765
1766 WARN_ON(!system_supports_fpsimd());
1767 WARN_ON(!in_softirq() && !irqs_disabled());
1768
1769 *last = *state;
1770}
1771
1772/*
1773 * Load the userland FPSIMD state of 'current' from memory, but only if the
1774 * FPSIMD state already held in the registers is /not/ the most recent FPSIMD
1775 * state of 'current'. This is called when we are preparing to return to
1776 * userspace to ensure that userspace sees a good register state.
1777 */
1778void fpsimd_restore_current_state(void)
1779{
1780 /*
1781 * TIF_FOREIGN_FPSTATE is set on the init task and copied by
1782 * arch_dup_task_struct() regardless of whether FP/SIMD is detected.
1783 * Thus user threads can have this set even when FP/SIMD hasn't been
1784 * detected.
1785 *
1786 * When FP/SIMD is detected, begin_new_exec() will set
1787 * TIF_FOREIGN_FPSTATE via flush_thread() -> fpsimd_flush_thread(),
1788 * and fpsimd_thread_switch() will set TIF_FOREIGN_FPSTATE when
1789 * switching tasks. We detect FP/SIMD before we exec the first user
1790 * process, ensuring this has TIF_FOREIGN_FPSTATE set and
1791 * do_notify_resume() will call fpsimd_restore_current_state() to
1792 * install the user FP/SIMD context.
1793 *
1794 * When FP/SIMD is not detected, nothing else will clear or set
1795 * TIF_FOREIGN_FPSTATE prior to the first return to userspace, and
1796 * we must clear TIF_FOREIGN_FPSTATE to avoid do_notify_resume()
1797 * looping forever calling fpsimd_restore_current_state().
1798 */
1799 if (!system_supports_fpsimd()) {
1800 clear_thread_flag(TIF_FOREIGN_FPSTATE);
1801 return;
1802 }
1803
1804 get_cpu_fpsimd_context();
1805
1806 if (test_and_clear_thread_flag(TIF_FOREIGN_FPSTATE)) {
1807 task_fpsimd_load();
1808 fpsimd_bind_task_to_cpu();
1809 }
1810
1811 put_cpu_fpsimd_context();
1812}
1813
1814/*
1815 * Load an updated userland FPSIMD state for 'current' from memory and set the
1816 * flag that indicates that the FPSIMD register contents are the most recent
1817 * FPSIMD state of 'current'. This is used by the signal code to restore the
1818 * register state when returning from a signal handler in FPSIMD only cases,
1819 * any SVE context will be discarded.
1820 */
1821void fpsimd_update_current_state(struct user_fpsimd_state const *state)
1822{
1823 if (WARN_ON(!system_supports_fpsimd()))
1824 return;
1825
1826 get_cpu_fpsimd_context();
1827
1828 current->thread.uw.fpsimd_state = *state;
1829 if (test_thread_flag(TIF_SVE))
1830 fpsimd_to_sve(current);
1831
1832 task_fpsimd_load();
1833 fpsimd_bind_task_to_cpu();
1834
1835 clear_thread_flag(TIF_FOREIGN_FPSTATE);
1836
1837 put_cpu_fpsimd_context();
1838}
1839
1840/*
1841 * Invalidate live CPU copies of task t's FPSIMD state
1842 *
1843 * This function may be called with preemption enabled. The barrier()
1844 * ensures that the assignment to fpsimd_cpu is visible to any
1845 * preemption/softirq that could race with set_tsk_thread_flag(), so
1846 * that TIF_FOREIGN_FPSTATE cannot be spuriously re-cleared.
1847 *
1848 * The final barrier ensures that TIF_FOREIGN_FPSTATE is seen set by any
1849 * subsequent code.
1850 */
1851void fpsimd_flush_task_state(struct task_struct *t)
1852{
1853 t->thread.fpsimd_cpu = NR_CPUS;
1854 /*
1855 * If we don't support fpsimd, bail out after we have
1856 * reset the fpsimd_cpu for this task and clear the
1857 * FPSTATE.
1858 */
1859 if (!system_supports_fpsimd())
1860 return;
1861 barrier();
1862 set_tsk_thread_flag(t, TIF_FOREIGN_FPSTATE);
1863
1864 barrier();
1865}
1866
1867/*
1868 * Save the FPSIMD state to memory and invalidate cpu view.
1869 * This function must be called with preemption disabled.
1870 */
1871void fpsimd_save_and_flush_cpu_state(void)
1872{
1873 unsigned long flags;
1874
1875 if (!system_supports_fpsimd())
1876 return;
1877 WARN_ON(preemptible());
1878 local_irq_save(flags);
1879 fpsimd_save_user_state();
1880 fpsimd_flush_cpu_state();
1881 local_irq_restore(flags);
1882}
1883
1884#ifdef CONFIG_KERNEL_MODE_NEON
1885
1886/*
1887 * Kernel-side NEON support functions
1888 */
1889
1890/*
1891 * kernel_neon_begin(): obtain the CPU FPSIMD registers for use by the calling
1892 * context
1893 *
1894 * Must not be called unless may_use_simd() returns true.
1895 * Task context in the FPSIMD registers is saved back to memory as necessary.
1896 *
1897 * A matching call to kernel_neon_end() must be made before returning from the
1898 * calling context.
1899 *
1900 * The caller may freely use the FPSIMD registers until kernel_neon_end() is
1901 * called.
1902 */
1903void kernel_neon_begin(void)
1904{
1905 if (WARN_ON(!system_supports_fpsimd()))
1906 return;
1907
1908 BUG_ON(!may_use_simd());
1909
1910 get_cpu_fpsimd_context();
1911
1912 /* Save unsaved fpsimd state, if any: */
1913 if (test_thread_flag(TIF_KERNEL_FPSTATE)) {
1914 BUG_ON(IS_ENABLED(CONFIG_PREEMPT_RT) || !in_serving_softirq());
1915 fpsimd_save_kernel_state(current);
1916 } else {
1917 fpsimd_save_user_state();
1918
1919 /*
1920 * Set the thread flag so that the kernel mode FPSIMD state
1921 * will be context switched along with the rest of the task
1922 * state.
1923 *
1924 * On non-PREEMPT_RT, softirqs may interrupt task level kernel
1925 * mode FPSIMD, but the task will not be preemptible so setting
1926 * TIF_KERNEL_FPSTATE for those would be both wrong (as it
1927 * would mark the task context FPSIMD state as requiring a
1928 * context switch) and unnecessary.
1929 *
1930 * On PREEMPT_RT, softirqs are serviced from a separate thread,
1931 * which is scheduled as usual, and this guarantees that these
1932 * softirqs are not interrupting use of the FPSIMD in kernel
1933 * mode in task context. So in this case, setting the flag here
1934 * is always appropriate.
1935 */
1936 if (IS_ENABLED(CONFIG_PREEMPT_RT) || !in_serving_softirq())
1937 set_thread_flag(TIF_KERNEL_FPSTATE);
1938 }
1939
1940 /* Invalidate any task state remaining in the fpsimd regs: */
1941 fpsimd_flush_cpu_state();
1942
1943 put_cpu_fpsimd_context();
1944}
1945EXPORT_SYMBOL_GPL(kernel_neon_begin);
1946
1947/*
1948 * kernel_neon_end(): give the CPU FPSIMD registers back to the current task
1949 *
1950 * Must be called from a context in which kernel_neon_begin() was previously
1951 * called, with no call to kernel_neon_end() in the meantime.
1952 *
1953 * The caller must not use the FPSIMD registers after this function is called,
1954 * unless kernel_neon_begin() is called again in the meantime.
1955 */
1956void kernel_neon_end(void)
1957{
1958 if (!system_supports_fpsimd())
1959 return;
1960
1961 /*
1962 * If we are returning from a nested use of kernel mode FPSIMD, restore
1963 * the task context kernel mode FPSIMD state. This can only happen when
1964 * running in softirq context on non-PREEMPT_RT.
1965 */
1966 if (!IS_ENABLED(CONFIG_PREEMPT_RT) && in_serving_softirq() &&
1967 test_thread_flag(TIF_KERNEL_FPSTATE))
1968 fpsimd_load_kernel_state(current);
1969 else
1970 clear_thread_flag(TIF_KERNEL_FPSTATE);
1971}
1972EXPORT_SYMBOL_GPL(kernel_neon_end);
1973
1974#ifdef CONFIG_EFI
1975
1976static DEFINE_PER_CPU(struct user_fpsimd_state, efi_fpsimd_state);
1977static DEFINE_PER_CPU(bool, efi_fpsimd_state_used);
1978static DEFINE_PER_CPU(bool, efi_sve_state_used);
1979static DEFINE_PER_CPU(bool, efi_sm_state);
1980
1981/*
1982 * EFI runtime services support functions
1983 *
1984 * The ABI for EFI runtime services allows EFI to use FPSIMD during the call.
1985 * This means that for EFI (and only for EFI), we have to assume that FPSIMD
1986 * is always used rather than being an optional accelerator.
1987 *
1988 * These functions provide the necessary support for ensuring FPSIMD
1989 * save/restore in the contexts from which EFI is used.
1990 *
1991 * Do not use them for any other purpose -- if tempted to do so, you are
1992 * either doing something wrong or you need to propose some refactoring.
1993 */
1994
1995/*
1996 * __efi_fpsimd_begin(): prepare FPSIMD for making an EFI runtime services call
1997 */
1998void __efi_fpsimd_begin(void)
1999{
2000 if (!system_supports_fpsimd())
2001 return;
2002
2003 WARN_ON(preemptible());
2004
2005 if (may_use_simd()) {
2006 kernel_neon_begin();
2007 } else {
2008 /*
2009 * If !efi_sve_state, SVE can't be in use yet and doesn't need
2010 * preserving:
2011 */
2012 if (system_supports_sve() && likely(efi_sve_state)) {
2013 char *sve_state = this_cpu_ptr(efi_sve_state);
2014 bool ffr = true;
2015 u64 svcr;
2016
2017 __this_cpu_write(efi_sve_state_used, true);
2018
2019 if (system_supports_sme()) {
2020 svcr = read_sysreg_s(SYS_SVCR);
2021
2022 __this_cpu_write(efi_sm_state,
2023 svcr & SVCR_SM_MASK);
2024
2025 /*
2026 * Unless we have FA64 FFR does not
2027 * exist in streaming mode.
2028 */
2029 if (!system_supports_fa64())
2030 ffr = !(svcr & SVCR_SM_MASK);
2031 }
2032
2033 sve_save_state(sve_state + sve_ffr_offset(sve_max_vl()),
2034 &this_cpu_ptr(&efi_fpsimd_state)->fpsr,
2035 ffr);
2036
2037 if (system_supports_sme())
2038 sysreg_clear_set_s(SYS_SVCR,
2039 SVCR_SM_MASK, 0);
2040
2041 } else {
2042 fpsimd_save_state(this_cpu_ptr(&efi_fpsimd_state));
2043 }
2044
2045 __this_cpu_write(efi_fpsimd_state_used, true);
2046 }
2047}
2048
2049/*
2050 * __efi_fpsimd_end(): clean up FPSIMD after an EFI runtime services call
2051 */
2052void __efi_fpsimd_end(void)
2053{
2054 if (!system_supports_fpsimd())
2055 return;
2056
2057 if (!__this_cpu_xchg(efi_fpsimd_state_used, false)) {
2058 kernel_neon_end();
2059 } else {
2060 if (system_supports_sve() &&
2061 likely(__this_cpu_read(efi_sve_state_used))) {
2062 char const *sve_state = this_cpu_ptr(efi_sve_state);
2063 bool ffr = true;
2064
2065 /*
2066 * Restore streaming mode; EFI calls are
2067 * normal function calls so should not return in
2068 * streaming mode.
2069 */
2070 if (system_supports_sme()) {
2071 if (__this_cpu_read(efi_sm_state)) {
2072 sysreg_clear_set_s(SYS_SVCR,
2073 0,
2074 SVCR_SM_MASK);
2075
2076 /*
2077 * Unless we have FA64 FFR does not
2078 * exist in streaming mode.
2079 */
2080 if (!system_supports_fa64())
2081 ffr = false;
2082 }
2083 }
2084
2085 sve_load_state(sve_state + sve_ffr_offset(sve_max_vl()),
2086 &this_cpu_ptr(&efi_fpsimd_state)->fpsr,
2087 ffr);
2088
2089 __this_cpu_write(efi_sve_state_used, false);
2090 } else {
2091 fpsimd_load_state(this_cpu_ptr(&efi_fpsimd_state));
2092 }
2093 }
2094}
2095
2096#endif /* CONFIG_EFI */
2097
2098#endif /* CONFIG_KERNEL_MODE_NEON */
2099
2100#ifdef CONFIG_CPU_PM
2101static int fpsimd_cpu_pm_notifier(struct notifier_block *self,
2102 unsigned long cmd, void *v)
2103{
2104 switch (cmd) {
2105 case CPU_PM_ENTER:
2106 fpsimd_save_and_flush_cpu_state();
2107 break;
2108 case CPU_PM_EXIT:
2109 break;
2110 case CPU_PM_ENTER_FAILED:
2111 default:
2112 return NOTIFY_DONE;
2113 }
2114 return NOTIFY_OK;
2115}
2116
2117static struct notifier_block fpsimd_cpu_pm_notifier_block = {
2118 .notifier_call = fpsimd_cpu_pm_notifier,
2119};
2120
2121static void __init fpsimd_pm_init(void)
2122{
2123 cpu_pm_register_notifier(&fpsimd_cpu_pm_notifier_block);
2124}
2125
2126#else
2127static inline void fpsimd_pm_init(void) { }
2128#endif /* CONFIG_CPU_PM */
2129
2130#ifdef CONFIG_HOTPLUG_CPU
2131static int fpsimd_cpu_dead(unsigned int cpu)
2132{
2133 per_cpu(fpsimd_last_state.st, cpu) = NULL;
2134 return 0;
2135}
2136
2137static inline void fpsimd_hotplug_init(void)
2138{
2139 cpuhp_setup_state_nocalls(CPUHP_ARM64_FPSIMD_DEAD, "arm64/fpsimd:dead",
2140 NULL, fpsimd_cpu_dead);
2141}
2142
2143#else
2144static inline void fpsimd_hotplug_init(void) { }
2145#endif
2146
2147void cpu_enable_fpsimd(const struct arm64_cpu_capabilities *__always_unused p)
2148{
2149 unsigned long enable = CPACR_EL1_FPEN_EL1EN | CPACR_EL1_FPEN_EL0EN;
2150 write_sysreg(read_sysreg(CPACR_EL1) | enable, CPACR_EL1);
2151 isb();
2152}
2153
2154/*
2155 * FP/SIMD support code initialisation.
2156 */
2157static int __init fpsimd_init(void)
2158{
2159 if (cpu_have_named_feature(FP)) {
2160 fpsimd_pm_init();
2161 fpsimd_hotplug_init();
2162 } else {
2163 pr_notice("Floating-point is not implemented\n");
2164 }
2165
2166 if (!cpu_have_named_feature(ASIMD))
2167 pr_notice("Advanced SIMD is not implemented\n");
2168
2169
2170 sve_sysctl_init();
2171 sme_sysctl_init();
2172
2173 return 0;
2174}
2175core_initcall(fpsimd_init);