1/*
  2 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
  3 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
  4 *
  5 * This program is free software; you can redistribute it and/or modify
  6 * it under the terms of the GNU General Public License, version 2, as
  7 * published by the Free Software Foundation.
  8 *
  9 * This program is distributed in the hope that it will be useful,
 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 12 * GNU General Public License for more details.
 13 *
 14 * You should have received a copy of the GNU General Public License
 15 * along with this program; if not, write to the Free Software
 16 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 17 */
 18
 19#include <linux/linkage.h>
 20#include <asm/assembler.h>
 21#include <asm/unified.h>
 22#include <asm/asm-offsets.h>
 23#include <asm/kvm_asm.h>
 24#include <asm/kvm_arm.h>
 25#include <asm/kvm_mmu.h>
 26
 27/********************************************************************
 28 * Hypervisor initialization
 29 *   - should be called with:
 30 *       r0 = top of Hyp stack (kernel VA)
 31 *       r1 = pointer to hyp vectors
 32 *       r2,r3 = Hypervisor pgd pointer
 33 *
 34 * The init scenario is:
 35 * - We jump in HYP with four parameters: boot HYP pgd, runtime HYP pgd,
 36 *   runtime stack, runtime vectors
 37 * - Enable the MMU with the boot pgd
 38 * - Jump to a target into the trampoline page (remember, this is the same
 39 *   physical page!)
 40 * - Now switch to the runtime pgd (same VA, and still the same physical
 41 *   page!)
 42 * - Invalidate TLBs
 43 * - Set stack and vectors
 44 * - Profit! (or eret, if you only care about the code).
 45 *
 46 * As we only have four registers available to pass parameters (and we
 47 * need six), we split the init in two phases:
 48 * - Phase 1: r0 = 0, r1 = 0, r2,r3 contain the boot PGD.
 49 *   Provides the basic HYP init, and enable the MMU.
 50 * - Phase 2: r0 = ToS, r1 = vectors, r2,r3 contain the runtime PGD.
 51 *   Switches to the runtime PGD, set stack and vectors.
 52 */
 53
 54	.text
 55	.pushsection    .hyp.idmap.text,"ax"
 56	.align 5
 57__kvm_hyp_init:
 58	.globl __kvm_hyp_init
 59
 60	@ Hyp-mode exception vector
 61	W(b)	.
 62	W(b)	.
 63	W(b)	.
 64	W(b)	.
 65	W(b)	.
 66	W(b)	__do_hyp_init
 67	W(b)	.
 68	W(b)	.
 69
 70__do_hyp_init:
 71	cmp	r0, #0			@ We have a SP?
 72	bne	phase2			@ Yes, second stage init
 73
 74	@ Set the HTTBR to point to the hypervisor PGD pointer passed
 75	mcrr	p15, 4, rr_lo_hi(r2, r3), c2
 76
 77	@ Set the HTCR and VTCR to the same shareability and cacheability
 78	@ settings as the non-secure TTBCR and with T0SZ == 0.
 79	mrc	p15, 4, r0, c2, c0, 2	@ HTCR
 80	ldr	r2, =HTCR_MASK
 81	bic	r0, r0, r2
 82	mrc	p15, 0, r1, c2, c0, 2	@ TTBCR
 83	and	r1, r1, #(HTCR_MASK & ~TTBCR_T0SZ)
 84	orr	r0, r0, r1
 85	mcr	p15, 4, r0, c2, c0, 2	@ HTCR
 86
 87	@ Use the same memory attributes for hyp. accesses as the kernel
 88	@ (copy MAIRx ro HMAIRx).
 89	mrc	p15, 0, r0, c10, c2, 0
 90	mcr	p15, 4, r0, c10, c2, 0
 91	mrc	p15, 0, r0, c10, c2, 1
 92	mcr	p15, 4, r0, c10, c2, 1
 93
 94	@ Invalidate the stale TLBs from Bootloader
 95	mcr	p15, 4, r0, c8, c7, 0	@ TLBIALLH
 96	dsb	ish
 97
 98	@ Set the HSCTLR to:
 99	@  - ARM/THUMB exceptions: Kernel config (Thumb-2 kernel)
100	@  - Endianness: Kernel config
101	@  - Fast Interrupt Features: Kernel config
102	@  - Write permission implies XN: disabled
103	@  - Instruction cache: enabled
104	@  - Data/Unified cache: enabled
105	@  - Memory alignment checks: enabled
106	@  - MMU: enabled (this code must be run from an identity mapping)
107	mrc	p15, 4, r0, c1, c0, 0	@ HSCR
108	ldr	r2, =HSCTLR_MASK
109	bic	r0, r0, r2
110	mrc	p15, 0, r1, c1, c0, 0	@ SCTLR
111	ldr	r2, =(HSCTLR_EE | HSCTLR_FI | HSCTLR_I | HSCTLR_C)
112	and	r1, r1, r2
113 ARM(	ldr	r2, =(HSCTLR_M | HSCTLR_A)			)
114 THUMB(	ldr	r2, =(HSCTLR_M | HSCTLR_A | HSCTLR_TE)		)
115	orr	r1, r1, r2
116	orr	r0, r0, r1
117	isb
118	mcr	p15, 4, r0, c1, c0, 0	@ HSCR
119
120	@ End of init phase-1
121	eret
122
123phase2:
124	@ Set stack pointer
125	mov	sp, r0
126
127	@ Set HVBAR to point to the HYP vectors
128	mcr	p15, 4, r1, c12, c0, 0	@ HVBAR
129
130	@ Jump to the trampoline page
131	ldr	r0, =TRAMPOLINE_VA
132	adr	r1, target
133	bfi	r0, r1, #0, #PAGE_SHIFT
134	ret	r0
135
136target:	@ We're now in the trampoline code, switch page tables
137	mcrr	p15, 4, rr_lo_hi(r2, r3), c2
138	isb
139
140	@ Invalidate the old TLBs
141	mcr	p15, 4, r0, c8, c7, 0	@ TLBIALLH
142	dsb	ish
143
144	eret
145
146	.ltorg
147
148	.globl __kvm_hyp_init_end
149__kvm_hyp_init_end:
150
151	.popsection