1/*
   2 * hcd_queue.c - DesignWare HS OTG Controller host queuing routines
   3 *
   4 * Copyright (C) 2004-2013 Synopsys, Inc.
   5 *
   6 * Redistribution and use in source and binary forms, with or without
   7 * modification, are permitted provided that the following conditions
   8 * are met:
   9 * 1. Redistributions of source code must retain the above copyright
  10 *    notice, this list of conditions, and the following disclaimer,
  11 *    without modification.
  12 * 2. Redistributions in binary form must reproduce the above copyright
  13 *    notice, this list of conditions and the following disclaimer in the
  14 *    documentation and/or other materials provided with the distribution.
  15 * 3. The names of the above-listed copyright holders may not be used
  16 *    to endorse or promote products derived from this software without
  17 *    specific prior written permission.
  18 *
  19 * ALTERNATIVELY, this software may be distributed under the terms of the
  20 * GNU General Public License ("GPL") as published by the Free Software
  21 * Foundation; either version 2 of the License, or (at your option) any
  22 * later version.
  23 *
  24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35 */
  36
  37/*
  38 * This file contains the functions to manage Queue Heads and Queue
  39 * Transfer Descriptors for Host mode
  40 */
  41#include <linux/gcd.h>
  42#include <linux/kernel.h>
  43#include <linux/module.h>
  44#include <linux/spinlock.h>
  45#include <linux/interrupt.h>
  46#include <linux/dma-mapping.h>
  47#include <linux/io.h>
 
  48#include <linux/slab.h>
  49#include <linux/usb.h>
  50
  51#include <linux/usb/hcd.h>
  52#include <linux/usb/ch11.h>
  53
  54#include "core.h"
  55#include "hcd.h"
  56
  57/* Wait this long before releasing periodic reservation */
  58#define DWC2_UNRESERVE_DELAY (msecs_to_jiffies(5))
  59
 
 
 
  60/**
  61 * dwc2_periodic_channel_available() - Checks that a channel is available for a
  62 * periodic transfer
  63 *
  64 * @hsotg: The HCD state structure for the DWC OTG controller
  65 *
  66 * Return: 0 if successful, negative error code otherwise
  67 */
  68static int dwc2_periodic_channel_available(struct dwc2_hsotg *hsotg)
  69{
  70	/*
  71	 * Currently assuming that there is a dedicated host channel for
  72	 * each periodic transaction plus at least one host channel for
  73	 * non-periodic transactions
  74	 */
  75	int status;
  76	int num_channels;
  77
  78	num_channels = hsotg->core_params->host_channels;
  79	if (hsotg->periodic_channels + hsotg->non_periodic_channels <
  80								num_channels
  81	    && hsotg->periodic_channels < num_channels - 1) {
  82		status = 0;
  83	} else {
  84		dev_dbg(hsotg->dev,
  85			"%s: Total channels: %d, Periodic: %d, "
  86			"Non-periodic: %d\n", __func__, num_channels,
  87			hsotg->periodic_channels, hsotg->non_periodic_channels);
  88		status = -ENOSPC;
  89	}
  90
  91	return status;
  92}
  93
  94/**
  95 * dwc2_check_periodic_bandwidth() - Checks that there is sufficient bandwidth
  96 * for the specified QH in the periodic schedule
  97 *
  98 * @hsotg: The HCD state structure for the DWC OTG controller
  99 * @qh:    QH containing periodic bandwidth required
 100 *
 101 * Return: 0 if successful, negative error code otherwise
 102 *
 103 * For simplicity, this calculation assumes that all the transfers in the
 104 * periodic schedule may occur in the same (micro)frame
 105 */
 106static int dwc2_check_periodic_bandwidth(struct dwc2_hsotg *hsotg,
 107					 struct dwc2_qh *qh)
 108{
 109	int status;
 110	s16 max_claimed_usecs;
 111
 112	status = 0;
 113
 114	if (qh->dev_speed == USB_SPEED_HIGH || qh->do_split) {
 115		/*
 116		 * High speed mode
 117		 * Max periodic usecs is 80% x 125 usec = 100 usec
 118		 */
 119		max_claimed_usecs = 100 - qh->host_us;
 120	} else {
 121		/*
 122		 * Full speed mode
 123		 * Max periodic usecs is 90% x 1000 usec = 900 usec
 124		 */
 125		max_claimed_usecs = 900 - qh->host_us;
 126	}
 127
 128	if (hsotg->periodic_usecs > max_claimed_usecs) {
 129		dev_err(hsotg->dev,
 130			"%s: already claimed usecs %d, required usecs %d\n",
 131			__func__, hsotg->periodic_usecs, qh->host_us);
 132		status = -ENOSPC;
 133	}
 134
 135	return status;
 136}
 137
 138/**
 139 * pmap_schedule() - Schedule time in a periodic bitmap (pmap).
 140 *
 141 * @map:             The bitmap representing the schedule; will be updated
 142 *                   upon success.
 143 * @bits_per_period: The schedule represents several periods.  This is how many
 144 *                   bits are in each period.  It's assumed that the beginning
 145 *                   of the schedule will repeat after its end.
 146 * @periods_in_map:  The number of periods in the schedule.
 147 * @num_bits:        The number of bits we need per period we want to reserve
 148 *                   in this function call.
 149 * @interval:        How often we need to be scheduled for the reservation this
 150 *                   time.  1 means every period.  2 means every other period.
 151 *                   ...you get the picture?
 152 * @start:           The bit number to start at.  Normally 0.  Must be within
 153 *                   the interval or we return failure right away.
 154 * @only_one_period: Normally we'll allow picking a start anywhere within the
 155 *                   first interval, since we can still make all repetition
 156 *                   requirements by doing that.  However, if you pass true
 157 *                   here then we'll return failure if we can't fit within
 158 *                   the period that "start" is in.
 159 *
 160 * The idea here is that we want to schedule time for repeating events that all
 161 * want the same resource.  The resource is divided into fixed-sized periods
 162 * and the events want to repeat every "interval" periods.  The schedule
 163 * granularity is one bit.
 164 *
 165 * To keep things "simple", we'll represent our schedule with a bitmap that
 166 * contains a fixed number of periods.  This gets rid of a lot of complexity
 167 * but does mean that we need to handle things specially (and non-ideally) if
 168 * the number of the periods in the schedule doesn't match well with the
 169 * intervals that we're trying to schedule.
 170 *
 171 * Here's an explanation of the scheme we'll implement, assuming 8 periods.
 172 * - If interval is 1, we need to take up space in each of the 8
 173 *   periods we're scheduling.  Easy.
 174 * - If interval is 2, we need to take up space in half of the
 175 *   periods.  Again, easy.
 176 * - If interval is 3, we actually need to fall back to interval 1.
 177 *   Why?  Because we might need time in any period.  AKA for the
 178 *   first 8 periods, we'll be in slot 0, 3, 6.  Then we'll be
 179 *   in slot 1, 4, 7.  Then we'll be in 2, 5.  Then we'll be back to
 180 *   0, 3, and 6.  Since we could be in any frame we need to reserve
 181 *   for all of them.  Sucks, but that's what you gotta do.  Note that
 182 *   if we were instead scheduling 8 * 3 = 24 we'd do much better, but
 183 *   then we need more memory and time to do scheduling.
 184 * - If interval is 4, easy.
 185 * - If interval is 5, we again need interval 1.  The schedule will be
 186 *   0, 5, 2, 7, 4, 1, 6, 3, 0
 187 * - If interval is 6, we need interval 2.  0, 6, 4, 2.
 188 * - If interval is 7, we need interval 1.
 189 * - If interval is 8, we need interval 8.
 190 *
 191 * If you do the math, you'll see that we need to pretend that interval is
 192 * equal to the greatest_common_divisor(interval, periods_in_map).
 193 *
 194 * Note that at the moment this function tends to front-pack the schedule.
 195 * In some cases that's really non-ideal (it's hard to schedule things that
 196 * need to repeat every period).  In other cases it's perfect (you can easily
 197 * schedule bigger, less often repeating things).
 198 *
 199 * Here's the algorithm in action (8 periods, 5 bits per period):
 200 *  |**   |     |**   |     |**   |     |**   |     |   OK 2 bits, intv 2 at 0
 201 *  |*****|  ***|*****|  ***|*****|  ***|*****|  ***|   OK 3 bits, intv 3 at 2
 202 *  |*****|* ***|*****|  ***|*****|* ***|*****|  ***|   OK 1 bits, intv 4 at 5
 203 *  |**   |*    |**   |     |**   |*    |**   |     | Remv 3 bits, intv 3 at 2
 204 *  |***  |*    |***  |     |***  |*    |***  |     |   OK 1 bits, intv 6 at 2
 205 *  |**** |*  * |**** |   * |**** |*  * |**** |   * |   OK 1 bits, intv 1 at 3
 206 *  |**** |**** |**** | *** |**** |**** |**** | *** |   OK 2 bits, intv 2 at 6
 207 *  |*****|*****|*****| ****|*****|*****|*****| ****|   OK 1 bits, intv 1 at 4
 208 *  |*****|*****|*****| ****|*****|*****|*****| ****| FAIL 1 bits, intv 1
 209 *  |  ***|*****|  ***| ****|  ***|*****|  ***| ****| Remv 2 bits, intv 2 at 0
 210 *  |  ***| ****|  ***| ****|  ***| ****|  ***| ****| Remv 1 bits, intv 4 at 5
 211 *  |   **| ****|   **| ****|   **| ****|   **| ****| Remv 1 bits, intv 6 at 2
 212 *  |    *| ** *|    *| ** *|    *| ** *|    *| ** *| Remv 1 bits, intv 1 at 3
 213 *  |    *|    *|    *|    *|    *|    *|    *|    *| Remv 2 bits, intv 2 at 6
 214 *  |     |     |     |     |     |     |     |     | Remv 1 bits, intv 1 at 4
 215 *  |**   |     |**   |     |**   |     |**   |     |   OK 2 bits, intv 2 at 0
 216 *  |***  |     |**   |     |***  |     |**   |     |   OK 1 bits, intv 4 at 2
 217 *  |*****|     |** **|     |*****|     |** **|     |   OK 2 bits, intv 2 at 3
 218 *  |*****|*    |** **|     |*****|*    |** **|     |   OK 1 bits, intv 4 at 5
 219 *  |*****|***  |** **| **  |*****|***  |** **| **  |   OK 2 bits, intv 2 at 6
 220 *  |*****|*****|** **| ****|*****|*****|** **| ****|   OK 2 bits, intv 2 at 8
 221 *  |*****|*****|*****| ****|*****|*****|*****| ****|   OK 1 bits, intv 4 at 12
 222 *
 223 * This function is pretty generic and could be easily abstracted if anything
 224 * needed similar scheduling.
 225 *
 226 * Returns either -ENOSPC or a >= 0 start bit which should be passed to the
 227 * unschedule routine.  The map bitmap will be updated on a non-error result.
 228 */
 229static int pmap_schedule(unsigned long *map, int bits_per_period,
 230			 int periods_in_map, int num_bits,
 231			 int interval, int start, bool only_one_period)
 232{
 233	int interval_bits;
 234	int to_reserve;
 235	int first_end;
 236	int i;
 237
 238	if (num_bits > bits_per_period)
 239		return -ENOSPC;
 240
 241	/* Adjust interval as per description */
 242	interval = gcd(interval, periods_in_map);
 243
 244	interval_bits = bits_per_period * interval;
 245	to_reserve = periods_in_map / interval;
 246
 247	/* If start has gotten us past interval then we can't schedule */
 248	if (start >= interval_bits)
 249		return -ENOSPC;
 250
 251	if (only_one_period)
 252		/* Must fit within same period as start; end at begin of next */
 253		first_end = (start / bits_per_period + 1) * bits_per_period;
 254	else
 255		/* Can fit anywhere in the first interval */
 256		first_end = interval_bits;
 257
 258	/*
 259	 * We'll try to pick the first repetition, then see if that time
 260	 * is free for each of the subsequent repetitions.  If it's not
 261	 * we'll adjust the start time for the next search of the first
 262	 * repetition.
 263	 */
 264	while (start + num_bits <= first_end) {
 265		int end;
 266
 267		/* Need to stay within this period */
 268		end = (start / bits_per_period + 1) * bits_per_period;
 269
 270		/* Look for num_bits us in this microframe starting at start */
 271		start = bitmap_find_next_zero_area(map, end, start, num_bits,
 272						   0);
 273
 274		/*
 275		 * We should get start >= end if we fail.  We might be
 276		 * able to check the next microframe depending on the
 277		 * interval, so continue on (start already updated).
 278		 */
 279		if (start >= end) {
 280			start = end;
 281			continue;
 282		}
 283
 284		/* At this point we have a valid point for first one */
 285		for (i = 1; i < to_reserve; i++) {
 286			int ith_start = start + interval_bits * i;
 287			int ith_end = end + interval_bits * i;
 288			int ret;
 289
 290			/* Use this as a dumb "check if bits are 0" */
 291			ret = bitmap_find_next_zero_area(
 292				map, ith_start + num_bits, ith_start, num_bits,
 293				0);
 294
 295			/* We got the right place, continue checking */
 296			if (ret == ith_start)
 297				continue;
 298
 299			/* Move start up for next time and exit for loop */
 300			ith_start = bitmap_find_next_zero_area(
 301				map, ith_end, ith_start, num_bits, 0);
 302			if (ith_start >= ith_end)
 303				/* Need a while new period next time */
 304				start = end;
 305			else
 306				start = ith_start - interval_bits * i;
 307			break;
 308		}
 309
 310		/* If didn't exit the for loop with a break, we have success */
 311		if (i == to_reserve)
 312			break;
 313	}
 314
 315	if (start + num_bits > first_end)
 316		return -ENOSPC;
 317
 318	for (i = 0; i < to_reserve; i++) {
 319		int ith_start = start + interval_bits * i;
 320
 321		bitmap_set(map, ith_start, num_bits);
 322	}
 323
 324	return start;
 325}
 326
 327/**
 328 * pmap_unschedule() - Undo work done by pmap_schedule()
 329 *
 330 * @map:             See pmap_schedule().
 331 * @bits_per_period: See pmap_schedule().
 332 * @periods_in_map:  See pmap_schedule().
 333 * @num_bits:        The number of bits that was passed to schedule.
 334 * @interval:        The interval that was passed to schedule.
 335 * @start:           The return value from pmap_schedule().
 336 */
 337static void pmap_unschedule(unsigned long *map, int bits_per_period,
 338			    int periods_in_map, int num_bits,
 339			    int interval, int start)
 340{
 341	int interval_bits;
 342	int to_release;
 343	int i;
 344
 345	/* Adjust interval as per description in pmap_schedule() */
 346	interval = gcd(interval, periods_in_map);
 347
 348	interval_bits = bits_per_period * interval;
 349	to_release = periods_in_map / interval;
 350
 351	for (i = 0; i < to_release; i++) {
 352		int ith_start = start + interval_bits * i;
 353
 354		bitmap_clear(map, ith_start, num_bits);
 355	}
 356}
 357
 358/*
 359 * cat_printf() - A printf() + strcat() helper
 
 
 
 360 *
 361 * This is useful for concatenating a bunch of strings where each string is
 362 * constructed using printf.
 
 
 363 *
 364 * @buf:   The destination buffer; will be updated to point after the printed
 365 *         data.
 366 * @size:  The number of bytes in the buffer (includes space for '\0').
 367 * @fmt:   The format for printf.
 368 * @...:   The args for printf.
 369 */
 370static void cat_printf(char **buf, size_t *size, const char *fmt, ...)
 
 371{
 372	va_list args;
 373	int i;
 374
 375	if (*size == 0)
 376		return;
 
 377
 378	va_start(args, fmt);
 379	i = vsnprintf(*buf, *size, fmt, args);
 380	va_end(args);
 381
 382	if (i >= *size) {
 383		(*buf)[*size - 1] = '\0';
 384		*buf += *size;
 385		*size = 0;
 386	} else {
 387		*buf += i;
 388		*size -= i;
 389	}
 390}
 391
 
 392/*
 393 * pmap_print() - Print the given periodic map
 394 *
 395 * Will attempt to print out the periodic schedule.
 396 *
 397 * @map:             See pmap_schedule().
 398 * @bits_per_period: See pmap_schedule().
 399 * @periods_in_map:  See pmap_schedule().
 400 * @period_name:     The name of 1 period, like "uFrame"
 401 * @units:           The name of the units, like "us".
 402 * @print_fn:        The function to call for printing.
 403 * @print_data:      Opaque data to pass to the print function.
 404 */
 405static void pmap_print(unsigned long *map, int bits_per_period,
 406		       int periods_in_map, const char *period_name,
 407		       const char *units,
 408		       void (*print_fn)(const char *str, void *data),
 409		       void *print_data)
 410{
 411	int period;
 412
 413	for (period = 0; period < periods_in_map; period++) {
 414		char tmp[64];
 415		char *buf = tmp;
 416		size_t buf_size = sizeof(tmp);
 417		int period_start = period * bits_per_period;
 418		int period_end = period_start + bits_per_period;
 419		int start = 0;
 420		int count = 0;
 421		bool printed = false;
 422		int i;
 423
 424		for (i = period_start; i < period_end + 1; i++) {
 425			/* Handle case when ith bit is set */
 426			if (i < period_end &&
 427			    bitmap_find_next_zero_area(map, i + 1,
 428						       i, 1, 0) != i) {
 429				if (count == 0)
 430					start = i - period_start;
 431				count++;
 432				continue;
 433			}
 434
 435			/* ith bit isn't set; don't care if count == 0 */
 436			if (count == 0)
 437				continue;
 438
 439			if (!printed)
 440				cat_printf(&buf, &buf_size, "%s %d: ",
 441					   period_name, period);
 442			else
 443				cat_printf(&buf, &buf_size, ", ");
 444			printed = true;
 445
 446			cat_printf(&buf, &buf_size, "%d %s -%3d %s", start,
 447				   units, start + count - 1, units);
 448			count = 0;
 449		}
 450
 451		if (printed)
 452			print_fn(tmp, print_data);
 453	}
 454}
 455
 456/**
 457 * dwc2_get_ls_map() - Get the map used for the given qh
 458 *
 459 * @hsotg: The HCD state structure for the DWC OTG controller.
 460 * @qh:    QH for the periodic transfer.
 461 *
 462 * We'll always get the periodic map out of our TT.  Note that even if we're
 463 * running the host straight in low speed / full speed mode it appears as if
 464 * a TT is allocated for us, so we'll use it.  If that ever changes we can
 465 * add logic here to get a map out of "hsotg" if !qh->do_split.
 466 *
 467 * Returns: the map or NULL if a map couldn't be found.
 468 */
 469static unsigned long *dwc2_get_ls_map(struct dwc2_hsotg *hsotg,
 470				      struct dwc2_qh *qh)
 471{
 472	unsigned long *map;
 473
 474	/* Don't expect to be missing a TT and be doing low speed scheduling */
 475	if (WARN_ON(!qh->dwc_tt))
 476		return NULL;
 477
 478	/* Get the map and adjust if this is a multi_tt hub */
 479	map = qh->dwc_tt->periodic_bitmaps;
 480	if (qh->dwc_tt->usb_tt->multi)
 481		map += DWC2_ELEMENTS_PER_LS_BITMAP * qh->ttport;
 482
 483	return map;
 484}
 485
 486struct dwc2_qh_print_data {
 487	struct dwc2_hsotg *hsotg;
 488	struct dwc2_qh *qh;
 489};
 490
 491/**
 492 * dwc2_qh_print() - Helper function for dwc2_qh_schedule_print()
 493 *
 494 * @str:  The string to print
 495 * @data: A pointer to a struct dwc2_qh_print_data
 496 */
 497static void dwc2_qh_print(const char *str, void *data)
 498{
 499	struct dwc2_qh_print_data *print_data = data;
 500
 501	dwc2_sch_dbg(print_data->hsotg, "QH=%p ...%s\n", print_data->qh, str);
 502}
 503
 504/**
 505 * dwc2_qh_schedule_print() - Print the periodic schedule
 506 *
 507 * @hsotg: The HCD state structure for the DWC OTG controller.
 508 * @qh:    QH to print.
 509 */
 510static void dwc2_qh_schedule_print(struct dwc2_hsotg *hsotg,
 511				   struct dwc2_qh *qh)
 512{
 513	struct dwc2_qh_print_data print_data = { hsotg, qh };
 514	int i;
 515
 516	/*
 517	 * The printing functions are quite slow and inefficient.
 518	 * If we don't have tracing turned on, don't run unless the special
 519	 * define is turned on.
 520	 */
 521#ifndef DWC2_PRINT_SCHEDULE
 522	return;
 523#endif
 524
 525	if (qh->schedule_low_speed) {
 526		unsigned long *map = dwc2_get_ls_map(hsotg, qh);
 527
 528		dwc2_sch_dbg(hsotg, "QH=%p LS/FS trans: %d=>%d us @ %d us",
 529			     qh, qh->device_us,
 530			     DWC2_ROUND_US_TO_SLICE(qh->device_us),
 531			     DWC2_US_PER_SLICE * qh->ls_start_schedule_slice);
 532
 533		if (map) {
 534			dwc2_sch_dbg(hsotg,
 535				     "QH=%p Whole low/full speed map %p now:\n",
 536				     qh, map);
 537			pmap_print(map, DWC2_LS_PERIODIC_SLICES_PER_FRAME,
 538				   DWC2_LS_SCHEDULE_FRAMES, "Frame ", "slices",
 539				   dwc2_qh_print, &print_data);
 540		}
 541	}
 542
 543	for (i = 0; i < qh->num_hs_transfers; i++) {
 544		struct dwc2_hs_transfer_time *trans_time = qh->hs_transfers + i;
 545		int uframe = trans_time->start_schedule_us /
 546			     DWC2_HS_PERIODIC_US_PER_UFRAME;
 547		int rel_us = trans_time->start_schedule_us %
 548			     DWC2_HS_PERIODIC_US_PER_UFRAME;
 549
 550		dwc2_sch_dbg(hsotg,
 551			     "QH=%p HS trans #%d: %d us @ uFrame %d + %d us\n",
 552			     qh, i, trans_time->duration_us, uframe, rel_us);
 553	}
 554	if (qh->num_hs_transfers) {
 555		dwc2_sch_dbg(hsotg, "QH=%p Whole high speed map now:\n", qh);
 556		pmap_print(hsotg->hs_periodic_bitmap,
 557			   DWC2_HS_PERIODIC_US_PER_UFRAME,
 558			   DWC2_HS_SCHEDULE_UFRAMES, "uFrame", "us",
 559			   dwc2_qh_print, &print_data);
 560	}
 561
 562}
 
 
 
 
 563
 564/**
 565 * dwc2_ls_pmap_schedule() - Schedule a low speed QH
 566 *
 567 * @hsotg:        The HCD state structure for the DWC OTG controller.
 568 * @qh:           QH for the periodic transfer.
 569 * @search_slice: We'll start trying to schedule at the passed slice.
 570 *                Remember that slices are the units of the low speed
 571 *                schedule (think 25us or so).
 572 *
 573 * Wraps pmap_schedule() with the right parameters for low speed scheduling.
 574 *
 575 * Normally we schedule low speed devices on the map associated with the TT.
 576 *
 577 * Returns: 0 for success or an error code.
 578 */
 579static int dwc2_ls_pmap_schedule(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
 580				 int search_slice)
 581{
 582	int slices = DIV_ROUND_UP(qh->device_us, DWC2_US_PER_SLICE);
 583	unsigned long *map = dwc2_get_ls_map(hsotg, qh);
 584	int slice;
 585
 586	if (map == NULL)
 587		return -EINVAL;
 588
 589	/*
 590	 * Schedule on the proper low speed map with our low speed scheduling
 591	 * parameters.  Note that we use the "device_interval" here since
 592	 * we want the low speed interval and the only way we'd be in this
 593	 * function is if the device is low speed.
 594	 *
 595	 * If we happen to be doing low speed and high speed scheduling for the
 596	 * same transaction (AKA we have a split) we always do low speed first.
 597	 * That means we can always pass "false" for only_one_period (that
 598	 * parameters is only useful when we're trying to get one schedule to
 599	 * match what we already planned in the other schedule).
 600	 */
 601	slice = pmap_schedule(map, DWC2_LS_PERIODIC_SLICES_PER_FRAME,
 602			      DWC2_LS_SCHEDULE_FRAMES, slices,
 603			      qh->device_interval, search_slice, false);
 604
 605	if (slice < 0)
 606		return slice;
 607
 608	qh->ls_start_schedule_slice = slice;
 609	return 0;
 610}
 611
 612/**
 613 * dwc2_ls_pmap_unschedule() - Undo work done by dwc2_ls_pmap_schedule()
 614 *
 615 * @hsotg:       The HCD state structure for the DWC OTG controller.
 616 * @qh:          QH for the periodic transfer.
 617 */
 618static void dwc2_ls_pmap_unschedule(struct dwc2_hsotg *hsotg,
 619				    struct dwc2_qh *qh)
 620{
 621	int slices = DIV_ROUND_UP(qh->device_us, DWC2_US_PER_SLICE);
 622	unsigned long *map = dwc2_get_ls_map(hsotg, qh);
 623
 624	/* Schedule should have failed, so no worries about no error code */
 625	if (map == NULL)
 626		return;
 627
 628	pmap_unschedule(map, DWC2_LS_PERIODIC_SLICES_PER_FRAME,
 629			DWC2_LS_SCHEDULE_FRAMES, slices, qh->device_interval,
 630			qh->ls_start_schedule_slice);
 631}
 632
 633/**
 634 * dwc2_hs_pmap_schedule - Schedule in the main high speed schedule
 635 *
 636 * This will schedule something on the main dwc2 schedule.
 637 *
 638 * We'll start looking in qh->hs_transfers[index].start_schedule_us.  We'll
 639 * update this with the result upon success.  We also use the duration from
 640 * the same structure.
 641 *
 642 * @hsotg:           The HCD state structure for the DWC OTG controller.
 643 * @qh:              QH for the periodic transfer.
 644 * @only_one_period: If true we will limit ourselves to just looking at
 645 *                   one period (aka one 100us chunk).  This is used if we have
 646 *                   already scheduled something on the low speed schedule and
 647 *                   need to find something that matches on the high speed one.
 648 * @index:           The index into qh->hs_transfers that we're working with.
 649 *
 650 * Returns: 0 for success or an error code.  Upon success the
 651 *          dwc2_hs_transfer_time specified by "index" will be updated.
 652 */
 653static int dwc2_hs_pmap_schedule(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
 654				 bool only_one_period, int index)
 655{
 656	struct dwc2_hs_transfer_time *trans_time = qh->hs_transfers + index;
 657	int us;
 658
 659	us = pmap_schedule(hsotg->hs_periodic_bitmap,
 660			   DWC2_HS_PERIODIC_US_PER_UFRAME,
 661			   DWC2_HS_SCHEDULE_UFRAMES, trans_time->duration_us,
 662			   qh->host_interval, trans_time->start_schedule_us,
 663			   only_one_period);
 664
 665	if (us < 0)
 666		return us;
 667
 668	trans_time->start_schedule_us = us;
 669	return 0;
 670}
 671
 672/**
 673 * dwc2_ls_pmap_unschedule() - Undo work done by dwc2_hs_pmap_schedule()
 674 *
 675 * @hsotg:       The HCD state structure for the DWC OTG controller.
 676 * @qh:          QH for the periodic transfer.
 
 677 */
 678static void dwc2_hs_pmap_unschedule(struct dwc2_hsotg *hsotg,
 679				    struct dwc2_qh *qh, int index)
 680{
 681	struct dwc2_hs_transfer_time *trans_time = qh->hs_transfers + index;
 682
 683	pmap_unschedule(hsotg->hs_periodic_bitmap,
 684			DWC2_HS_PERIODIC_US_PER_UFRAME,
 685			DWC2_HS_SCHEDULE_UFRAMES, trans_time->duration_us,
 686			qh->host_interval, trans_time->start_schedule_us);
 687}
 688
 689/**
 690 * dwc2_uframe_schedule_split - Schedule a QH for a periodic split xfer.
 691 *
 692 * This is the most complicated thing in USB.  We have to find matching time
 693 * in both the global high speed schedule for the port and the low speed
 694 * schedule for the TT associated with the given device.
 695 *
 696 * Being here means that the host must be running in high speed mode and the
 697 * device is in low or full speed mode (and behind a hub).
 698 *
 699 * @hsotg:       The HCD state structure for the DWC OTG controller.
 700 * @qh:          QH for the periodic transfer.
 701 */
 702static int dwc2_uframe_schedule_split(struct dwc2_hsotg *hsotg,
 703				      struct dwc2_qh *qh)
 704{
 705	int bytecount = dwc2_hb_mult(qh->maxp) * dwc2_max_packet(qh->maxp);
 706	int ls_search_slice;
 707	int err = 0;
 708	int host_interval_in_sched;
 709
 710	/*
 711	 * The interval (how often to repeat) in the actual host schedule.
 712	 * See pmap_schedule() for gcd() explanation.
 713	 */
 714	host_interval_in_sched = gcd(qh->host_interval,
 715				     DWC2_HS_SCHEDULE_UFRAMES);
 716
 717	/*
 718	 * We always try to find space in the low speed schedule first, then
 719	 * try to find high speed time that matches.  If we don't, we'll bump
 720	 * up the place we start searching in the low speed schedule and try
 721	 * again.  To start we'll look right at the beginning of the low speed
 722	 * schedule.
 723	 *
 724	 * Note that this will tend to front-load the high speed schedule.
 725	 * We may eventually want to try to avoid this by either considering
 726	 * both schedules together or doing some sort of round robin.
 727	 */
 728	ls_search_slice = 0;
 729
 730	while (ls_search_slice < DWC2_LS_SCHEDULE_SLICES) {
 731		int start_s_uframe;
 732		int ssplit_s_uframe;
 733		int second_s_uframe;
 734		int rel_uframe;
 735		int first_count;
 736		int middle_count;
 737		int end_count;
 738		int first_data_bytes;
 739		int other_data_bytes;
 740		int i;
 741
 742		if (qh->schedule_low_speed) {
 743			err = dwc2_ls_pmap_schedule(hsotg, qh, ls_search_slice);
 744
 745			/*
 746			 * If we got an error here there's no other magic we
 747			 * can do, so bail.  All the looping above is only
 748			 * helpful to redo things if we got a low speed slot
 749			 * and then couldn't find a matching high speed slot.
 750			 */
 751			if (err)
 752				return err;
 753		} else {
 754			/* Must be missing the tt structure?  Why? */
 755			WARN_ON_ONCE(1);
 756		}
 757
 758		/*
 759		 * This will give us a number 0 - 7 if
 760		 * DWC2_LS_SCHEDULE_FRAMES == 1, or 0 - 15 if == 2, or ...
 761		 */
 762		start_s_uframe = qh->ls_start_schedule_slice /
 763				 DWC2_SLICES_PER_UFRAME;
 764
 765		/* Get a number that's always 0 - 7 */
 766		rel_uframe = (start_s_uframe % 8);
 767
 768		/*
 769		 * If we were going to start in uframe 7 then we would need to
 770		 * issue a start split in uframe 6, which spec says is not OK.
 771		 * Move on to the next full frame (assuming there is one).
 772		 *
 773		 * See 11.18.4 Host Split Transaction Scheduling Requirements
 774		 * bullet 1.
 775		 */
 776		if (rel_uframe == 7) {
 777			if (qh->schedule_low_speed)
 778				dwc2_ls_pmap_unschedule(hsotg, qh);
 779			ls_search_slice =
 780				(qh->ls_start_schedule_slice /
 781				 DWC2_LS_PERIODIC_SLICES_PER_FRAME + 1) *
 782				DWC2_LS_PERIODIC_SLICES_PER_FRAME;
 783			continue;
 784		}
 785
 786		/*
 787		 * For ISOC in:
 788		 * - start split            (frame -1)
 789		 * - complete split w/ data (frame +1)
 790		 * - complete split w/ data (frame +2)
 791		 * - ...
 792		 * - complete split w/ data (frame +num_data_packets)
 793		 * - complete split w/ data (frame +num_data_packets+1)
 794		 * - complete split w/ data (frame +num_data_packets+2, max 8)
 795		 *   ...though if frame was "0" then max is 7...
 796		 *
 797		 * For ISOC out we might need to do:
 798		 * - start split w/ data    (frame -1)
 799		 * - start split w/ data    (frame +0)
 800		 * - ...
 801		 * - start split w/ data    (frame +num_data_packets-2)
 802		 *
 803		 * For INTERRUPT in we might need to do:
 804		 * - start split            (frame -1)
 805		 * - complete split w/ data (frame +1)
 806		 * - complete split w/ data (frame +2)
 807		 * - complete split w/ data (frame +3, max 8)
 808		 *
 809		 * For INTERRUPT out we might need to do:
 810		 * - start split w/ data    (frame -1)
 811		 * - complete split         (frame +1)
 812		 * - complete split         (frame +2)
 813		 * - complete split         (frame +3, max 8)
 814		 *
 815		 * Start adjusting!
 816		 */
 817		ssplit_s_uframe = (start_s_uframe +
 818				   host_interval_in_sched - 1) %
 819				  host_interval_in_sched;
 820		if (qh->ep_type == USB_ENDPOINT_XFER_ISOC && !qh->ep_is_in)
 821			second_s_uframe = start_s_uframe;
 822		else
 823			second_s_uframe = start_s_uframe + 1;
 824
 825		/* First data transfer might not be all 188 bytes. */
 826		first_data_bytes = 188 -
 827			DIV_ROUND_UP(188 * (qh->ls_start_schedule_slice %
 828					    DWC2_SLICES_PER_UFRAME),
 829				     DWC2_SLICES_PER_UFRAME);
 830		if (first_data_bytes > bytecount)
 831			first_data_bytes = bytecount;
 832		other_data_bytes = bytecount - first_data_bytes;
 833
 834		/*
 835		 * For now, skip OUT xfers where first xfer is partial
 836		 *
 837		 * Main dwc2 code assumes:
 838		 * - INT transfers never get split in two.
 839		 * - ISOC transfers can always transfer 188 bytes the first
 840		 *   time.
 841		 *
 842		 * Until that code is fixed, try again if the first transfer
 843		 * couldn't transfer everything.
 844		 *
 845		 * This code can be removed if/when the rest of dwc2 handles
 846		 * the above cases.  Until it's fixed we just won't be able
 847		 * to schedule quite as tightly.
 848		 */
 849		if (!qh->ep_is_in &&
 850		    (first_data_bytes != min_t(int, 188, bytecount))) {
 851			dwc2_sch_dbg(hsotg,
 852				     "QH=%p avoiding broken 1st xfer (%d, %d)\n",
 853				     qh, first_data_bytes, bytecount);
 854			if (qh->schedule_low_speed)
 855				dwc2_ls_pmap_unschedule(hsotg, qh);
 856			ls_search_slice = (start_s_uframe + 1) *
 857				DWC2_SLICES_PER_UFRAME;
 858			continue;
 859		}
 860
 861		/* Start by assuming transfers for the bytes */
 862		qh->num_hs_transfers = 1 + DIV_ROUND_UP(other_data_bytes, 188);
 863
 864		/*
 865		 * Everything except ISOC OUT has extra transfers.  Rules are
 866		 * complicated.  See 11.18.4 Host Split Transaction Scheduling
 867		 * Requirements bullet 3.
 868		 */
 869		if (qh->ep_type == USB_ENDPOINT_XFER_INT) {
 870			if (rel_uframe == 6)
 871				qh->num_hs_transfers += 2;
 872			else
 873				qh->num_hs_transfers += 3;
 874
 875			if (qh->ep_is_in) {
 876				/*
 877				 * First is start split, middle/end is data.
 878				 * Allocate full data bytes for all data.
 879				 */
 880				first_count = 4;
 881				middle_count = bytecount;
 882				end_count = bytecount;
 883			} else {
 884				/*
 885				 * First is data, middle/end is complete.
 886				 * First transfer and second can have data.
 887				 * Rest should just have complete split.
 888				 */
 889				first_count = first_data_bytes;
 890				middle_count = max_t(int, 4, other_data_bytes);
 891				end_count = 4;
 892			}
 893		} else {
 894			if (qh->ep_is_in) {
 895				int last;
 896
 897				/* Account for the start split */
 898				qh->num_hs_transfers++;
 899
 900				/* Calculate "L" value from spec */
 901				last = rel_uframe + qh->num_hs_transfers + 1;
 902
 903				/* Start with basic case */
 904				if (last <= 6)
 905					qh->num_hs_transfers += 2;
 906				else
 907					qh->num_hs_transfers += 1;
 908
 909				/* Adjust downwards */
 910				if (last >= 6 && rel_uframe == 0)
 911					qh->num_hs_transfers--;
 912
 913				/* 1st = start; rest can contain data */
 914				first_count = 4;
 915				middle_count = min_t(int, 188, bytecount);
 916				end_count = middle_count;
 917			} else {
 918				/* All contain data, last might be smaller */
 919				first_count = first_data_bytes;
 920				middle_count = min_t(int, 188,
 921						     other_data_bytes);
 922				end_count = other_data_bytes % 188;
 923			}
 924		}
 925
 926		/* Assign durations per uFrame */
 927		qh->hs_transfers[0].duration_us = HS_USECS_ISO(first_count);
 928		for (i = 1; i < qh->num_hs_transfers - 1; i++)
 929			qh->hs_transfers[i].duration_us =
 930				HS_USECS_ISO(middle_count);
 931		if (qh->num_hs_transfers > 1)
 932			qh->hs_transfers[qh->num_hs_transfers - 1].duration_us =
 933				HS_USECS_ISO(end_count);
 934
 935		/*
 936		 * Assign start us.  The call below to dwc2_hs_pmap_schedule()
 937		 * will start with these numbers but may adjust within the same
 938		 * microframe.
 939		 */
 940		qh->hs_transfers[0].start_schedule_us =
 941			ssplit_s_uframe * DWC2_HS_PERIODIC_US_PER_UFRAME;
 942		for (i = 1; i < qh->num_hs_transfers; i++)
 943			qh->hs_transfers[i].start_schedule_us =
 944				((second_s_uframe + i - 1) %
 945				 DWC2_HS_SCHEDULE_UFRAMES) *
 946				DWC2_HS_PERIODIC_US_PER_UFRAME;
 947
 948		/* Try to schedule with filled in hs_transfers above */
 949		for (i = 0; i < qh->num_hs_transfers; i++) {
 950			err = dwc2_hs_pmap_schedule(hsotg, qh, true, i);
 951			if (err)
 952				break;
 953		}
 954
 955		/* If we scheduled all w/out breaking out then we're all good */
 956		if (i == qh->num_hs_transfers)
 957			break;
 958
 959		for (; i >= 0; i--)
 960			dwc2_hs_pmap_unschedule(hsotg, qh, i);
 961
 962		if (qh->schedule_low_speed)
 963			dwc2_ls_pmap_unschedule(hsotg, qh);
 964
 965		/* Try again starting in the next microframe */
 966		ls_search_slice = (start_s_uframe + 1) * DWC2_SLICES_PER_UFRAME;
 967	}
 968
 969	if (ls_search_slice >= DWC2_LS_SCHEDULE_SLICES)
 970		return -ENOSPC;
 971
 972	return 0;
 973}
 974
 975/**
 976 * dwc2_uframe_schedule_hs - Schedule a QH for a periodic high speed xfer.
 977 *
 978 * Basically this just wraps dwc2_hs_pmap_schedule() to provide a clean
 979 * interface.
 980 *
 981 * @hsotg:       The HCD state structure for the DWC OTG controller.
 982 * @qh:          QH for the periodic transfer.
 983 */
 984static int dwc2_uframe_schedule_hs(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
 985{
 986	/* In non-split host and device time are the same */
 987	WARN_ON(qh->host_us != qh->device_us);
 988	WARN_ON(qh->host_interval != qh->device_interval);
 989	WARN_ON(qh->num_hs_transfers != 1);
 990
 991	/* We'll have one transfer; init start to 0 before calling scheduler */
 992	qh->hs_transfers[0].start_schedule_us = 0;
 993	qh->hs_transfers[0].duration_us = qh->host_us;
 994
 995	return dwc2_hs_pmap_schedule(hsotg, qh, false, 0);
 996}
 997
 998/**
 999 * dwc2_uframe_schedule_ls - Schedule a QH for a periodic low/full speed xfer.
1000 *
1001 * Basically this just wraps dwc2_ls_pmap_schedule() to provide a clean
1002 * interface.
1003 *
1004 * @hsotg:       The HCD state structure for the DWC OTG controller.
1005 * @qh:          QH for the periodic transfer.
1006 */
1007static int dwc2_uframe_schedule_ls(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1008{
1009	/* In non-split host and device time are the same */
1010	WARN_ON(qh->host_us != qh->device_us);
1011	WARN_ON(qh->host_interval != qh->device_interval);
1012	WARN_ON(!qh->schedule_low_speed);
1013
1014	/* Run on the main low speed schedule (no split = no hub = no TT) */
1015	return dwc2_ls_pmap_schedule(hsotg, qh, 0);
1016}
1017
1018/**
1019 * dwc2_uframe_schedule - Schedule a QH for a periodic xfer.
1020 *
1021 * Calls one of the 3 sub-function depending on what type of transfer this QH
1022 * is for.  Also adds some printing.
1023 *
1024 * @hsotg:       The HCD state structure for the DWC OTG controller.
1025 * @qh:          QH for the periodic transfer.
1026 */
1027static int dwc2_uframe_schedule(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1028{
1029	int ret;
1030
1031	if (qh->dev_speed == USB_SPEED_HIGH)
1032		ret = dwc2_uframe_schedule_hs(hsotg, qh);
1033	else if (!qh->do_split)
1034		ret = dwc2_uframe_schedule_ls(hsotg, qh);
1035	else
1036		ret = dwc2_uframe_schedule_split(hsotg, qh);
1037
1038	if (ret)
1039		dwc2_sch_dbg(hsotg, "QH=%p Failed to schedule %d\n", qh, ret);
1040	else
1041		dwc2_qh_schedule_print(hsotg, qh);
1042
1043	return ret;
1044}
1045
1046/**
1047 * dwc2_uframe_unschedule - Undoes dwc2_uframe_schedule().
1048 *
1049 * @hsotg:       The HCD state structure for the DWC OTG controller.
1050 * @qh:          QH for the periodic transfer.
1051 */
1052static void dwc2_uframe_unschedule(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1053{
1054	int i;
1055
1056	for (i = 0; i < qh->num_hs_transfers; i++)
1057		dwc2_hs_pmap_unschedule(hsotg, qh, i);
1058
1059	if (qh->schedule_low_speed)
1060		dwc2_ls_pmap_unschedule(hsotg, qh);
1061
1062	dwc2_sch_dbg(hsotg, "QH=%p Unscheduled\n", qh);
1063}
1064
1065/**
1066 * dwc2_pick_first_frame() - Choose 1st frame for qh that's already scheduled
1067 *
1068 * Takes a qh that has already been scheduled (which means we know we have the
1069 * bandwdith reserved for us) and set the next_active_frame and the
1070 * start_active_frame.
1071 *
1072 * This is expected to be called on qh's that weren't previously actively
1073 * running.  It just picks the next frame that we can fit into without any
1074 * thought about the past.
1075 *
1076 * @hsotg: The HCD state structure for the DWC OTG controller
1077 * @qh:    QH for a periodic endpoint
1078 *
1079 */
1080static void dwc2_pick_first_frame(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1081{
1082	u16 frame_number;
1083	u16 earliest_frame;
1084	u16 next_active_frame;
1085	u16 relative_frame;
1086	u16 interval;
1087
1088	/*
1089	 * Use the real frame number rather than the cached value as of the
1090	 * last SOF to give us a little extra slop.
1091	 */
1092	frame_number = dwc2_hcd_get_frame_number(hsotg);
1093
1094	/*
1095	 * We wouldn't want to start any earlier than the next frame just in
1096	 * case the frame number ticks as we're doing this calculation.
1097	 *
1098	 * NOTE: if we could quantify how long till we actually get scheduled
1099	 * we might be able to avoid the "+ 1" by looking at the upper part of
1100	 * HFNUM (the FRREM field).  For now we'll just use the + 1 though.
1101	 */
1102	earliest_frame = dwc2_frame_num_inc(frame_number, 1);
1103	next_active_frame = earliest_frame;
1104
1105	/* Get the "no microframe schduler" out of the way... */
1106	if (hsotg->core_params->uframe_sched <= 0) {
1107		if (qh->do_split)
1108			/* Splits are active at microframe 0 minus 1 */
1109			next_active_frame |= 0x7;
1110		goto exit;
1111	}
1112
1113	if (qh->dev_speed == USB_SPEED_HIGH || qh->do_split) {
1114		/*
1115		 * We're either at high speed or we're doing a split (which
1116		 * means we're talking high speed to a hub).  In any case
1117		 * the first frame should be based on when the first scheduled
1118		 * event is.
1119		 */
1120		WARN_ON(qh->num_hs_transfers < 1);
1121
1122		relative_frame = qh->hs_transfers[0].start_schedule_us /
1123				 DWC2_HS_PERIODIC_US_PER_UFRAME;
1124
1125		/* Adjust interval as per high speed schedule */
1126		interval = gcd(qh->host_interval, DWC2_HS_SCHEDULE_UFRAMES);
1127
1128	} else {
1129		/*
1130		 * Low or full speed directly on dwc2.  Just about the same
1131		 * as high speed but on a different schedule and with slightly
1132		 * different adjustments.  Note that this works because when
1133		 * the host and device are both low speed then frames in the
1134		 * controller tick at low speed.
1135		 */
1136		relative_frame = qh->ls_start_schedule_slice /
1137				 DWC2_LS_PERIODIC_SLICES_PER_FRAME;
1138		interval = gcd(qh->host_interval, DWC2_LS_SCHEDULE_FRAMES);
1139	}
1140
1141	/* Scheduler messed up if frame is past interval */
1142	WARN_ON(relative_frame >= interval);
1143
1144	/*
1145	 * We know interval must divide (HFNUM_MAX_FRNUM + 1) now that we've
1146	 * done the gcd(), so it's safe to move to the beginning of the current
1147	 * interval like this.
1148	 *
1149	 * After this we might be before earliest_frame, but don't worry,
1150	 * we'll fix it...
1151	 */
1152	next_active_frame = (next_active_frame / interval) * interval;
1153
1154	/*
1155	 * Actually choose to start at the frame number we've been
1156	 * scheduled for.
1157	 */
1158	next_active_frame = dwc2_frame_num_inc(next_active_frame,
1159					       relative_frame);
1160
1161	/*
1162	 * We actually need 1 frame before since the next_active_frame is
1163	 * the frame number we'll be put on the ready list and we won't be on
1164	 * the bus until 1 frame later.
1165	 */
1166	next_active_frame = dwc2_frame_num_dec(next_active_frame, 1);
1167
1168	/*
1169	 * By now we might actually be before the earliest_frame.  Let's move
1170	 * up intervals until we're not.
1171	 */
1172	while (dwc2_frame_num_gt(earliest_frame, next_active_frame))
1173		next_active_frame = dwc2_frame_num_inc(next_active_frame,
1174						       interval);
1175
1176exit:
1177	qh->next_active_frame = next_active_frame;
1178	qh->start_active_frame = next_active_frame;
1179
1180	dwc2_sch_vdbg(hsotg, "QH=%p First fn=%04x nxt=%04x\n",
1181		     qh, frame_number, qh->next_active_frame);
1182}
1183
1184/**
1185 * dwc2_do_reserve() - Make a periodic reservation
1186 *
1187 * Try to allocate space in the periodic schedule.  Depending on parameters
1188 * this might use the microframe scheduler or the dumb scheduler.
1189 *
1190 * @hsotg: The HCD state structure for the DWC OTG controller
1191 * @qh:    QH for the periodic transfer.
1192 *
1193 * Returns: 0 upon success; error upon failure.
1194 */
1195static int dwc2_do_reserve(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1196{
1197	int status;
1198
1199	if (hsotg->core_params->uframe_sched > 0) {
1200		status = dwc2_uframe_schedule(hsotg, qh);
1201	} else {
1202		status = dwc2_periodic_channel_available(hsotg);
1203		if (status) {
1204			dev_info(hsotg->dev,
1205				 "%s: No host channel available for periodic transfer\n",
1206				 __func__);
1207			return status;
1208		}
1209
1210		status = dwc2_check_periodic_bandwidth(hsotg, qh);
1211	}
1212
1213	if (status) {
1214		dev_dbg(hsotg->dev,
1215			"%s: Insufficient periodic bandwidth for periodic transfer\n",
1216			__func__);
1217		return status;
1218	}
1219
1220	if (hsotg->core_params->uframe_sched <= 0)
1221		/* Reserve periodic channel */
1222		hsotg->periodic_channels++;
1223
1224	/* Update claimed usecs per (micro)frame */
1225	hsotg->periodic_usecs += qh->host_us;
1226
1227	dwc2_pick_first_frame(hsotg, qh);
1228
1229	return 0;
1230}
1231
1232/**
1233 * dwc2_do_unreserve() - Actually release the periodic reservation
1234 *
1235 * This function actually releases the periodic bandwidth that was reserved
1236 * by the given qh.
1237 *
1238 * @hsotg: The HCD state structure for the DWC OTG controller
1239 * @qh:    QH for the periodic transfer.
1240 */
1241static void dwc2_do_unreserve(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1242{
1243	assert_spin_locked(&hsotg->lock);
1244
1245	WARN_ON(!qh->unreserve_pending);
1246
1247	/* No more unreserve pending--we're doing it */
1248	qh->unreserve_pending = false;
1249
1250	if (WARN_ON(!list_empty(&qh->qh_list_entry)))
1251		list_del_init(&qh->qh_list_entry);
1252
1253	/* Update claimed usecs per (micro)frame */
1254	hsotg->periodic_usecs -= qh->host_us;
1255
1256	if (hsotg->core_params->uframe_sched > 0) {
1257		dwc2_uframe_unschedule(hsotg, qh);
1258	} else {
1259		/* Release periodic channel reservation */
1260		hsotg->periodic_channels--;
1261	}
1262}
1263
1264/**
1265 * dwc2_unreserve_timer_fn() - Timer function to release periodic reservation
1266 *
1267 * According to the kernel doc for usb_submit_urb() (specifically the part about
1268 * "Reserved Bandwidth Transfers"), we need to keep a reservation active as
1269 * long as a device driver keeps submitting.  Since we're using HCD_BH to give
1270 * back the URB we need to give the driver a little bit of time before we
1271 * release the reservation.  This worker is called after the appropriate
1272 * delay.
1273 *
1274 * @work: Pointer to a qh unreserve_work.
1275 */
1276static void dwc2_unreserve_timer_fn(unsigned long data)
1277{
1278	struct dwc2_qh *qh = (struct dwc2_qh *)data;
1279	struct dwc2_hsotg *hsotg = qh->hsotg;
1280	unsigned long flags;
1281
1282	/*
1283	 * Wait for the lock, or for us to be scheduled again.  We
1284	 * could be scheduled again if:
1285	 * - We started executing but didn't get the lock yet.
1286	 * - A new reservation came in, but cancel didn't take effect
1287	 *   because we already started executing.
1288	 * - The timer has been kicked again.
1289	 * In that case cancel and wait for the next call.
1290	 */
1291	while (!spin_trylock_irqsave(&hsotg->lock, flags)) {
1292		if (timer_pending(&qh->unreserve_timer))
1293			return;
1294	}
1295
1296	/*
1297	 * Might be no more unreserve pending if:
1298	 * - We started executing but didn't get the lock yet.
1299	 * - A new reservation came in, but cancel didn't take effect
1300	 *   because we already started executing.
1301	 *
1302	 * We can't put this in the loop above because unreserve_pending needs
1303	 * to be accessed under lock, so we can only check it once we got the
1304	 * lock.
1305	 */
1306	if (qh->unreserve_pending)
1307		dwc2_do_unreserve(hsotg, qh);
1308
1309	spin_unlock_irqrestore(&hsotg->lock, flags);
1310}
1311
1312/**
1313 * dwc2_check_max_xfer_size() - Checks that the max transfer size allowed in a
1314 * host channel is large enough to handle the maximum data transfer in a single
1315 * (micro)frame for a periodic transfer
1316 *
1317 * @hsotg: The HCD state structure for the DWC OTG controller
1318 * @qh:    QH for a periodic endpoint
1319 *
1320 * Return: 0 if successful, negative error code otherwise
1321 */
1322static int dwc2_check_max_xfer_size(struct dwc2_hsotg *hsotg,
1323				    struct dwc2_qh *qh)
1324{
1325	u32 max_xfer_size;
1326	u32 max_channel_xfer_size;
1327	int status = 0;
1328
1329	max_xfer_size = dwc2_max_packet(qh->maxp) * dwc2_hb_mult(qh->maxp);
1330	max_channel_xfer_size = hsotg->core_params->max_transfer_size;
1331
1332	if (max_xfer_size > max_channel_xfer_size) {
1333		dev_err(hsotg->dev,
1334			"%s: Periodic xfer length %d > max xfer length for channel %d\n",
1335			__func__, max_xfer_size, max_channel_xfer_size);
1336		status = -ENOSPC;
1337	}
1338
1339	return status;
1340}
1341
1342/**
1343 * dwc2_schedule_periodic() - Schedules an interrupt or isochronous transfer in
1344 * the periodic schedule
1345 *
1346 * @hsotg: The HCD state structure for the DWC OTG controller
1347 * @qh:    QH for the periodic transfer. The QH should already contain the
1348 *         scheduling information.
1349 *
1350 * Return: 0 if successful, negative error code otherwise
1351 */
1352static int dwc2_schedule_periodic(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1353{
1354	int status;
1355
1356	status = dwc2_check_max_xfer_size(hsotg, qh);
1357	if (status) {
1358		dev_dbg(hsotg->dev,
1359			"%s: Channel max transfer size too small for periodic transfer\n",
1360			__func__);
1361		return status;
1362	}
1363
1364	/* Cancel pending unreserve; if canceled OK, unreserve was pending */
1365	if (del_timer(&qh->unreserve_timer))
1366		WARN_ON(!qh->unreserve_pending);
1367
1368	/*
1369	 * Only need to reserve if there's not an unreserve pending, since if an
1370	 * unreserve is pending then by definition our old reservation is still
1371	 * valid.  Unreserve might still be pending even if we didn't cancel if
1372	 * dwc2_unreserve_timer_fn() already started.  Code in the timer handles
1373	 * that case.
1374	 */
1375	if (!qh->unreserve_pending) {
1376		status = dwc2_do_reserve(hsotg, qh);
1377		if (status)
1378			return status;
1379	} else {
1380		/*
1381		 * It might have been a while, so make sure that frame_number
1382		 * is still good.  Note: we could also try to use the similar
1383		 * dwc2_next_periodic_start() but that schedules much more
1384		 * tightly and we might need to hurry and queue things up.
1385		 */
1386		if (dwc2_frame_num_le(qh->next_active_frame,
1387				      hsotg->frame_number))
1388			dwc2_pick_first_frame(hsotg, qh);
1389	}
1390
1391	qh->unreserve_pending = 0;
1392
1393	if (hsotg->core_params->dma_desc_enable > 0)
1394		/* Don't rely on SOF and start in ready schedule */
1395		list_add_tail(&qh->qh_list_entry, &hsotg->periodic_sched_ready);
1396	else
1397		/* Always start in inactive schedule */
1398		list_add_tail(&qh->qh_list_entry,
1399			      &hsotg->periodic_sched_inactive);
1400
1401	return 0;
1402}
1403
1404/**
1405 * dwc2_deschedule_periodic() - Removes an interrupt or isochronous transfer
1406 * from the periodic schedule
1407 *
1408 * @hsotg: The HCD state structure for the DWC OTG controller
1409 * @qh:	   QH for the periodic transfer
1410 */
1411static void dwc2_deschedule_periodic(struct dwc2_hsotg *hsotg,
1412				     struct dwc2_qh *qh)
1413{
1414	bool did_modify;
1415
1416	assert_spin_locked(&hsotg->lock);
1417
1418	/*
1419	 * Schedule the unreserve to happen in a little bit.  Cases here:
1420	 * - Unreserve worker might be sitting there waiting to grab the lock.
1421	 *   In this case it will notice it's been schedule again and will
1422	 *   quit.
1423	 * - Unreserve worker might not be scheduled.
1424	 *
1425	 * We should never already be scheduled since dwc2_schedule_periodic()
1426	 * should have canceled the scheduled unreserve timer (hence the
1427	 * warning on did_modify).
1428	 *
1429	 * We add + 1 to the timer to guarantee that at least 1 jiffy has
1430	 * passed (otherwise if the jiffy counter might tick right after we
1431	 * read it and we'll get no delay).
1432	 */
1433	did_modify = mod_timer(&qh->unreserve_timer,
1434			       jiffies + DWC2_UNRESERVE_DELAY + 1);
1435	WARN_ON(did_modify);
1436	qh->unreserve_pending = 1;
1437
1438	list_del_init(&qh->qh_list_entry);
1439}
1440
1441/**
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1442 * dwc2_qh_init() - Initializes a QH structure
1443 *
1444 * @hsotg: The HCD state structure for the DWC OTG controller
1445 * @qh:    The QH to init
1446 * @urb:   Holds the information about the device/endpoint needed to initialize
1447 *         the QH
1448 * @mem_flags: Flags for allocating memory.
1449 */
1450static void dwc2_qh_init(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
1451			 struct dwc2_hcd_urb *urb, gfp_t mem_flags)
1452{
1453	int dev_speed = dwc2_host_get_speed(hsotg, urb->priv);
1454	u8 ep_type = dwc2_hcd_get_pipe_type(&urb->pipe_info);
1455	bool ep_is_in = !!dwc2_hcd_is_pipe_in(&urb->pipe_info);
1456	bool ep_is_isoc = (ep_type == USB_ENDPOINT_XFER_ISOC);
1457	bool ep_is_int = (ep_type == USB_ENDPOINT_XFER_INT);
1458	u32 hprt = dwc2_readl(hsotg->regs + HPRT0);
1459	u32 prtspd = (hprt & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
1460	bool do_split = (prtspd == HPRT0_SPD_HIGH_SPEED &&
1461			 dev_speed != USB_SPEED_HIGH);
1462	int maxp = dwc2_hcd_get_mps(&urb->pipe_info);
1463	int bytecount = dwc2_hb_mult(maxp) * dwc2_max_packet(maxp);
 
1464	char *speed, *type;
1465
1466	/* Initialize QH */
1467	qh->hsotg = hsotg;
1468	setup_timer(&qh->unreserve_timer, dwc2_unreserve_timer_fn,
1469		    (unsigned long)qh);
 
1470	qh->ep_type = ep_type;
1471	qh->ep_is_in = ep_is_in;
1472
1473	qh->data_toggle = DWC2_HC_PID_DATA0;
1474	qh->maxp = maxp;
 
1475	INIT_LIST_HEAD(&qh->qtd_list);
1476	INIT_LIST_HEAD(&qh->qh_list_entry);
1477
1478	qh->do_split = do_split;
1479	qh->dev_speed = dev_speed;
1480
1481	if (ep_is_int || ep_is_isoc) {
1482		/* Compute scheduling parameters once and save them */
1483		int host_speed = do_split ? USB_SPEED_HIGH : dev_speed;
1484		struct dwc2_tt *dwc_tt = dwc2_host_get_tt_info(hsotg, urb->priv,
1485							       mem_flags,
1486							       &qh->ttport);
1487		int device_ns;
1488
1489		qh->dwc_tt = dwc_tt;
1490
1491		qh->host_us = NS_TO_US(usb_calc_bus_time(host_speed, ep_is_in,
1492				       ep_is_isoc, bytecount));
1493		device_ns = usb_calc_bus_time(dev_speed, ep_is_in,
1494					      ep_is_isoc, bytecount);
1495
1496		if (do_split && dwc_tt)
1497			device_ns += dwc_tt->usb_tt->think_time;
1498		qh->device_us = NS_TO_US(device_ns);
1499
1500
1501		qh->device_interval = urb->interval;
1502		qh->host_interval = urb->interval * (do_split ? 8 : 1);
1503
1504		/*
1505		 * Schedule low speed if we're running the host in low or
1506		 * full speed OR if we've got a "TT" to deal with to access this
1507		 * device.
1508		 */
1509		qh->schedule_low_speed = prtspd != HPRT0_SPD_HIGH_SPEED ||
1510					 dwc_tt;
1511
1512		if (do_split) {
1513			/* We won't know num transfers until we schedule */
1514			qh->num_hs_transfers = -1;
1515		} else if (dev_speed == USB_SPEED_HIGH) {
1516			qh->num_hs_transfers = 1;
1517		} else {
1518			qh->num_hs_transfers = 0;
1519		}
1520
1521		/* We'll schedule later when we have something to do */
1522	}
1523
1524	switch (dev_speed) {
1525	case USB_SPEED_LOW:
1526		speed = "low";
1527		break;
1528	case USB_SPEED_FULL:
1529		speed = "full";
1530		break;
1531	case USB_SPEED_HIGH:
1532		speed = "high";
1533		break;
1534	default:
1535		speed = "?";
1536		break;
1537	}
1538
1539	switch (qh->ep_type) {
1540	case USB_ENDPOINT_XFER_ISOC:
1541		type = "isochronous";
1542		break;
1543	case USB_ENDPOINT_XFER_INT:
1544		type = "interrupt";
1545		break;
1546	case USB_ENDPOINT_XFER_CONTROL:
1547		type = "control";
1548		break;
1549	case USB_ENDPOINT_XFER_BULK:
1550		type = "bulk";
1551		break;
1552	default:
1553		type = "?";
1554		break;
1555	}
1556
1557	dwc2_sch_dbg(hsotg, "QH=%p Init %s, %s speed, %d bytes:\n", qh, type,
1558		     speed, bytecount);
1559	dwc2_sch_dbg(hsotg, "QH=%p ...addr=%d, ep=%d, %s\n", qh,
1560		     dwc2_hcd_get_dev_addr(&urb->pipe_info),
1561		     dwc2_hcd_get_ep_num(&urb->pipe_info),
1562		     ep_is_in ? "IN" : "OUT");
1563	if (ep_is_int || ep_is_isoc) {
1564		dwc2_sch_dbg(hsotg,
1565			     "QH=%p ...duration: host=%d us, device=%d us\n",
1566			     qh, qh->host_us, qh->device_us);
1567		dwc2_sch_dbg(hsotg, "QH=%p ...interval: host=%d, device=%d\n",
1568			     qh, qh->host_interval, qh->device_interval);
1569		if (qh->schedule_low_speed)
1570			dwc2_sch_dbg(hsotg, "QH=%p ...low speed schedule=%p\n",
1571				     qh, dwc2_get_ls_map(hsotg, qh));
1572	}
1573}
1574
1575/**
1576 * dwc2_hcd_qh_create() - Allocates and initializes a QH
1577 *
1578 * @hsotg:        The HCD state structure for the DWC OTG controller
1579 * @urb:          Holds the information about the device/endpoint needed
1580 *                to initialize the QH
1581 * @atomic_alloc: Flag to do atomic allocation if needed
1582 *
1583 * Return: Pointer to the newly allocated QH, or NULL on error
1584 */
1585struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg,
1586					  struct dwc2_hcd_urb *urb,
1587					  gfp_t mem_flags)
1588{
1589	struct dwc2_qh *qh;
1590
1591	if (!urb->priv)
1592		return NULL;
1593
1594	/* Allocate memory */
1595	qh = kzalloc(sizeof(*qh), mem_flags);
1596	if (!qh)
1597		return NULL;
1598
1599	dwc2_qh_init(hsotg, qh, urb, mem_flags);
1600
1601	if (hsotg->core_params->dma_desc_enable > 0 &&
1602	    dwc2_hcd_qh_init_ddma(hsotg, qh, mem_flags) < 0) {
1603		dwc2_hcd_qh_free(hsotg, qh);
1604		return NULL;
1605	}
1606
1607	return qh;
1608}
1609
1610/**
1611 * dwc2_hcd_qh_free() - Frees the QH
1612 *
1613 * @hsotg: HCD instance
1614 * @qh:    The QH to free
1615 *
1616 * QH should already be removed from the list. QTD list should already be empty
1617 * if called from URB Dequeue.
1618 *
1619 * Must NOT be called with interrupt disabled or spinlock held
1620 */
1621void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1622{
1623	/* Make sure any unreserve work is finished. */
1624	if (del_timer_sync(&qh->unreserve_timer)) {
1625		unsigned long flags;
1626
1627		spin_lock_irqsave(&hsotg->lock, flags);
1628		dwc2_do_unreserve(hsotg, qh);
1629		spin_unlock_irqrestore(&hsotg->lock, flags);
1630	}
 
 
 
 
 
 
 
 
 
 
1631	dwc2_host_put_tt_info(hsotg, qh->dwc_tt);
1632
1633	if (qh->desc_list)
1634		dwc2_hcd_qh_free_ddma(hsotg, qh);
 
 
 
1635	kfree(qh);
1636}
1637
1638/**
1639 * dwc2_hcd_qh_add() - Adds a QH to either the non periodic or periodic
1640 * schedule if it is not already in the schedule. If the QH is already in
1641 * the schedule, no action is taken.
1642 *
1643 * @hsotg: The HCD state structure for the DWC OTG controller
1644 * @qh:    The QH to add
1645 *
1646 * Return: 0 if successful, negative error code otherwise
1647 */
1648int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1649{
1650	int status;
1651	u32 intr_mask;
 
1652
1653	if (dbg_qh(qh))
1654		dev_vdbg(hsotg->dev, "%s()\n", __func__);
1655
1656	if (!list_empty(&qh->qh_list_entry))
1657		/* QH already in a schedule */
1658		return 0;
1659
1660	/* Add the new QH to the appropriate schedule */
1661	if (dwc2_qh_is_non_per(qh)) {
1662		/* Schedule right away */
1663		qh->start_active_frame = hsotg->frame_number;
1664		qh->next_active_frame = qh->start_active_frame;
1665
1666		/* Always start in inactive schedule */
1667		list_add_tail(&qh->qh_list_entry,
1668			      &hsotg->non_periodic_sched_inactive);
 
 
 
 
 
 
 
1669		return 0;
1670	}
1671
1672	status = dwc2_schedule_periodic(hsotg, qh);
1673	if (status)
1674		return status;
1675	if (!hsotg->periodic_qh_count) {
1676		intr_mask = dwc2_readl(hsotg->regs + GINTMSK);
1677		intr_mask |= GINTSTS_SOF;
1678		dwc2_writel(intr_mask, hsotg->regs + GINTMSK);
1679	}
1680	hsotg->periodic_qh_count++;
1681
1682	return 0;
1683}
1684
1685/**
1686 * dwc2_hcd_qh_unlink() - Removes a QH from either the non-periodic or periodic
1687 * schedule. Memory is not freed.
1688 *
1689 * @hsotg: The HCD state structure
1690 * @qh:    QH to remove from schedule
1691 */
1692void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1693{
1694	u32 intr_mask;
1695
1696	dev_vdbg(hsotg->dev, "%s()\n", __func__);
1697
 
 
 
1698	if (list_empty(&qh->qh_list_entry))
1699		/* QH is not in a schedule */
1700		return;
1701
1702	if (dwc2_qh_is_non_per(qh)) {
1703		if (hsotg->non_periodic_qh_ptr == &qh->qh_list_entry)
1704			hsotg->non_periodic_qh_ptr =
1705					hsotg->non_periodic_qh_ptr->next;
1706		list_del_init(&qh->qh_list_entry);
1707		return;
1708	}
1709
1710	dwc2_deschedule_periodic(hsotg, qh);
1711	hsotg->periodic_qh_count--;
1712	if (!hsotg->periodic_qh_count) {
1713		intr_mask = dwc2_readl(hsotg->regs + GINTMSK);
 
1714		intr_mask &= ~GINTSTS_SOF;
1715		dwc2_writel(intr_mask, hsotg->regs + GINTMSK);
1716	}
1717}
1718
1719/**
1720 * dwc2_next_for_periodic_split() - Set next_active_frame midway thru a split.
1721 *
1722 * This is called for setting next_active_frame for periodic splits for all but
1723 * the first packet of the split.  Confusing?  I thought so...
1724 *
1725 * Periodic splits are single low/full speed transfers that we end up splitting
1726 * up into several high speed transfers.  They always fit into one full (1 ms)
1727 * frame but might be split over several microframes (125 us each).  We to put
1728 * each of the parts on a very specific high speed frame.
1729 *
1730 * This function figures out where the next active uFrame needs to be.
1731 *
1732 * @hsotg:        The HCD state structure
1733 * @qh:           QH for the periodic transfer.
1734 * @frame_number: The current frame number.
1735 *
1736 * Return: number missed by (or 0 if we didn't miss).
1737 */
1738static int dwc2_next_for_periodic_split(struct dwc2_hsotg *hsotg,
1739					 struct dwc2_qh *qh, u16 frame_number)
1740{
1741	u16 old_frame = qh->next_active_frame;
1742	u16 prev_frame_number = dwc2_frame_num_dec(frame_number, 1);
1743	int missed = 0;
1744	u16 incr;
1745
1746	/*
1747	 * See dwc2_uframe_schedule_split() for split scheduling.
1748	 *
1749	 * Basically: increment 1 normally, but 2 right after the start split
1750	 * (except for ISOC out).
1751	 */
1752	if (old_frame == qh->start_active_frame &&
1753	    !(qh->ep_type == USB_ENDPOINT_XFER_ISOC && !qh->ep_is_in))
1754		incr = 2;
1755	else
1756		incr = 1;
1757
1758	qh->next_active_frame = dwc2_frame_num_inc(old_frame, incr);
1759
1760	/*
1761	 * Note that it's OK for frame_number to be 1 frame past
1762	 * next_active_frame.  Remember that next_active_frame is supposed to
1763	 * be 1 frame _before_ when we want to be scheduled.  If we're 1 frame
1764	 * past it just means schedule ASAP.
1765	 *
1766	 * It's _not_ OK, however, if we're more than one frame past.
1767	 */
1768	if (dwc2_frame_num_gt(prev_frame_number, qh->next_active_frame)) {
1769		/*
1770		 * OOPS, we missed.  That's actually pretty bad since
1771		 * the hub will be unhappy; try ASAP I guess.
1772		 */
1773		missed = dwc2_frame_num_dec(prev_frame_number,
1774					    qh->next_active_frame);
1775		qh->next_active_frame = frame_number;
1776	}
1777
1778	return missed;
1779}
1780
1781/**
1782 * dwc2_next_periodic_start() - Set next_active_frame for next transfer start
1783 *
1784 * This is called for setting next_active_frame for a periodic transfer for
1785 * all cases other than midway through a periodic split.  This will also update
1786 * start_active_frame.
1787 *
1788 * Since we _always_ keep start_active_frame as the start of the previous
1789 * transfer this is normally pretty easy: we just add our interval to
1790 * start_active_frame and we've got our answer.
1791 *
1792 * The tricks come into play if we miss.  In that case we'll look for the next
1793 * slot we can fit into.
1794 *
1795 * @hsotg:        The HCD state structure
1796 * @qh:           QH for the periodic transfer.
1797 * @frame_number: The current frame number.
1798 *
1799 * Return: number missed by (or 0 if we didn't miss).
1800 */
1801static int dwc2_next_periodic_start(struct dwc2_hsotg *hsotg,
1802				     struct dwc2_qh *qh, u16 frame_number)
1803{
1804	int missed = 0;
1805	u16 interval = qh->host_interval;
1806	u16 prev_frame_number = dwc2_frame_num_dec(frame_number, 1);
1807
1808	qh->start_active_frame = dwc2_frame_num_inc(qh->start_active_frame,
1809						    interval);
1810
1811	/*
1812	 * The dwc2_frame_num_gt() function used below won't work terribly well
1813	 * with if we just incremented by a really large intervals since the
1814	 * frame counter only goes to 0x3fff.  It's terribly unlikely that we
1815	 * will have missed in this case anyway.  Just go to exit.  If we want
1816	 * to try to do better we'll need to keep track of a bigger counter
1817	 * somewhere in the driver and handle overflows.
1818	 */
1819	if (interval >= 0x1000)
1820		goto exit;
1821
1822	/*
1823	 * Test for misses, which is when it's too late to schedule.
1824	 *
1825	 * A few things to note:
1826	 * - We compare against prev_frame_number since start_active_frame
1827	 *   and next_active_frame are always 1 frame before we want things
1828	 *   to be active and we assume we can still get scheduled in the
1829	 *   current frame number.
1830	 * - It's possible for start_active_frame (now incremented) to be
1831	 *   next_active_frame if we got an EO MISS (even_odd miss) which
1832	 *   basically means that we detected there wasn't enough time for
1833	 *   the last packet and dwc2_hc_set_even_odd_frame() rescheduled us
1834	 *   at the last second.  We want to make sure we don't schedule
1835	 *   another transfer for the same frame.  My test webcam doesn't seem
1836	 *   terribly upset by missing a transfer but really doesn't like when
1837	 *   we do two transfers in the same frame.
1838	 * - Some misses are expected.  Specifically, in order to work
1839	 *   perfectly dwc2 really needs quite spectacular interrupt latency
1840	 *   requirements.  It needs to be able to handle its interrupts
1841	 *   completely within 125 us of them being asserted. That not only
1842	 *   means that the dwc2 interrupt handler needs to be fast but it
1843	 *   means that nothing else in the system has to block dwc2 for a long
1844	 *   time.  We can help with the dwc2 parts of this, but it's hard to
1845	 *   guarantee that a system will have interrupt latency < 125 us, so
1846	 *   we have to be robust to some misses.
1847	 */
1848	if (qh->start_active_frame == qh->next_active_frame ||
1849	    dwc2_frame_num_gt(prev_frame_number, qh->start_active_frame)) {
1850		u16 ideal_start = qh->start_active_frame;
1851		int periods_in_map;
1852
1853		/*
1854		 * Adjust interval as per gcd with map size.
1855		 * See pmap_schedule() for more details here.
1856		 */
1857		if (qh->do_split || qh->dev_speed == USB_SPEED_HIGH)
1858			periods_in_map = DWC2_HS_SCHEDULE_UFRAMES;
1859		else
1860			periods_in_map = DWC2_LS_SCHEDULE_FRAMES;
1861		interval = gcd(interval, periods_in_map);
1862
1863		do {
1864			qh->start_active_frame = dwc2_frame_num_inc(
1865				qh->start_active_frame, interval);
1866		} while (dwc2_frame_num_gt(prev_frame_number,
1867					   qh->start_active_frame));
1868
1869		missed = dwc2_frame_num_dec(qh->start_active_frame,
1870					    ideal_start);
1871	}
1872
1873exit:
1874	qh->next_active_frame = qh->start_active_frame;
1875
1876	return missed;
1877}
1878
1879/*
1880 * Deactivates a QH. For non-periodic QHs, removes the QH from the active
1881 * non-periodic schedule. The QH is added to the inactive non-periodic
1882 * schedule if any QTDs are still attached to the QH.
1883 *
1884 * For periodic QHs, the QH is removed from the periodic queued schedule. If
1885 * there are any QTDs still attached to the QH, the QH is added to either the
1886 * periodic inactive schedule or the periodic ready schedule and its next
1887 * scheduled frame is calculated. The QH is placed in the ready schedule if
1888 * the scheduled frame has been reached already. Otherwise it's placed in the
1889 * inactive schedule. If there are no QTDs attached to the QH, the QH is
1890 * completely removed from the periodic schedule.
1891 */
1892void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
1893			    int sched_next_periodic_split)
1894{
1895	u16 old_frame = qh->next_active_frame;
1896	u16 frame_number;
1897	int missed;
1898
1899	if (dbg_qh(qh))
1900		dev_vdbg(hsotg->dev, "%s()\n", __func__);
1901
1902	if (dwc2_qh_is_non_per(qh)) {
1903		dwc2_hcd_qh_unlink(hsotg, qh);
1904		if (!list_empty(&qh->qtd_list))
1905			/* Add back to inactive non-periodic schedule */
1906			dwc2_hcd_qh_add(hsotg, qh);
1907		return;
1908	}
1909
1910	/*
1911	 * Use the real frame number rather than the cached value as of the
1912	 * last SOF just to get us a little closer to reality.  Note that
1913	 * means we don't actually know if we've already handled the SOF
1914	 * interrupt for this frame.
1915	 */
1916	frame_number = dwc2_hcd_get_frame_number(hsotg);
1917
1918	if (sched_next_periodic_split)
1919		missed = dwc2_next_for_periodic_split(hsotg, qh, frame_number);
1920	else
1921		missed = dwc2_next_periodic_start(hsotg, qh, frame_number);
1922
1923	dwc2_sch_vdbg(hsotg,
1924		     "QH=%p next(%d) fn=%04x, sch=%04x=>%04x (%+d) miss=%d %s\n",
1925		     qh, sched_next_periodic_split, frame_number, old_frame,
1926		     qh->next_active_frame,
1927		     dwc2_frame_num_dec(qh->next_active_frame, old_frame),
1928		missed, missed ? "MISS" : "");
1929
1930	if (list_empty(&qh->qtd_list)) {
1931		dwc2_hcd_qh_unlink(hsotg, qh);
1932		return;
1933	}
1934
1935	/*
1936	 * Remove from periodic_sched_queued and move to
1937	 * appropriate queue
1938	 *
1939	 * Note: we purposely use the frame_number from the "hsotg" structure
1940	 * since we know SOF interrupt will handle future frames.
1941	 */
1942	if (dwc2_frame_num_le(qh->next_active_frame, hsotg->frame_number))
1943		list_move_tail(&qh->qh_list_entry,
1944			       &hsotg->periodic_sched_ready);
1945	else
1946		list_move_tail(&qh->qh_list_entry,
1947			       &hsotg->periodic_sched_inactive);
1948}
1949
1950/**
1951 * dwc2_hcd_qtd_init() - Initializes a QTD structure
1952 *
1953 * @qtd: The QTD to initialize
1954 * @urb: The associated URB
1955 */
1956void dwc2_hcd_qtd_init(struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb)
1957{
1958	qtd->urb = urb;
1959	if (dwc2_hcd_get_pipe_type(&urb->pipe_info) ==
1960			USB_ENDPOINT_XFER_CONTROL) {
1961		/*
1962		 * The only time the QTD data toggle is used is on the data
1963		 * phase of control transfers. This phase always starts with
1964		 * DATA1.
1965		 */
1966		qtd->data_toggle = DWC2_HC_PID_DATA1;
1967		qtd->control_phase = DWC2_CONTROL_SETUP;
1968	}
1969
1970	/* Start split */
1971	qtd->complete_split = 0;
1972	qtd->isoc_split_pos = DWC2_HCSPLT_XACTPOS_ALL;
1973	qtd->isoc_split_offset = 0;
1974	qtd->in_process = 0;
1975
1976	/* Store the qtd ptr in the urb to reference the QTD */
1977	urb->qtd = qtd;
1978}
1979
1980/**
1981 * dwc2_hcd_qtd_add() - Adds a QTD to the QTD-list of a QH
1982 *			Caller must hold driver lock.
1983 *
1984 * @hsotg:        The DWC HCD structure
1985 * @qtd:          The QTD to add
1986 * @qh:           Queue head to add qtd to
1987 *
1988 * Return: 0 if successful, negative error code otherwise
1989 *
1990 * If the QH to which the QTD is added is not currently scheduled, it is placed
1991 * into the proper schedule based on its EP type.
1992 */
1993int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
1994		     struct dwc2_qh *qh)
1995{
1996	int retval;
1997
1998	if (unlikely(!qh)) {
1999		dev_err(hsotg->dev, "%s: Invalid QH\n", __func__);
2000		retval = -EINVAL;
2001		goto fail;
2002	}
2003
2004	retval = dwc2_hcd_qh_add(hsotg, qh);
2005	if (retval)
2006		goto fail;
2007
2008	qtd->qh = qh;
2009	list_add_tail(&qtd->qtd_list_entry, &qh->qtd_list);
2010
2011	return 0;
2012fail:
2013	return retval;
2014}