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1/*
2 * Cadence SPI controller driver (master mode only)
3 *
4 * Copyright (C) 2008 - 2014 Xilinx, Inc.
5 *
6 * based on Blackfin On-Chip SPI Driver (spi_bfin5xx.c)
7 *
8 * This program is free software; you can redistribute it and/or modify it under
9 * the terms of the GNU General Public License version 2 as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/clk.h>
15#include <linux/delay.h>
16#include <linux/interrupt.h>
17#include <linux/io.h>
18#include <linux/module.h>
19#include <linux/of_irq.h>
20#include <linux/of_address.h>
21#include <linux/platform_device.h>
22#include <linux/spi/spi.h>
23
24/* Name of this driver */
25#define CDNS_SPI_NAME "cdns-spi"
26
27/* Register offset definitions */
28#define CDNS_SPI_CR_OFFSET 0x00 /* Configuration Register, RW */
29#define CDNS_SPI_ISR_OFFSET 0x04 /* Interrupt Status Register, RO */
30#define CDNS_SPI_IER_OFFSET 0x08 /* Interrupt Enable Register, WO */
31#define CDNS_SPI_IDR_OFFSET 0x0c /* Interrupt Disable Register, WO */
32#define CDNS_SPI_IMR_OFFSET 0x10 /* Interrupt Enabled Mask Register, RO */
33#define CDNS_SPI_ER_OFFSET 0x14 /* Enable/Disable Register, RW */
34#define CDNS_SPI_DR_OFFSET 0x18 /* Delay Register, RW */
35#define CDNS_SPI_TXD_OFFSET 0x1C /* Data Transmit Register, WO */
36#define CDNS_SPI_RXD_OFFSET 0x20 /* Data Receive Register, RO */
37#define CDNS_SPI_SICR_OFFSET 0x24 /* Slave Idle Count Register, RW */
38#define CDNS_SPI_THLD_OFFSET 0x28 /* Transmit FIFO Watermark Register,RW */
39
40/*
41 * SPI Configuration Register bit Masks
42 *
43 * This register contains various control bits that affect the operation
44 * of the SPI controller
45 */
46#define CDNS_SPI_CR_MANSTRT_MASK 0x00010000 /* Manual TX Start */
47#define CDNS_SPI_CR_CPHA_MASK 0x00000004 /* Clock Phase Control */
48#define CDNS_SPI_CR_CPOL_MASK 0x00000002 /* Clock Polarity Control */
49#define CDNS_SPI_CR_SSCTRL_MASK 0x00003C00 /* Slave Select Mask */
50#define CDNS_SPI_CR_PERI_SEL_MASK 0x00000200 /* Peripheral Select Decode */
51#define CDNS_SPI_CR_BAUD_DIV_MASK 0x00000038 /* Baud Rate Divisor Mask */
52#define CDNS_SPI_CR_MSTREN_MASK 0x00000001 /* Master Enable Mask */
53#define CDNS_SPI_CR_MANSTRTEN_MASK 0x00008000 /* Manual TX Enable Mask */
54#define CDNS_SPI_CR_SSFORCE_MASK 0x00004000 /* Manual SS Enable Mask */
55#define CDNS_SPI_CR_BAUD_DIV_4_MASK 0x00000008 /* Default Baud Div Mask */
56#define CDNS_SPI_CR_DEFAULT_MASK (CDNS_SPI_CR_MSTREN_MASK | \
57 CDNS_SPI_CR_SSCTRL_MASK | \
58 CDNS_SPI_CR_SSFORCE_MASK | \
59 CDNS_SPI_CR_BAUD_DIV_4_MASK)
60
61/*
62 * SPI Configuration Register - Baud rate and slave select
63 *
64 * These are the values used in the calculation of baud rate divisor and
65 * setting the slave select.
66 */
67
68#define CDNS_SPI_BAUD_DIV_MAX 7 /* Baud rate divisor maximum */
69#define CDNS_SPI_BAUD_DIV_MIN 1 /* Baud rate divisor minimum */
70#define CDNS_SPI_BAUD_DIV_SHIFT 3 /* Baud rate divisor shift in CR */
71#define CDNS_SPI_SS_SHIFT 10 /* Slave Select field shift in CR */
72#define CDNS_SPI_SS0 0x1 /* Slave Select zero */
73
74/*
75 * SPI Interrupt Registers bit Masks
76 *
77 * All the four interrupt registers (Status/Mask/Enable/Disable) have the same
78 * bit definitions.
79 */
80#define CDNS_SPI_IXR_TXOW_MASK 0x00000004 /* SPI TX FIFO Overwater */
81#define CDNS_SPI_IXR_MODF_MASK 0x00000002 /* SPI Mode Fault */
82#define CDNS_SPI_IXR_RXNEMTY_MASK 0x00000010 /* SPI RX FIFO Not Empty */
83#define CDNS_SPI_IXR_DEFAULT_MASK (CDNS_SPI_IXR_TXOW_MASK | \
84 CDNS_SPI_IXR_MODF_MASK)
85#define CDNS_SPI_IXR_TXFULL_MASK 0x00000008 /* SPI TX Full */
86#define CDNS_SPI_IXR_ALL_MASK 0x0000007F /* SPI all interrupts */
87
88/*
89 * SPI Enable Register bit Masks
90 *
91 * This register is used to enable or disable the SPI controller
92 */
93#define CDNS_SPI_ER_ENABLE_MASK 0x00000001 /* SPI Enable Bit Mask */
94#define CDNS_SPI_ER_DISABLE_MASK 0x0 /* SPI Disable Bit Mask */
95
96/* SPI FIFO depth in bytes */
97#define CDNS_SPI_FIFO_DEPTH 128
98
99/* Default number of chip select lines */
100#define CDNS_SPI_DEFAULT_NUM_CS 4
101
102/**
103 * struct cdns_spi - This definition defines spi driver instance
104 * @regs: Virtual address of the SPI controller registers
105 * @ref_clk: Pointer to the peripheral clock
106 * @pclk: Pointer to the APB clock
107 * @speed_hz: Current SPI bus clock speed in Hz
108 * @txbuf: Pointer to the TX buffer
109 * @rxbuf: Pointer to the RX buffer
110 * @tx_bytes: Number of bytes left to transfer
111 * @rx_bytes: Number of bytes requested
112 * @dev_busy: Device busy flag
113 * @is_decoded_cs: Flag for decoder property set or not
114 */
115struct cdns_spi {
116 void __iomem *regs;
117 struct clk *ref_clk;
118 struct clk *pclk;
119 u32 speed_hz;
120 const u8 *txbuf;
121 u8 *rxbuf;
122 int tx_bytes;
123 int rx_bytes;
124 u8 dev_busy;
125 u32 is_decoded_cs;
126};
127
128/* Macros for the SPI controller read/write */
129static inline u32 cdns_spi_read(struct cdns_spi *xspi, u32 offset)
130{
131 return readl_relaxed(xspi->regs + offset);
132}
133
134static inline void cdns_spi_write(struct cdns_spi *xspi, u32 offset, u32 val)
135{
136 writel_relaxed(val, xspi->regs + offset);
137}
138
139/**
140 * cdns_spi_init_hw - Initialize the hardware and configure the SPI controller
141 * @xspi: Pointer to the cdns_spi structure
142 *
143 * On reset the SPI controller is configured to be in master mode, baud rate
144 * divisor is set to 4, threshold value for TX FIFO not full interrupt is set
145 * to 1 and size of the word to be transferred as 8 bit.
146 * This function initializes the SPI controller to disable and clear all the
147 * interrupts, enable manual slave select and manual start, deselect all the
148 * chip select lines, and enable the SPI controller.
149 */
150static void cdns_spi_init_hw(struct cdns_spi *xspi)
151{
152 u32 ctrl_reg = CDNS_SPI_CR_DEFAULT_MASK;
153
154 if (xspi->is_decoded_cs)
155 ctrl_reg |= CDNS_SPI_CR_PERI_SEL_MASK;
156
157 cdns_spi_write(xspi, CDNS_SPI_ER_OFFSET,
158 CDNS_SPI_ER_DISABLE_MASK);
159 cdns_spi_write(xspi, CDNS_SPI_IDR_OFFSET,
160 CDNS_SPI_IXR_ALL_MASK);
161
162 /* Clear the RX FIFO */
163 while (cdns_spi_read(xspi, CDNS_SPI_ISR_OFFSET) &
164 CDNS_SPI_IXR_RXNEMTY_MASK)
165 cdns_spi_read(xspi, CDNS_SPI_RXD_OFFSET);
166
167 cdns_spi_write(xspi, CDNS_SPI_ISR_OFFSET,
168 CDNS_SPI_IXR_ALL_MASK);
169 cdns_spi_write(xspi, CDNS_SPI_CR_OFFSET, ctrl_reg);
170 cdns_spi_write(xspi, CDNS_SPI_ER_OFFSET,
171 CDNS_SPI_ER_ENABLE_MASK);
172}
173
174/**
175 * cdns_spi_chipselect - Select or deselect the chip select line
176 * @spi: Pointer to the spi_device structure
177 * @is_on: Select(0) or deselect (1) the chip select line
178 */
179static void cdns_spi_chipselect(struct spi_device *spi, bool is_high)
180{
181 struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
182 u32 ctrl_reg;
183
184 ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR_OFFSET);
185
186 if (is_high) {
187 /* Deselect the slave */
188 ctrl_reg |= CDNS_SPI_CR_SSCTRL_MASK;
189 } else {
190 /* Select the slave */
191 ctrl_reg &= ~CDNS_SPI_CR_SSCTRL_MASK;
192 if (!(xspi->is_decoded_cs))
193 ctrl_reg |= ((~(CDNS_SPI_SS0 << spi->chip_select)) <<
194 CDNS_SPI_SS_SHIFT) &
195 CDNS_SPI_CR_SSCTRL_MASK;
196 else
197 ctrl_reg |= (spi->chip_select << CDNS_SPI_SS_SHIFT) &
198 CDNS_SPI_CR_SSCTRL_MASK;
199 }
200
201 cdns_spi_write(xspi, CDNS_SPI_CR_OFFSET, ctrl_reg);
202}
203
204/**
205 * cdns_spi_config_clock_mode - Sets clock polarity and phase
206 * @spi: Pointer to the spi_device structure
207 *
208 * Sets the requested clock polarity and phase.
209 */
210static void cdns_spi_config_clock_mode(struct spi_device *spi)
211{
212 struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
213 u32 ctrl_reg, new_ctrl_reg;
214
215 new_ctrl_reg = ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR_OFFSET);
216
217 /* Set the SPI clock phase and clock polarity */
218 new_ctrl_reg &= ~(CDNS_SPI_CR_CPHA_MASK | CDNS_SPI_CR_CPOL_MASK);
219 if (spi->mode & SPI_CPHA)
220 new_ctrl_reg |= CDNS_SPI_CR_CPHA_MASK;
221 if (spi->mode & SPI_CPOL)
222 new_ctrl_reg |= CDNS_SPI_CR_CPOL_MASK;
223
224 if (new_ctrl_reg != ctrl_reg) {
225 /*
226 * Just writing the CR register does not seem to apply the clock
227 * setting changes. This is problematic when changing the clock
228 * polarity as it will cause the SPI slave to see spurious clock
229 * transitions. To workaround the issue toggle the ER register.
230 */
231 cdns_spi_write(xspi, CDNS_SPI_ER_OFFSET,
232 CDNS_SPI_ER_DISABLE_MASK);
233 cdns_spi_write(xspi, CDNS_SPI_CR_OFFSET, new_ctrl_reg);
234 cdns_spi_write(xspi, CDNS_SPI_ER_OFFSET,
235 CDNS_SPI_ER_ENABLE_MASK);
236 }
237}
238
239/**
240 * cdns_spi_config_clock_freq - Sets clock frequency
241 * @spi: Pointer to the spi_device structure
242 * @transfer: Pointer to the spi_transfer structure which provides
243 * information about next transfer setup parameters
244 *
245 * Sets the requested clock frequency.
246 * Note: If the requested frequency is not an exact match with what can be
247 * obtained using the prescalar value the driver sets the clock frequency which
248 * is lower than the requested frequency (maximum lower) for the transfer. If
249 * the requested frequency is higher or lower than that is supported by the SPI
250 * controller the driver will set the highest or lowest frequency supported by
251 * controller.
252 */
253static void cdns_spi_config_clock_freq(struct spi_device *spi,
254 struct spi_transfer *transfer)
255{
256 struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
257 u32 ctrl_reg, baud_rate_val;
258 unsigned long frequency;
259
260 frequency = clk_get_rate(xspi->ref_clk);
261
262 ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR_OFFSET);
263
264 /* Set the clock frequency */
265 if (xspi->speed_hz != transfer->speed_hz) {
266 /* first valid value is 1 */
267 baud_rate_val = CDNS_SPI_BAUD_DIV_MIN;
268 while ((baud_rate_val < CDNS_SPI_BAUD_DIV_MAX) &&
269 (frequency / (2 << baud_rate_val)) > transfer->speed_hz)
270 baud_rate_val++;
271
272 ctrl_reg &= ~CDNS_SPI_CR_BAUD_DIV_MASK;
273 ctrl_reg |= baud_rate_val << CDNS_SPI_BAUD_DIV_SHIFT;
274
275 xspi->speed_hz = frequency / (2 << baud_rate_val);
276 }
277 cdns_spi_write(xspi, CDNS_SPI_CR_OFFSET, ctrl_reg);
278}
279
280/**
281 * cdns_spi_setup_transfer - Configure SPI controller for specified transfer
282 * @spi: Pointer to the spi_device structure
283 * @transfer: Pointer to the spi_transfer structure which provides
284 * information about next transfer setup parameters
285 *
286 * Sets the operational mode of SPI controller for the next SPI transfer and
287 * sets the requested clock frequency.
288 *
289 * Return: Always 0
290 */
291static int cdns_spi_setup_transfer(struct spi_device *spi,
292 struct spi_transfer *transfer)
293{
294 struct cdns_spi *xspi = spi_master_get_devdata(spi->master);
295
296 cdns_spi_config_clock_freq(spi, transfer);
297
298 dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u clock speed\n",
299 __func__, spi->mode, spi->bits_per_word,
300 xspi->speed_hz);
301
302 return 0;
303}
304
305/**
306 * cdns_spi_fill_tx_fifo - Fills the TX FIFO with as many bytes as possible
307 * @xspi: Pointer to the cdns_spi structure
308 */
309static void cdns_spi_fill_tx_fifo(struct cdns_spi *xspi)
310{
311 unsigned long trans_cnt = 0;
312
313 while ((trans_cnt < CDNS_SPI_FIFO_DEPTH) &&
314 (xspi->tx_bytes > 0)) {
315 if (xspi->txbuf)
316 cdns_spi_write(xspi, CDNS_SPI_TXD_OFFSET,
317 *xspi->txbuf++);
318 else
319 cdns_spi_write(xspi, CDNS_SPI_TXD_OFFSET, 0);
320
321 xspi->tx_bytes--;
322 trans_cnt++;
323 }
324}
325
326/**
327 * cdns_spi_irq - Interrupt service routine of the SPI controller
328 * @irq: IRQ number
329 * @dev_id: Pointer to the xspi structure
330 *
331 * This function handles TX empty and Mode Fault interrupts only.
332 * On TX empty interrupt this function reads the received data from RX FIFO and
333 * fills the TX FIFO if there is any data remaining to be transferred.
334 * On Mode Fault interrupt this function indicates that transfer is completed,
335 * the SPI subsystem will identify the error as the remaining bytes to be
336 * transferred is non-zero.
337 *
338 * Return: IRQ_HANDLED when handled; IRQ_NONE otherwise.
339 */
340static irqreturn_t cdns_spi_irq(int irq, void *dev_id)
341{
342 struct spi_master *master = dev_id;
343 struct cdns_spi *xspi = spi_master_get_devdata(master);
344 u32 intr_status, status;
345
346 status = IRQ_NONE;
347 intr_status = cdns_spi_read(xspi, CDNS_SPI_ISR_OFFSET);
348 cdns_spi_write(xspi, CDNS_SPI_ISR_OFFSET, intr_status);
349
350 if (intr_status & CDNS_SPI_IXR_MODF_MASK) {
351 /* Indicate that transfer is completed, the SPI subsystem will
352 * identify the error as the remaining bytes to be
353 * transferred is non-zero
354 */
355 cdns_spi_write(xspi, CDNS_SPI_IDR_OFFSET,
356 CDNS_SPI_IXR_DEFAULT_MASK);
357 spi_finalize_current_transfer(master);
358 status = IRQ_HANDLED;
359 } else if (intr_status & CDNS_SPI_IXR_TXOW_MASK) {
360 unsigned long trans_cnt;
361
362 trans_cnt = xspi->rx_bytes - xspi->tx_bytes;
363
364 /* Read out the data from the RX FIFO */
365 while (trans_cnt) {
366 u8 data;
367
368 data = cdns_spi_read(xspi, CDNS_SPI_RXD_OFFSET);
369 if (xspi->rxbuf)
370 *xspi->rxbuf++ = data;
371
372 xspi->rx_bytes--;
373 trans_cnt--;
374 }
375
376 if (xspi->tx_bytes) {
377 /* There is more data to send */
378 cdns_spi_fill_tx_fifo(xspi);
379 } else {
380 /* Transfer is completed */
381 cdns_spi_write(xspi, CDNS_SPI_IDR_OFFSET,
382 CDNS_SPI_IXR_DEFAULT_MASK);
383 spi_finalize_current_transfer(master);
384 }
385 status = IRQ_HANDLED;
386 }
387
388 return status;
389}
390static int cdns_prepare_message(struct spi_master *master,
391 struct spi_message *msg)
392{
393 cdns_spi_config_clock_mode(msg->spi);
394 return 0;
395}
396
397/**
398 * cdns_transfer_one - Initiates the SPI transfer
399 * @master: Pointer to spi_master structure
400 * @spi: Pointer to the spi_device structure
401 * @transfer: Pointer to the spi_transfer structure which provides
402 * information about next transfer parameters
403 *
404 * This function fills the TX FIFO, starts the SPI transfer and
405 * returns a positive transfer count so that core will wait for completion.
406 *
407 * Return: Number of bytes transferred in the last transfer
408 */
409static int cdns_transfer_one(struct spi_master *master,
410 struct spi_device *spi,
411 struct spi_transfer *transfer)
412{
413 struct cdns_spi *xspi = spi_master_get_devdata(master);
414
415 xspi->txbuf = transfer->tx_buf;
416 xspi->rxbuf = transfer->rx_buf;
417 xspi->tx_bytes = transfer->len;
418 xspi->rx_bytes = transfer->len;
419
420 cdns_spi_setup_transfer(spi, transfer);
421
422 cdns_spi_fill_tx_fifo(xspi);
423
424 cdns_spi_write(xspi, CDNS_SPI_IER_OFFSET,
425 CDNS_SPI_IXR_DEFAULT_MASK);
426 return transfer->len;
427}
428
429/**
430 * cdns_prepare_transfer_hardware - Prepares hardware for transfer.
431 * @master: Pointer to the spi_master structure which provides
432 * information about the controller.
433 *
434 * This function enables SPI master controller.
435 *
436 * Return: 0 always
437 */
438static int cdns_prepare_transfer_hardware(struct spi_master *master)
439{
440 struct cdns_spi *xspi = spi_master_get_devdata(master);
441
442 cdns_spi_write(xspi, CDNS_SPI_ER_OFFSET,
443 CDNS_SPI_ER_ENABLE_MASK);
444
445 return 0;
446}
447
448/**
449 * cdns_unprepare_transfer_hardware - Relaxes hardware after transfer
450 * @master: Pointer to the spi_master structure which provides
451 * information about the controller.
452 *
453 * This function disables the SPI master controller.
454 *
455 * Return: 0 always
456 */
457static int cdns_unprepare_transfer_hardware(struct spi_master *master)
458{
459 struct cdns_spi *xspi = spi_master_get_devdata(master);
460
461 cdns_spi_write(xspi, CDNS_SPI_ER_OFFSET,
462 CDNS_SPI_ER_DISABLE_MASK);
463
464 return 0;
465}
466
467/**
468 * cdns_spi_probe - Probe method for the SPI driver
469 * @pdev: Pointer to the platform_device structure
470 *
471 * This function initializes the driver data structures and the hardware.
472 *
473 * Return: 0 on success and error value on error
474 */
475static int cdns_spi_probe(struct platform_device *pdev)
476{
477 int ret = 0, irq;
478 struct spi_master *master;
479 struct cdns_spi *xspi;
480 struct resource *res;
481 u32 num_cs;
482
483 master = spi_alloc_master(&pdev->dev, sizeof(*xspi));
484 if (master == NULL)
485 return -ENOMEM;
486
487 xspi = spi_master_get_devdata(master);
488 master->dev.of_node = pdev->dev.of_node;
489 platform_set_drvdata(pdev, master);
490
491 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
492 xspi->regs = devm_ioremap_resource(&pdev->dev, res);
493 if (IS_ERR(xspi->regs)) {
494 ret = PTR_ERR(xspi->regs);
495 goto remove_master;
496 }
497
498 xspi->pclk = devm_clk_get(&pdev->dev, "pclk");
499 if (IS_ERR(xspi->pclk)) {
500 dev_err(&pdev->dev, "pclk clock not found.\n");
501 ret = PTR_ERR(xspi->pclk);
502 goto remove_master;
503 }
504
505 xspi->ref_clk = devm_clk_get(&pdev->dev, "ref_clk");
506 if (IS_ERR(xspi->ref_clk)) {
507 dev_err(&pdev->dev, "ref_clk clock not found.\n");
508 ret = PTR_ERR(xspi->ref_clk);
509 goto remove_master;
510 }
511
512 ret = clk_prepare_enable(xspi->pclk);
513 if (ret) {
514 dev_err(&pdev->dev, "Unable to enable APB clock.\n");
515 goto remove_master;
516 }
517
518 ret = clk_prepare_enable(xspi->ref_clk);
519 if (ret) {
520 dev_err(&pdev->dev, "Unable to enable device clock.\n");
521 goto clk_dis_apb;
522 }
523
524 ret = of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs);
525 if (ret < 0)
526 master->num_chipselect = CDNS_SPI_DEFAULT_NUM_CS;
527 else
528 master->num_chipselect = num_cs;
529
530 ret = of_property_read_u32(pdev->dev.of_node, "is-decoded-cs",
531 &xspi->is_decoded_cs);
532 if (ret < 0)
533 xspi->is_decoded_cs = 0;
534
535 /* SPI controller initializations */
536 cdns_spi_init_hw(xspi);
537
538 irq = platform_get_irq(pdev, 0);
539 if (irq <= 0) {
540 ret = -ENXIO;
541 dev_err(&pdev->dev, "irq number is invalid\n");
542 goto remove_master;
543 }
544
545 ret = devm_request_irq(&pdev->dev, irq, cdns_spi_irq,
546 0, pdev->name, master);
547 if (ret != 0) {
548 ret = -ENXIO;
549 dev_err(&pdev->dev, "request_irq failed\n");
550 goto remove_master;
551 }
552
553 master->prepare_transfer_hardware = cdns_prepare_transfer_hardware;
554 master->prepare_message = cdns_prepare_message;
555 master->transfer_one = cdns_transfer_one;
556 master->unprepare_transfer_hardware = cdns_unprepare_transfer_hardware;
557 master->set_cs = cdns_spi_chipselect;
558 master->mode_bits = SPI_CPOL | SPI_CPHA;
559
560 /* Set to default valid value */
561 master->max_speed_hz = clk_get_rate(xspi->ref_clk) / 4;
562 xspi->speed_hz = master->max_speed_hz;
563
564 master->bits_per_word_mask = SPI_BPW_MASK(8);
565
566 ret = spi_register_master(master);
567 if (ret) {
568 dev_err(&pdev->dev, "spi_register_master failed\n");
569 goto clk_dis_all;
570 }
571
572 return ret;
573
574clk_dis_all:
575 clk_disable_unprepare(xspi->ref_clk);
576clk_dis_apb:
577 clk_disable_unprepare(xspi->pclk);
578remove_master:
579 spi_master_put(master);
580 return ret;
581}
582
583/**
584 * cdns_spi_remove - Remove method for the SPI driver
585 * @pdev: Pointer to the platform_device structure
586 *
587 * This function is called if a device is physically removed from the system or
588 * if the driver module is being unloaded. It frees all resources allocated to
589 * the device.
590 *
591 * Return: 0 on success and error value on error
592 */
593static int cdns_spi_remove(struct platform_device *pdev)
594{
595 struct spi_master *master = platform_get_drvdata(pdev);
596 struct cdns_spi *xspi = spi_master_get_devdata(master);
597
598 cdns_spi_write(xspi, CDNS_SPI_ER_OFFSET,
599 CDNS_SPI_ER_DISABLE_MASK);
600
601 clk_disable_unprepare(xspi->ref_clk);
602 clk_disable_unprepare(xspi->pclk);
603
604 spi_unregister_master(master);
605
606 return 0;
607}
608
609/**
610 * cdns_spi_suspend - Suspend method for the SPI driver
611 * @dev: Address of the platform_device structure
612 *
613 * This function disables the SPI controller and
614 * changes the driver state to "suspend"
615 *
616 * Return: Always 0
617 */
618static int __maybe_unused cdns_spi_suspend(struct device *dev)
619{
620 struct platform_device *pdev = to_platform_device(dev);
621 struct spi_master *master = platform_get_drvdata(pdev);
622 struct cdns_spi *xspi = spi_master_get_devdata(master);
623
624 spi_master_suspend(master);
625
626 clk_disable_unprepare(xspi->ref_clk);
627
628 clk_disable_unprepare(xspi->pclk);
629
630 return 0;
631}
632
633/**
634 * cdns_spi_resume - Resume method for the SPI driver
635 * @dev: Address of the platform_device structure
636 *
637 * This function changes the driver state to "ready"
638 *
639 * Return: 0 on success and error value on error
640 */
641static int __maybe_unused cdns_spi_resume(struct device *dev)
642{
643 struct platform_device *pdev = to_platform_device(dev);
644 struct spi_master *master = platform_get_drvdata(pdev);
645 struct cdns_spi *xspi = spi_master_get_devdata(master);
646 int ret = 0;
647
648 ret = clk_prepare_enable(xspi->pclk);
649 if (ret) {
650 dev_err(dev, "Cannot enable APB clock.\n");
651 return ret;
652 }
653
654 ret = clk_prepare_enable(xspi->ref_clk);
655 if (ret) {
656 dev_err(dev, "Cannot enable device clock.\n");
657 clk_disable(xspi->pclk);
658 return ret;
659 }
660 spi_master_resume(master);
661
662 return 0;
663}
664
665static SIMPLE_DEV_PM_OPS(cdns_spi_dev_pm_ops, cdns_spi_suspend,
666 cdns_spi_resume);
667
668static const struct of_device_id cdns_spi_of_match[] = {
669 { .compatible = "xlnx,zynq-spi-r1p6" },
670 { .compatible = "cdns,spi-r1p6" },
671 { /* end of table */ }
672};
673MODULE_DEVICE_TABLE(of, cdns_spi_of_match);
674
675/* cdns_spi_driver - This structure defines the SPI subsystem platform driver */
676static struct platform_driver cdns_spi_driver = {
677 .probe = cdns_spi_probe,
678 .remove = cdns_spi_remove,
679 .driver = {
680 .name = CDNS_SPI_NAME,
681 .of_match_table = cdns_spi_of_match,
682 .pm = &cdns_spi_dev_pm_ops,
683 },
684};
685
686module_platform_driver(cdns_spi_driver);
687
688MODULE_AUTHOR("Xilinx, Inc.");
689MODULE_DESCRIPTION("Cadence SPI driver");
690MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Cadence SPI controller driver (host and target mode)
4 *
5 * Copyright (C) 2008 - 2014 Xilinx, Inc.
6 *
7 * based on Blackfin On-Chip SPI Driver (spi_bfin5xx.c)
8 */
9
10#include <linux/clk.h>
11#include <linux/delay.h>
12#include <linux/gpio/consumer.h>
13#include <linux/interrupt.h>
14#include <linux/io.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/of_irq.h>
18#include <linux/of_address.h>
19#include <linux/platform_device.h>
20#include <linux/pm_runtime.h>
21#include <linux/reset.h>
22#include <linux/spi/spi.h>
23
24/* Name of this driver */
25#define CDNS_SPI_NAME "cdns-spi"
26
27/* Register offset definitions */
28#define CDNS_SPI_CR 0x00 /* Configuration Register, RW */
29#define CDNS_SPI_ISR 0x04 /* Interrupt Status Register, RO */
30#define CDNS_SPI_IER 0x08 /* Interrupt Enable Register, WO */
31#define CDNS_SPI_IDR 0x0c /* Interrupt Disable Register, WO */
32#define CDNS_SPI_IMR 0x10 /* Interrupt Enabled Mask Register, RO */
33#define CDNS_SPI_ER 0x14 /* Enable/Disable Register, RW */
34#define CDNS_SPI_DR 0x18 /* Delay Register, RW */
35#define CDNS_SPI_TXD 0x1C /* Data Transmit Register, WO */
36#define CDNS_SPI_RXD 0x20 /* Data Receive Register, RO */
37#define CDNS_SPI_SICR 0x24 /* Slave Idle Count Register, RW */
38#define CDNS_SPI_THLD 0x28 /* Transmit FIFO Watermark Register,RW */
39
40#define SPI_AUTOSUSPEND_TIMEOUT 3000
41/*
42 * SPI Configuration Register bit Masks
43 *
44 * This register contains various control bits that affect the operation
45 * of the SPI controller
46 */
47#define CDNS_SPI_CR_MANSTRT 0x00010000 /* Manual TX Start */
48#define CDNS_SPI_CR_CPHA 0x00000004 /* Clock Phase Control */
49#define CDNS_SPI_CR_CPOL 0x00000002 /* Clock Polarity Control */
50#define CDNS_SPI_CR_SSCTRL 0x00003C00 /* Slave Select Mask */
51#define CDNS_SPI_CR_PERI_SEL 0x00000200 /* Peripheral Select Decode */
52#define CDNS_SPI_CR_BAUD_DIV 0x00000038 /* Baud Rate Divisor Mask */
53#define CDNS_SPI_CR_MSTREN 0x00000001 /* Master Enable Mask */
54#define CDNS_SPI_CR_MANSTRTEN 0x00008000 /* Manual TX Enable Mask */
55#define CDNS_SPI_CR_SSFORCE 0x00004000 /* Manual SS Enable Mask */
56#define CDNS_SPI_CR_BAUD_DIV_4 0x00000008 /* Default Baud Div Mask */
57#define CDNS_SPI_CR_DEFAULT (CDNS_SPI_CR_MSTREN | \
58 CDNS_SPI_CR_SSCTRL | \
59 CDNS_SPI_CR_SSFORCE | \
60 CDNS_SPI_CR_BAUD_DIV_4)
61
62/*
63 * SPI Configuration Register - Baud rate and target select
64 *
65 * These are the values used in the calculation of baud rate divisor and
66 * setting the target select.
67 */
68
69#define CDNS_SPI_BAUD_DIV_MAX 7 /* Baud rate divisor maximum */
70#define CDNS_SPI_BAUD_DIV_MIN 1 /* Baud rate divisor minimum */
71#define CDNS_SPI_BAUD_DIV_SHIFT 3 /* Baud rate divisor shift in CR */
72#define CDNS_SPI_SS_SHIFT 10 /* Slave Select field shift in CR */
73#define CDNS_SPI_SS0 0x1 /* Slave Select zero */
74#define CDNS_SPI_NOSS 0xF /* No Slave select */
75
76/*
77 * SPI Interrupt Registers bit Masks
78 *
79 * All the four interrupt registers (Status/Mask/Enable/Disable) have the same
80 * bit definitions.
81 */
82#define CDNS_SPI_IXR_TXOW 0x00000004 /* SPI TX FIFO Overwater */
83#define CDNS_SPI_IXR_MODF 0x00000002 /* SPI Mode Fault */
84#define CDNS_SPI_IXR_RXNEMTY 0x00000010 /* SPI RX FIFO Not Empty */
85#define CDNS_SPI_IXR_DEFAULT (CDNS_SPI_IXR_TXOW | \
86 CDNS_SPI_IXR_MODF)
87#define CDNS_SPI_IXR_TXFULL 0x00000008 /* SPI TX Full */
88#define CDNS_SPI_IXR_ALL 0x0000007F /* SPI all interrupts */
89
90/*
91 * SPI Enable Register bit Masks
92 *
93 * This register is used to enable or disable the SPI controller
94 */
95#define CDNS_SPI_ER_ENABLE 0x00000001 /* SPI Enable Bit Mask */
96#define CDNS_SPI_ER_DISABLE 0x0 /* SPI Disable Bit Mask */
97
98/* Default number of chip select lines */
99#define CDNS_SPI_DEFAULT_NUM_CS 4
100
101/**
102 * struct cdns_spi - This definition defines spi driver instance
103 * @regs: Virtual address of the SPI controller registers
104 * @ref_clk: Pointer to the peripheral clock
105 * @pclk: Pointer to the APB clock
106 * @clk_rate: Reference clock frequency, taken from @ref_clk
107 * @speed_hz: Current SPI bus clock speed in Hz
108 * @txbuf: Pointer to the TX buffer
109 * @rxbuf: Pointer to the RX buffer
110 * @tx_bytes: Number of bytes left to transfer
111 * @rx_bytes: Number of bytes requested
112 * @dev_busy: Device busy flag
113 * @is_decoded_cs: Flag for decoder property set or not
114 * @tx_fifo_depth: Depth of the TX FIFO
115 * @rstc: Optional reset control for SPI controller
116 */
117struct cdns_spi {
118 void __iomem *regs;
119 struct clk *ref_clk;
120 struct clk *pclk;
121 unsigned int clk_rate;
122 u32 speed_hz;
123 const u8 *txbuf;
124 u8 *rxbuf;
125 int tx_bytes;
126 int rx_bytes;
127 u8 dev_busy;
128 u32 is_decoded_cs;
129 unsigned int tx_fifo_depth;
130 struct reset_control *rstc;
131};
132
133/* Macros for the SPI controller read/write */
134static inline u32 cdns_spi_read(struct cdns_spi *xspi, u32 offset)
135{
136 return readl_relaxed(xspi->regs + offset);
137}
138
139static inline void cdns_spi_write(struct cdns_spi *xspi, u32 offset, u32 val)
140{
141 writel_relaxed(val, xspi->regs + offset);
142}
143
144/**
145 * cdns_spi_init_hw - Initialize the hardware and configure the SPI controller
146 * @xspi: Pointer to the cdns_spi structure
147 * @is_target: Flag to indicate target or host mode
148 * * On reset the SPI controller is configured to target or host mode.
149 * In host mode baud rate divisor is set to 4, threshold value for TX FIFO
150 * not full interrupt is set to 1 and size of the word to be transferred as 8 bit.
151 *
152 * This function initializes the SPI controller to disable and clear all the
153 * interrupts, enable manual target select and manual start, deselect all the
154 * chip select lines, and enable the SPI controller.
155 */
156static void cdns_spi_init_hw(struct cdns_spi *xspi, bool is_target)
157{
158 u32 ctrl_reg = 0;
159
160 if (!is_target)
161 ctrl_reg |= CDNS_SPI_CR_DEFAULT;
162
163 if (xspi->is_decoded_cs)
164 ctrl_reg |= CDNS_SPI_CR_PERI_SEL;
165
166 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
167 cdns_spi_write(xspi, CDNS_SPI_IDR, CDNS_SPI_IXR_ALL);
168
169 /* Clear the RX FIFO */
170 while (cdns_spi_read(xspi, CDNS_SPI_ISR) & CDNS_SPI_IXR_RXNEMTY)
171 cdns_spi_read(xspi, CDNS_SPI_RXD);
172
173 cdns_spi_write(xspi, CDNS_SPI_ISR, CDNS_SPI_IXR_ALL);
174 cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
175 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
176}
177
178/**
179 * cdns_spi_chipselect - Select or deselect the chip select line
180 * @spi: Pointer to the spi_device structure
181 * @is_high: Select(0) or deselect (1) the chip select line
182 */
183static void cdns_spi_chipselect(struct spi_device *spi, bool is_high)
184{
185 struct cdns_spi *xspi = spi_controller_get_devdata(spi->controller);
186 u32 ctrl_reg;
187
188 ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
189
190 if (is_high) {
191 /* Deselect the target */
192 ctrl_reg |= CDNS_SPI_CR_SSCTRL;
193 } else {
194 /* Select the target */
195 ctrl_reg &= ~CDNS_SPI_CR_SSCTRL;
196 if (!(xspi->is_decoded_cs))
197 ctrl_reg |= ((~(CDNS_SPI_SS0 << spi_get_chipselect(spi, 0))) <<
198 CDNS_SPI_SS_SHIFT) &
199 CDNS_SPI_CR_SSCTRL;
200 else
201 ctrl_reg |= (spi_get_chipselect(spi, 0) << CDNS_SPI_SS_SHIFT) &
202 CDNS_SPI_CR_SSCTRL;
203 }
204
205 cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
206}
207
208/**
209 * cdns_spi_config_clock_mode - Sets clock polarity and phase
210 * @spi: Pointer to the spi_device structure
211 *
212 * Sets the requested clock polarity and phase.
213 */
214static void cdns_spi_config_clock_mode(struct spi_device *spi)
215{
216 struct cdns_spi *xspi = spi_controller_get_devdata(spi->controller);
217 u32 ctrl_reg, new_ctrl_reg;
218
219 new_ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
220 ctrl_reg = new_ctrl_reg;
221
222 /* Set the SPI clock phase and clock polarity */
223 new_ctrl_reg &= ~(CDNS_SPI_CR_CPHA | CDNS_SPI_CR_CPOL);
224 if (spi->mode & SPI_CPHA)
225 new_ctrl_reg |= CDNS_SPI_CR_CPHA;
226 if (spi->mode & SPI_CPOL)
227 new_ctrl_reg |= CDNS_SPI_CR_CPOL;
228
229 if (new_ctrl_reg != ctrl_reg) {
230 /*
231 * Just writing the CR register does not seem to apply the clock
232 * setting changes. This is problematic when changing the clock
233 * polarity as it will cause the SPI target to see spurious clock
234 * transitions. To workaround the issue toggle the ER register.
235 */
236 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
237 cdns_spi_write(xspi, CDNS_SPI_CR, new_ctrl_reg);
238 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
239 }
240}
241
242/**
243 * cdns_spi_config_clock_freq - Sets clock frequency
244 * @spi: Pointer to the spi_device structure
245 * @transfer: Pointer to the spi_transfer structure which provides
246 * information about next transfer setup parameters
247 *
248 * Sets the requested clock frequency.
249 * Note: If the requested frequency is not an exact match with what can be
250 * obtained using the prescalar value the driver sets the clock frequency which
251 * is lower than the requested frequency (maximum lower) for the transfer. If
252 * the requested frequency is higher or lower than that is supported by the SPI
253 * controller the driver will set the highest or lowest frequency supported by
254 * controller.
255 */
256static void cdns_spi_config_clock_freq(struct spi_device *spi,
257 struct spi_transfer *transfer)
258{
259 struct cdns_spi *xspi = spi_controller_get_devdata(spi->controller);
260 u32 ctrl_reg, baud_rate_val;
261 unsigned long frequency;
262
263 frequency = xspi->clk_rate;
264
265 ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
266
267 /* Set the clock frequency */
268 if (xspi->speed_hz != transfer->speed_hz) {
269 /* first valid value is 1 */
270 baud_rate_val = CDNS_SPI_BAUD_DIV_MIN;
271 while ((baud_rate_val < CDNS_SPI_BAUD_DIV_MAX) &&
272 (frequency / (2 << baud_rate_val)) > transfer->speed_hz)
273 baud_rate_val++;
274
275 ctrl_reg &= ~CDNS_SPI_CR_BAUD_DIV;
276 ctrl_reg |= baud_rate_val << CDNS_SPI_BAUD_DIV_SHIFT;
277
278 xspi->speed_hz = frequency / (2 << baud_rate_val);
279 }
280 cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg);
281}
282
283/**
284 * cdns_spi_setup_transfer - Configure SPI controller for specified transfer
285 * @spi: Pointer to the spi_device structure
286 * @transfer: Pointer to the spi_transfer structure which provides
287 * information about next transfer setup parameters
288 *
289 * Sets the operational mode of SPI controller for the next SPI transfer and
290 * sets the requested clock frequency.
291 *
292 * Return: Always 0
293 */
294static int cdns_spi_setup_transfer(struct spi_device *spi,
295 struct spi_transfer *transfer)
296{
297 struct cdns_spi *xspi = spi_controller_get_devdata(spi->controller);
298
299 cdns_spi_config_clock_freq(spi, transfer);
300
301 dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u clock speed\n",
302 __func__, spi->mode, spi->bits_per_word,
303 xspi->speed_hz);
304
305 return 0;
306}
307
308/**
309 * cdns_spi_process_fifo - Fills the TX FIFO, and drain the RX FIFO
310 * @xspi: Pointer to the cdns_spi structure
311 * @ntx: Number of bytes to pack into the TX FIFO
312 * @nrx: Number of bytes to drain from the RX FIFO
313 */
314static void cdns_spi_process_fifo(struct cdns_spi *xspi, int ntx, int nrx)
315{
316 ntx = clamp(ntx, 0, xspi->tx_bytes);
317 nrx = clamp(nrx, 0, xspi->rx_bytes);
318
319 xspi->tx_bytes -= ntx;
320 xspi->rx_bytes -= nrx;
321
322 while (ntx || nrx) {
323 if (nrx) {
324 u8 data = cdns_spi_read(xspi, CDNS_SPI_RXD);
325
326 if (xspi->rxbuf)
327 *xspi->rxbuf++ = data;
328
329 nrx--;
330 }
331
332 if (ntx) {
333 if (xspi->txbuf)
334 cdns_spi_write(xspi, CDNS_SPI_TXD, *xspi->txbuf++);
335 else
336 cdns_spi_write(xspi, CDNS_SPI_TXD, 0);
337
338 ntx--;
339 }
340
341 }
342}
343
344/**
345 * cdns_spi_irq - Interrupt service routine of the SPI controller
346 * @irq: IRQ number
347 * @dev_id: Pointer to the xspi structure
348 *
349 * This function handles TX empty and Mode Fault interrupts only.
350 * On TX empty interrupt this function reads the received data from RX FIFO and
351 * fills the TX FIFO if there is any data remaining to be transferred.
352 * On Mode Fault interrupt this function indicates that transfer is completed,
353 * the SPI subsystem will identify the error as the remaining bytes to be
354 * transferred is non-zero.
355 *
356 * Return: IRQ_HANDLED when handled; IRQ_NONE otherwise.
357 */
358static irqreturn_t cdns_spi_irq(int irq, void *dev_id)
359{
360 struct spi_controller *ctlr = dev_id;
361 struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
362 irqreturn_t status;
363 u32 intr_status;
364
365 status = IRQ_NONE;
366 intr_status = cdns_spi_read(xspi, CDNS_SPI_ISR);
367 cdns_spi_write(xspi, CDNS_SPI_ISR, intr_status);
368
369 if (intr_status & CDNS_SPI_IXR_MODF) {
370 /* Indicate that transfer is completed, the SPI subsystem will
371 * identify the error as the remaining bytes to be
372 * transferred is non-zero
373 */
374 cdns_spi_write(xspi, CDNS_SPI_IDR, CDNS_SPI_IXR_DEFAULT);
375 spi_finalize_current_transfer(ctlr);
376 status = IRQ_HANDLED;
377 } else if (intr_status & CDNS_SPI_IXR_TXOW) {
378 int threshold = cdns_spi_read(xspi, CDNS_SPI_THLD);
379 int trans_cnt = xspi->rx_bytes - xspi->tx_bytes;
380
381 if (threshold > 1)
382 trans_cnt -= threshold;
383
384 /* Set threshold to one if number of pending are
385 * less than half fifo
386 */
387 if (xspi->tx_bytes < xspi->tx_fifo_depth >> 1)
388 cdns_spi_write(xspi, CDNS_SPI_THLD, 1);
389
390 if (xspi->tx_bytes) {
391 cdns_spi_process_fifo(xspi, trans_cnt, trans_cnt);
392 } else {
393 /* Fixed delay due to controller limitation with
394 * RX_NEMPTY incorrect status
395 * Xilinx AR:65885 contains more details
396 */
397 udelay(10);
398 cdns_spi_process_fifo(xspi, 0, trans_cnt);
399 cdns_spi_write(xspi, CDNS_SPI_IDR,
400 CDNS_SPI_IXR_DEFAULT);
401 spi_finalize_current_transfer(ctlr);
402 }
403 status = IRQ_HANDLED;
404 }
405
406 return status;
407}
408
409static int cdns_prepare_message(struct spi_controller *ctlr,
410 struct spi_message *msg)
411{
412 if (!spi_controller_is_target(ctlr))
413 cdns_spi_config_clock_mode(msg->spi);
414 return 0;
415}
416
417/**
418 * cdns_transfer_one - Initiates the SPI transfer
419 * @ctlr: Pointer to spi_controller structure
420 * @spi: Pointer to the spi_device structure
421 * @transfer: Pointer to the spi_transfer structure which provides
422 * information about next transfer parameters
423 *
424 * This function in host mode fills the TX FIFO, starts the SPI transfer and
425 * returns a positive transfer count so that core will wait for completion.
426 * This function in target mode fills the TX FIFO and wait for transfer trigger.
427 *
428 * Return: Number of bytes transferred in the last transfer
429 */
430static int cdns_transfer_one(struct spi_controller *ctlr,
431 struct spi_device *spi,
432 struct spi_transfer *transfer)
433{
434 struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
435
436 xspi->txbuf = transfer->tx_buf;
437 xspi->rxbuf = transfer->rx_buf;
438 xspi->tx_bytes = transfer->len;
439 xspi->rx_bytes = transfer->len;
440
441 if (!spi_controller_is_target(ctlr)) {
442 cdns_spi_setup_transfer(spi, transfer);
443 } else {
444 /* Set TX empty threshold to half of FIFO depth
445 * only if TX bytes are more than FIFO depth.
446 */
447 if (xspi->tx_bytes > xspi->tx_fifo_depth)
448 cdns_spi_write(xspi, CDNS_SPI_THLD, xspi->tx_fifo_depth >> 1);
449 }
450
451 /* When xspi in busy condition, bytes may send failed,
452 * then spi control didn't work thoroughly, add one byte delay
453 */
454 if (cdns_spi_read(xspi, CDNS_SPI_ISR) & CDNS_SPI_IXR_TXFULL)
455 udelay(10);
456
457 cdns_spi_process_fifo(xspi, xspi->tx_fifo_depth, 0);
458
459 cdns_spi_write(xspi, CDNS_SPI_IER, CDNS_SPI_IXR_DEFAULT);
460 return transfer->len;
461}
462
463/**
464 * cdns_prepare_transfer_hardware - Prepares hardware for transfer.
465 * @ctlr: Pointer to the spi_controller structure which provides
466 * information about the controller.
467 *
468 * This function enables SPI host controller.
469 *
470 * Return: 0 always
471 */
472static int cdns_prepare_transfer_hardware(struct spi_controller *ctlr)
473{
474 struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
475
476 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_ENABLE);
477
478 return 0;
479}
480
481/**
482 * cdns_unprepare_transfer_hardware - Relaxes hardware after transfer
483 * @ctlr: Pointer to the spi_controller structure which provides
484 * information about the controller.
485 *
486 * This function disables the SPI host controller when no target selected.
487 * This function flush out if any pending data in FIFO.
488 *
489 * Return: 0 always
490 */
491static int cdns_unprepare_transfer_hardware(struct spi_controller *ctlr)
492{
493 struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
494 u32 ctrl_reg;
495 unsigned int cnt = xspi->tx_fifo_depth;
496
497 if (spi_controller_is_target(ctlr)) {
498 while (cnt--)
499 cdns_spi_read(xspi, CDNS_SPI_RXD);
500 }
501
502 /* Disable the SPI if target is deselected */
503 ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
504 ctrl_reg = (ctrl_reg & CDNS_SPI_CR_SSCTRL) >> CDNS_SPI_SS_SHIFT;
505 if (ctrl_reg == CDNS_SPI_NOSS || spi_controller_is_target(ctlr))
506 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
507
508 /* Reset to default */
509 cdns_spi_write(xspi, CDNS_SPI_THLD, 0x1);
510 return 0;
511}
512
513/**
514 * cdns_spi_detect_fifo_depth - Detect the FIFO depth of the hardware
515 * @xspi: Pointer to the cdns_spi structure
516 *
517 * The depth of the TX FIFO is a synthesis configuration parameter of the SPI
518 * IP. The FIFO threshold register is sized so that its maximum value can be the
519 * FIFO size - 1. This is used to detect the size of the FIFO.
520 */
521static void cdns_spi_detect_fifo_depth(struct cdns_spi *xspi)
522{
523 /* The MSBs will get truncated giving us the size of the FIFO */
524 cdns_spi_write(xspi, CDNS_SPI_THLD, 0xffff);
525 xspi->tx_fifo_depth = cdns_spi_read(xspi, CDNS_SPI_THLD) + 1;
526
527 /* Reset to default */
528 cdns_spi_write(xspi, CDNS_SPI_THLD, 0x1);
529}
530
531/**
532 * cdns_target_abort - Abort target transfer
533 * @ctlr: Pointer to the spi_controller structure
534 *
535 * This function abort target transfer if there any transfer timeout.
536 *
537 * Return: 0 always
538 */
539static int cdns_target_abort(struct spi_controller *ctlr)
540{
541 struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
542 u32 intr_status;
543
544 intr_status = cdns_spi_read(xspi, CDNS_SPI_ISR);
545 cdns_spi_write(xspi, CDNS_SPI_ISR, intr_status);
546 cdns_spi_write(xspi, CDNS_SPI_IDR, (CDNS_SPI_IXR_MODF | CDNS_SPI_IXR_RXNEMTY));
547 spi_finalize_current_transfer(ctlr);
548
549 return 0;
550}
551
552/**
553 * cdns_spi_probe - Probe method for the SPI driver
554 * @pdev: Pointer to the platform_device structure
555 *
556 * This function initializes the driver data structures and the hardware.
557 *
558 * Return: 0 on success and error value on error
559 */
560static int cdns_spi_probe(struct platform_device *pdev)
561{
562 int ret = 0, irq;
563 struct spi_controller *ctlr;
564 struct cdns_spi *xspi;
565 u32 num_cs;
566 bool target;
567
568 target = of_property_read_bool(pdev->dev.of_node, "spi-slave");
569 if (target)
570 ctlr = spi_alloc_target(&pdev->dev, sizeof(*xspi));
571 else
572 ctlr = spi_alloc_host(&pdev->dev, sizeof(*xspi));
573
574 if (!ctlr)
575 return -ENOMEM;
576
577 xspi = spi_controller_get_devdata(ctlr);
578 ctlr->dev.of_node = pdev->dev.of_node;
579 platform_set_drvdata(pdev, ctlr);
580
581 xspi->regs = devm_platform_ioremap_resource(pdev, 0);
582 if (IS_ERR(xspi->regs)) {
583 ret = PTR_ERR(xspi->regs);
584 goto remove_ctlr;
585 }
586
587 xspi->pclk = devm_clk_get_enabled(&pdev->dev, "pclk");
588 if (IS_ERR(xspi->pclk)) {
589 dev_err(&pdev->dev, "pclk clock not found.\n");
590 ret = PTR_ERR(xspi->pclk);
591 goto remove_ctlr;
592 }
593
594 xspi->rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, "spi");
595 if (IS_ERR(xspi->rstc)) {
596 ret = dev_err_probe(&pdev->dev, PTR_ERR(xspi->rstc),
597 "Cannot get SPI reset.\n");
598 goto remove_ctlr;
599 }
600
601 reset_control_assert(xspi->rstc);
602 reset_control_deassert(xspi->rstc);
603
604 xspi->ref_clk = devm_clk_get_enabled(&pdev->dev, "ref_clk");
605 if (IS_ERR(xspi->ref_clk)) {
606 dev_err(&pdev->dev, "ref_clk clock not found.\n");
607 ret = PTR_ERR(xspi->ref_clk);
608 goto remove_ctlr;
609 }
610
611 if (!spi_controller_is_target(ctlr)) {
612 pm_runtime_use_autosuspend(&pdev->dev);
613 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
614 pm_runtime_get_noresume(&pdev->dev);
615 pm_runtime_set_active(&pdev->dev);
616 pm_runtime_enable(&pdev->dev);
617
618 ret = of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs);
619 if (ret < 0)
620 ctlr->num_chipselect = CDNS_SPI_DEFAULT_NUM_CS;
621 else
622 ctlr->num_chipselect = num_cs;
623
624 ret = of_property_read_u32(pdev->dev.of_node, "is-decoded-cs",
625 &xspi->is_decoded_cs);
626 if (ret < 0)
627 xspi->is_decoded_cs = 0;
628 }
629
630 cdns_spi_detect_fifo_depth(xspi);
631
632 /* SPI controller initializations */
633 cdns_spi_init_hw(xspi, spi_controller_is_target(ctlr));
634
635 irq = platform_get_irq(pdev, 0);
636 if (irq < 0) {
637 ret = irq;
638 goto clk_dis_all;
639 }
640
641 ret = devm_request_irq(&pdev->dev, irq, cdns_spi_irq,
642 0, pdev->name, ctlr);
643 if (ret != 0) {
644 ret = -ENXIO;
645 dev_err(&pdev->dev, "request_irq failed\n");
646 goto clk_dis_all;
647 }
648
649 ctlr->use_gpio_descriptors = true;
650 ctlr->prepare_transfer_hardware = cdns_prepare_transfer_hardware;
651 ctlr->prepare_message = cdns_prepare_message;
652 ctlr->transfer_one = cdns_transfer_one;
653 ctlr->unprepare_transfer_hardware = cdns_unprepare_transfer_hardware;
654 ctlr->mode_bits = SPI_CPOL | SPI_CPHA;
655 ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
656
657 if (!spi_controller_is_target(ctlr)) {
658 ctlr->mode_bits |= SPI_CS_HIGH;
659 ctlr->set_cs = cdns_spi_chipselect;
660 ctlr->auto_runtime_pm = true;
661 xspi->clk_rate = clk_get_rate(xspi->ref_clk);
662 /* Set to default valid value */
663 ctlr->max_speed_hz = xspi->clk_rate / 4;
664 xspi->speed_hz = ctlr->max_speed_hz;
665 pm_runtime_mark_last_busy(&pdev->dev);
666 pm_runtime_put_autosuspend(&pdev->dev);
667 } else {
668 ctlr->mode_bits |= SPI_NO_CS;
669 ctlr->target_abort = cdns_target_abort;
670 }
671 ret = spi_register_controller(ctlr);
672 if (ret) {
673 dev_err(&pdev->dev, "spi_register_controller failed\n");
674 goto clk_dis_all;
675 }
676
677 return ret;
678
679clk_dis_all:
680 if (!spi_controller_is_target(ctlr)) {
681 pm_runtime_disable(&pdev->dev);
682 pm_runtime_set_suspended(&pdev->dev);
683 }
684remove_ctlr:
685 spi_controller_put(ctlr);
686 return ret;
687}
688
689/**
690 * cdns_spi_remove - Remove method for the SPI driver
691 * @pdev: Pointer to the platform_device structure
692 *
693 * This function is called if a device is physically removed from the system or
694 * if the driver module is being unloaded. It frees all resources allocated to
695 * the device.
696 */
697static void cdns_spi_remove(struct platform_device *pdev)
698{
699 struct spi_controller *ctlr = platform_get_drvdata(pdev);
700 struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
701
702 cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
703
704 if (!spi_controller_is_target(ctlr)) {
705 pm_runtime_disable(&pdev->dev);
706 pm_runtime_set_suspended(&pdev->dev);
707 }
708
709 spi_unregister_controller(ctlr);
710}
711
712/**
713 * cdns_spi_suspend - Suspend method for the SPI driver
714 * @dev: Address of the platform_device structure
715 *
716 * This function disables the SPI controller and
717 * changes the driver state to "suspend"
718 *
719 * Return: 0 on success and error value on error
720 */
721static int __maybe_unused cdns_spi_suspend(struct device *dev)
722{
723 struct spi_controller *ctlr = dev_get_drvdata(dev);
724
725 return spi_controller_suspend(ctlr);
726}
727
728/**
729 * cdns_spi_resume - Resume method for the SPI driver
730 * @dev: Address of the platform_device structure
731 *
732 * This function changes the driver state to "ready"
733 *
734 * Return: 0 on success and error value on error
735 */
736static int __maybe_unused cdns_spi_resume(struct device *dev)
737{
738 struct spi_controller *ctlr = dev_get_drvdata(dev);
739 struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
740
741 cdns_spi_init_hw(xspi, spi_controller_is_target(ctlr));
742 return spi_controller_resume(ctlr);
743}
744
745/**
746 * cdns_spi_runtime_resume - Runtime resume method for the SPI driver
747 * @dev: Address of the platform_device structure
748 *
749 * This function enables the clocks
750 *
751 * Return: 0 on success and error value on error
752 */
753static int __maybe_unused cdns_spi_runtime_resume(struct device *dev)
754{
755 struct spi_controller *ctlr = dev_get_drvdata(dev);
756 struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
757 int ret;
758
759 ret = clk_prepare_enable(xspi->pclk);
760 if (ret) {
761 dev_err(dev, "Cannot enable APB clock.\n");
762 return ret;
763 }
764
765 ret = clk_prepare_enable(xspi->ref_clk);
766 if (ret) {
767 dev_err(dev, "Cannot enable device clock.\n");
768 clk_disable_unprepare(xspi->pclk);
769 return ret;
770 }
771 return 0;
772}
773
774/**
775 * cdns_spi_runtime_suspend - Runtime suspend method for the SPI driver
776 * @dev: Address of the platform_device structure
777 *
778 * This function disables the clocks
779 *
780 * Return: Always 0
781 */
782static int __maybe_unused cdns_spi_runtime_suspend(struct device *dev)
783{
784 struct spi_controller *ctlr = dev_get_drvdata(dev);
785 struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
786
787 clk_disable_unprepare(xspi->ref_clk);
788 clk_disable_unprepare(xspi->pclk);
789
790 return 0;
791}
792
793static const struct dev_pm_ops cdns_spi_dev_pm_ops = {
794 SET_RUNTIME_PM_OPS(cdns_spi_runtime_suspend,
795 cdns_spi_runtime_resume, NULL)
796 SET_SYSTEM_SLEEP_PM_OPS(cdns_spi_suspend, cdns_spi_resume)
797};
798
799static const struct of_device_id cdns_spi_of_match[] = {
800 { .compatible = "xlnx,zynq-spi-r1p6" },
801 { .compatible = "cdns,spi-r1p6" },
802 { /* end of table */ }
803};
804MODULE_DEVICE_TABLE(of, cdns_spi_of_match);
805
806/* cdns_spi_driver - This structure defines the SPI subsystem platform driver */
807static struct platform_driver cdns_spi_driver = {
808 .probe = cdns_spi_probe,
809 .remove = cdns_spi_remove,
810 .driver = {
811 .name = CDNS_SPI_NAME,
812 .of_match_table = cdns_spi_of_match,
813 .pm = &cdns_spi_dev_pm_ops,
814 },
815};
816
817module_platform_driver(cdns_spi_driver);
818
819MODULE_AUTHOR("Xilinx, Inc.");
820MODULE_DESCRIPTION("Cadence SPI driver");
821MODULE_LICENSE("GPL");