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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2016 Broadcom
4 */
5
6/**
7 * DOC: VC4 DSI0/DSI1 module
8 *
9 * BCM2835 contains two DSI modules, DSI0 and DSI1. DSI0 is a
10 * single-lane DSI controller, while DSI1 is a more modern 4-lane DSI
11 * controller.
12 *
13 * Most Raspberry Pi boards expose DSI1 as their "DISPLAY" connector,
14 * while the compute module brings both DSI0 and DSI1 out.
15 *
16 * This driver has been tested for DSI1 video-mode display only
17 * currently, with most of the information necessary for DSI0
18 * hopefully present.
19 */
20
21#include <linux/clk-provider.h>
22#include <linux/clk.h>
23#include <linux/completion.h>
24#include <linux/component.h>
25#include <linux/dma-mapping.h>
26#include <linux/dmaengine.h>
27#include <linux/io.h>
28#include <linux/of.h>
29#include <linux/of_address.h>
30#include <linux/platform_device.h>
31#include <linux/pm_runtime.h>
32
33#include <drm/drm_atomic_helper.h>
34#include <drm/drm_bridge.h>
35#include <drm/drm_edid.h>
36#include <drm/drm_mipi_dsi.h>
37#include <drm/drm_of.h>
38#include <drm/drm_panel.h>
39#include <drm/drm_probe_helper.h>
40#include <drm/drm_simple_kms_helper.h>
41
42#include "vc4_drv.h"
43#include "vc4_regs.h"
44
45#define DSI_CMD_FIFO_DEPTH 16
46#define DSI_PIX_FIFO_DEPTH 256
47#define DSI_PIX_FIFO_WIDTH 4
48
49#define DSI0_CTRL 0x00
50
51/* Command packet control. */
52#define DSI0_TXPKT1C 0x04 /* AKA PKTC */
53#define DSI1_TXPKT1C 0x04
54# define DSI_TXPKT1C_TRIG_CMD_MASK VC4_MASK(31, 24)
55# define DSI_TXPKT1C_TRIG_CMD_SHIFT 24
56# define DSI_TXPKT1C_CMD_REPEAT_MASK VC4_MASK(23, 10)
57# define DSI_TXPKT1C_CMD_REPEAT_SHIFT 10
58
59# define DSI_TXPKT1C_DISPLAY_NO_MASK VC4_MASK(9, 8)
60# define DSI_TXPKT1C_DISPLAY_NO_SHIFT 8
61/* Short, trigger, BTA, or a long packet that fits all in CMDFIFO. */
62# define DSI_TXPKT1C_DISPLAY_NO_SHORT 0
63/* Primary display where cmdfifo provides part of the payload and
64 * pixelvalve the rest.
65 */
66# define DSI_TXPKT1C_DISPLAY_NO_PRIMARY 1
67/* Secondary display where cmdfifo provides part of the payload and
68 * pixfifo the rest.
69 */
70# define DSI_TXPKT1C_DISPLAY_NO_SECONDARY 2
71
72# define DSI_TXPKT1C_CMD_TX_TIME_MASK VC4_MASK(7, 6)
73# define DSI_TXPKT1C_CMD_TX_TIME_SHIFT 6
74
75# define DSI_TXPKT1C_CMD_CTRL_MASK VC4_MASK(5, 4)
76# define DSI_TXPKT1C_CMD_CTRL_SHIFT 4
77/* Command only. Uses TXPKT1H and DISPLAY_NO */
78# define DSI_TXPKT1C_CMD_CTRL_TX 0
79/* Command with BTA for either ack or read data. */
80# define DSI_TXPKT1C_CMD_CTRL_RX 1
81/* Trigger according to TRIG_CMD */
82# define DSI_TXPKT1C_CMD_CTRL_TRIG 2
83/* BTA alone for getting error status after a command, or a TE trigger
84 * without a previous command.
85 */
86# define DSI_TXPKT1C_CMD_CTRL_BTA 3
87
88# define DSI_TXPKT1C_CMD_MODE_LP BIT(3)
89# define DSI_TXPKT1C_CMD_TYPE_LONG BIT(2)
90# define DSI_TXPKT1C_CMD_TE_EN BIT(1)
91# define DSI_TXPKT1C_CMD_EN BIT(0)
92
93/* Command packet header. */
94#define DSI0_TXPKT1H 0x08 /* AKA PKTH */
95#define DSI1_TXPKT1H 0x08
96# define DSI_TXPKT1H_BC_CMDFIFO_MASK VC4_MASK(31, 24)
97# define DSI_TXPKT1H_BC_CMDFIFO_SHIFT 24
98# define DSI_TXPKT1H_BC_PARAM_MASK VC4_MASK(23, 8)
99# define DSI_TXPKT1H_BC_PARAM_SHIFT 8
100# define DSI_TXPKT1H_BC_DT_MASK VC4_MASK(7, 0)
101# define DSI_TXPKT1H_BC_DT_SHIFT 0
102
103#define DSI0_RXPKT1H 0x0c /* AKA RX1_PKTH */
104#define DSI1_RXPKT1H 0x14
105# define DSI_RXPKT1H_CRC_ERR BIT(31)
106# define DSI_RXPKT1H_DET_ERR BIT(30)
107# define DSI_RXPKT1H_ECC_ERR BIT(29)
108# define DSI_RXPKT1H_COR_ERR BIT(28)
109# define DSI_RXPKT1H_INCOMP_PKT BIT(25)
110# define DSI_RXPKT1H_PKT_TYPE_LONG BIT(24)
111/* Byte count if DSI_RXPKT1H_PKT_TYPE_LONG */
112# define DSI_RXPKT1H_BC_PARAM_MASK VC4_MASK(23, 8)
113# define DSI_RXPKT1H_BC_PARAM_SHIFT 8
114/* Short return bytes if !DSI_RXPKT1H_PKT_TYPE_LONG */
115# define DSI_RXPKT1H_SHORT_1_MASK VC4_MASK(23, 16)
116# define DSI_RXPKT1H_SHORT_1_SHIFT 16
117# define DSI_RXPKT1H_SHORT_0_MASK VC4_MASK(15, 8)
118# define DSI_RXPKT1H_SHORT_0_SHIFT 8
119# define DSI_RXPKT1H_DT_LP_CMD_MASK VC4_MASK(7, 0)
120# define DSI_RXPKT1H_DT_LP_CMD_SHIFT 0
121
122#define DSI0_RXPKT2H 0x10 /* AKA RX2_PKTH */
123#define DSI1_RXPKT2H 0x18
124# define DSI_RXPKT1H_DET_ERR BIT(30)
125# define DSI_RXPKT1H_ECC_ERR BIT(29)
126# define DSI_RXPKT1H_COR_ERR BIT(28)
127# define DSI_RXPKT1H_INCOMP_PKT BIT(25)
128# define DSI_RXPKT1H_BC_PARAM_MASK VC4_MASK(23, 8)
129# define DSI_RXPKT1H_BC_PARAM_SHIFT 8
130# define DSI_RXPKT1H_DT_MASK VC4_MASK(7, 0)
131# define DSI_RXPKT1H_DT_SHIFT 0
132
133#define DSI0_TXPKT_CMD_FIFO 0x14 /* AKA CMD_DATAF */
134#define DSI1_TXPKT_CMD_FIFO 0x1c
135
136#define DSI0_DISP0_CTRL 0x18
137# define DSI_DISP0_PIX_CLK_DIV_MASK VC4_MASK(21, 13)
138# define DSI_DISP0_PIX_CLK_DIV_SHIFT 13
139# define DSI_DISP0_LP_STOP_CTRL_MASK VC4_MASK(12, 11)
140# define DSI_DISP0_LP_STOP_CTRL_SHIFT 11
141# define DSI_DISP0_LP_STOP_DISABLE 0
142# define DSI_DISP0_LP_STOP_PERLINE 1
143# define DSI_DISP0_LP_STOP_PERFRAME 2
144
145/* Transmit RGB pixels and null packets only during HACTIVE, instead
146 * of going to LP-STOP.
147 */
148# define DSI_DISP_HACTIVE_NULL BIT(10)
149/* Transmit blanking packet only during vblank, instead of allowing LP-STOP. */
150# define DSI_DISP_VBLP_CTRL BIT(9)
151/* Transmit blanking packet only during HFP, instead of allowing LP-STOP. */
152# define DSI_DISP_HFP_CTRL BIT(8)
153/* Transmit blanking packet only during HBP, instead of allowing LP-STOP. */
154# define DSI_DISP_HBP_CTRL BIT(7)
155# define DSI_DISP0_CHANNEL_MASK VC4_MASK(6, 5)
156# define DSI_DISP0_CHANNEL_SHIFT 5
157/* Enables end events for HSYNC/VSYNC, not just start events. */
158# define DSI_DISP0_ST_END BIT(4)
159# define DSI_DISP0_PFORMAT_MASK VC4_MASK(3, 2)
160# define DSI_DISP0_PFORMAT_SHIFT 2
161# define DSI_PFORMAT_RGB565 0
162# define DSI_PFORMAT_RGB666_PACKED 1
163# define DSI_PFORMAT_RGB666 2
164# define DSI_PFORMAT_RGB888 3
165/* Default is VIDEO mode. */
166# define DSI_DISP0_COMMAND_MODE BIT(1)
167# define DSI_DISP0_ENABLE BIT(0)
168
169#define DSI0_DISP1_CTRL 0x1c
170#define DSI1_DISP1_CTRL 0x2c
171/* Format of the data written to TXPKT_PIX_FIFO. */
172# define DSI_DISP1_PFORMAT_MASK VC4_MASK(2, 1)
173# define DSI_DISP1_PFORMAT_SHIFT 1
174# define DSI_DISP1_PFORMAT_16BIT 0
175# define DSI_DISP1_PFORMAT_24BIT 1
176# define DSI_DISP1_PFORMAT_32BIT_LE 2
177# define DSI_DISP1_PFORMAT_32BIT_BE 3
178
179/* DISP1 is always command mode. */
180# define DSI_DISP1_ENABLE BIT(0)
181
182#define DSI0_TXPKT_PIX_FIFO 0x20 /* AKA PIX_FIFO */
183
184#define DSI0_INT_STAT 0x24
185#define DSI0_INT_EN 0x28
186# define DSI0_INT_FIFO_ERR BIT(25)
187# define DSI0_INT_CMDC_DONE_MASK VC4_MASK(24, 23)
188# define DSI0_INT_CMDC_DONE_SHIFT 23
189# define DSI0_INT_CMDC_DONE_NO_REPEAT 1
190# define DSI0_INT_CMDC_DONE_REPEAT 3
191# define DSI0_INT_PHY_DIR_RTF BIT(22)
192# define DSI0_INT_PHY_D1_ULPS BIT(21)
193# define DSI0_INT_PHY_D1_STOP BIT(20)
194# define DSI0_INT_PHY_RXLPDT BIT(19)
195# define DSI0_INT_PHY_RXTRIG BIT(18)
196# define DSI0_INT_PHY_D0_ULPS BIT(17)
197# define DSI0_INT_PHY_D0_LPDT BIT(16)
198# define DSI0_INT_PHY_D0_FTR BIT(15)
199# define DSI0_INT_PHY_D0_STOP BIT(14)
200/* Signaled when the clock lane enters the given state. */
201# define DSI0_INT_PHY_CLK_ULPS BIT(13)
202# define DSI0_INT_PHY_CLK_HS BIT(12)
203# define DSI0_INT_PHY_CLK_FTR BIT(11)
204/* Signaled on timeouts */
205# define DSI0_INT_PR_TO BIT(10)
206# define DSI0_INT_TA_TO BIT(9)
207# define DSI0_INT_LPRX_TO BIT(8)
208# define DSI0_INT_HSTX_TO BIT(7)
209/* Contention on a line when trying to drive the line low */
210# define DSI0_INT_ERR_CONT_LP1 BIT(6)
211# define DSI0_INT_ERR_CONT_LP0 BIT(5)
212/* Control error: incorrect line state sequence on data lane 0. */
213# define DSI0_INT_ERR_CONTROL BIT(4)
214# define DSI0_INT_ERR_SYNC_ESC BIT(3)
215# define DSI0_INT_RX2_PKT BIT(2)
216# define DSI0_INT_RX1_PKT BIT(1)
217# define DSI0_INT_CMD_PKT BIT(0)
218
219#define DSI0_INTERRUPTS_ALWAYS_ENABLED (DSI0_INT_ERR_SYNC_ESC | \
220 DSI0_INT_ERR_CONTROL | \
221 DSI0_INT_ERR_CONT_LP0 | \
222 DSI0_INT_ERR_CONT_LP1 | \
223 DSI0_INT_HSTX_TO | \
224 DSI0_INT_LPRX_TO | \
225 DSI0_INT_TA_TO | \
226 DSI0_INT_PR_TO)
227
228# define DSI1_INT_PHY_D3_ULPS BIT(30)
229# define DSI1_INT_PHY_D3_STOP BIT(29)
230# define DSI1_INT_PHY_D2_ULPS BIT(28)
231# define DSI1_INT_PHY_D2_STOP BIT(27)
232# define DSI1_INT_PHY_D1_ULPS BIT(26)
233# define DSI1_INT_PHY_D1_STOP BIT(25)
234# define DSI1_INT_PHY_D0_ULPS BIT(24)
235# define DSI1_INT_PHY_D0_STOP BIT(23)
236# define DSI1_INT_FIFO_ERR BIT(22)
237# define DSI1_INT_PHY_DIR_RTF BIT(21)
238# define DSI1_INT_PHY_RXLPDT BIT(20)
239# define DSI1_INT_PHY_RXTRIG BIT(19)
240# define DSI1_INT_PHY_D0_LPDT BIT(18)
241# define DSI1_INT_PHY_DIR_FTR BIT(17)
242
243/* Signaled when the clock lane enters the given state. */
244# define DSI1_INT_PHY_CLOCK_ULPS BIT(16)
245# define DSI1_INT_PHY_CLOCK_HS BIT(15)
246# define DSI1_INT_PHY_CLOCK_STOP BIT(14)
247
248/* Signaled on timeouts */
249# define DSI1_INT_PR_TO BIT(13)
250# define DSI1_INT_TA_TO BIT(12)
251# define DSI1_INT_LPRX_TO BIT(11)
252# define DSI1_INT_HSTX_TO BIT(10)
253
254/* Contention on a line when trying to drive the line low */
255# define DSI1_INT_ERR_CONT_LP1 BIT(9)
256# define DSI1_INT_ERR_CONT_LP0 BIT(8)
257
258/* Control error: incorrect line state sequence on data lane 0. */
259# define DSI1_INT_ERR_CONTROL BIT(7)
260/* LPDT synchronization error (bits received not a multiple of 8. */
261
262# define DSI1_INT_ERR_SYNC_ESC BIT(6)
263/* Signaled after receiving an error packet from the display in
264 * response to a read.
265 */
266# define DSI1_INT_RXPKT2 BIT(5)
267/* Signaled after receiving a packet. The header and optional short
268 * response will be in RXPKT1H, and a long response will be in the
269 * RXPKT_FIFO.
270 */
271# define DSI1_INT_RXPKT1 BIT(4)
272# define DSI1_INT_TXPKT2_DONE BIT(3)
273# define DSI1_INT_TXPKT2_END BIT(2)
274/* Signaled after all repeats of TXPKT1 are transferred. */
275# define DSI1_INT_TXPKT1_DONE BIT(1)
276/* Signaled after each TXPKT1 repeat is scheduled. */
277# define DSI1_INT_TXPKT1_END BIT(0)
278
279#define DSI1_INTERRUPTS_ALWAYS_ENABLED (DSI1_INT_ERR_SYNC_ESC | \
280 DSI1_INT_ERR_CONTROL | \
281 DSI1_INT_ERR_CONT_LP0 | \
282 DSI1_INT_ERR_CONT_LP1 | \
283 DSI1_INT_HSTX_TO | \
284 DSI1_INT_LPRX_TO | \
285 DSI1_INT_TA_TO | \
286 DSI1_INT_PR_TO)
287
288#define DSI0_STAT 0x2c
289#define DSI0_HSTX_TO_CNT 0x30
290#define DSI0_LPRX_TO_CNT 0x34
291#define DSI0_TA_TO_CNT 0x38
292#define DSI0_PR_TO_CNT 0x3c
293#define DSI0_PHYC 0x40
294# define DSI1_PHYC_ESC_CLK_LPDT_MASK VC4_MASK(25, 20)
295# define DSI1_PHYC_ESC_CLK_LPDT_SHIFT 20
296# define DSI1_PHYC_HS_CLK_CONTINUOUS BIT(18)
297# define DSI0_PHYC_ESC_CLK_LPDT_MASK VC4_MASK(17, 12)
298# define DSI0_PHYC_ESC_CLK_LPDT_SHIFT 12
299# define DSI1_PHYC_CLANE_ULPS BIT(17)
300# define DSI1_PHYC_CLANE_ENABLE BIT(16)
301# define DSI_PHYC_DLANE3_ULPS BIT(13)
302# define DSI_PHYC_DLANE3_ENABLE BIT(12)
303# define DSI0_PHYC_HS_CLK_CONTINUOUS BIT(10)
304# define DSI0_PHYC_CLANE_ULPS BIT(9)
305# define DSI_PHYC_DLANE2_ULPS BIT(9)
306# define DSI0_PHYC_CLANE_ENABLE BIT(8)
307# define DSI_PHYC_DLANE2_ENABLE BIT(8)
308# define DSI_PHYC_DLANE1_ULPS BIT(5)
309# define DSI_PHYC_DLANE1_ENABLE BIT(4)
310# define DSI_PHYC_DLANE0_FORCE_STOP BIT(2)
311# define DSI_PHYC_DLANE0_ULPS BIT(1)
312# define DSI_PHYC_DLANE0_ENABLE BIT(0)
313
314#define DSI0_HS_CLT0 0x44
315#define DSI0_HS_CLT1 0x48
316#define DSI0_HS_CLT2 0x4c
317#define DSI0_HS_DLT3 0x50
318#define DSI0_HS_DLT4 0x54
319#define DSI0_HS_DLT5 0x58
320#define DSI0_HS_DLT6 0x5c
321#define DSI0_HS_DLT7 0x60
322
323#define DSI0_PHY_AFEC0 0x64
324# define DSI0_PHY_AFEC0_DDR2CLK_EN BIT(26)
325# define DSI0_PHY_AFEC0_DDRCLK_EN BIT(25)
326# define DSI0_PHY_AFEC0_LATCH_ULPS BIT(24)
327# define DSI1_PHY_AFEC0_IDR_DLANE3_MASK VC4_MASK(31, 29)
328# define DSI1_PHY_AFEC0_IDR_DLANE3_SHIFT 29
329# define DSI1_PHY_AFEC0_IDR_DLANE2_MASK VC4_MASK(28, 26)
330# define DSI1_PHY_AFEC0_IDR_DLANE2_SHIFT 26
331# define DSI1_PHY_AFEC0_IDR_DLANE1_MASK VC4_MASK(27, 23)
332# define DSI1_PHY_AFEC0_IDR_DLANE1_SHIFT 23
333# define DSI1_PHY_AFEC0_IDR_DLANE0_MASK VC4_MASK(22, 20)
334# define DSI1_PHY_AFEC0_IDR_DLANE0_SHIFT 20
335# define DSI1_PHY_AFEC0_IDR_CLANE_MASK VC4_MASK(19, 17)
336# define DSI1_PHY_AFEC0_IDR_CLANE_SHIFT 17
337# define DSI0_PHY_AFEC0_ACTRL_DLANE1_MASK VC4_MASK(23, 20)
338# define DSI0_PHY_AFEC0_ACTRL_DLANE1_SHIFT 20
339# define DSI0_PHY_AFEC0_ACTRL_DLANE0_MASK VC4_MASK(19, 16)
340# define DSI0_PHY_AFEC0_ACTRL_DLANE0_SHIFT 16
341# define DSI0_PHY_AFEC0_ACTRL_CLANE_MASK VC4_MASK(15, 12)
342# define DSI0_PHY_AFEC0_ACTRL_CLANE_SHIFT 12
343# define DSI1_PHY_AFEC0_DDR2CLK_EN BIT(16)
344# define DSI1_PHY_AFEC0_DDRCLK_EN BIT(15)
345# define DSI1_PHY_AFEC0_LATCH_ULPS BIT(14)
346# define DSI1_PHY_AFEC0_RESET BIT(13)
347# define DSI1_PHY_AFEC0_PD BIT(12)
348# define DSI0_PHY_AFEC0_RESET BIT(11)
349# define DSI1_PHY_AFEC0_PD_BG BIT(11)
350# define DSI0_PHY_AFEC0_PD BIT(10)
351# define DSI1_PHY_AFEC0_PD_DLANE1 BIT(10)
352# define DSI0_PHY_AFEC0_PD_BG BIT(9)
353# define DSI1_PHY_AFEC0_PD_DLANE2 BIT(9)
354# define DSI0_PHY_AFEC0_PD_DLANE1 BIT(8)
355# define DSI1_PHY_AFEC0_PD_DLANE3 BIT(8)
356# define DSI_PHY_AFEC0_PTATADJ_MASK VC4_MASK(7, 4)
357# define DSI_PHY_AFEC0_PTATADJ_SHIFT 4
358# define DSI_PHY_AFEC0_CTATADJ_MASK VC4_MASK(3, 0)
359# define DSI_PHY_AFEC0_CTATADJ_SHIFT 0
360
361#define DSI0_PHY_AFEC1 0x68
362# define DSI0_PHY_AFEC1_IDR_DLANE1_MASK VC4_MASK(10, 8)
363# define DSI0_PHY_AFEC1_IDR_DLANE1_SHIFT 8
364# define DSI0_PHY_AFEC1_IDR_DLANE0_MASK VC4_MASK(6, 4)
365# define DSI0_PHY_AFEC1_IDR_DLANE0_SHIFT 4
366# define DSI0_PHY_AFEC1_IDR_CLANE_MASK VC4_MASK(2, 0)
367# define DSI0_PHY_AFEC1_IDR_CLANE_SHIFT 0
368
369#define DSI0_TST_SEL 0x6c
370#define DSI0_TST_MON 0x70
371#define DSI0_ID 0x74
372# define DSI_ID_VALUE 0x00647369
373
374#define DSI1_CTRL 0x00
375# define DSI_CTRL_HS_CLKC_MASK VC4_MASK(15, 14)
376# define DSI_CTRL_HS_CLKC_SHIFT 14
377# define DSI_CTRL_HS_CLKC_BYTE 0
378# define DSI_CTRL_HS_CLKC_DDR2 1
379# define DSI_CTRL_HS_CLKC_DDR 2
380
381# define DSI_CTRL_RX_LPDT_EOT_DISABLE BIT(13)
382# define DSI_CTRL_LPDT_EOT_DISABLE BIT(12)
383# define DSI_CTRL_HSDT_EOT_DISABLE BIT(11)
384# define DSI_CTRL_SOFT_RESET_CFG BIT(10)
385# define DSI_CTRL_CAL_BYTE BIT(9)
386# define DSI_CTRL_INV_BYTE BIT(8)
387# define DSI_CTRL_CLR_LDF BIT(7)
388# define DSI0_CTRL_CLR_PBCF BIT(6)
389# define DSI1_CTRL_CLR_RXF BIT(6)
390# define DSI0_CTRL_CLR_CPBCF BIT(5)
391# define DSI1_CTRL_CLR_PDF BIT(5)
392# define DSI0_CTRL_CLR_PDF BIT(4)
393# define DSI1_CTRL_CLR_CDF BIT(4)
394# define DSI0_CTRL_CLR_CDF BIT(3)
395# define DSI0_CTRL_CTRL2 BIT(2)
396# define DSI1_CTRL_DISABLE_DISP_CRCC BIT(2)
397# define DSI0_CTRL_CTRL1 BIT(1)
398# define DSI1_CTRL_DISABLE_DISP_ECCC BIT(1)
399# define DSI0_CTRL_CTRL0 BIT(0)
400# define DSI1_CTRL_EN BIT(0)
401# define DSI0_CTRL_RESET_FIFOS (DSI_CTRL_CLR_LDF | \
402 DSI0_CTRL_CLR_PBCF | \
403 DSI0_CTRL_CLR_CPBCF | \
404 DSI0_CTRL_CLR_PDF | \
405 DSI0_CTRL_CLR_CDF)
406# define DSI1_CTRL_RESET_FIFOS (DSI_CTRL_CLR_LDF | \
407 DSI1_CTRL_CLR_RXF | \
408 DSI1_CTRL_CLR_PDF | \
409 DSI1_CTRL_CLR_CDF)
410
411#define DSI1_TXPKT2C 0x0c
412#define DSI1_TXPKT2H 0x10
413#define DSI1_TXPKT_PIX_FIFO 0x20
414#define DSI1_RXPKT_FIFO 0x24
415#define DSI1_DISP0_CTRL 0x28
416#define DSI1_INT_STAT 0x30
417#define DSI1_INT_EN 0x34
418/* State reporting bits. These mostly behave like INT_STAT, where
419 * writing a 1 clears the bit.
420 */
421#define DSI1_STAT 0x38
422# define DSI1_STAT_PHY_D3_ULPS BIT(31)
423# define DSI1_STAT_PHY_D3_STOP BIT(30)
424# define DSI1_STAT_PHY_D2_ULPS BIT(29)
425# define DSI1_STAT_PHY_D2_STOP BIT(28)
426# define DSI1_STAT_PHY_D1_ULPS BIT(27)
427# define DSI1_STAT_PHY_D1_STOP BIT(26)
428# define DSI1_STAT_PHY_D0_ULPS BIT(25)
429# define DSI1_STAT_PHY_D0_STOP BIT(24)
430# define DSI1_STAT_FIFO_ERR BIT(23)
431# define DSI1_STAT_PHY_RXLPDT BIT(22)
432# define DSI1_STAT_PHY_RXTRIG BIT(21)
433# define DSI1_STAT_PHY_D0_LPDT BIT(20)
434/* Set when in forward direction */
435# define DSI1_STAT_PHY_DIR BIT(19)
436# define DSI1_STAT_PHY_CLOCK_ULPS BIT(18)
437# define DSI1_STAT_PHY_CLOCK_HS BIT(17)
438# define DSI1_STAT_PHY_CLOCK_STOP BIT(16)
439# define DSI1_STAT_PR_TO BIT(15)
440# define DSI1_STAT_TA_TO BIT(14)
441# define DSI1_STAT_LPRX_TO BIT(13)
442# define DSI1_STAT_HSTX_TO BIT(12)
443# define DSI1_STAT_ERR_CONT_LP1 BIT(11)
444# define DSI1_STAT_ERR_CONT_LP0 BIT(10)
445# define DSI1_STAT_ERR_CONTROL BIT(9)
446# define DSI1_STAT_ERR_SYNC_ESC BIT(8)
447# define DSI1_STAT_RXPKT2 BIT(7)
448# define DSI1_STAT_RXPKT1 BIT(6)
449# define DSI1_STAT_TXPKT2_BUSY BIT(5)
450# define DSI1_STAT_TXPKT2_DONE BIT(4)
451# define DSI1_STAT_TXPKT2_END BIT(3)
452# define DSI1_STAT_TXPKT1_BUSY BIT(2)
453# define DSI1_STAT_TXPKT1_DONE BIT(1)
454# define DSI1_STAT_TXPKT1_END BIT(0)
455
456#define DSI1_HSTX_TO_CNT 0x3c
457#define DSI1_LPRX_TO_CNT 0x40
458#define DSI1_TA_TO_CNT 0x44
459#define DSI1_PR_TO_CNT 0x48
460#define DSI1_PHYC 0x4c
461
462#define DSI1_HS_CLT0 0x50
463# define DSI_HS_CLT0_CZERO_MASK VC4_MASK(26, 18)
464# define DSI_HS_CLT0_CZERO_SHIFT 18
465# define DSI_HS_CLT0_CPRE_MASK VC4_MASK(17, 9)
466# define DSI_HS_CLT0_CPRE_SHIFT 9
467# define DSI_HS_CLT0_CPREP_MASK VC4_MASK(8, 0)
468# define DSI_HS_CLT0_CPREP_SHIFT 0
469
470#define DSI1_HS_CLT1 0x54
471# define DSI_HS_CLT1_CTRAIL_MASK VC4_MASK(17, 9)
472# define DSI_HS_CLT1_CTRAIL_SHIFT 9
473# define DSI_HS_CLT1_CPOST_MASK VC4_MASK(8, 0)
474# define DSI_HS_CLT1_CPOST_SHIFT 0
475
476#define DSI1_HS_CLT2 0x58
477# define DSI_HS_CLT2_WUP_MASK VC4_MASK(23, 0)
478# define DSI_HS_CLT2_WUP_SHIFT 0
479
480#define DSI1_HS_DLT3 0x5c
481# define DSI_HS_DLT3_EXIT_MASK VC4_MASK(26, 18)
482# define DSI_HS_DLT3_EXIT_SHIFT 18
483# define DSI_HS_DLT3_ZERO_MASK VC4_MASK(17, 9)
484# define DSI_HS_DLT3_ZERO_SHIFT 9
485# define DSI_HS_DLT3_PRE_MASK VC4_MASK(8, 0)
486# define DSI_HS_DLT3_PRE_SHIFT 0
487
488#define DSI1_HS_DLT4 0x60
489# define DSI_HS_DLT4_ANLAT_MASK VC4_MASK(22, 18)
490# define DSI_HS_DLT4_ANLAT_SHIFT 18
491# define DSI_HS_DLT4_TRAIL_MASK VC4_MASK(17, 9)
492# define DSI_HS_DLT4_TRAIL_SHIFT 9
493# define DSI_HS_DLT4_LPX_MASK VC4_MASK(8, 0)
494# define DSI_HS_DLT4_LPX_SHIFT 0
495
496#define DSI1_HS_DLT5 0x64
497# define DSI_HS_DLT5_INIT_MASK VC4_MASK(23, 0)
498# define DSI_HS_DLT5_INIT_SHIFT 0
499
500#define DSI1_HS_DLT6 0x68
501# define DSI_HS_DLT6_TA_GET_MASK VC4_MASK(31, 24)
502# define DSI_HS_DLT6_TA_GET_SHIFT 24
503# define DSI_HS_DLT6_TA_SURE_MASK VC4_MASK(23, 16)
504# define DSI_HS_DLT6_TA_SURE_SHIFT 16
505# define DSI_HS_DLT6_TA_GO_MASK VC4_MASK(15, 8)
506# define DSI_HS_DLT6_TA_GO_SHIFT 8
507# define DSI_HS_DLT6_LP_LPX_MASK VC4_MASK(7, 0)
508# define DSI_HS_DLT6_LP_LPX_SHIFT 0
509
510#define DSI1_HS_DLT7 0x6c
511# define DSI_HS_DLT7_LP_WUP_MASK VC4_MASK(23, 0)
512# define DSI_HS_DLT7_LP_WUP_SHIFT 0
513
514#define DSI1_PHY_AFEC0 0x70
515
516#define DSI1_PHY_AFEC1 0x74
517# define DSI1_PHY_AFEC1_ACTRL_DLANE3_MASK VC4_MASK(19, 16)
518# define DSI1_PHY_AFEC1_ACTRL_DLANE3_SHIFT 16
519# define DSI1_PHY_AFEC1_ACTRL_DLANE2_MASK VC4_MASK(15, 12)
520# define DSI1_PHY_AFEC1_ACTRL_DLANE2_SHIFT 12
521# define DSI1_PHY_AFEC1_ACTRL_DLANE1_MASK VC4_MASK(11, 8)
522# define DSI1_PHY_AFEC1_ACTRL_DLANE1_SHIFT 8
523# define DSI1_PHY_AFEC1_ACTRL_DLANE0_MASK VC4_MASK(7, 4)
524# define DSI1_PHY_AFEC1_ACTRL_DLANE0_SHIFT 4
525# define DSI1_PHY_AFEC1_ACTRL_CLANE_MASK VC4_MASK(3, 0)
526# define DSI1_PHY_AFEC1_ACTRL_CLANE_SHIFT 0
527
528#define DSI1_TST_SEL 0x78
529#define DSI1_TST_MON 0x7c
530#define DSI1_PHY_TST1 0x80
531#define DSI1_PHY_TST2 0x84
532#define DSI1_PHY_FIFO_STAT 0x88
533/* Actually, all registers in the range that aren't otherwise claimed
534 * will return the ID.
535 */
536#define DSI1_ID 0x8c
537
538struct vc4_dsi_variant {
539 /* Whether we're on bcm2835's DSI0 or DSI1. */
540 unsigned int port;
541
542 bool broken_axi_workaround;
543
544 const char *debugfs_name;
545 const struct debugfs_reg32 *regs;
546 size_t nregs;
547
548};
549
550/* General DSI hardware state. */
551struct vc4_dsi {
552 struct vc4_encoder encoder;
553 struct mipi_dsi_host dsi_host;
554
555 struct kref kref;
556
557 struct platform_device *pdev;
558
559 struct drm_bridge *out_bridge;
560 struct drm_bridge bridge;
561
562 void __iomem *regs;
563
564 struct dma_chan *reg_dma_chan;
565 dma_addr_t reg_dma_paddr;
566 u32 *reg_dma_mem;
567 dma_addr_t reg_paddr;
568
569 const struct vc4_dsi_variant *variant;
570
571 /* DSI channel for the panel we're connected to. */
572 u32 channel;
573 u32 lanes;
574 u32 format;
575 u32 divider;
576 u32 mode_flags;
577
578 /* Input clock from CPRMAN to the digital PHY, for the DSI
579 * escape clock.
580 */
581 struct clk *escape_clock;
582
583 /* Input clock to the analog PHY, used to generate the DSI bit
584 * clock.
585 */
586 struct clk *pll_phy_clock;
587
588 /* HS Clocks generated within the DSI analog PHY. */
589 struct clk_fixed_factor phy_clocks[3];
590
591 struct clk_hw_onecell_data *clk_onecell;
592
593 /* Pixel clock output to the pixelvalve, generated from the HS
594 * clock.
595 */
596 struct clk *pixel_clock;
597
598 struct completion xfer_completion;
599 int xfer_result;
600
601 struct debugfs_regset32 regset;
602};
603
604#define host_to_dsi(host) \
605 container_of_const(host, struct vc4_dsi, dsi_host)
606
607#define to_vc4_dsi(_encoder) \
608 container_of_const(_encoder, struct vc4_dsi, encoder.base)
609
610#define bridge_to_vc4_dsi(_bridge) \
611 container_of_const(_bridge, struct vc4_dsi, bridge)
612
613static inline void
614dsi_dma_workaround_write(struct vc4_dsi *dsi, u32 offset, u32 val)
615{
616 struct drm_device *drm = dsi->bridge.dev;
617 struct dma_chan *chan = dsi->reg_dma_chan;
618 struct dma_async_tx_descriptor *tx;
619 dma_cookie_t cookie;
620 int ret;
621
622 kunit_fail_current_test("Accessing a register in a unit test!\n");
623
624 /* DSI0 should be able to write normally. */
625 if (!chan) {
626 writel(val, dsi->regs + offset);
627 return;
628 }
629
630 *dsi->reg_dma_mem = val;
631
632 tx = chan->device->device_prep_dma_memcpy(chan,
633 dsi->reg_paddr + offset,
634 dsi->reg_dma_paddr,
635 4, 0);
636 if (!tx) {
637 drm_err(drm, "Failed to set up DMA register write\n");
638 return;
639 }
640
641 cookie = tx->tx_submit(tx);
642 ret = dma_submit_error(cookie);
643 if (ret) {
644 drm_err(drm, "Failed to submit DMA: %d\n", ret);
645 return;
646 }
647 ret = dma_sync_wait(chan, cookie);
648 if (ret)
649 drm_err(drm, "Failed to wait for DMA: %d\n", ret);
650}
651
652#define DSI_READ(offset) \
653 ({ \
654 kunit_fail_current_test("Accessing a register in a unit test!\n"); \
655 readl(dsi->regs + (offset)); \
656 })
657
658#define DSI_WRITE(offset, val) dsi_dma_workaround_write(dsi, offset, val)
659#define DSI_PORT_READ(offset) \
660 DSI_READ(dsi->variant->port ? DSI1_##offset : DSI0_##offset)
661#define DSI_PORT_WRITE(offset, val) \
662 DSI_WRITE(dsi->variant->port ? DSI1_##offset : DSI0_##offset, val)
663#define DSI_PORT_BIT(bit) (dsi->variant->port ? DSI1_##bit : DSI0_##bit)
664
665static const struct debugfs_reg32 dsi0_regs[] = {
666 VC4_REG32(DSI0_CTRL),
667 VC4_REG32(DSI0_STAT),
668 VC4_REG32(DSI0_HSTX_TO_CNT),
669 VC4_REG32(DSI0_LPRX_TO_CNT),
670 VC4_REG32(DSI0_TA_TO_CNT),
671 VC4_REG32(DSI0_PR_TO_CNT),
672 VC4_REG32(DSI0_DISP0_CTRL),
673 VC4_REG32(DSI0_DISP1_CTRL),
674 VC4_REG32(DSI0_INT_STAT),
675 VC4_REG32(DSI0_INT_EN),
676 VC4_REG32(DSI0_PHYC),
677 VC4_REG32(DSI0_HS_CLT0),
678 VC4_REG32(DSI0_HS_CLT1),
679 VC4_REG32(DSI0_HS_CLT2),
680 VC4_REG32(DSI0_HS_DLT3),
681 VC4_REG32(DSI0_HS_DLT4),
682 VC4_REG32(DSI0_HS_DLT5),
683 VC4_REG32(DSI0_HS_DLT6),
684 VC4_REG32(DSI0_HS_DLT7),
685 VC4_REG32(DSI0_PHY_AFEC0),
686 VC4_REG32(DSI0_PHY_AFEC1),
687 VC4_REG32(DSI0_ID),
688};
689
690static const struct debugfs_reg32 dsi1_regs[] = {
691 VC4_REG32(DSI1_CTRL),
692 VC4_REG32(DSI1_STAT),
693 VC4_REG32(DSI1_HSTX_TO_CNT),
694 VC4_REG32(DSI1_LPRX_TO_CNT),
695 VC4_REG32(DSI1_TA_TO_CNT),
696 VC4_REG32(DSI1_PR_TO_CNT),
697 VC4_REG32(DSI1_DISP0_CTRL),
698 VC4_REG32(DSI1_DISP1_CTRL),
699 VC4_REG32(DSI1_INT_STAT),
700 VC4_REG32(DSI1_INT_EN),
701 VC4_REG32(DSI1_PHYC),
702 VC4_REG32(DSI1_HS_CLT0),
703 VC4_REG32(DSI1_HS_CLT1),
704 VC4_REG32(DSI1_HS_CLT2),
705 VC4_REG32(DSI1_HS_DLT3),
706 VC4_REG32(DSI1_HS_DLT4),
707 VC4_REG32(DSI1_HS_DLT5),
708 VC4_REG32(DSI1_HS_DLT6),
709 VC4_REG32(DSI1_HS_DLT7),
710 VC4_REG32(DSI1_PHY_AFEC0),
711 VC4_REG32(DSI1_PHY_AFEC1),
712 VC4_REG32(DSI1_ID),
713};
714
715static void vc4_dsi_latch_ulps(struct vc4_dsi *dsi, bool latch)
716{
717 u32 afec0 = DSI_PORT_READ(PHY_AFEC0);
718
719 if (latch)
720 afec0 |= DSI_PORT_BIT(PHY_AFEC0_LATCH_ULPS);
721 else
722 afec0 &= ~DSI_PORT_BIT(PHY_AFEC0_LATCH_ULPS);
723
724 DSI_PORT_WRITE(PHY_AFEC0, afec0);
725}
726
727/* Enters or exits Ultra Low Power State. */
728static void vc4_dsi_ulps(struct vc4_dsi *dsi, bool ulps)
729{
730 bool non_continuous = dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS;
731 u32 phyc_ulps = ((non_continuous ? DSI_PORT_BIT(PHYC_CLANE_ULPS) : 0) |
732 DSI_PHYC_DLANE0_ULPS |
733 (dsi->lanes > 1 ? DSI_PHYC_DLANE1_ULPS : 0) |
734 (dsi->lanes > 2 ? DSI_PHYC_DLANE2_ULPS : 0) |
735 (dsi->lanes > 3 ? DSI_PHYC_DLANE3_ULPS : 0));
736 u32 stat_ulps = ((non_continuous ? DSI1_STAT_PHY_CLOCK_ULPS : 0) |
737 DSI1_STAT_PHY_D0_ULPS |
738 (dsi->lanes > 1 ? DSI1_STAT_PHY_D1_ULPS : 0) |
739 (dsi->lanes > 2 ? DSI1_STAT_PHY_D2_ULPS : 0) |
740 (dsi->lanes > 3 ? DSI1_STAT_PHY_D3_ULPS : 0));
741 u32 stat_stop = ((non_continuous ? DSI1_STAT_PHY_CLOCK_STOP : 0) |
742 DSI1_STAT_PHY_D0_STOP |
743 (dsi->lanes > 1 ? DSI1_STAT_PHY_D1_STOP : 0) |
744 (dsi->lanes > 2 ? DSI1_STAT_PHY_D2_STOP : 0) |
745 (dsi->lanes > 3 ? DSI1_STAT_PHY_D3_STOP : 0));
746 int ret;
747 bool ulps_currently_enabled = (DSI_PORT_READ(PHY_AFEC0) &
748 DSI_PORT_BIT(PHY_AFEC0_LATCH_ULPS));
749
750 if (ulps == ulps_currently_enabled)
751 return;
752
753 DSI_PORT_WRITE(STAT, stat_ulps);
754 DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) | phyc_ulps);
755 ret = wait_for((DSI_PORT_READ(STAT) & stat_ulps) == stat_ulps, 200);
756 if (ret) {
757 dev_warn(&dsi->pdev->dev,
758 "Timeout waiting for DSI ULPS entry: STAT 0x%08x",
759 DSI_PORT_READ(STAT));
760 DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) & ~phyc_ulps);
761 vc4_dsi_latch_ulps(dsi, false);
762 return;
763 }
764
765 /* The DSI module can't be disabled while the module is
766 * generating ULPS state. So, to be able to disable the
767 * module, we have the AFE latch the ULPS state and continue
768 * on to having the module enter STOP.
769 */
770 vc4_dsi_latch_ulps(dsi, ulps);
771
772 DSI_PORT_WRITE(STAT, stat_stop);
773 DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) & ~phyc_ulps);
774 ret = wait_for((DSI_PORT_READ(STAT) & stat_stop) == stat_stop, 200);
775 if (ret) {
776 dev_warn(&dsi->pdev->dev,
777 "Timeout waiting for DSI STOP entry: STAT 0x%08x",
778 DSI_PORT_READ(STAT));
779 DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) & ~phyc_ulps);
780 return;
781 }
782}
783
784static u32
785dsi_hs_timing(u32 ui_ns, u32 ns, u32 ui)
786{
787 /* The HS timings have to be rounded up to a multiple of 8
788 * because we're using the byte clock.
789 */
790 return roundup(ui + DIV_ROUND_UP(ns, ui_ns), 8);
791}
792
793/* ESC always runs at 100Mhz. */
794#define ESC_TIME_NS 10
795
796static u32
797dsi_esc_timing(u32 ns)
798{
799 return DIV_ROUND_UP(ns, ESC_TIME_NS);
800}
801
802static void vc4_dsi_bridge_disable(struct drm_bridge *bridge,
803 struct drm_bridge_state *state)
804{
805 struct vc4_dsi *dsi = bridge_to_vc4_dsi(bridge);
806 u32 disp0_ctrl;
807
808 disp0_ctrl = DSI_PORT_READ(DISP0_CTRL);
809 disp0_ctrl &= ~DSI_DISP0_ENABLE;
810 DSI_PORT_WRITE(DISP0_CTRL, disp0_ctrl);
811}
812
813static void vc4_dsi_bridge_post_disable(struct drm_bridge *bridge,
814 struct drm_bridge_state *state)
815{
816 struct vc4_dsi *dsi = bridge_to_vc4_dsi(bridge);
817 struct device *dev = &dsi->pdev->dev;
818
819 clk_disable_unprepare(dsi->pll_phy_clock);
820 clk_disable_unprepare(dsi->escape_clock);
821 clk_disable_unprepare(dsi->pixel_clock);
822
823 pm_runtime_put(dev);
824}
825
826/* Extends the mode's blank intervals to handle BCM2835's integer-only
827 * DSI PLL divider.
828 *
829 * On 2835, PLLD is set to 2Ghz, and may not be changed by the display
830 * driver since most peripherals are hanging off of the PLLD_PER
831 * divider. PLLD_DSI1, which drives our DSI bit clock (and therefore
832 * the pixel clock), only has an integer divider off of DSI.
833 *
834 * To get our panel mode to refresh at the expected 60Hz, we need to
835 * extend the horizontal blank time. This means we drive a
836 * higher-than-expected clock rate to the panel, but that's what the
837 * firmware does too.
838 */
839static bool vc4_dsi_bridge_mode_fixup(struct drm_bridge *bridge,
840 const struct drm_display_mode *mode,
841 struct drm_display_mode *adjusted_mode)
842{
843 struct vc4_dsi *dsi = bridge_to_vc4_dsi(bridge);
844 struct clk *phy_parent = clk_get_parent(dsi->pll_phy_clock);
845 unsigned long parent_rate = clk_get_rate(phy_parent);
846 unsigned long pixel_clock_hz = mode->clock * 1000;
847 unsigned long pll_clock = pixel_clock_hz * dsi->divider;
848 int divider;
849
850 /* Find what divider gets us a faster clock than the requested
851 * pixel clock.
852 */
853 for (divider = 1; divider < 255; divider++) {
854 if (parent_rate / (divider + 1) < pll_clock)
855 break;
856 }
857
858 /* Now that we've picked a PLL divider, calculate back to its
859 * pixel clock.
860 */
861 pll_clock = parent_rate / divider;
862 pixel_clock_hz = pll_clock / dsi->divider;
863
864 adjusted_mode->clock = pixel_clock_hz / 1000;
865
866 /* Given the new pixel clock, adjust HFP to keep vrefresh the same. */
867 adjusted_mode->htotal = adjusted_mode->clock * mode->htotal /
868 mode->clock;
869 adjusted_mode->hsync_end += adjusted_mode->htotal - mode->htotal;
870 adjusted_mode->hsync_start += adjusted_mode->htotal - mode->htotal;
871
872 return true;
873}
874
875static void vc4_dsi_bridge_pre_enable(struct drm_bridge *bridge,
876 struct drm_bridge_state *old_state)
877{
878 struct drm_atomic_state *state = old_state->base.state;
879 struct vc4_dsi *dsi = bridge_to_vc4_dsi(bridge);
880 const struct drm_crtc_state *crtc_state;
881 struct device *dev = &dsi->pdev->dev;
882 const struct drm_display_mode *mode;
883 struct drm_connector *connector;
884 bool debug_dump_regs = false;
885 unsigned long hs_clock;
886 struct drm_crtc *crtc;
887 u32 ui_ns;
888 /* Minimum LP state duration in escape clock cycles. */
889 u32 lpx = dsi_esc_timing(60);
890 unsigned long pixel_clock_hz;
891 unsigned long dsip_clock;
892 unsigned long phy_clock;
893 int ret;
894
895 ret = pm_runtime_resume_and_get(dev);
896 if (ret) {
897 drm_err(bridge->dev, "Failed to runtime PM enable on DSI%d\n", dsi->variant->port);
898 return;
899 }
900
901 if (debug_dump_regs) {
902 struct drm_printer p = drm_info_printer(&dsi->pdev->dev);
903 dev_info(&dsi->pdev->dev, "DSI regs before:\n");
904 drm_print_regset32(&p, &dsi->regset);
905 }
906
907 /*
908 * Retrieve the CRTC adjusted mode. This requires a little dance to go
909 * from the bridge to the encoder, to the connector and to the CRTC.
910 */
911 connector = drm_atomic_get_new_connector_for_encoder(state,
912 bridge->encoder);
913 crtc = drm_atomic_get_new_connector_state(state, connector)->crtc;
914 crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
915 mode = &crtc_state->adjusted_mode;
916
917 pixel_clock_hz = mode->clock * 1000;
918
919 /* Round up the clk_set_rate() request slightly, since
920 * PLLD_DSI1 is an integer divider and its rate selection will
921 * never round up.
922 */
923 phy_clock = (pixel_clock_hz + 1000) * dsi->divider;
924 ret = clk_set_rate(dsi->pll_phy_clock, phy_clock);
925 if (ret) {
926 dev_err(&dsi->pdev->dev,
927 "Failed to set phy clock to %ld: %d\n", phy_clock, ret);
928 }
929
930 /* Reset the DSI and all its fifos. */
931 DSI_PORT_WRITE(CTRL,
932 DSI_CTRL_SOFT_RESET_CFG |
933 DSI_PORT_BIT(CTRL_RESET_FIFOS));
934
935 DSI_PORT_WRITE(CTRL,
936 DSI_CTRL_HSDT_EOT_DISABLE |
937 DSI_CTRL_RX_LPDT_EOT_DISABLE);
938
939 /* Clear all stat bits so we see what has happened during enable. */
940 DSI_PORT_WRITE(STAT, DSI_PORT_READ(STAT));
941
942 /* Set AFE CTR00/CTR1 to release powerdown of analog. */
943 if (dsi->variant->port == 0) {
944 u32 afec0 = (VC4_SET_FIELD(7, DSI_PHY_AFEC0_PTATADJ) |
945 VC4_SET_FIELD(7, DSI_PHY_AFEC0_CTATADJ));
946
947 if (dsi->lanes < 2)
948 afec0 |= DSI0_PHY_AFEC0_PD_DLANE1;
949
950 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO))
951 afec0 |= DSI0_PHY_AFEC0_RESET;
952
953 DSI_PORT_WRITE(PHY_AFEC0, afec0);
954
955 /* AFEC reset hold time */
956 mdelay(1);
957
958 DSI_PORT_WRITE(PHY_AFEC1,
959 VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_DLANE1) |
960 VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_DLANE0) |
961 VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_CLANE));
962 } else {
963 u32 afec0 = (VC4_SET_FIELD(7, DSI_PHY_AFEC0_PTATADJ) |
964 VC4_SET_FIELD(7, DSI_PHY_AFEC0_CTATADJ) |
965 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_CLANE) |
966 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE0) |
967 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE1) |
968 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE2) |
969 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE3));
970
971 if (dsi->lanes < 4)
972 afec0 |= DSI1_PHY_AFEC0_PD_DLANE3;
973 if (dsi->lanes < 3)
974 afec0 |= DSI1_PHY_AFEC0_PD_DLANE2;
975 if (dsi->lanes < 2)
976 afec0 |= DSI1_PHY_AFEC0_PD_DLANE1;
977
978 afec0 |= DSI1_PHY_AFEC0_RESET;
979
980 DSI_PORT_WRITE(PHY_AFEC0, afec0);
981
982 DSI_PORT_WRITE(PHY_AFEC1, 0);
983
984 /* AFEC reset hold time */
985 mdelay(1);
986 }
987
988 ret = clk_prepare_enable(dsi->escape_clock);
989 if (ret) {
990 drm_err(bridge->dev, "Failed to turn on DSI escape clock: %d\n",
991 ret);
992 return;
993 }
994
995 ret = clk_prepare_enable(dsi->pll_phy_clock);
996 if (ret) {
997 drm_err(bridge->dev, "Failed to turn on DSI PLL: %d\n", ret);
998 return;
999 }
1000
1001 hs_clock = clk_get_rate(dsi->pll_phy_clock);
1002
1003 /* Yes, we set the DSI0P/DSI1P pixel clock to the byte rate,
1004 * not the pixel clock rate. DSIxP take from the APHY's byte,
1005 * DDR2, or DDR4 clock (we use byte) and feed into the PV at
1006 * that rate. Separately, a value derived from PIX_CLK_DIV
1007 * and HS_CLKC is fed into the PV to divide down to the actual
1008 * pixel clock for pushing pixels into DSI.
1009 */
1010 dsip_clock = phy_clock / 8;
1011 ret = clk_set_rate(dsi->pixel_clock, dsip_clock);
1012 if (ret) {
1013 dev_err(dev, "Failed to set pixel clock to %ldHz: %d\n",
1014 dsip_clock, ret);
1015 }
1016
1017 ret = clk_prepare_enable(dsi->pixel_clock);
1018 if (ret) {
1019 drm_err(bridge->dev, "Failed to turn on DSI pixel clock: %d\n", ret);
1020 return;
1021 }
1022
1023 /* How many ns one DSI unit interval is. Note that the clock
1024 * is DDR, so there's an extra divide by 2.
1025 */
1026 ui_ns = DIV_ROUND_UP(500000000, hs_clock);
1027
1028 DSI_PORT_WRITE(HS_CLT0,
1029 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 262, 0),
1030 DSI_HS_CLT0_CZERO) |
1031 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 0, 8),
1032 DSI_HS_CLT0_CPRE) |
1033 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 38, 0),
1034 DSI_HS_CLT0_CPREP));
1035
1036 DSI_PORT_WRITE(HS_CLT1,
1037 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 60, 0),
1038 DSI_HS_CLT1_CTRAIL) |
1039 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 60, 52),
1040 DSI_HS_CLT1_CPOST));
1041
1042 DSI_PORT_WRITE(HS_CLT2,
1043 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 1000000, 0),
1044 DSI_HS_CLT2_WUP));
1045
1046 DSI_PORT_WRITE(HS_DLT3,
1047 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 100, 0),
1048 DSI_HS_DLT3_EXIT) |
1049 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 105, 6),
1050 DSI_HS_DLT3_ZERO) |
1051 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 40, 4),
1052 DSI_HS_DLT3_PRE));
1053
1054 DSI_PORT_WRITE(HS_DLT4,
1055 VC4_SET_FIELD(dsi_hs_timing(ui_ns, lpx * ESC_TIME_NS, 0),
1056 DSI_HS_DLT4_LPX) |
1057 VC4_SET_FIELD(max(dsi_hs_timing(ui_ns, 0, 8),
1058 dsi_hs_timing(ui_ns, 60, 4)),
1059 DSI_HS_DLT4_TRAIL) |
1060 VC4_SET_FIELD(0, DSI_HS_DLT4_ANLAT));
1061
1062 /* T_INIT is how long STOP is driven after power-up to
1063 * indicate to the slave (also coming out of power-up) that
1064 * master init is complete, and should be greater than the
1065 * maximum of two value: T_INIT,MASTER and T_INIT,SLAVE. The
1066 * D-PHY spec gives a minimum 100us for T_INIT,MASTER and
1067 * T_INIT,SLAVE, while allowing protocols on top of it to give
1068 * greater minimums. The vc4 firmware uses an extremely
1069 * conservative 5ms, and we maintain that here.
1070 */
1071 DSI_PORT_WRITE(HS_DLT5, VC4_SET_FIELD(dsi_hs_timing(ui_ns,
1072 5 * 1000 * 1000, 0),
1073 DSI_HS_DLT5_INIT));
1074
1075 DSI_PORT_WRITE(HS_DLT6,
1076 VC4_SET_FIELD(lpx * 5, DSI_HS_DLT6_TA_GET) |
1077 VC4_SET_FIELD(lpx, DSI_HS_DLT6_TA_SURE) |
1078 VC4_SET_FIELD(lpx * 4, DSI_HS_DLT6_TA_GO) |
1079 VC4_SET_FIELD(lpx, DSI_HS_DLT6_LP_LPX));
1080
1081 DSI_PORT_WRITE(HS_DLT7,
1082 VC4_SET_FIELD(dsi_esc_timing(1000000),
1083 DSI_HS_DLT7_LP_WUP));
1084
1085 DSI_PORT_WRITE(PHYC,
1086 DSI_PHYC_DLANE0_ENABLE |
1087 (dsi->lanes >= 2 ? DSI_PHYC_DLANE1_ENABLE : 0) |
1088 (dsi->lanes >= 3 ? DSI_PHYC_DLANE2_ENABLE : 0) |
1089 (dsi->lanes >= 4 ? DSI_PHYC_DLANE3_ENABLE : 0) |
1090 DSI_PORT_BIT(PHYC_CLANE_ENABLE) |
1091 ((dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) ?
1092 0 : DSI_PORT_BIT(PHYC_HS_CLK_CONTINUOUS)) |
1093 (dsi->variant->port == 0 ?
1094 VC4_SET_FIELD(lpx - 1, DSI0_PHYC_ESC_CLK_LPDT) :
1095 VC4_SET_FIELD(lpx - 1, DSI1_PHYC_ESC_CLK_LPDT)));
1096
1097 DSI_PORT_WRITE(CTRL,
1098 DSI_PORT_READ(CTRL) |
1099 DSI_CTRL_CAL_BYTE);
1100
1101 /* HS timeout in HS clock cycles: disabled. */
1102 DSI_PORT_WRITE(HSTX_TO_CNT, 0);
1103 /* LP receive timeout in HS clocks. */
1104 DSI_PORT_WRITE(LPRX_TO_CNT, 0xffffff);
1105 /* Bus turnaround timeout */
1106 DSI_PORT_WRITE(TA_TO_CNT, 100000);
1107 /* Display reset sequence timeout */
1108 DSI_PORT_WRITE(PR_TO_CNT, 100000);
1109
1110 /* Set up DISP1 for transferring long command payloads through
1111 * the pixfifo.
1112 */
1113 DSI_PORT_WRITE(DISP1_CTRL,
1114 VC4_SET_FIELD(DSI_DISP1_PFORMAT_32BIT_LE,
1115 DSI_DISP1_PFORMAT) |
1116 DSI_DISP1_ENABLE);
1117
1118 /* Ungate the block. */
1119 if (dsi->variant->port == 0)
1120 DSI_PORT_WRITE(CTRL, DSI_PORT_READ(CTRL) | DSI0_CTRL_CTRL0);
1121 else
1122 DSI_PORT_WRITE(CTRL, DSI_PORT_READ(CTRL) | DSI1_CTRL_EN);
1123
1124 /* Bring AFE out of reset. */
1125 DSI_PORT_WRITE(PHY_AFEC0,
1126 DSI_PORT_READ(PHY_AFEC0) &
1127 ~DSI_PORT_BIT(PHY_AFEC0_RESET));
1128
1129 vc4_dsi_ulps(dsi, false);
1130
1131 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
1132 DSI_PORT_WRITE(DISP0_CTRL,
1133 VC4_SET_FIELD(dsi->divider,
1134 DSI_DISP0_PIX_CLK_DIV) |
1135 VC4_SET_FIELD(dsi->format, DSI_DISP0_PFORMAT) |
1136 VC4_SET_FIELD(DSI_DISP0_LP_STOP_PERFRAME,
1137 DSI_DISP0_LP_STOP_CTRL) |
1138 DSI_DISP0_ST_END);
1139 } else {
1140 DSI_PORT_WRITE(DISP0_CTRL,
1141 DSI_DISP0_COMMAND_MODE);
1142 }
1143}
1144
1145static void vc4_dsi_bridge_enable(struct drm_bridge *bridge,
1146 struct drm_bridge_state *old_state)
1147{
1148 struct vc4_dsi *dsi = bridge_to_vc4_dsi(bridge);
1149 bool debug_dump_regs = false;
1150 u32 disp0_ctrl;
1151
1152 disp0_ctrl = DSI_PORT_READ(DISP0_CTRL);
1153 disp0_ctrl |= DSI_DISP0_ENABLE;
1154 DSI_PORT_WRITE(DISP0_CTRL, disp0_ctrl);
1155
1156 if (debug_dump_regs) {
1157 struct drm_printer p = drm_info_printer(&dsi->pdev->dev);
1158 dev_info(&dsi->pdev->dev, "DSI regs after:\n");
1159 drm_print_regset32(&p, &dsi->regset);
1160 }
1161}
1162
1163static int vc4_dsi_bridge_attach(struct drm_bridge *bridge,
1164 enum drm_bridge_attach_flags flags)
1165{
1166 struct vc4_dsi *dsi = bridge_to_vc4_dsi(bridge);
1167
1168 /* Attach the panel or bridge to the dsi bridge */
1169 return drm_bridge_attach(bridge->encoder, dsi->out_bridge,
1170 &dsi->bridge, flags);
1171}
1172
1173static ssize_t vc4_dsi_host_transfer(struct mipi_dsi_host *host,
1174 const struct mipi_dsi_msg *msg)
1175{
1176 struct vc4_dsi *dsi = host_to_dsi(host);
1177 struct drm_device *drm = dsi->bridge.dev;
1178 struct mipi_dsi_packet packet;
1179 u32 pkth = 0, pktc = 0;
1180 int i, ret;
1181 bool is_long = mipi_dsi_packet_format_is_long(msg->type);
1182 u32 cmd_fifo_len = 0, pix_fifo_len = 0;
1183
1184 mipi_dsi_create_packet(&packet, msg);
1185
1186 pkth |= VC4_SET_FIELD(packet.header[0], DSI_TXPKT1H_BC_DT);
1187 pkth |= VC4_SET_FIELD(packet.header[1] |
1188 (packet.header[2] << 8),
1189 DSI_TXPKT1H_BC_PARAM);
1190 if (is_long) {
1191 /* Divide data across the various FIFOs we have available.
1192 * The command FIFO takes byte-oriented data, but is of
1193 * limited size. The pixel FIFO (never actually used for
1194 * pixel data in reality) is word oriented, and substantially
1195 * larger. So, we use the pixel FIFO for most of the data,
1196 * sending the residual bytes in the command FIFO at the start.
1197 *
1198 * With this arrangement, the command FIFO will never get full.
1199 */
1200 if (packet.payload_length <= 16) {
1201 cmd_fifo_len = packet.payload_length;
1202 pix_fifo_len = 0;
1203 } else {
1204 cmd_fifo_len = (packet.payload_length %
1205 DSI_PIX_FIFO_WIDTH);
1206 pix_fifo_len = ((packet.payload_length - cmd_fifo_len) /
1207 DSI_PIX_FIFO_WIDTH);
1208 }
1209
1210 WARN_ON_ONCE(pix_fifo_len >= DSI_PIX_FIFO_DEPTH);
1211
1212 pkth |= VC4_SET_FIELD(cmd_fifo_len, DSI_TXPKT1H_BC_CMDFIFO);
1213 }
1214
1215 if (msg->rx_len) {
1216 pktc |= VC4_SET_FIELD(DSI_TXPKT1C_CMD_CTRL_RX,
1217 DSI_TXPKT1C_CMD_CTRL);
1218 } else {
1219 pktc |= VC4_SET_FIELD(DSI_TXPKT1C_CMD_CTRL_TX,
1220 DSI_TXPKT1C_CMD_CTRL);
1221 }
1222
1223 for (i = 0; i < cmd_fifo_len; i++)
1224 DSI_PORT_WRITE(TXPKT_CMD_FIFO, packet.payload[i]);
1225 for (i = 0; i < pix_fifo_len; i++) {
1226 const u8 *pix = packet.payload + cmd_fifo_len + i * 4;
1227
1228 DSI_PORT_WRITE(TXPKT_PIX_FIFO,
1229 pix[0] |
1230 pix[1] << 8 |
1231 pix[2] << 16 |
1232 pix[3] << 24);
1233 }
1234
1235 if (msg->flags & MIPI_DSI_MSG_USE_LPM)
1236 pktc |= DSI_TXPKT1C_CMD_MODE_LP;
1237 if (is_long)
1238 pktc |= DSI_TXPKT1C_CMD_TYPE_LONG;
1239
1240 /* Send one copy of the packet. Larger repeats are used for pixel
1241 * data in command mode.
1242 */
1243 pktc |= VC4_SET_FIELD(1, DSI_TXPKT1C_CMD_REPEAT);
1244
1245 pktc |= DSI_TXPKT1C_CMD_EN;
1246 if (pix_fifo_len) {
1247 pktc |= VC4_SET_FIELD(DSI_TXPKT1C_DISPLAY_NO_SECONDARY,
1248 DSI_TXPKT1C_DISPLAY_NO);
1249 } else {
1250 pktc |= VC4_SET_FIELD(DSI_TXPKT1C_DISPLAY_NO_SHORT,
1251 DSI_TXPKT1C_DISPLAY_NO);
1252 }
1253
1254 /* Enable the appropriate interrupt for the transfer completion. */
1255 dsi->xfer_result = 0;
1256 reinit_completion(&dsi->xfer_completion);
1257 if (dsi->variant->port == 0) {
1258 DSI_PORT_WRITE(INT_STAT,
1259 DSI0_INT_CMDC_DONE_MASK | DSI1_INT_PHY_DIR_RTF);
1260 if (msg->rx_len) {
1261 DSI_PORT_WRITE(INT_EN, (DSI0_INTERRUPTS_ALWAYS_ENABLED |
1262 DSI0_INT_PHY_DIR_RTF));
1263 } else {
1264 DSI_PORT_WRITE(INT_EN,
1265 (DSI0_INTERRUPTS_ALWAYS_ENABLED |
1266 VC4_SET_FIELD(DSI0_INT_CMDC_DONE_NO_REPEAT,
1267 DSI0_INT_CMDC_DONE)));
1268 }
1269 } else {
1270 DSI_PORT_WRITE(INT_STAT,
1271 DSI1_INT_TXPKT1_DONE | DSI1_INT_PHY_DIR_RTF);
1272 if (msg->rx_len) {
1273 DSI_PORT_WRITE(INT_EN, (DSI1_INTERRUPTS_ALWAYS_ENABLED |
1274 DSI1_INT_PHY_DIR_RTF));
1275 } else {
1276 DSI_PORT_WRITE(INT_EN, (DSI1_INTERRUPTS_ALWAYS_ENABLED |
1277 DSI1_INT_TXPKT1_DONE));
1278 }
1279 }
1280
1281 /* Send the packet. */
1282 DSI_PORT_WRITE(TXPKT1H, pkth);
1283 DSI_PORT_WRITE(TXPKT1C, pktc);
1284
1285 if (!wait_for_completion_timeout(&dsi->xfer_completion,
1286 msecs_to_jiffies(1000))) {
1287 dev_err(&dsi->pdev->dev, "transfer interrupt wait timeout");
1288 dev_err(&dsi->pdev->dev, "instat: 0x%08x\n",
1289 DSI_PORT_READ(INT_STAT));
1290 ret = -ETIMEDOUT;
1291 } else {
1292 ret = dsi->xfer_result;
1293 }
1294
1295 DSI_PORT_WRITE(INT_EN, DSI_PORT_BIT(INTERRUPTS_ALWAYS_ENABLED));
1296
1297 if (ret)
1298 goto reset_fifo_and_return;
1299
1300 if (ret == 0 && msg->rx_len) {
1301 u32 rxpkt1h = DSI_PORT_READ(RXPKT1H);
1302 u8 *msg_rx = msg->rx_buf;
1303
1304 if (rxpkt1h & DSI_RXPKT1H_PKT_TYPE_LONG) {
1305 u32 rxlen = VC4_GET_FIELD(rxpkt1h,
1306 DSI_RXPKT1H_BC_PARAM);
1307
1308 if (rxlen != msg->rx_len) {
1309 drm_err(drm, "DSI returned %db, expecting %db\n",
1310 rxlen, (int)msg->rx_len);
1311 ret = -ENXIO;
1312 goto reset_fifo_and_return;
1313 }
1314
1315 for (i = 0; i < msg->rx_len; i++)
1316 msg_rx[i] = DSI_READ(DSI1_RXPKT_FIFO);
1317 } else {
1318 /* FINISHME: Handle AWER */
1319
1320 msg_rx[0] = VC4_GET_FIELD(rxpkt1h,
1321 DSI_RXPKT1H_SHORT_0);
1322 if (msg->rx_len > 1) {
1323 msg_rx[1] = VC4_GET_FIELD(rxpkt1h,
1324 DSI_RXPKT1H_SHORT_1);
1325 }
1326 }
1327 }
1328
1329 return ret;
1330
1331reset_fifo_and_return:
1332 drm_err(drm, "DSI transfer failed, resetting: %d\n", ret);
1333
1334 DSI_PORT_WRITE(TXPKT1C, DSI_PORT_READ(TXPKT1C) & ~DSI_TXPKT1C_CMD_EN);
1335 udelay(1);
1336 DSI_PORT_WRITE(CTRL,
1337 DSI_PORT_READ(CTRL) |
1338 DSI_PORT_BIT(CTRL_RESET_FIFOS));
1339
1340 DSI_PORT_WRITE(TXPKT1C, 0);
1341 DSI_PORT_WRITE(INT_EN, DSI_PORT_BIT(INTERRUPTS_ALWAYS_ENABLED));
1342 return ret;
1343}
1344
1345static const struct component_ops vc4_dsi_ops;
1346static int vc4_dsi_host_attach(struct mipi_dsi_host *host,
1347 struct mipi_dsi_device *device)
1348{
1349 struct vc4_dsi *dsi = host_to_dsi(host);
1350 int ret;
1351
1352 dsi->lanes = device->lanes;
1353 dsi->channel = device->channel;
1354 dsi->mode_flags = device->mode_flags;
1355
1356 switch (device->format) {
1357 case MIPI_DSI_FMT_RGB888:
1358 dsi->format = DSI_PFORMAT_RGB888;
1359 dsi->divider = 24 / dsi->lanes;
1360 break;
1361 case MIPI_DSI_FMT_RGB666:
1362 dsi->format = DSI_PFORMAT_RGB666;
1363 dsi->divider = 24 / dsi->lanes;
1364 break;
1365 case MIPI_DSI_FMT_RGB666_PACKED:
1366 dsi->format = DSI_PFORMAT_RGB666_PACKED;
1367 dsi->divider = 18 / dsi->lanes;
1368 break;
1369 case MIPI_DSI_FMT_RGB565:
1370 dsi->format = DSI_PFORMAT_RGB565;
1371 dsi->divider = 16 / dsi->lanes;
1372 break;
1373 default:
1374 dev_err(&dsi->pdev->dev, "Unknown DSI format: %d.\n",
1375 dsi->format);
1376 return 0;
1377 }
1378
1379 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) {
1380 dev_err(&dsi->pdev->dev,
1381 "Only VIDEO mode panels supported currently.\n");
1382 return 0;
1383 }
1384
1385 drm_bridge_add(&dsi->bridge);
1386
1387 ret = component_add(&dsi->pdev->dev, &vc4_dsi_ops);
1388 if (ret) {
1389 drm_bridge_remove(&dsi->bridge);
1390 return ret;
1391 }
1392
1393 return 0;
1394}
1395
1396static int vc4_dsi_host_detach(struct mipi_dsi_host *host,
1397 struct mipi_dsi_device *device)
1398{
1399 struct vc4_dsi *dsi = host_to_dsi(host);
1400
1401 component_del(&dsi->pdev->dev, &vc4_dsi_ops);
1402 drm_bridge_remove(&dsi->bridge);
1403 return 0;
1404}
1405
1406static const struct mipi_dsi_host_ops vc4_dsi_host_ops = {
1407 .attach = vc4_dsi_host_attach,
1408 .detach = vc4_dsi_host_detach,
1409 .transfer = vc4_dsi_host_transfer,
1410};
1411
1412static const struct drm_bridge_funcs vc4_dsi_bridge_funcs = {
1413 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
1414 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
1415 .atomic_reset = drm_atomic_helper_bridge_reset,
1416 .atomic_pre_enable = vc4_dsi_bridge_pre_enable,
1417 .atomic_enable = vc4_dsi_bridge_enable,
1418 .atomic_disable = vc4_dsi_bridge_disable,
1419 .atomic_post_disable = vc4_dsi_bridge_post_disable,
1420 .attach = vc4_dsi_bridge_attach,
1421 .mode_fixup = vc4_dsi_bridge_mode_fixup,
1422};
1423
1424static int vc4_dsi_late_register(struct drm_encoder *encoder)
1425{
1426 struct drm_device *drm = encoder->dev;
1427 struct vc4_dsi *dsi = to_vc4_dsi(encoder);
1428
1429 vc4_debugfs_add_regset32(drm, dsi->variant->debugfs_name, &dsi->regset);
1430
1431 return 0;
1432}
1433
1434static const struct drm_encoder_funcs vc4_dsi_encoder_funcs = {
1435 .late_register = vc4_dsi_late_register,
1436};
1437
1438static const struct vc4_dsi_variant bcm2711_dsi1_variant = {
1439 .port = 1,
1440 .debugfs_name = "dsi1_regs",
1441 .regs = dsi1_regs,
1442 .nregs = ARRAY_SIZE(dsi1_regs),
1443};
1444
1445static const struct vc4_dsi_variant bcm2835_dsi0_variant = {
1446 .port = 0,
1447 .debugfs_name = "dsi0_regs",
1448 .regs = dsi0_regs,
1449 .nregs = ARRAY_SIZE(dsi0_regs),
1450};
1451
1452static const struct vc4_dsi_variant bcm2835_dsi1_variant = {
1453 .port = 1,
1454 .broken_axi_workaround = true,
1455 .debugfs_name = "dsi1_regs",
1456 .regs = dsi1_regs,
1457 .nregs = ARRAY_SIZE(dsi1_regs),
1458};
1459
1460static const struct of_device_id vc4_dsi_dt_match[] = {
1461 { .compatible = "brcm,bcm2711-dsi1", &bcm2711_dsi1_variant },
1462 { .compatible = "brcm,bcm2835-dsi0", &bcm2835_dsi0_variant },
1463 { .compatible = "brcm,bcm2835-dsi1", &bcm2835_dsi1_variant },
1464 {}
1465};
1466
1467static void dsi_handle_error(struct vc4_dsi *dsi,
1468 irqreturn_t *ret, u32 stat, u32 bit,
1469 const char *type)
1470{
1471 if (!(stat & bit))
1472 return;
1473
1474 drm_err(dsi->bridge.dev, "DSI%d: %s error\n", dsi->variant->port,
1475 type);
1476 *ret = IRQ_HANDLED;
1477}
1478
1479/*
1480 * Initial handler for port 1 where we need the reg_dma workaround.
1481 * The register DMA writes sleep, so we can't do it in the top half.
1482 * Instead we use IRQF_ONESHOT so that the IRQ gets disabled in the
1483 * parent interrupt contrller until our interrupt thread is done.
1484 */
1485static irqreturn_t vc4_dsi_irq_defer_to_thread_handler(int irq, void *data)
1486{
1487 struct vc4_dsi *dsi = data;
1488 u32 stat = DSI_PORT_READ(INT_STAT);
1489
1490 if (!stat)
1491 return IRQ_NONE;
1492
1493 return IRQ_WAKE_THREAD;
1494}
1495
1496/*
1497 * Normal IRQ handler for port 0, or the threaded IRQ handler for port
1498 * 1 where we need the reg_dma workaround.
1499 */
1500static irqreturn_t vc4_dsi_irq_handler(int irq, void *data)
1501{
1502 struct vc4_dsi *dsi = data;
1503 u32 stat = DSI_PORT_READ(INT_STAT);
1504 irqreturn_t ret = IRQ_NONE;
1505
1506 DSI_PORT_WRITE(INT_STAT, stat);
1507
1508 dsi_handle_error(dsi, &ret, stat,
1509 DSI_PORT_BIT(INT_ERR_SYNC_ESC), "LPDT sync");
1510 dsi_handle_error(dsi, &ret, stat,
1511 DSI_PORT_BIT(INT_ERR_CONTROL), "data lane 0 sequence");
1512 dsi_handle_error(dsi, &ret, stat,
1513 DSI_PORT_BIT(INT_ERR_CONT_LP0), "LP0 contention");
1514 dsi_handle_error(dsi, &ret, stat,
1515 DSI_PORT_BIT(INT_ERR_CONT_LP1), "LP1 contention");
1516 dsi_handle_error(dsi, &ret, stat,
1517 DSI_PORT_BIT(INT_HSTX_TO), "HSTX timeout");
1518 dsi_handle_error(dsi, &ret, stat,
1519 DSI_PORT_BIT(INT_LPRX_TO), "LPRX timeout");
1520 dsi_handle_error(dsi, &ret, stat,
1521 DSI_PORT_BIT(INT_TA_TO), "turnaround timeout");
1522 dsi_handle_error(dsi, &ret, stat,
1523 DSI_PORT_BIT(INT_PR_TO), "peripheral reset timeout");
1524
1525 if (stat & ((dsi->variant->port ? DSI1_INT_TXPKT1_DONE :
1526 DSI0_INT_CMDC_DONE_MASK) |
1527 DSI_PORT_BIT(INT_PHY_DIR_RTF))) {
1528 complete(&dsi->xfer_completion);
1529 ret = IRQ_HANDLED;
1530 } else if (stat & DSI_PORT_BIT(INT_HSTX_TO)) {
1531 complete(&dsi->xfer_completion);
1532 dsi->xfer_result = -ETIMEDOUT;
1533 ret = IRQ_HANDLED;
1534 }
1535
1536 return ret;
1537}
1538
1539/**
1540 * vc4_dsi_init_phy_clocks - Exposes clocks generated by the analog
1541 * PHY that are consumed by CPRMAN (clk-bcm2835.c).
1542 * @dsi: DSI encoder
1543 */
1544static int
1545vc4_dsi_init_phy_clocks(struct vc4_dsi *dsi)
1546{
1547 struct device *dev = &dsi->pdev->dev;
1548 const char *parent_name = __clk_get_name(dsi->pll_phy_clock);
1549 static const struct {
1550 const char *name;
1551 int div;
1552 } phy_clocks[] = {
1553 { "byte", 8 },
1554 { "ddr2", 4 },
1555 { "ddr", 2 },
1556 };
1557 int i;
1558
1559 dsi->clk_onecell = devm_kzalloc(dev,
1560 sizeof(*dsi->clk_onecell) +
1561 ARRAY_SIZE(phy_clocks) *
1562 sizeof(struct clk_hw *),
1563 GFP_KERNEL);
1564 if (!dsi->clk_onecell)
1565 return -ENOMEM;
1566 dsi->clk_onecell->num = ARRAY_SIZE(phy_clocks);
1567
1568 for (i = 0; i < ARRAY_SIZE(phy_clocks); i++) {
1569 struct clk_fixed_factor *fix = &dsi->phy_clocks[i];
1570 struct clk_init_data init;
1571 char clk_name[16];
1572 int ret;
1573
1574 snprintf(clk_name, sizeof(clk_name),
1575 "dsi%u_%s", dsi->variant->port, phy_clocks[i].name);
1576
1577 /* We just use core fixed factor clock ops for the PHY
1578 * clocks. The clocks are actually gated by the
1579 * PHY_AFEC0_DDRCLK_EN bits, which we should be
1580 * setting if we use the DDR/DDR2 clocks. However,
1581 * vc4_dsi_encoder_enable() is setting up both AFEC0,
1582 * setting both our parent DSI PLL's rate and this
1583 * clock's rate, so it knows if DDR/DDR2 are going to
1584 * be used and could enable the gates itself.
1585 */
1586 fix->mult = 1;
1587 fix->div = phy_clocks[i].div;
1588 fix->hw.init = &init;
1589
1590 memset(&init, 0, sizeof(init));
1591 init.parent_names = &parent_name;
1592 init.num_parents = 1;
1593 init.name = clk_name;
1594 init.ops = &clk_fixed_factor_ops;
1595
1596 ret = devm_clk_hw_register(dev, &fix->hw);
1597 if (ret)
1598 return ret;
1599
1600 dsi->clk_onecell->hws[i] = &fix->hw;
1601 }
1602
1603 return of_clk_add_hw_provider(dev->of_node,
1604 of_clk_hw_onecell_get,
1605 dsi->clk_onecell);
1606}
1607
1608static void vc4_dsi_dma_mem_release(void *ptr)
1609{
1610 struct vc4_dsi *dsi = ptr;
1611 struct device *dev = &dsi->pdev->dev;
1612
1613 dma_free_coherent(dev, 4, dsi->reg_dma_mem, dsi->reg_dma_paddr);
1614 dsi->reg_dma_mem = NULL;
1615}
1616
1617static void vc4_dsi_dma_chan_release(void *ptr)
1618{
1619 struct vc4_dsi *dsi = ptr;
1620
1621 dma_release_channel(dsi->reg_dma_chan);
1622 dsi->reg_dma_chan = NULL;
1623}
1624
1625static void vc4_dsi_release(struct kref *kref)
1626{
1627 struct vc4_dsi *dsi =
1628 container_of(kref, struct vc4_dsi, kref);
1629
1630 kfree(dsi);
1631}
1632
1633static void vc4_dsi_get(struct vc4_dsi *dsi)
1634{
1635 kref_get(&dsi->kref);
1636}
1637
1638static void vc4_dsi_put(struct vc4_dsi *dsi)
1639{
1640 kref_put(&dsi->kref, &vc4_dsi_release);
1641}
1642
1643static void vc4_dsi_release_action(struct drm_device *drm, void *ptr)
1644{
1645 struct vc4_dsi *dsi = ptr;
1646
1647 vc4_dsi_put(dsi);
1648}
1649
1650static int vc4_dsi_bind(struct device *dev, struct device *master, void *data)
1651{
1652 struct platform_device *pdev = to_platform_device(dev);
1653 struct drm_device *drm = dev_get_drvdata(master);
1654 struct vc4_dsi *dsi = dev_get_drvdata(dev);
1655 struct drm_encoder *encoder = &dsi->encoder.base;
1656 int ret;
1657
1658 vc4_dsi_get(dsi);
1659
1660 ret = drmm_add_action_or_reset(drm, vc4_dsi_release_action, dsi);
1661 if (ret)
1662 return ret;
1663
1664 dsi->variant = of_device_get_match_data(dev);
1665
1666 dsi->encoder.type = dsi->variant->port ?
1667 VC4_ENCODER_TYPE_DSI1 : VC4_ENCODER_TYPE_DSI0;
1668
1669 dsi->regs = vc4_ioremap_regs(pdev, 0);
1670 if (IS_ERR(dsi->regs))
1671 return PTR_ERR(dsi->regs);
1672
1673 dsi->regset.base = dsi->regs;
1674 dsi->regset.regs = dsi->variant->regs;
1675 dsi->regset.nregs = dsi->variant->nregs;
1676
1677 if (DSI_PORT_READ(ID) != DSI_ID_VALUE) {
1678 dev_err(dev, "Port returned 0x%08x for ID instead of 0x%08x\n",
1679 DSI_PORT_READ(ID), DSI_ID_VALUE);
1680 return -ENODEV;
1681 }
1682
1683 /* DSI1 on BCM2835/6/7 has a broken AXI slave that doesn't respond to
1684 * writes from the ARM. It does handle writes from the DMA engine,
1685 * so set up a channel for talking to it.
1686 */
1687 if (dsi->variant->broken_axi_workaround) {
1688 dma_cap_mask_t dma_mask;
1689
1690 dsi->reg_dma_mem = dma_alloc_coherent(dev, 4,
1691 &dsi->reg_dma_paddr,
1692 GFP_KERNEL);
1693 if (!dsi->reg_dma_mem) {
1694 drm_err(drm, "Failed to get DMA memory\n");
1695 return -ENOMEM;
1696 }
1697
1698 ret = devm_add_action_or_reset(dev, vc4_dsi_dma_mem_release, dsi);
1699 if (ret)
1700 return ret;
1701
1702 dma_cap_zero(dma_mask);
1703 dma_cap_set(DMA_MEMCPY, dma_mask);
1704
1705 dsi->reg_dma_chan = dma_request_chan_by_mask(&dma_mask);
1706 if (IS_ERR(dsi->reg_dma_chan)) {
1707 ret = PTR_ERR(dsi->reg_dma_chan);
1708 if (ret != -EPROBE_DEFER)
1709 drm_err(drm, "Failed to get DMA channel: %d\n",
1710 ret);
1711 return ret;
1712 }
1713
1714 ret = devm_add_action_or_reset(dev, vc4_dsi_dma_chan_release, dsi);
1715 if (ret)
1716 return ret;
1717
1718 /* Get the physical address of the device's registers. The
1719 * struct resource for the regs gives us the bus address
1720 * instead.
1721 */
1722 dsi->reg_paddr = be32_to_cpup(of_get_address(dev->of_node,
1723 0, NULL, NULL));
1724 }
1725
1726 init_completion(&dsi->xfer_completion);
1727 /* At startup enable error-reporting interrupts and nothing else. */
1728 DSI_PORT_WRITE(INT_EN, DSI1_INTERRUPTS_ALWAYS_ENABLED);
1729 /* Clear any existing interrupt state. */
1730 DSI_PORT_WRITE(INT_STAT, DSI_PORT_READ(INT_STAT));
1731
1732 if (dsi->reg_dma_mem)
1733 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0),
1734 vc4_dsi_irq_defer_to_thread_handler,
1735 vc4_dsi_irq_handler,
1736 IRQF_ONESHOT,
1737 "vc4 dsi", dsi);
1738 else
1739 ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
1740 vc4_dsi_irq_handler, 0, "vc4 dsi", dsi);
1741 if (ret) {
1742 if (ret != -EPROBE_DEFER)
1743 dev_err(dev, "Failed to get interrupt: %d\n", ret);
1744 return ret;
1745 }
1746
1747 dsi->escape_clock = devm_clk_get(dev, "escape");
1748 if (IS_ERR(dsi->escape_clock)) {
1749 ret = PTR_ERR(dsi->escape_clock);
1750 if (ret != -EPROBE_DEFER)
1751 dev_err(dev, "Failed to get escape clock: %d\n", ret);
1752 return ret;
1753 }
1754
1755 dsi->pll_phy_clock = devm_clk_get(dev, "phy");
1756 if (IS_ERR(dsi->pll_phy_clock)) {
1757 ret = PTR_ERR(dsi->pll_phy_clock);
1758 if (ret != -EPROBE_DEFER)
1759 dev_err(dev, "Failed to get phy clock: %d\n", ret);
1760 return ret;
1761 }
1762
1763 dsi->pixel_clock = devm_clk_get(dev, "pixel");
1764 if (IS_ERR(dsi->pixel_clock)) {
1765 ret = PTR_ERR(dsi->pixel_clock);
1766 if (ret != -EPROBE_DEFER)
1767 dev_err(dev, "Failed to get pixel clock: %d\n", ret);
1768 return ret;
1769 }
1770
1771 dsi->out_bridge = drmm_of_get_bridge(drm, dev->of_node, 0, 0);
1772 if (IS_ERR(dsi->out_bridge))
1773 return PTR_ERR(dsi->out_bridge);
1774
1775 /* The esc clock rate is supposed to always be 100Mhz. */
1776 ret = clk_set_rate(dsi->escape_clock, 100 * 1000000);
1777 if (ret) {
1778 dev_err(dev, "Failed to set esc clock: %d\n", ret);
1779 return ret;
1780 }
1781
1782 ret = vc4_dsi_init_phy_clocks(dsi);
1783 if (ret)
1784 return ret;
1785
1786 ret = drmm_encoder_init(drm, encoder,
1787 &vc4_dsi_encoder_funcs,
1788 DRM_MODE_ENCODER_DSI,
1789 NULL);
1790 if (ret)
1791 return ret;
1792
1793 ret = devm_pm_runtime_enable(dev);
1794 if (ret)
1795 return ret;
1796
1797 ret = drm_bridge_attach(encoder, &dsi->bridge, NULL, 0);
1798 if (ret)
1799 return ret;
1800
1801 return 0;
1802}
1803
1804static const struct component_ops vc4_dsi_ops = {
1805 .bind = vc4_dsi_bind,
1806};
1807
1808static int vc4_dsi_dev_probe(struct platform_device *pdev)
1809{
1810 struct device *dev = &pdev->dev;
1811 struct vc4_dsi *dsi;
1812
1813 dsi = kzalloc(sizeof(*dsi), GFP_KERNEL);
1814 if (!dsi)
1815 return -ENOMEM;
1816 dev_set_drvdata(dev, dsi);
1817
1818 kref_init(&dsi->kref);
1819
1820 dsi->pdev = pdev;
1821 dsi->bridge.funcs = &vc4_dsi_bridge_funcs;
1822#ifdef CONFIG_OF
1823 dsi->bridge.of_node = dev->of_node;
1824#endif
1825 dsi->bridge.type = DRM_MODE_CONNECTOR_DSI;
1826 dsi->dsi_host.ops = &vc4_dsi_host_ops;
1827 dsi->dsi_host.dev = dev;
1828 mipi_dsi_host_register(&dsi->dsi_host);
1829
1830 return 0;
1831}
1832
1833static void vc4_dsi_dev_remove(struct platform_device *pdev)
1834{
1835 struct device *dev = &pdev->dev;
1836 struct vc4_dsi *dsi = dev_get_drvdata(dev);
1837
1838 mipi_dsi_host_unregister(&dsi->dsi_host);
1839 vc4_dsi_put(dsi);
1840}
1841
1842struct platform_driver vc4_dsi_driver = {
1843 .probe = vc4_dsi_dev_probe,
1844 .remove = vc4_dsi_dev_remove,
1845 .driver = {
1846 .name = "vc4_dsi",
1847 .of_match_table = vc4_dsi_dt_match,
1848 },
1849};