1/*
   2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice (including the next
  12 * paragraph) shall be included in all copies or substantial portions of the
  13 * Software.
  14 *
  15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21 * SOFTWARE.
  22 *
  23 * Authors:
  24 *    Kevin Tian <kevin.tian@intel.com>
  25 *    Eddie Dong <eddie.dong@intel.com>
  26 *    Zhiyuan Lv <zhiyuan.lv@intel.com>
  27 *
  28 * Contributors:
  29 *    Min He <min.he@intel.com>
  30 *    Tina Zhang <tina.zhang@intel.com>
  31 *    Pei Zhang <pei.zhang@intel.com>
  32 *    Niu Bing <bing.niu@intel.com>
  33 *    Ping Gao <ping.a.gao@intel.com>
  34 *    Zhi Wang <zhi.a.wang@intel.com>
  35 *
  36
  37 */
  38
  39#include <drm/display/drm_dp.h>
  40
  41#include "i915_drv.h"
  42#include "i915_reg.h"
  43#include "gvt.h"
  44#include "i915_pvinfo.h"
  45#include "intel_mchbar_regs.h"
  46#include "display/bxt_dpio_phy_regs.h"
  47#include "display/i9xx_plane_regs.h"
  48#include "display/intel_cursor_regs.h"
  49#include "display/intel_display_types.h"
  50#include "display/intel_dmc_regs.h"
  51#include "display/intel_dp_aux_regs.h"
  52#include "display/intel_dpio_phy.h"
  53#include "display/intel_fbc.h"
  54#include "display/intel_fdi_regs.h"
  55#include "display/intel_pps_regs.h"
  56#include "display/intel_psr_regs.h"
  57#include "display/intel_sprite_regs.h"
  58#include "display/skl_universal_plane_regs.h"
  59#include "display/skl_watermark_regs.h"
  60#include "display/vlv_dsi_pll_regs.h"
  61#include "gt/intel_gt_regs.h"
  62#include <linux/vmalloc.h>
  63
  64/* XXX FIXME i915 has changed PP_XXX definition */
  65#define PCH_PP_STATUS  _MMIO(0xc7200)
  66#define PCH_PP_CONTROL _MMIO(0xc7204)
  67#define PCH_PP_ON_DELAYS _MMIO(0xc7208)
  68#define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
  69#define PCH_PP_DIVISOR _MMIO(0xc7210)
  70
  71unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt)
  72{
  73	struct drm_i915_private *i915 = gvt->gt->i915;
  74
  75	if (IS_BROADWELL(i915))
  76		return D_BDW;
  77	else if (IS_SKYLAKE(i915))
  78		return D_SKL;
  79	else if (IS_KABYLAKE(i915))
  80		return D_KBL;
  81	else if (IS_BROXTON(i915))
  82		return D_BXT;
  83	else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915))
  84		return D_CFL;
  85
  86	return 0;
  87}
  88
  89static bool intel_gvt_match_device(struct intel_gvt *gvt,
  90		unsigned long device)
  91{
  92	return intel_gvt_get_device_type(gvt) & device;
  93}
  94
  95static void read_vreg(struct intel_vgpu *vgpu, unsigned int offset,
  96	void *p_data, unsigned int bytes)
  97{
  98	memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
  99}
 100
 101static void write_vreg(struct intel_vgpu *vgpu, unsigned int offset,
 102	void *p_data, unsigned int bytes)
 103{
 104	memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
 105}
 106
 107struct intel_gvt_mmio_info *intel_gvt_find_mmio_info(struct intel_gvt *gvt,
 108						  unsigned int offset)
 109{
 110	struct intel_gvt_mmio_info *e;
 111
 112	hash_for_each_possible(gvt->mmio.mmio_info_table, e, node, offset) {
 113		if (e->offset == offset)
 114			return e;
 115	}
 116	return NULL;
 117}
 118
 119static int setup_mmio_info(struct intel_gvt *gvt, u32 offset, u32 size,
 120			   u16 flags, u32 addr_mask, u32 ro_mask, u32 device,
 121			   gvt_mmio_func read, gvt_mmio_func write)
 122{
 123	struct intel_gvt_mmio_info *p;
 124	u32 start, end, i;
 125
 126	if (!intel_gvt_match_device(gvt, device))
 127		return 0;
 128
 129	if (WARN_ON(!IS_ALIGNED(offset, 4)))
 130		return -EINVAL;
 131
 132	start = offset;
 133	end = offset + size;
 134
 135	for (i = start; i < end; i += 4) {
 136		p = intel_gvt_find_mmio_info(gvt, i);
 137		if (!p) {
 138			WARN(1, "assign a handler to a non-tracked mmio %x\n",
 139				i);
 140			return -ENODEV;
 141		}
 142		p->ro_mask = ro_mask;
 143		gvt->mmio.mmio_attribute[i / 4] = flags;
 144		if (read)
 145			p->read = read;
 146		if (write)
 147			p->write = write;
 148	}
 149	return 0;
 150}
 151
 152/**
 153 * intel_gvt_render_mmio_to_engine - convert a mmio offset into the engine
 154 * @gvt: a GVT device
 155 * @offset: register offset
 156 *
 157 * Returns:
 158 * The engine containing the offset within its mmio page.
 159 */
 160const struct intel_engine_cs *
 161intel_gvt_render_mmio_to_engine(struct intel_gvt *gvt, unsigned int offset)
 162{
 163	struct intel_engine_cs *engine;
 164	enum intel_engine_id id;
 165
 166	offset &= ~GENMASK(11, 0);
 167	for_each_engine(engine, gvt->gt, id)
 168		if (engine->mmio_base == offset)
 169			return engine;
 170
 171	return NULL;
 172}
 173
 174#define offset_to_fence_num(offset) \
 175	((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3)
 176
 177#define fence_num_to_offset(num) \
 178	(num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0)))
 179
 180
 181void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason)
 182{
 183	switch (reason) {
 184	case GVT_FAILSAFE_UNSUPPORTED_GUEST:
 185		pr_err("Detected your guest driver doesn't support GVT-g.\n");
 186		break;
 187	case GVT_FAILSAFE_INSUFFICIENT_RESOURCE:
 188		pr_err("Graphics resource is not enough for the guest\n");
 189		break;
 190	case GVT_FAILSAFE_GUEST_ERR:
 191		pr_err("GVT Internal error  for the guest\n");
 192		break;
 193	default:
 194		break;
 195	}
 196	pr_err("Now vgpu %d will enter failsafe mode.\n", vgpu->id);
 197	vgpu->failsafe = true;
 198}
 199
 200static int sanitize_fence_mmio_access(struct intel_vgpu *vgpu,
 201		unsigned int fence_num, void *p_data, unsigned int bytes)
 202{
 203	unsigned int max_fence = vgpu_fence_sz(vgpu);
 204
 205	if (fence_num >= max_fence) {
 206		gvt_vgpu_err("access oob fence reg %d/%d\n",
 207			     fence_num, max_fence);
 208
 209		/* When guest access oob fence regs without access
 210		 * pv_info first, we treat guest not supporting GVT,
 211		 * and we will let vgpu enter failsafe mode.
 212		 */
 213		if (!vgpu->pv_notified)
 214			enter_failsafe_mode(vgpu,
 215					GVT_FAILSAFE_UNSUPPORTED_GUEST);
 216
 217		memset(p_data, 0, bytes);
 218		return -EINVAL;
 219	}
 220	return 0;
 221}
 222
 223static int gamw_echo_dev_rw_ia_write(struct intel_vgpu *vgpu,
 224		unsigned int offset, void *p_data, unsigned int bytes)
 225{
 226	u32 ips = (*(u32 *)p_data) & GAMW_ECO_ENABLE_64K_IPS_FIELD;
 227
 228	if (GRAPHICS_VER(vgpu->gvt->gt->i915) <= 10) {
 229		if (ips == GAMW_ECO_ENABLE_64K_IPS_FIELD)
 230			gvt_dbg_core("vgpu%d: ips enabled\n", vgpu->id);
 231		else if (!ips)
 232			gvt_dbg_core("vgpu%d: ips disabled\n", vgpu->id);
 233		else {
 234			/* All engines must be enabled together for vGPU,
 235			 * since we don't know which engine the ppgtt will
 236			 * bind to when shadowing.
 237			 */
 238			gvt_vgpu_err("Unsupported IPS setting %x, cannot enable 64K gtt.\n",
 239				     ips);
 240			return -EINVAL;
 241		}
 242	}
 243
 244	write_vreg(vgpu, offset, p_data, bytes);
 245	return 0;
 246}
 247
 248static int fence_mmio_read(struct intel_vgpu *vgpu, unsigned int off,
 249		void *p_data, unsigned int bytes)
 250{
 251	int ret;
 252
 253	ret = sanitize_fence_mmio_access(vgpu, offset_to_fence_num(off),
 254			p_data, bytes);
 255	if (ret)
 256		return ret;
 257	read_vreg(vgpu, off, p_data, bytes);
 258	return 0;
 259}
 260
 261static int fence_mmio_write(struct intel_vgpu *vgpu, unsigned int off,
 262		void *p_data, unsigned int bytes)
 263{
 264	struct intel_gvt *gvt = vgpu->gvt;
 265	unsigned int fence_num = offset_to_fence_num(off);
 266	int ret;
 267
 268	ret = sanitize_fence_mmio_access(vgpu, fence_num, p_data, bytes);
 269	if (ret)
 270		return ret;
 271	write_vreg(vgpu, off, p_data, bytes);
 272
 273	mmio_hw_access_pre(gvt->gt);
 274	intel_vgpu_write_fence(vgpu, fence_num,
 275			vgpu_vreg64(vgpu, fence_num_to_offset(fence_num)));
 276	mmio_hw_access_post(gvt->gt);
 277	return 0;
 278}
 279
 280#define CALC_MODE_MASK_REG(old, new) \
 281	(((new) & GENMASK(31, 16)) \
 282	 | ((((old) & GENMASK(15, 0)) & ~((new) >> 16)) \
 283	 | ((new) & ((new) >> 16))))
 284
 285static int mul_force_wake_write(struct intel_vgpu *vgpu,
 286		unsigned int offset, void *p_data, unsigned int bytes)
 287{
 288	u32 old, new;
 289	u32 ack_reg_offset;
 290
 291	old = vgpu_vreg(vgpu, offset);
 292	new = CALC_MODE_MASK_REG(old, *(u32 *)p_data);
 293
 294	if (GRAPHICS_VER(vgpu->gvt->gt->i915)  >=  9) {
 295		switch (offset) {
 296		case FORCEWAKE_RENDER_GEN9_REG:
 297			ack_reg_offset = FORCEWAKE_ACK_RENDER_GEN9_REG;
 298			break;
 299		case FORCEWAKE_GT_GEN9_REG:
 300			ack_reg_offset = FORCEWAKE_ACK_GT_GEN9_REG;
 301			break;
 302		case FORCEWAKE_MEDIA_GEN9_REG:
 303			ack_reg_offset = FORCEWAKE_ACK_MEDIA_GEN9_REG;
 304			break;
 305		default:
 306			/*should not hit here*/
 307			gvt_vgpu_err("invalid forcewake offset 0x%x\n", offset);
 308			return -EINVAL;
 309		}
 310	} else {
 311		ack_reg_offset = FORCEWAKE_ACK_HSW_REG;
 312	}
 313
 314	vgpu_vreg(vgpu, offset) = new;
 315	vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0));
 316	return 0;
 317}
 318
 319static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
 320			    void *p_data, unsigned int bytes)
 321{
 322	intel_engine_mask_t engine_mask = 0;
 323	u32 data;
 324
 325	write_vreg(vgpu, offset, p_data, bytes);
 326	data = vgpu_vreg(vgpu, offset);
 327
 328	if (data & GEN6_GRDOM_FULL) {
 329		gvt_dbg_mmio("vgpu%d: request full GPU reset\n", vgpu->id);
 330		engine_mask = ALL_ENGINES;
 331	} else {
 332		if (data & GEN6_GRDOM_RENDER) {
 333			gvt_dbg_mmio("vgpu%d: request RCS reset\n", vgpu->id);
 334			engine_mask |= BIT(RCS0);
 335		}
 336		if (data & GEN6_GRDOM_MEDIA) {
 337			gvt_dbg_mmio("vgpu%d: request VCS reset\n", vgpu->id);
 338			engine_mask |= BIT(VCS0);
 339		}
 340		if (data & GEN6_GRDOM_BLT) {
 341			gvt_dbg_mmio("vgpu%d: request BCS Reset\n", vgpu->id);
 342			engine_mask |= BIT(BCS0);
 343		}
 344		if (data & GEN6_GRDOM_VECS) {
 345			gvt_dbg_mmio("vgpu%d: request VECS Reset\n", vgpu->id);
 346			engine_mask |= BIT(VECS0);
 347		}
 348		if (data & GEN8_GRDOM_MEDIA2) {
 349			gvt_dbg_mmio("vgpu%d: request VCS2 Reset\n", vgpu->id);
 350			engine_mask |= BIT(VCS1);
 351		}
 352		if (data & GEN9_GRDOM_GUC) {
 353			gvt_dbg_mmio("vgpu%d: request GUC Reset\n", vgpu->id);
 354			vgpu_vreg_t(vgpu, GUC_STATUS) |= GS_MIA_IN_RESET;
 355		}
 356		engine_mask &= vgpu->gvt->gt->info.engine_mask;
 357	}
 358
 359	/* vgpu_lock already hold by emulate mmio r/w */
 360	intel_gvt_reset_vgpu_locked(vgpu, false, engine_mask);
 361
 362	/* sw will wait for the device to ack the reset request */
 363	vgpu_vreg(vgpu, offset) = 0;
 364
 365	return 0;
 366}
 367
 368static int gmbus_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
 369		void *p_data, unsigned int bytes)
 370{
 371	return intel_gvt_i2c_handle_gmbus_read(vgpu, offset, p_data, bytes);
 372}
 373
 374static int gmbus_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
 375		void *p_data, unsigned int bytes)
 376{
 377	return intel_gvt_i2c_handle_gmbus_write(vgpu, offset, p_data, bytes);
 378}
 379
 380static int pch_pp_control_mmio_write(struct intel_vgpu *vgpu,
 381		unsigned int offset, void *p_data, unsigned int bytes)
 382{
 383	write_vreg(vgpu, offset, p_data, bytes);
 384
 385	if (vgpu_vreg(vgpu, offset) & PANEL_POWER_ON) {
 386		vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_ON;
 387		vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_SEQUENCE_STATE_ON_IDLE;
 388		vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_SEQUENCE_POWER_DOWN;
 389		vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_CYCLE_DELAY_ACTIVE;
 390
 391	} else
 392		vgpu_vreg_t(vgpu, PCH_PP_STATUS) &=
 393			~(PP_ON | PP_SEQUENCE_POWER_DOWN
 394					| PP_CYCLE_DELAY_ACTIVE);
 395	return 0;
 396}
 397
 398static int transconf_mmio_write(struct intel_vgpu *vgpu,
 399		unsigned int offset, void *p_data, unsigned int bytes)
 400{
 401	write_vreg(vgpu, offset, p_data, bytes);
 402
 403	if (vgpu_vreg(vgpu, offset) & TRANS_ENABLE)
 404		vgpu_vreg(vgpu, offset) |= TRANS_STATE_ENABLE;
 405	else
 406		vgpu_vreg(vgpu, offset) &= ~TRANS_STATE_ENABLE;
 407	return 0;
 408}
 409
 410static int lcpll_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
 411		void *p_data, unsigned int bytes)
 412{
 413	write_vreg(vgpu, offset, p_data, bytes);
 414
 415	if (vgpu_vreg(vgpu, offset) & LCPLL_PLL_DISABLE)
 416		vgpu_vreg(vgpu, offset) &= ~LCPLL_PLL_LOCK;
 417	else
 418		vgpu_vreg(vgpu, offset) |= LCPLL_PLL_LOCK;
 419
 420	if (vgpu_vreg(vgpu, offset) & LCPLL_CD_SOURCE_FCLK)
 421		vgpu_vreg(vgpu, offset) |= LCPLL_CD_SOURCE_FCLK_DONE;
 422	else
 423		vgpu_vreg(vgpu, offset) &= ~LCPLL_CD_SOURCE_FCLK_DONE;
 424
 425	return 0;
 426}
 427
 428static int dpy_reg_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
 429		void *p_data, unsigned int bytes)
 430{
 431	switch (offset) {
 432	case 0xe651c:
 433	case 0xe661c:
 434	case 0xe671c:
 435	case 0xe681c:
 436		vgpu_vreg(vgpu, offset) = 1 << 17;
 437		break;
 438	case 0xe6c04:
 439		vgpu_vreg(vgpu, offset) = 0x3;
 440		break;
 441	case 0xe6e1c:
 442		vgpu_vreg(vgpu, offset) = 0x2f << 16;
 443		break;
 444	default:
 445		return -EINVAL;
 446	}
 447
 448	read_vreg(vgpu, offset, p_data, bytes);
 449	return 0;
 450}
 451
 452/*
 453 * Only PIPE_A is enabled in current vGPU display and PIPE_A is tied to
 454 *   TRANSCODER_A in HW. DDI/PORT could be PORT_x depends on
 455 *   setup_virtual_dp_monitor().
 456 * emulate_monitor_status_change() set up PLL for PORT_x as the initial enabled
 457 *   DPLL. Later guest driver may setup a different DPLLx when setting mode.
 458 * So the correct sequence to find DP stream clock is:
 459 *   Check TRANS_DDI_FUNC_CTL on TRANSCODER_A to get PORT_x.
 460 *   Check correct PLLx for PORT_x to get PLL frequency and DP bitrate.
 461 * Then Refresh rate then can be calculated based on follow equations:
 462 *   Pixel clock = h_total * v_total * refresh_rate
 463 *   stream clock = Pixel clock
 464 *   ls_clk = DP bitrate
 465 *   Link M/N = strm_clk / ls_clk
 466 */
 467
 468static u32 bdw_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port)
 469{
 470	u32 dp_br = 0;
 471	u32 ddi_pll_sel = vgpu_vreg_t(vgpu, PORT_CLK_SEL(port));
 472
 473	switch (ddi_pll_sel) {
 474	case PORT_CLK_SEL_LCPLL_2700:
 475		dp_br = 270000 * 2;
 476		break;
 477	case PORT_CLK_SEL_LCPLL_1350:
 478		dp_br = 135000 * 2;
 479		break;
 480	case PORT_CLK_SEL_LCPLL_810:
 481		dp_br = 81000 * 2;
 482		break;
 483	case PORT_CLK_SEL_SPLL:
 484	{
 485		switch (vgpu_vreg_t(vgpu, SPLL_CTL) & SPLL_FREQ_MASK) {
 486		case SPLL_FREQ_810MHz:
 487			dp_br = 81000 * 2;
 488			break;
 489		case SPLL_FREQ_1350MHz:
 490			dp_br = 135000 * 2;
 491			break;
 492		case SPLL_FREQ_2700MHz:
 493			dp_br = 270000 * 2;
 494			break;
 495		default:
 496			gvt_dbg_dpy("vgpu-%d PORT_%c can't get freq from SPLL 0x%08x\n",
 497				    vgpu->id, port_name(port), vgpu_vreg_t(vgpu, SPLL_CTL));
 498			break;
 499		}
 500		break;
 501	}
 502	case PORT_CLK_SEL_WRPLL1:
 503	case PORT_CLK_SEL_WRPLL2:
 504	{
 505		u32 wrpll_ctl;
 506		int refclk, n, p, r;
 507
 508		if (ddi_pll_sel == PORT_CLK_SEL_WRPLL1)
 509			wrpll_ctl = vgpu_vreg_t(vgpu, WRPLL_CTL(DPLL_ID_WRPLL1));
 510		else
 511			wrpll_ctl = vgpu_vreg_t(vgpu, WRPLL_CTL(DPLL_ID_WRPLL2));
 512
 513		switch (wrpll_ctl & WRPLL_REF_MASK) {
 514		case WRPLL_REF_PCH_SSC:
 515			refclk = vgpu->gvt->gt->i915->display.dpll.ref_clks.ssc;
 516			break;
 517		case WRPLL_REF_LCPLL:
 518			refclk = 2700000;
 519			break;
 520		default:
 521			gvt_dbg_dpy("vgpu-%d PORT_%c WRPLL can't get refclk 0x%08x\n",
 522				    vgpu->id, port_name(port), wrpll_ctl);
 523			goto out;
 524		}
 525
 526		r = wrpll_ctl & WRPLL_DIVIDER_REF_MASK;
 527		p = (wrpll_ctl & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
 528		n = (wrpll_ctl & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
 529
 530		dp_br = (refclk * n / 10) / (p * r) * 2;
 531		break;
 532	}
 533	default:
 534		gvt_dbg_dpy("vgpu-%d PORT_%c has invalid clock select 0x%08x\n",
 535			    vgpu->id, port_name(port), vgpu_vreg_t(vgpu, PORT_CLK_SEL(port)));
 536		break;
 537	}
 538
 539out:
 540	return dp_br;
 541}
 542
 543static u32 bxt_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port)
 544{
 545	u32 dp_br = 0;
 546	int refclk = vgpu->gvt->gt->i915->display.dpll.ref_clks.nssc;
 547	enum dpio_phy phy = DPIO_PHY0;
 548	enum dpio_channel ch = DPIO_CH0;
 549	struct dpll clock = {};
 550	u32 temp;
 551
 552	/* Port to PHY mapping is fixed, see bxt_ddi_phy_info{} */
 553	switch (port) {
 554	case PORT_A:
 555		phy = DPIO_PHY1;
 556		ch = DPIO_CH0;
 557		break;
 558	case PORT_B:
 559		phy = DPIO_PHY0;
 560		ch = DPIO_CH0;
 561		break;
 562	case PORT_C:
 563		phy = DPIO_PHY0;
 564		ch = DPIO_CH1;
 565		break;
 566	default:
 567		gvt_dbg_dpy("vgpu-%d no PHY for PORT_%c\n", vgpu->id, port_name(port));
 568		goto out;
 569	}
 570
 571	temp = vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(port));
 572	if (!(temp & PORT_PLL_ENABLE) || !(temp & PORT_PLL_LOCK)) {
 573		gvt_dbg_dpy("vgpu-%d PORT_%c PLL_ENABLE 0x%08x isn't enabled or locked\n",
 574			    vgpu->id, port_name(port), temp);
 575		goto out;
 576	}
 577
 578	clock.m1 = 2;
 579	clock.m2 = REG_FIELD_GET(PORT_PLL_M2_INT_MASK,
 580				 vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 0))) << 22;
 581	if (vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 3)) & PORT_PLL_M2_FRAC_ENABLE)
 582		clock.m2 |= REG_FIELD_GET(PORT_PLL_M2_FRAC_MASK,
 583					  vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 2)));
 584	clock.n = REG_FIELD_GET(PORT_PLL_N_MASK,
 585				vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 1)));
 586	clock.p1 = REG_FIELD_GET(PORT_PLL_P1_MASK,
 587				 vgpu_vreg_t(vgpu, BXT_PORT_PLL_EBB_0(phy, ch)));
 588	clock.p2 = REG_FIELD_GET(PORT_PLL_P2_MASK,
 589				 vgpu_vreg_t(vgpu, BXT_PORT_PLL_EBB_0(phy, ch)));
 590	clock.m = clock.m1 * clock.m2;
 591	clock.p = clock.p1 * clock.p2 * 5;
 592
 593	if (clock.n == 0 || clock.p == 0) {
 594		gvt_dbg_dpy("vgpu-%d PORT_%c PLL has invalid divider\n", vgpu->id, port_name(port));
 595		goto out;
 596	}
 597
 598	clock.vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock.m), clock.n << 22);
 599	clock.dot = DIV_ROUND_CLOSEST(clock.vco, clock.p);
 600
 601	dp_br = clock.dot;
 602
 603out:
 604	return dp_br;
 605}
 606
 607static u32 skl_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port)
 608{
 609	u32 dp_br = 0;
 610	enum intel_dpll_id dpll_id = DPLL_ID_SKL_DPLL0;
 611
 612	/* Find the enabled DPLL for the DDI/PORT */
 613	if (!(vgpu_vreg_t(vgpu, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)) &&
 614	    (vgpu_vreg_t(vgpu, DPLL_CTRL2) & DPLL_CTRL2_DDI_SEL_OVERRIDE(port))) {
 615		dpll_id += (vgpu_vreg_t(vgpu, DPLL_CTRL2) &
 616			DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >>
 617			DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port);
 618	} else {
 619		gvt_dbg_dpy("vgpu-%d DPLL for PORT_%c isn't turned on\n",
 620			    vgpu->id, port_name(port));
 621		return dp_br;
 622	}
 623
 624	/* Find PLL output frequency from correct DPLL, and get bir rate */
 625	switch ((vgpu_vreg_t(vgpu, DPLL_CTRL1) &
 626		DPLL_CTRL1_LINK_RATE_MASK(dpll_id)) >>
 627		DPLL_CTRL1_LINK_RATE_SHIFT(dpll_id)) {
 628		case DPLL_CTRL1_LINK_RATE_810:
 629			dp_br = 81000 * 2;
 630			break;
 631		case DPLL_CTRL1_LINK_RATE_1080:
 632			dp_br = 108000 * 2;
 633			break;
 634		case DPLL_CTRL1_LINK_RATE_1350:
 635			dp_br = 135000 * 2;
 636			break;
 637		case DPLL_CTRL1_LINK_RATE_1620:
 638			dp_br = 162000 * 2;
 639			break;
 640		case DPLL_CTRL1_LINK_RATE_2160:
 641			dp_br = 216000 * 2;
 642			break;
 643		case DPLL_CTRL1_LINK_RATE_2700:
 644			dp_br = 270000 * 2;
 645			break;
 646		default:
 647			dp_br = 0;
 648			gvt_dbg_dpy("vgpu-%d PORT_%c fail to get DPLL-%d freq\n",
 649				    vgpu->id, port_name(port), dpll_id);
 650	}
 651
 652	return dp_br;
 653}
 654
 655static void vgpu_update_refresh_rate(struct intel_vgpu *vgpu)
 656{
 657	struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
 658	enum port port;
 659	u32 dp_br, link_m, link_n, htotal, vtotal;
 660
 661	/* Find DDI/PORT assigned to TRANSCODER_A, expect B or D */
 662	port = (vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) &
 663		TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
 664	if (port != PORT_B && port != PORT_D) {
 665		gvt_dbg_dpy("vgpu-%d unsupported PORT_%c\n", vgpu->id, port_name(port));
 666		return;
 667	}
 668
 669	/* Calculate DP bitrate from PLL */
 670	if (IS_BROADWELL(dev_priv))
 671		dp_br = bdw_vgpu_get_dp_bitrate(vgpu, port);
 672	else if (IS_BROXTON(dev_priv))
 673		dp_br = bxt_vgpu_get_dp_bitrate(vgpu, port);
 674	else
 675		dp_br = skl_vgpu_get_dp_bitrate(vgpu, port);
 676
 677	/* Get DP link symbol clock M/N */
 678	link_m = vgpu_vreg_t(vgpu, PIPE_LINK_M1(dev_priv, TRANSCODER_A));
 679	link_n = vgpu_vreg_t(vgpu, PIPE_LINK_N1(dev_priv, TRANSCODER_A));
 680
 681	/* Get H/V total from transcoder timing */
 682	htotal = (vgpu_vreg_t(vgpu, TRANS_HTOTAL(dev_priv, TRANSCODER_A)) >> TRANS_HTOTAL_SHIFT);
 683	vtotal = (vgpu_vreg_t(vgpu, TRANS_VTOTAL(dev_priv, TRANSCODER_A)) >> TRANS_VTOTAL_SHIFT);
 684
 685	if (dp_br && link_n && htotal && vtotal) {
 686		u64 pixel_clk = 0;
 687		u32 new_rate = 0;
 688		u32 *old_rate = &(intel_vgpu_port(vgpu, vgpu->display.port_num)->vrefresh_k);
 689
 690		/* Calcuate pixel clock by (ls_clk * M / N) */
 691		pixel_clk = div_u64(mul_u32_u32(link_m, dp_br), link_n);
 692		pixel_clk *= MSEC_PER_SEC;
 693
 694		/* Calcuate refresh rate by (pixel_clk / (h_total * v_total)) */
 695		new_rate = DIV64_U64_ROUND_CLOSEST(mul_u64_u32_shr(pixel_clk, MSEC_PER_SEC, 0), mul_u32_u32(htotal + 1, vtotal + 1));
 696
 697		if (*old_rate != new_rate)
 698			*old_rate = new_rate;
 699
 700		gvt_dbg_dpy("vgpu-%d PIPE_%c refresh rate updated to %d\n",
 701			    vgpu->id, pipe_name(PIPE_A), new_rate);
 702	}
 703}
 704
 705static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
 706		void *p_data, unsigned int bytes)
 707{
 708	u32 data;
 709
 710	write_vreg(vgpu, offset, p_data, bytes);
 711	data = vgpu_vreg(vgpu, offset);
 712
 713	if (data & TRANSCONF_ENABLE) {
 714		vgpu_vreg(vgpu, offset) |= TRANSCONF_STATE_ENABLE;
 715		vgpu_update_refresh_rate(vgpu);
 716		vgpu_update_vblank_emulation(vgpu, true);
 717	} else {
 718		vgpu_vreg(vgpu, offset) &= ~TRANSCONF_STATE_ENABLE;
 719		vgpu_update_vblank_emulation(vgpu, false);
 720	}
 721	return 0;
 722}
 723
 724/* sorted in ascending order */
 725static i915_reg_t force_nonpriv_white_list[] = {
 726	_MMIO(0xd80),
 727	GEN9_CS_DEBUG_MODE1, //_MMIO(0x20ec)
 728	GEN9_CTX_PREEMPT_REG,//_MMIO(0x2248)
 729	CL_PRIMITIVES_COUNT, //_MMIO(0x2340)
 730	PS_INVOCATION_COUNT, //_MMIO(0x2348)
 731	PS_DEPTH_COUNT, //_MMIO(0x2350)
 732	GEN8_CS_CHICKEN1,//_MMIO(0x2580)
 733	_MMIO(0x2690),
 734	_MMIO(0x2694),
 735	_MMIO(0x2698),
 736	_MMIO(0x2754),
 737	_MMIO(0x28a0),
 738	_MMIO(0x4de0),
 739	_MMIO(0x4de4),
 740	_MMIO(0x4dfc),
 741	GEN7_COMMON_SLICE_CHICKEN1,//_MMIO(0x7010)
 742	_MMIO(0x7014),
 743	HDC_CHICKEN0,//_MMIO(0x7300)
 744	GEN8_HDC_CHICKEN1,//_MMIO(0x7304)
 745	_MMIO(0x7700),
 746	_MMIO(0x7704),
 747	_MMIO(0x7708),
 748	_MMIO(0x770c),
 749	_MMIO(0x83a8),
 750	_MMIO(0xb110),
 751	_MMIO(0xb118),
 752	_MMIO(0xe100),
 753	_MMIO(0xe18c),
 754	_MMIO(0xe48c),
 755	_MMIO(0xe5f4),
 756	_MMIO(0x64844),
 757};
 758
 759/* a simple bsearch */
 760static inline bool in_whitelist(u32 reg)
 761{
 762	int left = 0, right = ARRAY_SIZE(force_nonpriv_white_list);
 763	i915_reg_t *array = force_nonpriv_white_list;
 764
 765	while (left < right) {
 766		int mid = (left + right)/2;
 767
 768		if (reg > array[mid].reg)
 769			left = mid + 1;
 770		else if (reg < array[mid].reg)
 771			right = mid;
 772		else
 773			return true;
 774	}
 775	return false;
 776}
 777
 778static int force_nonpriv_write(struct intel_vgpu *vgpu,
 779	unsigned int offset, void *p_data, unsigned int bytes)
 780{
 781	u32 reg_nonpriv = (*(u32 *)p_data) & REG_GENMASK(25, 2);
 782	const struct intel_engine_cs *engine =
 783		intel_gvt_render_mmio_to_engine(vgpu->gvt, offset);
 784
 785	if (bytes != 4 || !IS_ALIGNED(offset, bytes) || !engine) {
 786		gvt_err("vgpu(%d) Invalid FORCE_NONPRIV offset %x(%dB)\n",
 787			vgpu->id, offset, bytes);
 788		return -EINVAL;
 789	}
 790
 791	if (!in_whitelist(reg_nonpriv) &&
 792	    reg_nonpriv != i915_mmio_reg_offset(RING_NOPID(engine->mmio_base))) {
 793		gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x at offset %x\n",
 794			vgpu->id, reg_nonpriv, offset);
 795	} else
 796		intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes);
 797
 798	return 0;
 799}
 800
 801static int ddi_buf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
 802		void *p_data, unsigned int bytes)
 803{
 804	write_vreg(vgpu, offset, p_data, bytes);
 805
 806	if (vgpu_vreg(vgpu, offset) & DDI_BUF_CTL_ENABLE) {
 807		vgpu_vreg(vgpu, offset) &= ~DDI_BUF_IS_IDLE;
 808	} else {
 809		vgpu_vreg(vgpu, offset) |= DDI_BUF_IS_IDLE;
 810		if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E)))
 811			vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E))
 812				&= ~DP_TP_STATUS_AUTOTRAIN_DONE;
 813	}
 814	return 0;
 815}
 816
 817static int fdi_rx_iir_mmio_write(struct intel_vgpu *vgpu,
 818		unsigned int offset, void *p_data, unsigned int bytes)
 819{
 820	vgpu_vreg(vgpu, offset) &= ~*(u32 *)p_data;
 821	return 0;
 822}
 823
 824#define FDI_LINK_TRAIN_PATTERN1         0
 825#define FDI_LINK_TRAIN_PATTERN2         1
 826
 827static int fdi_auto_training_started(struct intel_vgpu *vgpu)
 828{
 829	u32 ddi_buf_ctl = vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_E));
 830	u32 rx_ctl = vgpu_vreg(vgpu, _FDI_RXA_CTL);
 831	u32 tx_ctl = vgpu_vreg_t(vgpu, DP_TP_CTL(PORT_E));
 832
 833	if ((ddi_buf_ctl & DDI_BUF_CTL_ENABLE) &&
 834			(rx_ctl & FDI_RX_ENABLE) &&
 835			(rx_ctl & FDI_AUTO_TRAINING) &&
 836			(tx_ctl & DP_TP_CTL_ENABLE) &&
 837			(tx_ctl & DP_TP_CTL_FDI_AUTOTRAIN))
 838		return 1;
 839	else
 840		return 0;
 841}
 842
 843static int check_fdi_rx_train_status(struct intel_vgpu *vgpu,
 844		enum pipe pipe, unsigned int train_pattern)
 845{
 846	i915_reg_t fdi_rx_imr, fdi_tx_ctl, fdi_rx_ctl;
 847	unsigned int fdi_rx_check_bits, fdi_tx_check_bits;
 848	unsigned int fdi_rx_train_bits, fdi_tx_train_bits;
 849	unsigned int fdi_iir_check_bits;
 850
 851	fdi_rx_imr = FDI_RX_IMR(pipe);
 852	fdi_tx_ctl = FDI_TX_CTL(pipe);
 853	fdi_rx_ctl = FDI_RX_CTL(pipe);
 854
 855	if (train_pattern == FDI_LINK_TRAIN_PATTERN1) {
 856		fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_1_CPT;
 857		fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_1;
 858		fdi_iir_check_bits = FDI_RX_BIT_LOCK;
 859	} else if (train_pattern == FDI_LINK_TRAIN_PATTERN2) {
 860		fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_2_CPT;
 861		fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_2;
 862		fdi_iir_check_bits = FDI_RX_SYMBOL_LOCK;
 863	} else {
 864		gvt_vgpu_err("Invalid train pattern %d\n", train_pattern);
 865		return -EINVAL;
 866	}
 867
 868	fdi_rx_check_bits = FDI_RX_ENABLE | fdi_rx_train_bits;
 869	fdi_tx_check_bits = FDI_TX_ENABLE | fdi_tx_train_bits;
 870
 871	/* If imr bit has been masked */
 872	if (vgpu_vreg_t(vgpu, fdi_rx_imr) & fdi_iir_check_bits)
 873		return 0;
 874
 875	if (((vgpu_vreg_t(vgpu, fdi_tx_ctl) & fdi_tx_check_bits)
 876			== fdi_tx_check_bits)
 877		&& ((vgpu_vreg_t(vgpu, fdi_rx_ctl) & fdi_rx_check_bits)
 878			== fdi_rx_check_bits))
 879		return 1;
 880	else
 881		return 0;
 882}
 883
 884#define INVALID_INDEX (~0U)
 885
 886static unsigned int calc_index(unsigned int offset, i915_reg_t _start,
 887			       i915_reg_t _next, i915_reg_t _end)
 888{
 889	u32 start = i915_mmio_reg_offset(_start);
 890	u32 next = i915_mmio_reg_offset(_next);
 891	u32 end = i915_mmio_reg_offset(_end);
 892	u32 stride = next - start;
 893
 894	if (offset < start || offset > end)
 895		return INVALID_INDEX;
 896	offset -= start;
 897	return offset / stride;
 898}
 899
 900#define FDI_RX_CTL_TO_PIPE(offset) \
 901	calc_index(offset, FDI_RX_CTL(PIPE_A), FDI_RX_CTL(PIPE_B), FDI_RX_CTL(PIPE_C))
 902
 903#define FDI_TX_CTL_TO_PIPE(offset) \
 904	calc_index(offset, FDI_TX_CTL(PIPE_A), FDI_TX_CTL(PIPE_B), FDI_TX_CTL(PIPE_C))
 905
 906#define FDI_RX_IMR_TO_PIPE(offset) \
 907	calc_index(offset, FDI_RX_IMR(PIPE_A), FDI_RX_IMR(PIPE_B), FDI_RX_IMR(PIPE_C))
 908
 909static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu,
 910		unsigned int offset, void *p_data, unsigned int bytes)
 911{
 912	i915_reg_t fdi_rx_iir;
 913	unsigned int index;
 914	int ret;
 915
 916	if (FDI_RX_CTL_TO_PIPE(offset) != INVALID_INDEX)
 917		index = FDI_RX_CTL_TO_PIPE(offset);
 918	else if (FDI_TX_CTL_TO_PIPE(offset) != INVALID_INDEX)
 919		index = FDI_TX_CTL_TO_PIPE(offset);
 920	else if (FDI_RX_IMR_TO_PIPE(offset) != INVALID_INDEX)
 921		index = FDI_RX_IMR_TO_PIPE(offset);
 922	else {
 923		gvt_vgpu_err("Unsupported registers %x\n", offset);
 924		return -EINVAL;
 925	}
 926
 927	write_vreg(vgpu, offset, p_data, bytes);
 928
 929	fdi_rx_iir = FDI_RX_IIR(index);
 930
 931	ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN1);
 932	if (ret < 0)
 933		return ret;
 934	if (ret)
 935		vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_BIT_LOCK;
 936
 937	ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN2);
 938	if (ret < 0)
 939		return ret;
 940	if (ret)
 941		vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_SYMBOL_LOCK;
 942
 943	if (offset == _FDI_RXA_CTL)
 944		if (fdi_auto_training_started(vgpu))
 945			vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) |=
 946				DP_TP_STATUS_AUTOTRAIN_DONE;
 947	return 0;
 948}
 949
 950#define DP_TP_CTL_TO_PORT(offset) \
 951	calc_index(offset, DP_TP_CTL(PORT_A), DP_TP_CTL(PORT_B), DP_TP_CTL(PORT_E))
 952
 953static int dp_tp_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
 954		void *p_data, unsigned int bytes)
 955{
 956	i915_reg_t status_reg;
 957	unsigned int index;
 958	u32 data;
 959
 960	write_vreg(vgpu, offset, p_data, bytes);
 961
 962	index = DP_TP_CTL_TO_PORT(offset);
 963	data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8;
 964	if (data == 0x2) {
 965		status_reg = DP_TP_STATUS(index);
 966		vgpu_vreg_t(vgpu, status_reg) |= (1 << 25);
 967	}
 968	return 0;
 969}
 970
 971static int dp_tp_status_mmio_write(struct intel_vgpu *vgpu,
 972		unsigned int offset, void *p_data, unsigned int bytes)
 973{
 974	u32 reg_val;
 975	u32 sticky_mask;
 976
 977	reg_val = *((u32 *)p_data);
 978	sticky_mask = GENMASK(27, 26) | (1 << 24);
 979
 980	vgpu_vreg(vgpu, offset) = (reg_val & ~sticky_mask) |
 981		(vgpu_vreg(vgpu, offset) & sticky_mask);
 982	vgpu_vreg(vgpu, offset) &= ~(reg_val & sticky_mask);
 983	return 0;
 984}
 985
 986static int pch_adpa_mmio_write(struct intel_vgpu *vgpu,
 987		unsigned int offset, void *p_data, unsigned int bytes)
 988{
 989	u32 data;
 990
 991	write_vreg(vgpu, offset, p_data, bytes);
 992	data = vgpu_vreg(vgpu, offset);
 993
 994	if (data & ADPA_CRT_HOTPLUG_FORCE_TRIGGER)
 995		vgpu_vreg(vgpu, offset) &= ~ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
 996	return 0;
 997}
 998
 999static int south_chicken2_mmio_write(struct intel_vgpu *vgpu,
1000		unsigned int offset, void *p_data, unsigned int bytes)
1001{
1002	u32 data;
1003
1004	write_vreg(vgpu, offset, p_data, bytes);
1005	data = vgpu_vreg(vgpu, offset);
1006
1007	if (data & FDI_MPHY_IOSFSB_RESET_CTL)
1008		vgpu_vreg(vgpu, offset) |= FDI_MPHY_IOSFSB_RESET_STATUS;
1009	else
1010		vgpu_vreg(vgpu, offset) &= ~FDI_MPHY_IOSFSB_RESET_STATUS;
1011	return 0;
1012}
1013
1014#define DSPSURF_TO_PIPE(dev_priv, offset) \
1015	calc_index(offset, DSPSURF(dev_priv, PIPE_A), DSPSURF(dev_priv, PIPE_B), DSPSURF(dev_priv, PIPE_C))
1016
1017static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1018		void *p_data, unsigned int bytes)
1019{
1020	struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
1021	u32 pipe = DSPSURF_TO_PIPE(dev_priv, offset);
1022	int event = SKL_FLIP_EVENT(pipe, PLANE_PRIMARY);
1023
1024	write_vreg(vgpu, offset, p_data, bytes);
1025	vgpu_vreg_t(vgpu, DSPSURFLIVE(dev_priv, pipe)) = vgpu_vreg(vgpu, offset);
1026
1027	vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(dev_priv, pipe))++;
1028
1029	if (vgpu_vreg_t(vgpu, DSPCNTR(dev_priv, pipe)) & PLANE_CTL_ASYNC_FLIP)
1030		intel_vgpu_trigger_virtual_event(vgpu, event);
1031	else
1032		set_bit(event, vgpu->irq.flip_done_event[pipe]);
1033
1034	return 0;
1035}
1036
1037#define SPRSURF_TO_PIPE(offset) \
1038	calc_index(offset, SPRSURF(PIPE_A), SPRSURF(PIPE_B), SPRSURF(PIPE_C))
1039
1040static int spr_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1041		void *p_data, unsigned int bytes)
1042{
1043	u32 pipe = SPRSURF_TO_PIPE(offset);
1044	int event = SKL_FLIP_EVENT(pipe, PLANE_SPRITE0);
1045
1046	write_vreg(vgpu, offset, p_data, bytes);
1047	vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
1048
1049	if (vgpu_vreg_t(vgpu, SPRCTL(pipe)) & PLANE_CTL_ASYNC_FLIP)
1050		intel_vgpu_trigger_virtual_event(vgpu, event);
1051	else
1052		set_bit(event, vgpu->irq.flip_done_event[pipe]);
1053
1054	return 0;
1055}
1056
1057static int reg50080_mmio_write(struct intel_vgpu *vgpu,
1058			       unsigned int offset, void *p_data,
1059			       unsigned int bytes)
1060{
1061	struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
1062	enum pipe pipe = REG_50080_TO_PIPE(offset);
1063	enum plane_id plane = REG_50080_TO_PLANE(offset);
1064	int event = SKL_FLIP_EVENT(pipe, plane);
1065
1066	write_vreg(vgpu, offset, p_data, bytes);
1067	if (plane == PLANE_PRIMARY) {
1068		vgpu_vreg_t(vgpu, DSPSURFLIVE(dev_priv, pipe)) = vgpu_vreg(vgpu, offset);
1069		vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(dev_priv, pipe))++;
1070	} else {
1071		vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
1072	}
1073
1074	if ((vgpu_vreg(vgpu, offset) & REG50080_FLIP_TYPE_MASK) == REG50080_FLIP_TYPE_ASYNC)
1075		intel_vgpu_trigger_virtual_event(vgpu, event);
1076	else
1077		set_bit(event, vgpu->irq.flip_done_event[pipe]);
1078
1079	return 0;
1080}
1081
1082static int trigger_aux_channel_interrupt(struct intel_vgpu *vgpu,
1083		unsigned int reg)
1084{
1085	struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
1086	enum intel_gvt_event_type event;
1087
1088	if (reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_A)))
1089		event = AUX_CHANNEL_A;
1090	else if (reg == i915_mmio_reg_offset(PCH_DP_AUX_CH_CTL(AUX_CH_B)) ||
1091		 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_B)))
1092		event = AUX_CHANNEL_B;
1093	else if (reg == i915_mmio_reg_offset(PCH_DP_AUX_CH_CTL(AUX_CH_C)) ||
1094		 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_C)))
1095		event = AUX_CHANNEL_C;
1096	else if (reg == i915_mmio_reg_offset(PCH_DP_AUX_CH_CTL(AUX_CH_D)) ||
1097		 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_D)))
1098		event = AUX_CHANNEL_D;
1099	else {
1100		drm_WARN_ON(&dev_priv->drm, true);
1101		return -EINVAL;
1102	}
1103
1104	intel_vgpu_trigger_virtual_event(vgpu, event);
1105	return 0;
1106}
1107
1108static int dp_aux_ch_ctl_trans_done(struct intel_vgpu *vgpu, u32 value,
1109		unsigned int reg, int len, bool data_valid)
1110{
1111	/* mark transaction done */
1112	value |= DP_AUX_CH_CTL_DONE;
1113	value &= ~DP_AUX_CH_CTL_SEND_BUSY;
1114	value &= ~DP_AUX_CH_CTL_RECEIVE_ERROR;
1115
1116	if (data_valid)
1117		value &= ~DP_AUX_CH_CTL_TIME_OUT_ERROR;
1118	else
1119		value |= DP_AUX_CH_CTL_TIME_OUT_ERROR;
1120
1121	/* message size */
1122	value &= ~(0xf << 20);
1123	value |= (len << 20);
1124	vgpu_vreg(vgpu, reg) = value;
1125
1126	if (value & DP_AUX_CH_CTL_INTERRUPT)
1127		return trigger_aux_channel_interrupt(vgpu, reg);
1128	return 0;
1129}
1130
1131static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd,
1132		u8 t)
1133{
1134	if ((t & DP_TRAINING_PATTERN_MASK) == DP_TRAINING_PATTERN_1) {
1135		/* training pattern 1 for CR */
1136		/* set LANE0_CR_DONE, LANE1_CR_DONE */
1137		dpcd->data[DP_LANE0_1_STATUS] |= DP_LANE_CR_DONE |
1138			DP_LANE_CR_DONE << 4;
1139		/* set LANE2_CR_DONE, LANE3_CR_DONE */
1140		dpcd->data[DP_LANE2_3_STATUS] |= DP_LANE_CR_DONE |
1141			DP_LANE_CR_DONE << 4;
1142	} else if ((t & DP_TRAINING_PATTERN_MASK) ==
1143			DP_TRAINING_PATTERN_2) {
1144		/* training pattern 2 for EQ */
1145		/* Set CHANNEL_EQ_DONE and  SYMBOL_LOCKED for Lane0_1 */
1146		dpcd->data[DP_LANE0_1_STATUS] |= DP_LANE_CHANNEL_EQ_DONE |
1147			DP_LANE_CHANNEL_EQ_DONE << 4;
1148		dpcd->data[DP_LANE0_1_STATUS] |= DP_LANE_SYMBOL_LOCKED |
1149			DP_LANE_SYMBOL_LOCKED << 4;
1150		/* Set CHANNEL_EQ_DONE and  SYMBOL_LOCKED for Lane2_3 */
1151		dpcd->data[DP_LANE2_3_STATUS] |= DP_LANE_CHANNEL_EQ_DONE |
1152			DP_LANE_CHANNEL_EQ_DONE << 4;
1153		dpcd->data[DP_LANE2_3_STATUS] |= DP_LANE_SYMBOL_LOCKED |
1154			DP_LANE_SYMBOL_LOCKED << 4;
1155		/* set INTERLANE_ALIGN_DONE */
1156		dpcd->data[DP_LANE_ALIGN_STATUS_UPDATED] |=
1157			DP_INTERLANE_ALIGN_DONE;
1158	} else if ((t & DP_TRAINING_PATTERN_MASK) ==
1159			DP_TRAINING_PATTERN_DISABLE) {
1160		/* finish link training */
1161		/* set sink status as synchronized */
1162		dpcd->data[DP_SINK_STATUS] = DP_RECEIVE_PORT_0_STATUS |
1163			DP_RECEIVE_PORT_1_STATUS;
1164	}
1165}
1166
1167#define OFFSET_TO_DP_AUX_PORT(offset) (((offset) & 0xF00) >> 8)
1168
1169#define dpy_is_valid_port(port)	\
1170		(((port) >= PORT_A) && ((port) < I915_MAX_PORTS))
1171
1172static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu,
1173		unsigned int offset, void *p_data, unsigned int bytes)
1174{
1175	struct intel_vgpu_display *display = &vgpu->display;
1176	int msg, addr, ctrl, op, len;
1177	int port_index = OFFSET_TO_DP_AUX_PORT(offset);
1178	struct intel_vgpu_dpcd_data *dpcd = NULL;
1179	struct intel_vgpu_port *port = NULL;
1180	u32 data;
1181
1182	if (!dpy_is_valid_port(port_index)) {
1183		gvt_vgpu_err("Unsupported DP port access!\n");
1184		return 0;
1185	}
1186
1187	write_vreg(vgpu, offset, p_data, bytes);
1188	data = vgpu_vreg(vgpu, offset);
1189
1190	if (GRAPHICS_VER(vgpu->gvt->gt->i915) >= 9 &&
1191	    offset != i915_mmio_reg_offset(DP_AUX_CH_CTL(port_index))) {
1192		/* SKL DPB/C/D aux ctl register changed */
1193		return 0;
1194	} else if (IS_BROADWELL(vgpu->gvt->gt->i915) &&
1195		   offset != i915_mmio_reg_offset(port_index ?
1196						  PCH_DP_AUX_CH_CTL(port_index) :
1197						  DP_AUX_CH_CTL(port_index))) {
1198		/* write to the data registers */
1199		return 0;
1200	}
1201
1202	if (!(data & DP_AUX_CH_CTL_SEND_BUSY)) {
1203		/* just want to clear the sticky bits */
1204		vgpu_vreg(vgpu, offset) = 0;
1205		return 0;
1206	}
1207
1208	port = &display->ports[port_index];
1209	dpcd = port->dpcd;
1210
1211	/* read out message from DATA1 register */
1212	msg = vgpu_vreg(vgpu, offset + 4);
1213	addr = (msg >> 8) & 0xffff;
1214	ctrl = (msg >> 24) & 0xff;
1215	len = msg & 0xff;
1216	op = ctrl >> 4;
1217
1218	if (op == DP_AUX_NATIVE_WRITE) {
1219		int t;
1220		u8 buf[16];
1221
1222		if ((addr + len + 1) >= DPCD_SIZE) {
1223			/*
1224			 * Write request exceeds what we supported,
1225			 * DCPD spec: When a Source Device is writing a DPCD
1226			 * address not supported by the Sink Device, the Sink
1227			 * Device shall reply with AUX NACK and “M” equal to
1228			 * zero.
1229			 */
1230
1231			/* NAK the write */
1232			vgpu_vreg(vgpu, offset + 4) = AUX_NATIVE_REPLY_NAK;
1233			dp_aux_ch_ctl_trans_done(vgpu, data, offset, 2, true);
1234			return 0;
1235		}
1236
1237		/*
1238		 * Write request format: Headr (command + address + size) occupies
1239		 * 4 bytes, followed by (len + 1) bytes of data. See details at
1240		 * intel_dp_aux_transfer().
1241		 */
1242		if ((len + 1 + 4) > AUX_BURST_SIZE) {
1243			gvt_vgpu_err("dp_aux_header: len %d is too large\n", len);
1244			return -EINVAL;
1245		}
1246
1247		/* unpack data from vreg to buf */
1248		for (t = 0; t < 4; t++) {
1249			u32 r = vgpu_vreg(vgpu, offset + 8 + t * 4);
1250
1251			buf[t * 4] = (r >> 24) & 0xff;
1252			buf[t * 4 + 1] = (r >> 16) & 0xff;
1253			buf[t * 4 + 2] = (r >> 8) & 0xff;
1254			buf[t * 4 + 3] = r & 0xff;
1255		}
1256
1257		/* write to virtual DPCD */
1258		if (dpcd && dpcd->data_valid) {
1259			for (t = 0; t <= len; t++) {
1260				int p = addr + t;
1261
1262				dpcd->data[p] = buf[t];
1263				/* check for link training */
1264				if (p == DP_TRAINING_PATTERN_SET)
1265					dp_aux_ch_ctl_link_training(dpcd,
1266							buf[t]);
1267			}
1268		}
1269
1270		/* ACK the write */
1271		vgpu_vreg(vgpu, offset + 4) = 0;
1272		dp_aux_ch_ctl_trans_done(vgpu, data, offset, 1,
1273				dpcd && dpcd->data_valid);
1274		return 0;
1275	}
1276
1277	if (op == DP_AUX_NATIVE_READ) {
1278		int idx, i, ret = 0;
1279
1280		if ((addr + len + 1) >= DPCD_SIZE) {
1281			/*
1282			 * read request exceeds what we supported
1283			 * DPCD spec: A Sink Device receiving a Native AUX CH
1284			 * read request for an unsupported DPCD address must
1285			 * reply with an AUX ACK and read data set equal to
1286			 * zero instead of replying with AUX NACK.
1287			 */
1288
1289			/* ACK the READ*/
1290			vgpu_vreg(vgpu, offset + 4) = 0;
1291			vgpu_vreg(vgpu, offset + 8) = 0;
1292			vgpu_vreg(vgpu, offset + 12) = 0;
1293			vgpu_vreg(vgpu, offset + 16) = 0;
1294			vgpu_vreg(vgpu, offset + 20) = 0;
1295
1296			dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2,
1297					true);
1298			return 0;
1299		}
1300
1301		for (idx = 1; idx <= 5; idx++) {
1302			/* clear the data registers */
1303			vgpu_vreg(vgpu, offset + 4 * idx) = 0;
1304		}
1305
1306		/*
1307		 * Read reply format: ACK (1 byte) plus (len + 1) bytes of data.
1308		 */
1309		if ((len + 2) > AUX_BURST_SIZE) {
1310			gvt_vgpu_err("dp_aux_header: len %d is too large\n", len);
1311			return -EINVAL;
1312		}
1313
1314		/* read from virtual DPCD to vreg */
1315		/* first 4 bytes: [ACK][addr][addr+1][addr+2] */
1316		if (dpcd && dpcd->data_valid) {
1317			for (i = 1; i <= (len + 1); i++) {
1318				int t;
1319
1320				t = dpcd->data[addr + i - 1];
1321				t <<= (24 - 8 * (i % 4));
1322				ret |= t;
1323
1324				if ((i % 4 == 3) || (i == (len + 1))) {
1325					vgpu_vreg(vgpu, offset +
1326							(i / 4 + 1) * 4) = ret;
1327					ret = 0;
1328				}
1329			}
1330		}
1331		dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2,
1332				dpcd && dpcd->data_valid);
1333		return 0;
1334	}
1335
1336	/* i2c transaction starts */
1337	intel_gvt_i2c_handle_aux_ch_write(vgpu, port_index, offset, p_data);
1338
1339	if (data & DP_AUX_CH_CTL_INTERRUPT)
1340		trigger_aux_channel_interrupt(vgpu, offset);
1341	return 0;
1342}
1343
1344static int mbctl_write(struct intel_vgpu *vgpu, unsigned int offset,
1345		void *p_data, unsigned int bytes)
1346{
1347	*(u32 *)p_data &= (~GEN6_MBCTL_ENABLE_BOOT_FETCH);
1348	write_vreg(vgpu, offset, p_data, bytes);
1349	return 0;
1350}
1351
1352static int vga_control_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1353		void *p_data, unsigned int bytes)
1354{
1355	bool vga_disable;
1356
1357	write_vreg(vgpu, offset, p_data, bytes);
1358	vga_disable = vgpu_vreg(vgpu, offset) & VGA_DISP_DISABLE;
1359
1360	gvt_dbg_core("vgpu%d: %s VGA mode\n", vgpu->id,
1361			vga_disable ? "Disable" : "Enable");
1362	return 0;
1363}
1364
1365static u32 read_virtual_sbi_register(struct intel_vgpu *vgpu,
1366		unsigned int sbi_offset)
1367{
1368	struct intel_vgpu_display *display = &vgpu->display;
1369	int num = display->sbi.number;
1370	int i;
1371
1372	for (i = 0; i < num; ++i)
1373		if (display->sbi.registers[i].offset == sbi_offset)
1374			break;
1375
1376	if (i == num)
1377		return 0;
1378
1379	return display->sbi.registers[i].value;
1380}
1381
1382static void write_virtual_sbi_register(struct intel_vgpu *vgpu,
1383		unsigned int offset, u32 value)
1384{
1385	struct intel_vgpu_display *display = &vgpu->display;
1386	int num = display->sbi.number;
1387	int i;
1388
1389	for (i = 0; i < num; ++i) {
1390		if (display->sbi.registers[i].offset == offset)
1391			break;
1392	}
1393
1394	if (i == num) {
1395		if (num == SBI_REG_MAX) {
1396			gvt_vgpu_err("SBI caching meets maximum limits\n");
1397			return;
1398		}
1399		display->sbi.number++;
1400	}
1401
1402	display->sbi.registers[i].offset = offset;
1403	display->sbi.registers[i].value = value;
1404}
1405
1406static int sbi_data_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
1407		void *p_data, unsigned int bytes)
1408{
1409	if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >>
1410				SBI_OPCODE_SHIFT) == SBI_CMD_CRRD) {
1411		unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) &
1412				SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT;
1413		vgpu_vreg(vgpu, offset) = read_virtual_sbi_register(vgpu,
1414				sbi_offset);
1415	}
1416	read_vreg(vgpu, offset, p_data, bytes);
1417	return 0;
1418}
1419
1420static int sbi_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1421		void *p_data, unsigned int bytes)
1422{
1423	u32 data;
1424
1425	write_vreg(vgpu, offset, p_data, bytes);
1426	data = vgpu_vreg(vgpu, offset);
1427
1428	data &= ~(SBI_STAT_MASK << SBI_STAT_SHIFT);
1429	data |= SBI_READY;
1430
1431	data &= ~(SBI_RESPONSE_MASK << SBI_RESPONSE_SHIFT);
1432	data |= SBI_RESPONSE_SUCCESS;
1433
1434	vgpu_vreg(vgpu, offset) = data;
1435
1436	if (((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >>
1437				SBI_OPCODE_SHIFT) == SBI_CMD_CRWR) {
1438		unsigned int sbi_offset = (vgpu_vreg_t(vgpu, SBI_ADDR) &
1439				SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT;
1440
1441		write_virtual_sbi_register(vgpu, sbi_offset,
1442					   vgpu_vreg_t(vgpu, SBI_DATA));
1443	}
1444	return 0;
1445}
1446
1447#define _vgtif_reg(x) \
1448	(VGT_PVINFO_PAGE + offsetof(struct vgt_if, x))
1449
1450static int pvinfo_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
1451		void *p_data, unsigned int bytes)
1452{
1453	bool invalid_read = false;
1454
1455	read_vreg(vgpu, offset, p_data, bytes);
1456
1457	switch (offset) {
1458	case _vgtif_reg(magic) ... _vgtif_reg(vgt_id):
1459		if (offset + bytes > _vgtif_reg(vgt_id) + 4)
1460			invalid_read = true;
1461		break;
1462	case _vgtif_reg(avail_rs.mappable_gmadr.base) ...
1463		_vgtif_reg(avail_rs.fence_num):
1464		if (offset + bytes >
1465			_vgtif_reg(avail_rs.fence_num) + 4)
1466			invalid_read = true;
1467		break;
1468	case 0x78010:	/* vgt_caps */
1469	case 0x7881c:
1470		break;
1471	default:
1472		invalid_read = true;
1473		break;
1474	}
1475	if (invalid_read)
1476		gvt_vgpu_err("invalid pvinfo read: [%x:%x] = %x\n",
1477				offset, bytes, *(u32 *)p_data);
1478	vgpu->pv_notified = true;
1479	return 0;
1480}
1481
1482static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification)
1483{
1484	enum intel_gvt_gtt_type root_entry_type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY;
1485	struct intel_vgpu_mm *mm;
1486	u64 *pdps;
1487
1488	pdps = (u64 *)&vgpu_vreg64_t(vgpu, vgtif_reg(pdp[0]));
1489
1490	switch (notification) {
1491	case VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE:
1492		root_entry_type = GTT_TYPE_PPGTT_ROOT_L3_ENTRY;
1493		fallthrough;
1494	case VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE:
1495		mm = intel_vgpu_get_ppgtt_mm(vgpu, root_entry_type, pdps);
1496		return PTR_ERR_OR_ZERO(mm);
1497	case VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY:
1498	case VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY:
1499		return intel_vgpu_put_ppgtt_mm(vgpu, pdps);
1500	case VGT_G2V_EXECLIST_CONTEXT_CREATE:
1501	case VGT_G2V_EXECLIST_CONTEXT_DESTROY:
1502	case 1:	/* Remove this in guest driver. */
1503		break;
1504	default:
1505		gvt_vgpu_err("Invalid PV notification %d\n", notification);
1506	}
1507	return 0;
1508}
1509
1510static int send_display_ready_uevent(struct intel_vgpu *vgpu, int ready)
1511{
1512	struct kobject *kobj = &vgpu->gvt->gt->i915->drm.primary->kdev->kobj;
1513	char *env[3] = {NULL, NULL, NULL};
1514	char vmid_str[20];
1515	char display_ready_str[20];
1516
1517	snprintf(display_ready_str, 20, "GVT_DISPLAY_READY=%d", ready);
1518	env[0] = display_ready_str;
1519
1520	snprintf(vmid_str, 20, "VMID=%d", vgpu->id);
1521	env[1] = vmid_str;
1522
1523	return kobject_uevent_env(kobj, KOBJ_ADD, env);
1524}
1525
1526static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1527		void *p_data, unsigned int bytes)
1528{
1529	u32 data = *(u32 *)p_data;
1530	bool invalid_write = false;
1531
1532	switch (offset) {
1533	case _vgtif_reg(display_ready):
1534		send_display_ready_uevent(vgpu, data ? 1 : 0);
1535		break;
1536	case _vgtif_reg(g2v_notify):
1537		handle_g2v_notification(vgpu, data);
1538		break;
1539	/* add xhot and yhot to handled list to avoid error log */
1540	case _vgtif_reg(cursor_x_hot):
1541	case _vgtif_reg(cursor_y_hot):
1542	case _vgtif_reg(pdp[0].lo):
1543	case _vgtif_reg(pdp[0].hi):
1544	case _vgtif_reg(pdp[1].lo):
1545	case _vgtif_reg(pdp[1].hi):
1546	case _vgtif_reg(pdp[2].lo):
1547	case _vgtif_reg(pdp[2].hi):
1548	case _vgtif_reg(pdp[3].lo):
1549	case _vgtif_reg(pdp[3].hi):
1550	case _vgtif_reg(execlist_context_descriptor_lo):
1551	case _vgtif_reg(execlist_context_descriptor_hi):
1552		break;
1553	case _vgtif_reg(rsv5[0])..._vgtif_reg(rsv5[3]):
1554		invalid_write = true;
1555		enter_failsafe_mode(vgpu, GVT_FAILSAFE_INSUFFICIENT_RESOURCE);
1556		break;
1557	default:
1558		invalid_write = true;
1559		gvt_vgpu_err("invalid pvinfo write offset %x bytes %x data %x\n",
1560				offset, bytes, data);
1561		break;
1562	}
1563
1564	if (!invalid_write)
1565		write_vreg(vgpu, offset, p_data, bytes);
1566
1567	return 0;
1568}
1569
1570static int pf_write(struct intel_vgpu *vgpu,
1571		unsigned int offset, void *p_data, unsigned int bytes)
1572{
1573	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
1574	u32 val = *(u32 *)p_data;
1575
1576	if ((offset == _PS_1A_CTRL || offset == _PS_2A_CTRL ||
1577	   offset == _PS_1B_CTRL || offset == _PS_2B_CTRL ||
1578	   offset == _PS_1C_CTRL) && (val & PS_BINDING_MASK) != PS_BINDING_PIPE) {
1579		drm_WARN_ONCE(&i915->drm, true,
1580			      "VM(%d): guest is trying to scaling a plane\n",
1581			      vgpu->id);
1582		return 0;
1583	}
1584
1585	return intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes);
1586}
1587
1588static int power_well_ctl_mmio_write(struct intel_vgpu *vgpu,
1589		unsigned int offset, void *p_data, unsigned int bytes)
1590{
1591	write_vreg(vgpu, offset, p_data, bytes);
1592
1593	if (vgpu_vreg(vgpu, offset) &
1594	    HSW_PWR_WELL_CTL_REQ(HSW_PW_CTL_IDX_GLOBAL))
1595		vgpu_vreg(vgpu, offset) |=
1596			HSW_PWR_WELL_CTL_STATE(HSW_PW_CTL_IDX_GLOBAL);
1597	else
1598		vgpu_vreg(vgpu, offset) &=
1599			~HSW_PWR_WELL_CTL_STATE(HSW_PW_CTL_IDX_GLOBAL);
1600	return 0;
1601}
1602
1603static int gen9_dbuf_ctl_mmio_write(struct intel_vgpu *vgpu,
1604		unsigned int offset, void *p_data, unsigned int bytes)
1605{
1606	write_vreg(vgpu, offset, p_data, bytes);
1607
1608	if (vgpu_vreg(vgpu, offset) & DBUF_POWER_REQUEST)
1609		vgpu_vreg(vgpu, offset) |= DBUF_POWER_STATE;
1610	else
1611		vgpu_vreg(vgpu, offset) &= ~DBUF_POWER_STATE;
1612
1613	return 0;
1614}
1615
1616static int fpga_dbg_mmio_write(struct intel_vgpu *vgpu,
1617	unsigned int offset, void *p_data, unsigned int bytes)
1618{
1619	write_vreg(vgpu, offset, p_data, bytes);
1620
1621	if (vgpu_vreg(vgpu, offset) & FPGA_DBG_RM_NOCLAIM)
1622		vgpu_vreg(vgpu, offset) &= ~FPGA_DBG_RM_NOCLAIM;
1623	return 0;
1624}
1625
1626static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset,
1627		void *p_data, unsigned int bytes)
1628{
1629	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
1630	u32 mode;
1631
1632	write_vreg(vgpu, offset, p_data, bytes);
1633	mode = vgpu_vreg(vgpu, offset);
1634
1635	if (GFX_MODE_BIT_SET_IN_MASK(mode, START_DMA)) {
1636		drm_WARN_ONCE(&i915->drm, 1,
1637				"VM(%d): iGVT-g doesn't support GuC\n",
1638				vgpu->id);
1639		return 0;
1640	}
1641
1642	return 0;
1643}
1644
1645static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset,
1646		void *p_data, unsigned int bytes)
1647{
1648	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
1649	u32 trtte = *(u32 *)p_data;
1650
1651	if ((trtte & 1) && (trtte & (1 << 1)) == 0) {
1652		drm_WARN(&i915->drm, 1,
1653				"VM(%d): Use physical address for TRTT!\n",
1654				vgpu->id);
1655		return -EINVAL;
1656	}
1657	write_vreg(vgpu, offset, p_data, bytes);
1658
1659	return 0;
1660}
1661
1662static int gen9_trtt_chicken_write(struct intel_vgpu *vgpu, unsigned int offset,
1663		void *p_data, unsigned int bytes)
1664{
1665	write_vreg(vgpu, offset, p_data, bytes);
1666	return 0;
1667}
1668
1669static int dpll_status_read(struct intel_vgpu *vgpu, unsigned int offset,
1670		void *p_data, unsigned int bytes)
1671{
1672	u32 v = 0;
1673
1674	if (vgpu_vreg(vgpu, 0x46010) & (1 << 31))
1675		v |= (1 << 0);
1676
1677	if (vgpu_vreg(vgpu, 0x46014) & (1 << 31))
1678		v |= (1 << 8);
1679
1680	if (vgpu_vreg(vgpu, 0x46040) & (1 << 31))
1681		v |= (1 << 16);
1682
1683	if (vgpu_vreg(vgpu, 0x46060) & (1 << 31))
1684		v |= (1 << 24);
1685
1686	vgpu_vreg(vgpu, offset) = v;
1687
1688	return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
1689}
1690
1691static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset,
1692		void *p_data, unsigned int bytes)
1693{
1694	u32 value = *(u32 *)p_data;
1695	u32 cmd = value & 0xff;
1696	u32 *data0 = &vgpu_vreg_t(vgpu, GEN6_PCODE_DATA);
1697
1698	switch (cmd) {
1699	case GEN9_PCODE_READ_MEM_LATENCY:
1700		if (IS_SKYLAKE(vgpu->gvt->gt->i915) ||
1701		    IS_KABYLAKE(vgpu->gvt->gt->i915) ||
1702		    IS_COFFEELAKE(vgpu->gvt->gt->i915) ||
1703		    IS_COMETLAKE(vgpu->gvt->gt->i915)) {
1704			/**
1705			 * "Read memory latency" command on gen9.
1706			 * Below memory latency values are read
1707			 * from skylake platform.
1708			 */
1709			if (!*data0)
1710				*data0 = 0x1e1a1100;
1711			else
1712				*data0 = 0x61514b3d;
1713		} else if (IS_BROXTON(vgpu->gvt->gt->i915)) {
1714			/**
1715			 * "Read memory latency" command on gen9.
1716			 * Below memory latency values are read
1717			 * from Broxton MRB.
1718			 */
1719			if (!*data0)
1720				*data0 = 0x16080707;
1721			else
1722				*data0 = 0x16161616;
1723		}
1724		break;
1725	case SKL_PCODE_CDCLK_CONTROL:
1726		if (IS_SKYLAKE(vgpu->gvt->gt->i915) ||
1727		    IS_KABYLAKE(vgpu->gvt->gt->i915) ||
1728		    IS_COFFEELAKE(vgpu->gvt->gt->i915) ||
1729		    IS_COMETLAKE(vgpu->gvt->gt->i915))
1730			*data0 = SKL_CDCLK_READY_FOR_CHANGE;
1731		break;
1732	case GEN6_PCODE_READ_RC6VIDS:
1733		*data0 |= 0x1;
1734		break;
1735	}
1736
1737	gvt_dbg_core("VM(%d) write %x to mailbox, return data0 %x\n",
1738		     vgpu->id, value, *data0);
1739	/**
1740	 * PCODE_READY clear means ready for pcode read/write,
1741	 * PCODE_ERROR_MASK clear means no error happened. In GVT-g we
1742	 * always emulate as pcode read/write success and ready for access
1743	 * anytime, since we don't touch real physical registers here.
1744	 */
1745	value &= ~(GEN6_PCODE_READY | GEN6_PCODE_ERROR_MASK);
1746	return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes);
1747}
1748
1749static int hws_pga_write(struct intel_vgpu *vgpu, unsigned int offset,
1750		void *p_data, unsigned int bytes)
1751{
1752	u32 value = *(u32 *)p_data;
1753	const struct intel_engine_cs *engine =
1754		intel_gvt_render_mmio_to_engine(vgpu->gvt, offset);
1755
1756	if (value != 0 &&
1757	    !intel_gvt_ggtt_validate_range(vgpu, value, I915_GTT_PAGE_SIZE)) {
1758		gvt_vgpu_err("write invalid HWSP address, reg:0x%x, value:0x%x\n",
1759			      offset, value);
1760		return -EINVAL;
1761	}
1762
1763	/*
1764	 * Need to emulate all the HWSP register write to ensure host can
1765	 * update the VM CSB status correctly. Here listed registers can
1766	 * support BDW, SKL or other platforms with same HWSP registers.
1767	 */
1768	if (unlikely(!engine)) {
1769		gvt_vgpu_err("access unknown hardware status page register:0x%x\n",
1770			     offset);
1771		return -EINVAL;
1772	}
1773	vgpu->hws_pga[engine->id] = value;
1774	gvt_dbg_mmio("VM(%d) write: 0x%x to HWSP: 0x%x\n",
1775		     vgpu->id, value, offset);
1776
1777	return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes);
1778}
1779
1780static int skl_power_well_ctl_write(struct intel_vgpu *vgpu,
1781		unsigned int offset, void *p_data, unsigned int bytes)
1782{
1783	u32 v = *(u32 *)p_data;
1784
1785	if (IS_BROXTON(vgpu->gvt->gt->i915))
1786		v &= (1 << 31) | (1 << 29);
1787	else
1788		v &= (1 << 31) | (1 << 29) | (1 << 9) |
1789			(1 << 7) | (1 << 5) | (1 << 3) | (1 << 1);
1790	v |= (v >> 1);
1791
1792	return intel_vgpu_default_mmio_write(vgpu, offset, &v, bytes);
1793}
1794
1795static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset,
1796		void *p_data, unsigned int bytes)
1797{
1798	u32 v = *(u32 *)p_data;
1799
1800	/* other bits are MBZ. */
1801	v &= (1 << 31) | (1 << 30);
1802	v & (1 << 31) ? (v |= (1 << 30)) : (v &= ~(1 << 30));
1803
1804	vgpu_vreg(vgpu, offset) = v;
1805
1806	return 0;
1807}
1808
1809static int bxt_de_pll_enable_write(struct intel_vgpu *vgpu,
1810		unsigned int offset, void *p_data, unsigned int bytes)
1811{
1812	u32 v = *(u32 *)p_data;
1813
1814	if (v & BXT_DE_PLL_PLL_ENABLE)
1815		v |= BXT_DE_PLL_LOCK;
1816
1817	vgpu_vreg(vgpu, offset) = v;
1818
1819	return 0;
1820}
1821
1822static int bxt_port_pll_enable_write(struct intel_vgpu *vgpu,
1823		unsigned int offset, void *p_data, unsigned int bytes)
1824{
1825	u32 v = *(u32 *)p_data;
1826
1827	if (v & PORT_PLL_ENABLE)
1828		v |= PORT_PLL_LOCK;
1829
1830	vgpu_vreg(vgpu, offset) = v;
1831
1832	return 0;
1833}
1834
1835static int bxt_phy_ctl_family_write(struct intel_vgpu *vgpu,
1836		unsigned int offset, void *p_data, unsigned int bytes)
1837{
1838	u32 v = *(u32 *)p_data;
1839	u32 data = v & COMMON_RESET_DIS ? BXT_PHY_LANE_ENABLED : 0;
1840
1841	switch (offset) {
1842	case _PHY_CTL_FAMILY_EDP:
1843		vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_A) = data;
1844		break;
1845	case _PHY_CTL_FAMILY_DDI:
1846		vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_B) = data;
1847		vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_C) = data;
1848		break;
1849	}
1850
1851	vgpu_vreg(vgpu, offset) = v;
1852
1853	return 0;
1854}
1855
1856static int bxt_port_tx_dw3_read(struct intel_vgpu *vgpu,
1857		unsigned int offset, void *p_data, unsigned int bytes)
1858{
1859	u32 v = vgpu_vreg(vgpu, offset);
1860
1861	v &= ~UNIQUE_TRANGE_EN_METHOD;
1862
1863	vgpu_vreg(vgpu, offset) = v;
1864
1865	return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
1866}
1867
1868static int bxt_pcs_dw12_grp_write(struct intel_vgpu *vgpu,
1869		unsigned int offset, void *p_data, unsigned int bytes)
1870{
1871	u32 v = *(u32 *)p_data;
1872
1873	if (offset == _PORT_PCS_DW12_GRP_A || offset == _PORT_PCS_DW12_GRP_B) {
1874		vgpu_vreg(vgpu, offset - 0x600) = v;
1875		vgpu_vreg(vgpu, offset - 0x800) = v;
1876	} else {
1877		vgpu_vreg(vgpu, offset - 0x400) = v;
1878		vgpu_vreg(vgpu, offset - 0x600) = v;
1879	}
1880
1881	vgpu_vreg(vgpu, offset) = v;
1882
1883	return 0;
1884}
1885
1886static int bxt_gt_disp_pwron_write(struct intel_vgpu *vgpu,
1887		unsigned int offset, void *p_data, unsigned int bytes)
1888{
1889	u32 v = *(u32 *)p_data;
1890
1891	if (v & BIT(0)) {
1892		vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &=
1893			~PHY_RESERVED;
1894		vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |=
1895			PHY_POWER_GOOD;
1896	}
1897
1898	if (v & BIT(1)) {
1899		vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &=
1900			~PHY_RESERVED;
1901		vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |=
1902			PHY_POWER_GOOD;
1903	}
1904
1905
1906	vgpu_vreg(vgpu, offset) = v;
1907
1908	return 0;
1909}
1910
1911static int edp_psr_imr_iir_write(struct intel_vgpu *vgpu,
1912		unsigned int offset, void *p_data, unsigned int bytes)
1913{
1914	vgpu_vreg(vgpu, offset) = 0;
1915	return 0;
1916}
1917
1918/*
1919 * FixMe:
1920 * If guest fills non-priv batch buffer on ApolloLake/Broxton as Mesa i965 did:
1921 * 717e7539124d (i965: Use a WC map and memcpy for the batch instead of pwrite.)
1922 * Due to the missing flush of bb filled by VM vCPU, host GPU hangs on executing
1923 * these MI_BATCH_BUFFER.
1924 * Temporarily workaround this by setting SNOOP bit for PAT3 used by PPGTT
1925 * PML4 PTE: PAT(0) PCD(1) PWT(1).
1926 * The performance is still expected to be low, will need further improvement.
1927 */
1928static int bxt_ppat_low_write(struct intel_vgpu *vgpu, unsigned int offset,
1929			      void *p_data, unsigned int bytes)
1930{
1931	u64 pat =
1932		GEN8_PPAT(0, CHV_PPAT_SNOOP) |
1933		GEN8_PPAT(1, 0) |
1934		GEN8_PPAT(2, 0) |
1935		GEN8_PPAT(3, CHV_PPAT_SNOOP) |
1936		GEN8_PPAT(4, CHV_PPAT_SNOOP) |
1937		GEN8_PPAT(5, CHV_PPAT_SNOOP) |
1938		GEN8_PPAT(6, CHV_PPAT_SNOOP) |
1939		GEN8_PPAT(7, CHV_PPAT_SNOOP);
1940
1941	vgpu_vreg(vgpu, offset) = lower_32_bits(pat);
1942
1943	return 0;
1944}
1945
1946static int guc_status_read(struct intel_vgpu *vgpu,
1947			   unsigned int offset, void *p_data,
1948			   unsigned int bytes)
1949{
1950	/* keep MIA_IN_RESET before clearing */
1951	read_vreg(vgpu, offset, p_data, bytes);
1952	vgpu_vreg(vgpu, offset) &= ~GS_MIA_IN_RESET;
1953	return 0;
1954}
1955
1956static int mmio_read_from_hw(struct intel_vgpu *vgpu,
1957		unsigned int offset, void *p_data, unsigned int bytes)
1958{
1959	struct intel_gvt *gvt = vgpu->gvt;
1960	const struct intel_engine_cs *engine =
1961		intel_gvt_render_mmio_to_engine(gvt, offset);
1962
1963	/**
1964	 * Read HW reg in following case
1965	 * a. the offset isn't a ring mmio
1966	 * b. the offset's ring is running on hw.
1967	 * c. the offset is ring time stamp mmio
1968	 */
1969
1970	if (!engine ||
1971	    vgpu == gvt->scheduler.engine_owner[engine->id] ||
1972	    offset == i915_mmio_reg_offset(RING_TIMESTAMP(engine->mmio_base)) ||
1973	    offset == i915_mmio_reg_offset(RING_TIMESTAMP_UDW(engine->mmio_base))) {
1974		mmio_hw_access_pre(gvt->gt);
1975		vgpu_vreg(vgpu, offset) =
1976			intel_uncore_read(gvt->gt->uncore, _MMIO(offset));
1977		mmio_hw_access_post(gvt->gt);
1978	}
1979
1980	return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
1981}
1982
1983static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1984		void *p_data, unsigned int bytes)
1985{
1986	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
1987	const struct intel_engine_cs *engine = intel_gvt_render_mmio_to_engine(vgpu->gvt, offset);
1988	struct intel_vgpu_execlist *execlist;
1989	u32 data = *(u32 *)p_data;
1990	int ret = 0;
1991
1992	if (drm_WARN_ON(&i915->drm, !engine))
1993		return -EINVAL;
1994
1995	/*
1996	 * Due to d3_entered is used to indicate skipping PPGTT invalidation on
1997	 * vGPU reset, it's set on D0->D3 on PCI config write, and cleared after
1998	 * vGPU reset if in resuming.
1999	 * In S0ix exit, the device power state also transite from D3 to D0 as
2000	 * S3 resume, but no vGPU reset (triggered by QEMU devic model). After
2001	 * S0ix exit, all engines continue to work. However the d3_entered
2002	 * remains set which will break next vGPU reset logic (miss the expected
2003	 * PPGTT invalidation).
2004	 * Engines can only work in D0. Thus the 1st elsp write gives GVT a
2005	 * chance to clear d3_entered.
2006	 */
2007	if (vgpu->d3_entered)
2008		vgpu->d3_entered = false;
2009
2010	execlist = &vgpu->submission.execlist[engine->id];
2011
2012	execlist->elsp_dwords.data[3 - execlist->elsp_dwords.index] = data;
2013	if (execlist->elsp_dwords.index == 3) {
2014		ret = intel_vgpu_submit_execlist(vgpu, engine);
2015		if(ret)
2016			gvt_vgpu_err("fail submit workload on ring %s\n",
2017				     engine->name);
2018	}
2019
2020	++execlist->elsp_dwords.index;
2021	execlist->elsp_dwords.index &= 0x3;
2022	return ret;
2023}
2024
2025static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
2026		void *p_data, unsigned int bytes)
2027{
2028	u32 data = *(u32 *)p_data;
2029	const struct intel_engine_cs *engine =
2030		intel_gvt_render_mmio_to_engine(vgpu->gvt, offset);
2031	bool enable_execlist;
2032	int ret;
2033
2034	(*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(1);
2035	if (IS_COFFEELAKE(vgpu->gvt->gt->i915) ||
2036	    IS_COMETLAKE(vgpu->gvt->gt->i915))
2037		(*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(2);
2038	write_vreg(vgpu, offset, p_data, bytes);
2039
2040	if (IS_MASKED_BITS_ENABLED(data, 1)) {
2041		enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);
2042		return 0;
2043	}
2044
2045	if ((IS_COFFEELAKE(vgpu->gvt->gt->i915) ||
2046	     IS_COMETLAKE(vgpu->gvt->gt->i915)) &&
2047	    IS_MASKED_BITS_ENABLED(data, 2)) {
2048		enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);
2049		return 0;
2050	}
2051
2052	/* when PPGTT mode enabled, we will check if guest has called
2053	 * pvinfo, if not, we will treat this guest as non-gvtg-aware
2054	 * guest, and stop emulating its cfg space, mmio, gtt, etc.
2055	 */
2056	if ((IS_MASKED_BITS_ENABLED(data, GFX_PPGTT_ENABLE) ||
2057	    IS_MASKED_BITS_ENABLED(data, GFX_RUN_LIST_ENABLE)) &&
2058	    !vgpu->pv_notified) {
2059		enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);
2060		return 0;
2061	}
2062	if (IS_MASKED_BITS_ENABLED(data, GFX_RUN_LIST_ENABLE) ||
2063	    IS_MASKED_BITS_DISABLED(data, GFX_RUN_LIST_ENABLE)) {
2064		enable_execlist = !!(data & GFX_RUN_LIST_ENABLE);
2065
2066		gvt_dbg_core("EXECLIST %s on ring %s\n",
2067			     (enable_execlist ? "enabling" : "disabling"),
2068			     engine->name);
2069
2070		if (!enable_execlist)
2071			return 0;
2072
2073		ret = intel_vgpu_select_submission_ops(vgpu,
2074						       engine->mask,
2075						       INTEL_VGPU_EXECLIST_SUBMISSION);
2076		if (ret)
2077			return ret;
2078
2079		intel_vgpu_start_schedule(vgpu);
2080	}
2081	return 0;
2082}
2083
2084static int gvt_reg_tlb_control_handler(struct intel_vgpu *vgpu,
2085		unsigned int offset, void *p_data, unsigned int bytes)
2086{
2087	unsigned int id = 0;
2088
2089	write_vreg(vgpu, offset, p_data, bytes);
2090	vgpu_vreg(vgpu, offset) = 0;
2091
2092	switch (offset) {
2093	case 0x4260:
2094		id = RCS0;
2095		break;
2096	case 0x4264:
2097		id = VCS0;
2098		break;
2099	case 0x4268:
2100		id = VCS1;
2101		break;
2102	case 0x426c:
2103		id = BCS0;
2104		break;
2105	case 0x4270:
2106		id = VECS0;
2107		break;
2108	default:
2109		return -EINVAL;
2110	}
2111	set_bit(id, (void *)vgpu->submission.tlb_handle_pending);
2112
2113	return 0;
2114}
2115
2116static int ring_reset_ctl_write(struct intel_vgpu *vgpu,
2117	unsigned int offset, void *p_data, unsigned int bytes)
2118{
2119	u32 data;
2120
2121	write_vreg(vgpu, offset, p_data, bytes);
2122	data = vgpu_vreg(vgpu, offset);
2123
2124	if (IS_MASKED_BITS_ENABLED(data, RESET_CTL_REQUEST_RESET))
2125		data |= RESET_CTL_READY_TO_RESET;
2126	else if (data & _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET))
2127		data &= ~RESET_CTL_READY_TO_RESET;
2128
2129	vgpu_vreg(vgpu, offset) = data;
2130	return 0;
2131}
2132
2133static int csfe_chicken1_mmio_write(struct intel_vgpu *vgpu,
2134				    unsigned int offset, void *p_data,
2135				    unsigned int bytes)
2136{
2137	u32 data = *(u32 *)p_data;
2138
2139	(*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(0x18);
2140	write_vreg(vgpu, offset, p_data, bytes);
2141
2142	if (IS_MASKED_BITS_ENABLED(data, 0x10) ||
2143	    IS_MASKED_BITS_ENABLED(data, 0x8))
2144		enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);
2145
2146	return 0;
2147}
2148
2149#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
2150	ret = setup_mmio_info(gvt, i915_mmio_reg_offset(reg), \
2151		s, f, am, rm, d, r, w); \
2152	if (ret) \
2153		return ret; \
2154} while (0)
2155
2156#define MMIO_DH(reg, d, r, w) \
2157	MMIO_F(reg, 4, 0, 0, 0, d, r, w)
2158
2159#define MMIO_DFH(reg, d, f, r, w) \
2160	MMIO_F(reg, 4, f, 0, 0, d, r, w)
2161
2162#define MMIO_GM(reg, d, r, w) \
2163	MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
2164
2165#define MMIO_GM_RDR(reg, d, r, w) \
2166	MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
2167
2168#define MMIO_RO(reg, d, f, rm, r, w) \
2169	MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w)
2170
2171#define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \
2172	MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
2173	MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
2174	MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
2175	MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
2176	if (HAS_ENGINE(gvt->gt, VCS1)) \
2177		MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
2178} while (0)
2179
2180#define MMIO_RING_DFH(prefix, d, f, r, w) \
2181	MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
2182
2183#define MMIO_RING_GM(prefix, d, r, w) \
2184	MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w)
2185
2186#define MMIO_RING_GM_RDR(prefix, d, r, w) \
2187	MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w)
2188
2189#define MMIO_RING_RO(prefix, d, f, rm, r, w) \
2190	MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w)
2191
2192static int init_generic_mmio_info(struct intel_gvt *gvt)
2193{
2194	struct drm_i915_private *dev_priv = gvt->gt->i915;
2195	int ret;
2196
2197	MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
2198		intel_vgpu_reg_imr_handler);
2199
2200	MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
2201	MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
2202	MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
2203
2204	MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL);
2205
2206
2207	MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
2208		gamw_echo_dev_rw_ia_write);
2209
2210	MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
2211	MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
2212	MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
2213
2214#define RING_REG(base) _MMIO((base) + 0x28)
2215	MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
2216#undef RING_REG
2217
2218#define RING_REG(base) _MMIO((base) + 0x134)
2219	MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
2220#undef RING_REG
2221
2222#define RING_REG(base) _MMIO((base) + 0x6c)
2223	MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);
2224#undef RING_REG
2225	MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);
2226
2227	MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL);
2228	MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL);
2229	MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL);
2230
2231	MMIO_RING_DFH(RING_TAIL, D_ALL, 0, NULL, NULL);
2232	MMIO_RING_DFH(RING_HEAD, D_ALL, 0, NULL, NULL);
2233	MMIO_RING_DFH(RING_CTL, D_ALL, 0, NULL, NULL);
2234	MMIO_RING_DFH(RING_ACTHD, D_ALL, 0, mmio_read_from_hw, NULL);
2235	MMIO_RING_GM(RING_START, D_ALL, NULL, NULL);
2236
2237	/* RING MODE */
2238#define RING_REG(base) _MMIO((base) + 0x29c)
2239	MMIO_RING_DFH(RING_REG, D_ALL,
2240		F_MODE_MASK | F_CMD_ACCESS | F_CMD_WRITE_PATCH, NULL,
2241		ring_mode_mmio_write);
2242#undef RING_REG
2243
2244	MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
2245		NULL, NULL);
2246	MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
2247			NULL, NULL);
2248	MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
2249			mmio_read_from_hw, NULL);
2250	MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
2251			mmio_read_from_hw, NULL);
2252
2253	MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2254	MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
2255		NULL, NULL);
2256	MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2257	MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2258	MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2259
2260	MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2261	MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2262	MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2263	MMIO_DFH(FF_SLICE_CS_CHICKEN2, D_ALL,
2264		 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2265	MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2266	MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
2267	MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
2268		NULL, NULL);
2269	MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
2270		 NULL, NULL);
2271	MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL);
2272	MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL);
2273	MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL);
2274	MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL);
2275	MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL);
2276	MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL);
2277	MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL);
2278	MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2279	MMIO_DFH(HSW_HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2280	MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2281
2282	/* display */
2283	MMIO_DH(TRANSCONF(dev_priv, TRANSCODER_A), D_ALL, NULL,
2284		pipeconf_mmio_write);
2285	MMIO_DH(TRANSCONF(dev_priv, TRANSCODER_B), D_ALL, NULL,
2286		pipeconf_mmio_write);
2287	MMIO_DH(TRANSCONF(dev_priv, TRANSCODER_C), D_ALL, NULL,
2288		pipeconf_mmio_write);
2289	MMIO_DH(TRANSCONF(dev_priv, TRANSCODER_EDP), D_ALL, NULL,
2290		pipeconf_mmio_write);
2291	MMIO_DH(DSPSURF(dev_priv, PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
2292	MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL,
2293		reg50080_mmio_write);
2294	MMIO_DH(DSPSURF(dev_priv, PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
2295	MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL,
2296		reg50080_mmio_write);
2297	MMIO_DH(DSPSURF(dev_priv, PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
2298	MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL,
2299		reg50080_mmio_write);
2300	MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);
2301	MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL,
2302		reg50080_mmio_write);
2303	MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write);
2304	MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL,
2305		reg50080_mmio_write);
2306	MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write);
2307	MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL,
2308		reg50080_mmio_write);
2309
2310	MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
2311		gmbus_mmio_write);
2312	MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
2313
2314	MMIO_F(PCH_DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
2315	       dp_aux_ch_ctl_mmio_write);
2316	MMIO_F(PCH_DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
2317	       dp_aux_ch_ctl_mmio_write);
2318	MMIO_F(PCH_DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
2319	       dp_aux_ch_ctl_mmio_write);
2320
2321	MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write);
2322
2323	MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write);
2324	MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write);
2325
2326	MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);
2327	MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);
2328	MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write);
2329	MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
2330	MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
2331	MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
2332	MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
2333	MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
2334	MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
2335	MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write);
2336	MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL);
2337	MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL);
2338	MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL);
2339	MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL);
2340	MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL);
2341	MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL);
2342
2343	MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
2344		PORTA_HOTPLUG_STATUS_MASK
2345		| PORTB_HOTPLUG_STATUS_MASK
2346		| PORTC_HOTPLUG_STATUS_MASK
2347		| PORTD_HOTPLUG_STATUS_MASK,
2348		NULL, NULL);
2349
2350	MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write);
2351	MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write);
2352	MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL);
2353	MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL);
2354	MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write);
2355
2356	MMIO_F(DP_AUX_CH_CTL(AUX_CH_A), 6 * 4, 0, 0, 0, D_ALL, NULL,
2357	       dp_aux_ch_ctl_mmio_write);
2358
2359	MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2360	MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2361	MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2362	MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2363	MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2364
2365	MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write);
2366	MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write);
2367	MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write);
2368	MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write);
2369	MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write);
2370
2371	MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write);
2372	MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write);
2373	MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write);
2374	MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write);
2375	MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL);
2376
2377	MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL);
2378	MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL);
2379	MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL);
2380	MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL);
2381
2382	MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL);
2383	MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL);
2384	MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
2385	MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write);
2386	MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL);
2387	MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL);
2388	MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL);
2389	MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write);
2390	MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write);
2391	MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write);
2392	MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write);
2393	MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write);
2394	MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write);
2395
2396	MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write);
2397	MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write);
2398	MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write);
2399
2400	MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL);
2401	MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL);
2402
2403	MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write);
2404	MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL);
2405
2406	MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write);
2407	MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2408	MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL);
2409	MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
2410	MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL);
2411	MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
2412
2413	MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
2414	MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2415	MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2416	MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2417
2418	MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2419	MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2420	MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL);
2421
2422	MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2423	MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2424	MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2425	MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2426	MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2427	MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2428	MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2429	MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2430	MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2431	MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2432	MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2433	MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2434	MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2435	MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2436	MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2437	MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2438	MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2439
2440	MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2441	MMIO_RING_GM(RING_BBADDR, D_ALL, NULL, NULL);
2442	MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL);
2443	MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL);
2444	MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL);
2445	MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL);
2446	MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL);
2447	MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2448	MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2449	MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2450	MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2451
2452	MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
2453	MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
2454	MMIO_DH(GUC_STATUS, D_ALL, guc_status_read, NULL);
2455
2456	return 0;
2457}
2458
2459static int init_bdw_mmio_info(struct intel_gvt *gvt)
2460{
2461	int ret;
2462
2463	MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2464	MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2465	MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2466
2467	MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2468	MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2469	MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2470
2471	MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2472	MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2473	MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2474
2475	MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2476	MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2477	MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2478
2479	MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL,
2480		intel_vgpu_reg_imr_handler);
2481	MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL,
2482		intel_vgpu_reg_ier_handler);
2483	MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL,
2484		intel_vgpu_reg_iir_handler);
2485
2486	MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL,
2487		intel_vgpu_reg_imr_handler);
2488	MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL,
2489		intel_vgpu_reg_ier_handler);
2490	MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL,
2491		intel_vgpu_reg_iir_handler);
2492
2493	MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL,
2494		intel_vgpu_reg_imr_handler);
2495	MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL,
2496		intel_vgpu_reg_ier_handler);
2497	MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL,
2498		intel_vgpu_reg_iir_handler);
2499
2500	MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2501	MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2502	MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2503
2504	MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2505	MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2506	MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2507
2508	MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2509	MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2510	MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2511
2512	MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,
2513		intel_vgpu_reg_master_irq_handler);
2514
2515	MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, 0,
2516		mmio_read_from_hw, NULL);
2517
2518#define RING_REG(base) _MMIO((base) + 0xd0)
2519	MMIO_RING_F(RING_REG, 4, F_RO, 0,
2520		~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
2521		ring_reset_ctl_write);
2522#undef RING_REG
2523
2524#define RING_REG(base) _MMIO((base) + 0x230)
2525	MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write);
2526#undef RING_REG
2527
2528#define RING_REG(base) _MMIO((base) + 0x234)
2529	MMIO_RING_F(RING_REG, 8, F_RO, 0, ~0, D_BDW_PLUS,
2530		NULL, NULL);
2531#undef RING_REG
2532
2533#define RING_REG(base) _MMIO((base) + 0x244)
2534	MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2535#undef RING_REG
2536
2537#define RING_REG(base) _MMIO((base) + 0x370)
2538	MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL);
2539#undef RING_REG
2540
2541#define RING_REG(base) _MMIO((base) + 0x3a0)
2542	MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
2543#undef RING_REG
2544
2545	MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
2546
2547#define RING_REG(base) _MMIO((base) + 0x270)
2548	MMIO_RING_F(RING_REG, 32, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
2549#undef RING_REG
2550
2551	MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write);
2552
2553	MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2554
2555	MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
2556		NULL, NULL);
2557	MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
2558		NULL, NULL);
2559	MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2560
2561	MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL);
2562	MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL);
2563	MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2564	MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL);
2565	MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL);
2566
2567	MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS | F_CMD_WRITE_PATCH, 0, 0,
2568		D_BDW_PLUS, NULL, force_nonpriv_write);
2569
2570	MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL);
2571
2572	MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL);
2573
2574	MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2575	MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2576	MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2577	MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2578
2579	MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL);
2580
2581	MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2582	MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2583	MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2584	MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2585	MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2586	MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2587	MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2588	MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2589	MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2590	MMIO_DFH(_MMIO(0x21f0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2591	return 0;
2592}
2593
2594static int init_skl_mmio_info(struct intel_gvt *gvt)
2595{
2596	int ret;
2597
2598	MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2599	MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL);
2600	MMIO_DH(FORCEWAKE_GT_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2601	MMIO_DH(FORCEWAKE_ACK_GT_GEN9, D_SKL_PLUS, NULL, NULL);
2602	MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2603	MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL);
2604
2605	MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
2606						dp_aux_ch_ctl_mmio_write);
2607	MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
2608						dp_aux_ch_ctl_mmio_write);
2609	MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
2610						dp_aux_ch_ctl_mmio_write);
2611
2612	MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write);
2613
2614	MMIO_DH(DBUF_CTL_S(0), D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write);
2615
2616	MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2617	MMIO_DFH(MMCD_MISC_CTRL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2618	MMIO_DH(CHICKEN_PAR1_1, D_SKL_PLUS, NULL, NULL);
2619	MMIO_DH(LCPLL1_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
2620	MMIO_DH(LCPLL2_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
2621	MMIO_DH(DPLL_STATUS, D_SKL_PLUS, dpll_status_read, NULL);
2622
2623	MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
2624	MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
2625	MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
2626	MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
2627	MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
2628	MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
2629
2630	MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
2631	MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
2632	MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
2633	MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
2634	MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
2635	MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
2636
2637	MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
2638	MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
2639	MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
2640	MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
2641	MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
2642	MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
2643
2644	MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
2645	MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
2646	MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
2647	MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
2648
2649	MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
2650	MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
2651	MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
2652	MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
2653
2654	MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
2655	MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
2656	MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
2657	MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
2658
2659	MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL);
2660	MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL);
2661	MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL);
2662
2663	MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
2664	MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
2665	MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
2666
2667	MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
2668	MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
2669	MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
2670
2671	MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
2672	MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
2673	MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
2674
2675	MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL);
2676	MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL);
2677	MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL);
2678
2679	MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
2680	MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
2681	MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
2682	MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
2683
2684	MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
2685	MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
2686	MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
2687	MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
2688
2689	MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
2690	MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
2691	MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
2692	MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
2693
2694	MMIO_DH(PLANE_AUX_DIST(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
2695	MMIO_DH(PLANE_AUX_DIST(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
2696	MMIO_DH(PLANE_AUX_DIST(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
2697	MMIO_DH(PLANE_AUX_DIST(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
2698
2699	MMIO_DH(PLANE_AUX_DIST(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
2700	MMIO_DH(PLANE_AUX_DIST(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
2701	MMIO_DH(PLANE_AUX_DIST(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
2702	MMIO_DH(PLANE_AUX_DIST(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
2703
2704	MMIO_DH(PLANE_AUX_DIST(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
2705	MMIO_DH(PLANE_AUX_DIST(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
2706	MMIO_DH(PLANE_AUX_DIST(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
2707	MMIO_DH(PLANE_AUX_DIST(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
2708
2709	MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
2710	MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
2711	MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
2712	MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
2713
2714	MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
2715	MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
2716	MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
2717	MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
2718
2719	MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
2720	MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
2721	MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
2722	MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
2723
2724	MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2725
2726	MMIO_F(GEN9_GFX_MOCS(0), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
2727		NULL, NULL);
2728	MMIO_F(GEN7_L3CNTLREG2, 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
2729		NULL, NULL);
2730
2731	MMIO_DFH(GEN7_FF_SLICE_CS_CHICKEN1, D_SKL_PLUS,
2732		 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2733	MMIO_DFH(GEN9_CS_DEBUG_MODE1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
2734		NULL, NULL);
2735
2736	/* TRTT */
2737	MMIO_DFH(TRVATTL3PTRDW(0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2738	MMIO_DFH(TRVATTL3PTRDW(1), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2739	MMIO_DFH(TRVATTL3PTRDW(2), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2740	MMIO_DFH(TRVATTL3PTRDW(3), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2741	MMIO_DFH(TRVADR, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2742	MMIO_DFH(TRTTE, D_SKL_PLUS, F_CMD_ACCESS | F_PM_SAVE,
2743		 NULL, gen9_trtte_write);
2744	MMIO_DFH(_MMIO(0x4dfc), D_SKL_PLUS, F_PM_SAVE,
2745		 NULL, gen9_trtt_chicken_write);
2746
2747	MMIO_DFH(GEN8_GARBCNTL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2748	MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write);
2749
2750#define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4)
2751	MMIO_RING_DFH(CSFE_CHICKEN1_REG, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
2752		      NULL, csfe_chicken1_mmio_write);
2753#undef CSFE_CHICKEN1_REG
2754	MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
2755		 NULL, NULL);
2756	MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
2757		 NULL, NULL);
2758
2759	MMIO_DFH(GAMT_CHKN_BIT_REG, D_KBL | D_CFL, F_CMD_ACCESS, NULL, NULL);
2760	MMIO_DFH(_MMIO(0xe4cc), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2761
2762	return 0;
2763}
2764
2765static int init_bxt_mmio_info(struct intel_gvt *gvt)
2766{
2767	int ret;
2768
2769	MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write);
2770	MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT,
2771		NULL, bxt_phy_ctl_family_write);
2772	MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT,
2773		NULL, bxt_phy_ctl_family_write);
2774	MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT,
2775		NULL, bxt_port_pll_enable_write);
2776	MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT,
2777		NULL, bxt_port_pll_enable_write);
2778	MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL,
2779		bxt_port_pll_enable_write);
2780
2781	MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT,
2782		NULL, bxt_pcs_dw12_grp_write);
2783	MMIO_DH(BXT_PORT_TX_DW3_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT,
2784		bxt_port_tx_dw3_read, NULL);
2785	MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT,
2786		NULL, bxt_pcs_dw12_grp_write);
2787	MMIO_DH(BXT_PORT_TX_DW3_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT,
2788		bxt_port_tx_dw3_read, NULL);
2789	MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT,
2790		NULL, bxt_pcs_dw12_grp_write);
2791	MMIO_DH(BXT_PORT_TX_DW3_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT,
2792		bxt_port_tx_dw3_read, NULL);
2793	MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write);
2794	MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL);
2795	MMIO_DFH(GEN8_L3CNTLREG, D_BXT, F_CMD_ACCESS, NULL, NULL);
2796	MMIO_DFH(_MMIO(0x20D8), D_BXT, F_CMD_ACCESS, NULL, NULL);
2797	MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS,
2798	       0, 0, D_BXT, NULL, NULL);
2799	MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40, F_CMD_ACCESS,
2800	       0, 0, D_BXT, NULL, NULL);
2801	MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS,
2802	       0, 0, D_BXT, NULL, NULL);
2803	MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40, F_CMD_ACCESS,
2804	       0, 0, D_BXT, NULL, NULL);
2805
2806	MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL);
2807
2808	MMIO_DH(GEN8_PRIVATE_PAT_LO, D_BXT, NULL, bxt_ppat_low_write);
2809
2810	return 0;
2811}
2812
2813static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt,
2814					      unsigned int offset)
2815{
2816	struct gvt_mmio_block *block = gvt->mmio.mmio_block;
2817	int num = gvt->mmio.num_mmio_block;
2818	int i;
2819
2820	for (i = 0; i < num; i++, block++) {
2821		if (offset >= i915_mmio_reg_offset(block->offset) &&
2822		    offset < i915_mmio_reg_offset(block->offset) + block->size)
2823			return block;
2824	}
2825	return NULL;
2826}
2827
2828/**
2829 * intel_gvt_clean_mmio_info - clean up MMIO information table for GVT device
2830 * @gvt: GVT device
2831 *
2832 * This function is called at the driver unloading stage, to clean up the MMIO
2833 * information table of GVT device
2834 *
2835 */
2836void intel_gvt_clean_mmio_info(struct intel_gvt *gvt)
2837{
2838	struct hlist_node *tmp;
2839	struct intel_gvt_mmio_info *e;
2840	int i;
2841
2842	hash_for_each_safe(gvt->mmio.mmio_info_table, i, tmp, e, node)
2843		kfree(e);
2844
2845	kfree(gvt->mmio.mmio_block);
2846	gvt->mmio.mmio_block = NULL;
2847	gvt->mmio.num_mmio_block = 0;
2848
2849	vfree(gvt->mmio.mmio_attribute);
2850	gvt->mmio.mmio_attribute = NULL;
2851}
2852
2853static int handle_mmio(struct intel_gvt_mmio_table_iter *iter, u32 offset,
2854		       u32 size)
2855{
2856	struct intel_gvt *gvt = iter->data;
2857	struct intel_gvt_mmio_info *info, *p;
2858	u32 start, end, i;
2859
2860	if (WARN_ON(!IS_ALIGNED(offset, 4)))
2861		return -EINVAL;
2862
2863	start = offset;
2864	end = offset + size;
2865
2866	for (i = start; i < end; i += 4) {
2867		p = intel_gvt_find_mmio_info(gvt, i);
2868		if (p) {
2869			WARN(1, "dup mmio definition offset %x\n", i);
2870
2871			/* We return -EEXIST here to make GVT-g load fail.
2872			 * So duplicated MMIO can be found as soon as
2873			 * possible.
2874			 */
2875			return -EEXIST;
2876		}
2877
2878		info = kzalloc(sizeof(*info), GFP_KERNEL);
2879		if (!info)
2880			return -ENOMEM;
2881
2882		info->offset = i;
2883		info->read = intel_vgpu_default_mmio_read;
2884		info->write = intel_vgpu_default_mmio_write;
2885		INIT_HLIST_NODE(&info->node);
2886		hash_add(gvt->mmio.mmio_info_table, &info->node, info->offset);
2887		gvt->mmio.num_tracked_mmio++;
2888	}
2889	return 0;
2890}
2891
2892static int handle_mmio_block(struct intel_gvt_mmio_table_iter *iter,
2893			     u32 offset, u32 size)
2894{
2895	struct intel_gvt *gvt = iter->data;
2896	struct gvt_mmio_block *block = gvt->mmio.mmio_block;
2897	void *ret;
2898
2899	ret = krealloc(block,
2900			 (gvt->mmio.num_mmio_block + 1) * sizeof(*block),
2901			 GFP_KERNEL);
2902	if (!ret)
2903		return -ENOMEM;
2904
2905	gvt->mmio.mmio_block = block = ret;
2906
2907	block += gvt->mmio.num_mmio_block;
2908
2909	memset(block, 0, sizeof(*block));
2910
2911	block->offset = _MMIO(offset);
2912	block->size = size;
2913
2914	gvt->mmio.num_mmio_block++;
2915
2916	return 0;
2917}
2918
2919static int handle_mmio_cb(struct intel_gvt_mmio_table_iter *iter, u32 offset,
2920			  u32 size)
2921{
2922	if (size < 1024 || offset == i915_mmio_reg_offset(GEN9_GFX_MOCS(0)))
2923		return handle_mmio(iter, offset, size);
2924	else
2925		return handle_mmio_block(iter, offset, size);
2926}
2927
2928static int init_mmio_info(struct intel_gvt *gvt)
2929{
2930	struct intel_gvt_mmio_table_iter iter = {
2931		.i915 = gvt->gt->i915,
2932		.data = gvt,
2933		.handle_mmio_cb = handle_mmio_cb,
2934	};
2935
2936	return intel_gvt_iterate_mmio_table(&iter);
2937}
2938
2939static int init_mmio_block_handlers(struct intel_gvt *gvt)
2940{
2941	struct gvt_mmio_block *block;
2942
2943	block = find_mmio_block(gvt, VGT_PVINFO_PAGE);
2944	if (!block) {
2945		WARN(1, "fail to assign handlers to mmio block %x\n",
2946		     i915_mmio_reg_offset(gvt->mmio.mmio_block->offset));
2947		return -ENODEV;
2948	}
2949
2950	block->read = pvinfo_mmio_read;
2951	block->write = pvinfo_mmio_write;
2952
2953	return 0;
2954}
2955
2956/**
2957 * intel_gvt_setup_mmio_info - setup MMIO information table for GVT device
2958 * @gvt: GVT device
2959 *
2960 * This function is called at the initialization stage, to setup the MMIO
2961 * information table for GVT device
2962 *
2963 * Returns:
2964 * zero on success, negative if failed.
2965 */
2966int intel_gvt_setup_mmio_info(struct intel_gvt *gvt)
2967{
2968	struct intel_gvt_device_info *info = &gvt->device_info;
2969	struct drm_i915_private *i915 = gvt->gt->i915;
2970	int size = info->mmio_size / 4 * sizeof(*gvt->mmio.mmio_attribute);
2971	int ret;
2972
2973	gvt->mmio.mmio_attribute = vzalloc(size);
2974	if (!gvt->mmio.mmio_attribute)
2975		return -ENOMEM;
2976
2977	ret = init_mmio_info(gvt);
2978	if (ret)
2979		goto err;
2980
2981	ret = init_mmio_block_handlers(gvt);
2982	if (ret)
2983		goto err;
2984
2985	ret = init_generic_mmio_info(gvt);
2986	if (ret)
2987		goto err;
2988
2989	if (IS_BROADWELL(i915)) {
2990		ret = init_bdw_mmio_info(gvt);
2991		if (ret)
2992			goto err;
2993	} else if (IS_SKYLAKE(i915) ||
2994		   IS_KABYLAKE(i915) ||
2995		   IS_COFFEELAKE(i915) ||
2996		   IS_COMETLAKE(i915)) {
2997		ret = init_bdw_mmio_info(gvt);
2998		if (ret)
2999			goto err;
3000		ret = init_skl_mmio_info(gvt);
3001		if (ret)
3002			goto err;
3003	} else if (IS_BROXTON(i915)) {
3004		ret = init_bdw_mmio_info(gvt);
3005		if (ret)
3006			goto err;
3007		ret = init_skl_mmio_info(gvt);
3008		if (ret)
3009			goto err;
3010		ret = init_bxt_mmio_info(gvt);
3011		if (ret)
3012			goto err;
3013	}
3014
3015	return 0;
3016err:
3017	intel_gvt_clean_mmio_info(gvt);
3018	return ret;
3019}
3020
3021/**
3022 * intel_gvt_for_each_tracked_mmio - iterate each tracked mmio
3023 * @gvt: a GVT device
3024 * @handler: the handler
3025 * @data: private data given to handler
3026 *
3027 * Returns:
3028 * Zero on success, negative error code if failed.
3029 */
3030int intel_gvt_for_each_tracked_mmio(struct intel_gvt *gvt,
3031	int (*handler)(struct intel_gvt *gvt, u32 offset, void *data),
3032	void *data)
3033{
3034	struct gvt_mmio_block *block = gvt->mmio.mmio_block;
3035	struct intel_gvt_mmio_info *e;
3036	int i, j, ret;
3037
3038	hash_for_each(gvt->mmio.mmio_info_table, i, e, node) {
3039		ret = handler(gvt, e->offset, data);
3040		if (ret)
3041			return ret;
3042	}
3043
3044	for (i = 0; i < gvt->mmio.num_mmio_block; i++, block++) {
3045		/* pvinfo data doesn't come from hw mmio */
3046		if (i915_mmio_reg_offset(block->offset) == VGT_PVINFO_PAGE)
3047			continue;
3048
3049		for (j = 0; j < block->size; j += 4) {
3050			ret = handler(gvt, i915_mmio_reg_offset(block->offset) + j, data);
3051			if (ret)
3052				return ret;
3053		}
3054	}
3055	return 0;
3056}
3057
3058/**
3059 * intel_vgpu_default_mmio_read - default MMIO read handler
3060 * @vgpu: a vGPU
3061 * @offset: access offset
3062 * @p_data: data return buffer
3063 * @bytes: access data length
3064 *
3065 * Returns:
3066 * Zero on success, negative error code if failed.
3067 */
3068int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
3069		void *p_data, unsigned int bytes)
3070{
3071	read_vreg(vgpu, offset, p_data, bytes);
3072	return 0;
3073}
3074
3075/**
3076 * intel_vgpu_default_mmio_write() - default MMIO write handler
3077 * @vgpu: a vGPU
3078 * @offset: access offset
3079 * @p_data: write data buffer
3080 * @bytes: access data length
3081 *
3082 * Returns:
3083 * Zero on success, negative error code if failed.
3084 */
3085int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
3086		void *p_data, unsigned int bytes)
3087{
3088	write_vreg(vgpu, offset, p_data, bytes);
3089	return 0;
3090}
3091
3092/**
3093 * intel_vgpu_mask_mmio_write - write mask register
3094 * @vgpu: a vGPU
3095 * @offset: access offset
3096 * @p_data: write data buffer
3097 * @bytes: access data length
3098 *
3099 * Returns:
3100 * Zero on success, negative error code if failed.
3101 */
3102int intel_vgpu_mask_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
3103		void *p_data, unsigned int bytes)
3104{
3105	u32 mask, old_vreg;
3106
3107	old_vreg = vgpu_vreg(vgpu, offset);
3108	write_vreg(vgpu, offset, p_data, bytes);
3109	mask = vgpu_vreg(vgpu, offset) >> 16;
3110	vgpu_vreg(vgpu, offset) = (old_vreg & ~mask) |
3111				(vgpu_vreg(vgpu, offset) & mask);
3112
3113	return 0;
3114}
3115
3116/**
3117 * intel_gvt_in_force_nonpriv_whitelist - if a mmio is in whitelist to be
3118 * force-nopriv register
3119 *
3120 * @gvt: a GVT device
3121 * @offset: register offset
3122 *
3123 * Returns:
3124 * True if the register is in force-nonpriv whitelist;
3125 * False if outside;
3126 */
3127bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt,
3128					  unsigned int offset)
3129{
3130	return in_whitelist(offset);
3131}
3132
3133/**
3134 * intel_vgpu_mmio_reg_rw - emulate tracked mmio registers
3135 * @vgpu: a vGPU
3136 * @offset: register offset
3137 * @pdata: data buffer
3138 * @bytes: data length
3139 * @is_read: read or write
3140 *
3141 * Returns:
3142 * Zero on success, negative error code if failed.
3143 */
3144int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset,
3145			   void *pdata, unsigned int bytes, bool is_read)
3146{
3147	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
3148	struct intel_gvt *gvt = vgpu->gvt;
3149	struct intel_gvt_mmio_info *mmio_info;
3150	struct gvt_mmio_block *mmio_block;
3151	gvt_mmio_func func;
3152	int ret;
3153
3154	if (drm_WARN_ON(&i915->drm, bytes > 8))
3155		return -EINVAL;
3156
3157	/*
3158	 * Handle special MMIO blocks.
3159	 */
3160	mmio_block = find_mmio_block(gvt, offset);
3161	if (mmio_block) {
3162		func = is_read ? mmio_block->read : mmio_block->write;
3163		if (func)
3164			return func(vgpu, offset, pdata, bytes);
3165		goto default_rw;
3166	}
3167
3168	/*
3169	 * Normal tracked MMIOs.
3170	 */
3171	mmio_info = intel_gvt_find_mmio_info(gvt, offset);
3172	if (!mmio_info) {
3173		gvt_dbg_mmio("untracked MMIO %08x len %d\n", offset, bytes);
3174		goto default_rw;
3175	}
3176
3177	if (is_read)
3178		return mmio_info->read(vgpu, offset, pdata, bytes);
3179	else {
3180		u64 ro_mask = mmio_info->ro_mask;
3181		u32 old_vreg = 0;
3182		u64 data = 0;
3183
3184		if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) {
3185			old_vreg = vgpu_vreg(vgpu, offset);
3186		}
3187
3188		if (likely(!ro_mask))
3189			ret = mmio_info->write(vgpu, offset, pdata, bytes);
3190		else if (!~ro_mask) {
3191			gvt_vgpu_err("try to write RO reg %x\n", offset);
3192			return 0;
3193		} else {
3194			/* keep the RO bits in the virtual register */
3195			memcpy(&data, pdata, bytes);
3196			data &= ~ro_mask;
3197			data |= vgpu_vreg(vgpu, offset) & ro_mask;
3198			ret = mmio_info->write(vgpu, offset, &data, bytes);
3199		}
3200
3201		/* higher 16bits of mode ctl regs are mask bits for change */
3202		if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) {
3203			u32 mask = vgpu_vreg(vgpu, offset) >> 16;
3204
3205			vgpu_vreg(vgpu, offset) = (old_vreg & ~mask)
3206					| (vgpu_vreg(vgpu, offset) & mask);
3207		}
3208	}
3209
3210	return ret;
3211
3212default_rw:
3213	return is_read ?
3214		intel_vgpu_default_mmio_read(vgpu, offset, pdata, bytes) :
3215		intel_vgpu_default_mmio_write(vgpu, offset, pdata, bytes);
3216}
3217
3218void intel_gvt_restore_fence(struct intel_gvt *gvt)
3219{
3220	struct intel_vgpu *vgpu;
3221	int i, id;
3222
3223	idr_for_each_entry(&(gvt)->vgpu_idr, vgpu, id) {
3224		mmio_hw_access_pre(gvt->gt);
3225		for (i = 0; i < vgpu_fence_sz(vgpu); i++)
3226			intel_vgpu_write_fence(vgpu, i, vgpu_vreg64(vgpu, fence_num_to_offset(i)));
3227		mmio_hw_access_post(gvt->gt);
3228	}
3229}
3230
3231static int mmio_pm_restore_handler(struct intel_gvt *gvt, u32 offset, void *data)
3232{
3233	struct intel_vgpu *vgpu = data;
3234	struct drm_i915_private *dev_priv = gvt->gt->i915;
3235
3236	if (gvt->mmio.mmio_attribute[offset >> 2] & F_PM_SAVE)
3237		intel_uncore_write(&dev_priv->uncore, _MMIO(offset), vgpu_vreg(vgpu, offset));
3238
3239	return 0;
3240}
3241
3242void intel_gvt_restore_mmio(struct intel_gvt *gvt)
3243{
3244	struct intel_vgpu *vgpu;
3245	int id;
3246
3247	idr_for_each_entry(&(gvt)->vgpu_idr, vgpu, id) {
3248		mmio_hw_access_pre(gvt->gt);
3249		intel_gvt_for_each_tracked_mmio(gvt, mmio_pm_restore_handler, vgpu);
3250		mmio_hw_access_post(gvt->gt);
3251	}
3252}