Loading...
1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
16 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
17 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
18 * USE OR OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * The above copyright notice and this permission notice (including the
21 * next paragraph) shall be included in all copies or substantial portions
22 * of the Software.
23 *
24 */
25/*
26 * Authors: Dave Airlie <airlied@redhat.com>
27 */
28
29#include <drm/drmP.h>
30#include "ast_drv.h"
31
32#include "ast_dram_tables.h"
33
34static void ast_init_dram_2300(struct drm_device *dev);
35
36void ast_enable_vga(struct drm_device *dev)
37{
38 struct ast_private *ast = dev->dev_private;
39
40 ast_io_write8(ast, AST_IO_VGA_ENABLE_PORT, 0x01);
41 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, 0x01);
42}
43
44void ast_enable_mmio(struct drm_device *dev)
45{
46 struct ast_private *ast = dev->dev_private;
47
48 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa1, 0xff, 0x04);
49}
50
51
52bool ast_is_vga_enabled(struct drm_device *dev)
53{
54 struct ast_private *ast = dev->dev_private;
55 u8 ch;
56
57 if (ast->chip == AST1180) {
58 /* TODO 1180 */
59 } else {
60 ch = ast_io_read8(ast, AST_IO_VGA_ENABLE_PORT);
61 if (ch) {
62 ast_open_key(ast);
63 ch = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xff);
64 return ch & 0x04;
65 }
66 }
67 return 0;
68}
69
70static const u8 extreginfo[] = { 0x0f, 0x04, 0x1c, 0xff };
71static const u8 extreginfo_ast2300a0[] = { 0x0f, 0x04, 0x1c, 0xff };
72static const u8 extreginfo_ast2300[] = { 0x0f, 0x04, 0x1f, 0xff };
73
74static void
75ast_set_def_ext_reg(struct drm_device *dev)
76{
77 struct ast_private *ast = dev->dev_private;
78 u8 i, index, reg;
79 const u8 *ext_reg_info;
80
81 /* reset scratch */
82 for (i = 0x81; i <= 0x8f; i++)
83 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, 0x00);
84
85 if (ast->chip == AST2300 || ast->chip == AST2400) {
86 if (dev->pdev->revision >= 0x20)
87 ext_reg_info = extreginfo_ast2300;
88 else
89 ext_reg_info = extreginfo_ast2300a0;
90 } else
91 ext_reg_info = extreginfo;
92
93 index = 0xa0;
94 while (*ext_reg_info != 0xff) {
95 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, index, 0x00, *ext_reg_info);
96 index++;
97 ext_reg_info++;
98 }
99
100 /* disable standard IO/MEM decode if secondary */
101 /* ast_set_index_reg-mask(ast, AST_IO_CRTC_PORT, 0xa1, 0xff, 0x3); */
102
103 /* Set Ext. Default */
104 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x8c, 0x00, 0x01);
105 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x00, 0x00);
106
107 /* Enable RAMDAC for A1 */
108 reg = 0x04;
109 if (ast->chip == AST2300 || ast->chip == AST2400)
110 reg |= 0x20;
111 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xff, reg);
112}
113
114u32 ast_mindwm(struct ast_private *ast, u32 r)
115{
116 uint32_t data;
117
118 ast_write32(ast, 0xf004, r & 0xffff0000);
119 ast_write32(ast, 0xf000, 0x1);
120
121 do {
122 data = ast_read32(ast, 0xf004) & 0xffff0000;
123 } while (data != (r & 0xffff0000));
124 return ast_read32(ast, 0x10000 + (r & 0x0000ffff));
125}
126
127void ast_moutdwm(struct ast_private *ast, u32 r, u32 v)
128{
129 uint32_t data;
130 ast_write32(ast, 0xf004, r & 0xffff0000);
131 ast_write32(ast, 0xf000, 0x1);
132 do {
133 data = ast_read32(ast, 0xf004) & 0xffff0000;
134 } while (data != (r & 0xffff0000));
135 ast_write32(ast, 0x10000 + (r & 0x0000ffff), v);
136}
137
138/*
139 * AST2100/2150 DLL CBR Setting
140 */
141#define CBR_SIZE_AST2150 ((16 << 10) - 1)
142#define CBR_PASSNUM_AST2150 5
143#define CBR_THRESHOLD_AST2150 10
144#define CBR_THRESHOLD2_AST2150 10
145#define TIMEOUT_AST2150 5000000
146
147#define CBR_PATNUM_AST2150 8
148
149static const u32 pattern_AST2150[14] = {
150 0xFF00FF00,
151 0xCC33CC33,
152 0xAA55AA55,
153 0xFFFE0001,
154 0x683501FE,
155 0x0F1929B0,
156 0x2D0B4346,
157 0x60767F02,
158 0x6FBE36A6,
159 0x3A253035,
160 0x3019686D,
161 0x41C6167E,
162 0x620152BF,
163 0x20F050E0
164};
165
166static u32 mmctestburst2_ast2150(struct ast_private *ast, u32 datagen)
167{
168 u32 data, timeout;
169
170 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
171 ast_moutdwm(ast, 0x1e6e0070, 0x00000001 | (datagen << 3));
172 timeout = 0;
173 do {
174 data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
175 if (++timeout > TIMEOUT_AST2150) {
176 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
177 return 0xffffffff;
178 }
179 } while (!data);
180 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
181 ast_moutdwm(ast, 0x1e6e0070, 0x00000003 | (datagen << 3));
182 timeout = 0;
183 do {
184 data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
185 if (++timeout > TIMEOUT_AST2150) {
186 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
187 return 0xffffffff;
188 }
189 } while (!data);
190 data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7;
191 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
192 return data;
193}
194
195#if 0 /* unused in DDX driver - here for completeness */
196static u32 mmctestsingle2_ast2150(struct ast_private *ast, u32 datagen)
197{
198 u32 data, timeout;
199
200 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
201 ast_moutdwm(ast, 0x1e6e0070, 0x00000005 | (datagen << 3));
202 timeout = 0;
203 do {
204 data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
205 if (++timeout > TIMEOUT_AST2150) {
206 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
207 return 0xffffffff;
208 }
209 } while (!data);
210 data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7;
211 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
212 return data;
213}
214#endif
215
216static int cbrtest_ast2150(struct ast_private *ast)
217{
218 int i;
219
220 for (i = 0; i < 8; i++)
221 if (mmctestburst2_ast2150(ast, i))
222 return 0;
223 return 1;
224}
225
226static int cbrscan_ast2150(struct ast_private *ast, int busw)
227{
228 u32 patcnt, loop;
229
230 for (patcnt = 0; patcnt < CBR_PATNUM_AST2150; patcnt++) {
231 ast_moutdwm(ast, 0x1e6e007c, pattern_AST2150[patcnt]);
232 for (loop = 0; loop < CBR_PASSNUM_AST2150; loop++) {
233 if (cbrtest_ast2150(ast))
234 break;
235 }
236 if (loop == CBR_PASSNUM_AST2150)
237 return 0;
238 }
239 return 1;
240}
241
242
243static void cbrdlli_ast2150(struct ast_private *ast, int busw)
244{
245 u32 dll_min[4], dll_max[4], dlli, data, passcnt;
246
247cbr_start:
248 dll_min[0] = dll_min[1] = dll_min[2] = dll_min[3] = 0xff;
249 dll_max[0] = dll_max[1] = dll_max[2] = dll_max[3] = 0x0;
250 passcnt = 0;
251
252 for (dlli = 0; dlli < 100; dlli++) {
253 ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24));
254 data = cbrscan_ast2150(ast, busw);
255 if (data != 0) {
256 if (data & 0x1) {
257 if (dll_min[0] > dlli)
258 dll_min[0] = dlli;
259 if (dll_max[0] < dlli)
260 dll_max[0] = dlli;
261 }
262 passcnt++;
263 } else if (passcnt >= CBR_THRESHOLD_AST2150)
264 goto cbr_start;
265 }
266 if (dll_max[0] == 0 || (dll_max[0]-dll_min[0]) < CBR_THRESHOLD_AST2150)
267 goto cbr_start;
268
269 dlli = dll_min[0] + (((dll_max[0] - dll_min[0]) * 7) >> 4);
270 ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24));
271}
272
273
274
275static void ast_init_dram_reg(struct drm_device *dev)
276{
277 struct ast_private *ast = dev->dev_private;
278 u8 j;
279 u32 data, temp, i;
280 const struct ast_dramstruct *dram_reg_info;
281
282 j = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
283
284 if ((j & 0x80) == 0) { /* VGA only */
285 if (ast->chip == AST2000) {
286 dram_reg_info = ast2000_dram_table_data;
287 ast_write32(ast, 0xf004, 0x1e6e0000);
288 ast_write32(ast, 0xf000, 0x1);
289 ast_write32(ast, 0x10100, 0xa8);
290
291 do {
292 ;
293 } while (ast_read32(ast, 0x10100) != 0xa8);
294 } else {/* AST2100/1100 */
295 if (ast->chip == AST2100 || ast->chip == 2200)
296 dram_reg_info = ast2100_dram_table_data;
297 else
298 dram_reg_info = ast1100_dram_table_data;
299
300 ast_write32(ast, 0xf004, 0x1e6e0000);
301 ast_write32(ast, 0xf000, 0x1);
302 ast_write32(ast, 0x12000, 0x1688A8A8);
303 do {
304 ;
305 } while (ast_read32(ast, 0x12000) != 0x01);
306
307 ast_write32(ast, 0x10000, 0xfc600309);
308 do {
309 ;
310 } while (ast_read32(ast, 0x10000) != 0x01);
311 }
312
313 while (dram_reg_info->index != 0xffff) {
314 if (dram_reg_info->index == 0xff00) {/* delay fn */
315 for (i = 0; i < 15; i++)
316 udelay(dram_reg_info->data);
317 } else if (dram_reg_info->index == 0x4 && ast->chip != AST2000) {
318 data = dram_reg_info->data;
319 if (ast->dram_type == AST_DRAM_1Gx16)
320 data = 0x00000d89;
321 else if (ast->dram_type == AST_DRAM_1Gx32)
322 data = 0x00000c8d;
323
324 temp = ast_read32(ast, 0x12070);
325 temp &= 0xc;
326 temp <<= 2;
327 ast_write32(ast, 0x10000 + dram_reg_info->index, data | temp);
328 } else
329 ast_write32(ast, 0x10000 + dram_reg_info->index, dram_reg_info->data);
330 dram_reg_info++;
331 }
332
333 /* AST 2100/2150 DRAM calibration */
334 data = ast_read32(ast, 0x10120);
335 if (data == 0x5061) { /* 266Mhz */
336 data = ast_read32(ast, 0x10004);
337 if (data & 0x40)
338 cbrdlli_ast2150(ast, 16); /* 16 bits */
339 else
340 cbrdlli_ast2150(ast, 32); /* 32 bits */
341 }
342
343 switch (ast->chip) {
344 case AST2000:
345 temp = ast_read32(ast, 0x10140);
346 ast_write32(ast, 0x10140, temp | 0x40);
347 break;
348 case AST1100:
349 case AST2100:
350 case AST2200:
351 case AST2150:
352 temp = ast_read32(ast, 0x1200c);
353 ast_write32(ast, 0x1200c, temp & 0xfffffffd);
354 temp = ast_read32(ast, 0x12040);
355 ast_write32(ast, 0x12040, temp | 0x40);
356 break;
357 default:
358 break;
359 }
360 }
361
362 /* wait ready */
363 do {
364 j = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
365 } while ((j & 0x40) == 0);
366}
367
368void ast_post_gpu(struct drm_device *dev)
369{
370 u32 reg;
371 struct ast_private *ast = dev->dev_private;
372
373 pci_read_config_dword(ast->dev->pdev, 0x04, ®);
374 reg |= 0x3;
375 pci_write_config_dword(ast->dev->pdev, 0x04, reg);
376
377 ast_enable_vga(dev);
378 ast_enable_mmio(dev);
379 ast_open_key(ast);
380 ast_set_def_ext_reg(dev);
381
382 if (ast->chip == AST2300 || ast->chip == AST2400)
383 ast_init_dram_2300(dev);
384 else
385 ast_init_dram_reg(dev);
386
387 ast_init_3rdtx(dev);
388}
389
390/* AST 2300 DRAM settings */
391#define AST_DDR3 0
392#define AST_DDR2 1
393
394struct ast2300_dram_param {
395 u32 dram_type;
396 u32 dram_chipid;
397 u32 dram_freq;
398 u32 vram_size;
399 u32 odt;
400 u32 wodt;
401 u32 rodt;
402 u32 dram_config;
403 u32 reg_PERIOD;
404 u32 reg_MADJ;
405 u32 reg_SADJ;
406 u32 reg_MRS;
407 u32 reg_EMRS;
408 u32 reg_AC1;
409 u32 reg_AC2;
410 u32 reg_DQSIC;
411 u32 reg_DRV;
412 u32 reg_IOZ;
413 u32 reg_DQIDLY;
414 u32 reg_FREQ;
415 u32 madj_max;
416 u32 dll2_finetune_step;
417};
418
419/*
420 * DQSI DLL CBR Setting
421 */
422#define CBR_SIZE0 ((1 << 10) - 1)
423#define CBR_SIZE1 ((4 << 10) - 1)
424#define CBR_SIZE2 ((64 << 10) - 1)
425#define CBR_PASSNUM 5
426#define CBR_PASSNUM2 5
427#define CBR_THRESHOLD 10
428#define CBR_THRESHOLD2 10
429#define TIMEOUT 5000000
430#define CBR_PATNUM 8
431
432static const u32 pattern[8] = {
433 0xFF00FF00,
434 0xCC33CC33,
435 0xAA55AA55,
436 0x88778877,
437 0x92CC4D6E,
438 0x543D3CDE,
439 0xF1E843C7,
440 0x7C61D253
441};
442
443static int mmc_test_burst(struct ast_private *ast, u32 datagen)
444{
445 u32 data, timeout;
446
447 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
448 ast_moutdwm(ast, 0x1e6e0070, 0x000000c1 | (datagen << 3));
449 timeout = 0;
450 do {
451 data = ast_mindwm(ast, 0x1e6e0070) & 0x3000;
452 if (data & 0x2000) {
453 return 0;
454 }
455 if (++timeout > TIMEOUT) {
456 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
457 return 0;
458 }
459 } while (!data);
460 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
461 return 1;
462}
463
464static int mmc_test_burst2(struct ast_private *ast, u32 datagen)
465{
466 u32 data, timeout;
467
468 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
469 ast_moutdwm(ast, 0x1e6e0070, 0x00000041 | (datagen << 3));
470 timeout = 0;
471 do {
472 data = ast_mindwm(ast, 0x1e6e0070) & 0x1000;
473 if (++timeout > TIMEOUT) {
474 ast_moutdwm(ast, 0x1e6e0070, 0x0);
475 return -1;
476 }
477 } while (!data);
478 data = ast_mindwm(ast, 0x1e6e0078);
479 data = (data | (data >> 16)) & 0xffff;
480 ast_moutdwm(ast, 0x1e6e0070, 0x0);
481 return data;
482}
483
484static int mmc_test_single(struct ast_private *ast, u32 datagen)
485{
486 u32 data, timeout;
487
488 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
489 ast_moutdwm(ast, 0x1e6e0070, 0x000000c5 | (datagen << 3));
490 timeout = 0;
491 do {
492 data = ast_mindwm(ast, 0x1e6e0070) & 0x3000;
493 if (data & 0x2000)
494 return 0;
495 if (++timeout > TIMEOUT) {
496 ast_moutdwm(ast, 0x1e6e0070, 0x0);
497 return 0;
498 }
499 } while (!data);
500 ast_moutdwm(ast, 0x1e6e0070, 0x0);
501 return 1;
502}
503
504static int mmc_test_single2(struct ast_private *ast, u32 datagen)
505{
506 u32 data, timeout;
507
508 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
509 ast_moutdwm(ast, 0x1e6e0070, 0x00000005 | (datagen << 3));
510 timeout = 0;
511 do {
512 data = ast_mindwm(ast, 0x1e6e0070) & 0x1000;
513 if (++timeout > TIMEOUT) {
514 ast_moutdwm(ast, 0x1e6e0070, 0x0);
515 return -1;
516 }
517 } while (!data);
518 data = ast_mindwm(ast, 0x1e6e0078);
519 data = (data | (data >> 16)) & 0xffff;
520 ast_moutdwm(ast, 0x1e6e0070, 0x0);
521 return data;
522}
523
524static int cbr_test(struct ast_private *ast)
525{
526 u32 data;
527 int i;
528 data = mmc_test_single2(ast, 0);
529 if ((data & 0xff) && (data & 0xff00))
530 return 0;
531 for (i = 0; i < 8; i++) {
532 data = mmc_test_burst2(ast, i);
533 if ((data & 0xff) && (data & 0xff00))
534 return 0;
535 }
536 if (!data)
537 return 3;
538 else if (data & 0xff)
539 return 2;
540 return 1;
541}
542
543static int cbr_scan(struct ast_private *ast)
544{
545 u32 data, data2, patcnt, loop;
546
547 data2 = 3;
548 for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) {
549 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
550 for (loop = 0; loop < CBR_PASSNUM2; loop++) {
551 if ((data = cbr_test(ast)) != 0) {
552 data2 &= data;
553 if (!data2)
554 return 0;
555 break;
556 }
557 }
558 if (loop == CBR_PASSNUM2)
559 return 0;
560 }
561 return data2;
562}
563
564static u32 cbr_test2(struct ast_private *ast)
565{
566 u32 data;
567
568 data = mmc_test_burst2(ast, 0);
569 if (data == 0xffff)
570 return 0;
571 data |= mmc_test_single2(ast, 0);
572 if (data == 0xffff)
573 return 0;
574
575 return ~data & 0xffff;
576}
577
578static u32 cbr_scan2(struct ast_private *ast)
579{
580 u32 data, data2, patcnt, loop;
581
582 data2 = 0xffff;
583 for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) {
584 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
585 for (loop = 0; loop < CBR_PASSNUM2; loop++) {
586 if ((data = cbr_test2(ast)) != 0) {
587 data2 &= data;
588 if (!data2)
589 return 0;
590 break;
591 }
592 }
593 if (loop == CBR_PASSNUM2)
594 return 0;
595 }
596 return data2;
597}
598
599static u32 cbr_test3(struct ast_private *ast)
600{
601 if (!mmc_test_burst(ast, 0))
602 return 0;
603 if (!mmc_test_single(ast, 0))
604 return 0;
605 return 1;
606}
607
608static u32 cbr_scan3(struct ast_private *ast)
609{
610 u32 patcnt, loop;
611
612 for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) {
613 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
614 for (loop = 0; loop < 2; loop++) {
615 if (cbr_test3(ast))
616 break;
617 }
618 if (loop == 2)
619 return 0;
620 }
621 return 1;
622}
623
624static bool finetuneDQI_L(struct ast_private *ast, struct ast2300_dram_param *param)
625{
626 u32 gold_sadj[2], dllmin[16], dllmax[16], dlli, data, cnt, mask, passcnt, retry = 0;
627 bool status = false;
628FINETUNE_START:
629 for (cnt = 0; cnt < 16; cnt++) {
630 dllmin[cnt] = 0xff;
631 dllmax[cnt] = 0x0;
632 }
633 passcnt = 0;
634 for (dlli = 0; dlli < 76; dlli++) {
635 ast_moutdwm(ast, 0x1E6E0068, 0x00001400 | (dlli << 16) | (dlli << 24));
636 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE1);
637 data = cbr_scan2(ast);
638 if (data != 0) {
639 mask = 0x00010001;
640 for (cnt = 0; cnt < 16; cnt++) {
641 if (data & mask) {
642 if (dllmin[cnt] > dlli) {
643 dllmin[cnt] = dlli;
644 }
645 if (dllmax[cnt] < dlli) {
646 dllmax[cnt] = dlli;
647 }
648 }
649 mask <<= 1;
650 }
651 passcnt++;
652 } else if (passcnt >= CBR_THRESHOLD2) {
653 break;
654 }
655 }
656 gold_sadj[0] = 0x0;
657 passcnt = 0;
658 for (cnt = 0; cnt < 16; cnt++) {
659 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) {
660 gold_sadj[0] += dllmin[cnt];
661 passcnt++;
662 }
663 }
664 if (retry++ > 10)
665 goto FINETUNE_DONE;
666 if (passcnt != 16) {
667 goto FINETUNE_START;
668 }
669 status = true;
670FINETUNE_DONE:
671 gold_sadj[0] = gold_sadj[0] >> 4;
672 gold_sadj[1] = gold_sadj[0];
673
674 data = 0;
675 for (cnt = 0; cnt < 8; cnt++) {
676 data >>= 3;
677 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) {
678 dlli = dllmin[cnt];
679 if (gold_sadj[0] >= dlli) {
680 dlli = ((gold_sadj[0] - dlli) * 19) >> 5;
681 if (dlli > 3) {
682 dlli = 3;
683 }
684 } else {
685 dlli = ((dlli - gold_sadj[0]) * 19) >> 5;
686 if (dlli > 4) {
687 dlli = 4;
688 }
689 dlli = (8 - dlli) & 0x7;
690 }
691 data |= dlli << 21;
692 }
693 }
694 ast_moutdwm(ast, 0x1E6E0080, data);
695
696 data = 0;
697 for (cnt = 8; cnt < 16; cnt++) {
698 data >>= 3;
699 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) {
700 dlli = dllmin[cnt];
701 if (gold_sadj[1] >= dlli) {
702 dlli = ((gold_sadj[1] - dlli) * 19) >> 5;
703 if (dlli > 3) {
704 dlli = 3;
705 } else {
706 dlli = (dlli - 1) & 0x7;
707 }
708 } else {
709 dlli = ((dlli - gold_sadj[1]) * 19) >> 5;
710 dlli += 1;
711 if (dlli > 4) {
712 dlli = 4;
713 }
714 dlli = (8 - dlli) & 0x7;
715 }
716 data |= dlli << 21;
717 }
718 }
719 ast_moutdwm(ast, 0x1E6E0084, data);
720 return status;
721} /* finetuneDQI_L */
722
723static void finetuneDQSI(struct ast_private *ast)
724{
725 u32 dlli, dqsip, dqidly;
726 u32 reg_mcr18, reg_mcr0c, passcnt[2], diff;
727 u32 g_dqidly, g_dqsip, g_margin, g_side;
728 u16 pass[32][2][2];
729 char tag[2][76];
730
731 /* Disable DQI CBR */
732 reg_mcr0c = ast_mindwm(ast, 0x1E6E000C);
733 reg_mcr18 = ast_mindwm(ast, 0x1E6E0018);
734 reg_mcr18 &= 0x0000ffff;
735 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18);
736
737 for (dlli = 0; dlli < 76; dlli++) {
738 tag[0][dlli] = 0x0;
739 tag[1][dlli] = 0x0;
740 }
741 for (dqidly = 0; dqidly < 32; dqidly++) {
742 pass[dqidly][0][0] = 0xff;
743 pass[dqidly][0][1] = 0x0;
744 pass[dqidly][1][0] = 0xff;
745 pass[dqidly][1][1] = 0x0;
746 }
747 for (dqidly = 0; dqidly < 32; dqidly++) {
748 passcnt[0] = passcnt[1] = 0;
749 for (dqsip = 0; dqsip < 2; dqsip++) {
750 ast_moutdwm(ast, 0x1E6E000C, 0);
751 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18 | (dqidly << 16) | (dqsip << 23));
752 ast_moutdwm(ast, 0x1E6E000C, reg_mcr0c);
753 for (dlli = 0; dlli < 76; dlli++) {
754 ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24));
755 ast_moutdwm(ast, 0x1E6E0070, 0);
756 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE0);
757 if (cbr_scan3(ast)) {
758 if (dlli == 0)
759 break;
760 passcnt[dqsip]++;
761 tag[dqsip][dlli] = 'P';
762 if (dlli < pass[dqidly][dqsip][0])
763 pass[dqidly][dqsip][0] = (u16) dlli;
764 if (dlli > pass[dqidly][dqsip][1])
765 pass[dqidly][dqsip][1] = (u16) dlli;
766 } else if (passcnt[dqsip] >= 5)
767 break;
768 else {
769 pass[dqidly][dqsip][0] = 0xff;
770 pass[dqidly][dqsip][1] = 0x0;
771 }
772 }
773 }
774 if (passcnt[0] == 0 && passcnt[1] == 0)
775 dqidly++;
776 }
777 /* Search margin */
778 g_dqidly = g_dqsip = g_margin = g_side = 0;
779
780 for (dqidly = 0; dqidly < 32; dqidly++) {
781 for (dqsip = 0; dqsip < 2; dqsip++) {
782 if (pass[dqidly][dqsip][0] > pass[dqidly][dqsip][1])
783 continue;
784 diff = pass[dqidly][dqsip][1] - pass[dqidly][dqsip][0];
785 if ((diff+2) < g_margin)
786 continue;
787 passcnt[0] = passcnt[1] = 0;
788 for (dlli = pass[dqidly][dqsip][0]; dlli > 0 && tag[dqsip][dlli] != 0; dlli--, passcnt[0]++);
789 for (dlli = pass[dqidly][dqsip][1]; dlli < 76 && tag[dqsip][dlli] != 0; dlli++, passcnt[1]++);
790 if (passcnt[0] > passcnt[1])
791 passcnt[0] = passcnt[1];
792 passcnt[1] = 0;
793 if (passcnt[0] > g_side)
794 passcnt[1] = passcnt[0] - g_side;
795 if (diff > (g_margin+1) && (passcnt[1] > 0 || passcnt[0] > 8)) {
796 g_margin = diff;
797 g_dqidly = dqidly;
798 g_dqsip = dqsip;
799 g_side = passcnt[0];
800 } else if (passcnt[1] > 1 && g_side < 8) {
801 if (diff > g_margin)
802 g_margin = diff;
803 g_dqidly = dqidly;
804 g_dqsip = dqsip;
805 g_side = passcnt[0];
806 }
807 }
808 }
809 reg_mcr18 = reg_mcr18 | (g_dqidly << 16) | (g_dqsip << 23);
810 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18);
811
812}
813static bool cbr_dll2(struct ast_private *ast, struct ast2300_dram_param *param)
814{
815 u32 dllmin[2], dllmax[2], dlli, data, passcnt, retry = 0;
816 bool status = false;
817
818 finetuneDQSI(ast);
819 if (finetuneDQI_L(ast, param) == false)
820 return status;
821
822CBR_START2:
823 dllmin[0] = dllmin[1] = 0xff;
824 dllmax[0] = dllmax[1] = 0x0;
825 passcnt = 0;
826 for (dlli = 0; dlli < 76; dlli++) {
827 ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24));
828 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE2);
829 data = cbr_scan(ast);
830 if (data != 0) {
831 if (data & 0x1) {
832 if (dllmin[0] > dlli) {
833 dllmin[0] = dlli;
834 }
835 if (dllmax[0] < dlli) {
836 dllmax[0] = dlli;
837 }
838 }
839 if (data & 0x2) {
840 if (dllmin[1] > dlli) {
841 dllmin[1] = dlli;
842 }
843 if (dllmax[1] < dlli) {
844 dllmax[1] = dlli;
845 }
846 }
847 passcnt++;
848 } else if (passcnt >= CBR_THRESHOLD) {
849 break;
850 }
851 }
852 if (retry++ > 10)
853 goto CBR_DONE2;
854 if (dllmax[0] == 0 || (dllmax[0]-dllmin[0]) < CBR_THRESHOLD) {
855 goto CBR_START2;
856 }
857 if (dllmax[1] == 0 || (dllmax[1]-dllmin[1]) < CBR_THRESHOLD) {
858 goto CBR_START2;
859 }
860 status = true;
861CBR_DONE2:
862 dlli = (dllmin[1] + dllmax[1]) >> 1;
863 dlli <<= 8;
864 dlli += (dllmin[0] + dllmax[0]) >> 1;
865 ast_moutdwm(ast, 0x1E6E0068, ast_mindwm(ast, 0x1E720058) | (dlli << 16));
866 return status;
867} /* CBRDLL2 */
868
869static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *param)
870{
871 u32 trap, trap_AC2, trap_MRS;
872
873 ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
874
875 /* Ger trap info */
876 trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3;
877 trap_AC2 = 0x00020000 + (trap << 16);
878 trap_AC2 |= 0x00300000 + ((trap & 0x2) << 19);
879 trap_MRS = 0x00000010 + (trap << 4);
880 trap_MRS |= ((trap & 0x2) << 18);
881
882 param->reg_MADJ = 0x00034C4C;
883 param->reg_SADJ = 0x00001800;
884 param->reg_DRV = 0x000000F0;
885 param->reg_PERIOD = param->dram_freq;
886 param->rodt = 0;
887
888 switch (param->dram_freq) {
889 case 336:
890 ast_moutdwm(ast, 0x1E6E2020, 0x0190);
891 param->wodt = 0;
892 param->reg_AC1 = 0x22202725;
893 param->reg_AC2 = 0xAA007613 | trap_AC2;
894 param->reg_DQSIC = 0x000000BA;
895 param->reg_MRS = 0x04001400 | trap_MRS;
896 param->reg_EMRS = 0x00000000;
897 param->reg_IOZ = 0x00000023;
898 param->reg_DQIDLY = 0x00000074;
899 param->reg_FREQ = 0x00004DC0;
900 param->madj_max = 96;
901 param->dll2_finetune_step = 3;
902 switch (param->dram_chipid) {
903 default:
904 case AST_DRAM_512Mx16:
905 case AST_DRAM_1Gx16:
906 param->reg_AC2 = 0xAA007613 | trap_AC2;
907 break;
908 case AST_DRAM_2Gx16:
909 param->reg_AC2 = 0xAA00761C | trap_AC2;
910 break;
911 case AST_DRAM_4Gx16:
912 param->reg_AC2 = 0xAA007636 | trap_AC2;
913 break;
914 }
915 break;
916 default:
917 case 396:
918 ast_moutdwm(ast, 0x1E6E2020, 0x03F1);
919 param->wodt = 1;
920 param->reg_AC1 = 0x33302825;
921 param->reg_AC2 = 0xCC009617 | trap_AC2;
922 param->reg_DQSIC = 0x000000E2;
923 param->reg_MRS = 0x04001600 | trap_MRS;
924 param->reg_EMRS = 0x00000000;
925 param->reg_IOZ = 0x00000034;
926 param->reg_DRV = 0x000000FA;
927 param->reg_DQIDLY = 0x00000089;
928 param->reg_FREQ = 0x00005040;
929 param->madj_max = 96;
930 param->dll2_finetune_step = 4;
931
932 switch (param->dram_chipid) {
933 default:
934 case AST_DRAM_512Mx16:
935 case AST_DRAM_1Gx16:
936 param->reg_AC2 = 0xCC009617 | trap_AC2;
937 break;
938 case AST_DRAM_2Gx16:
939 param->reg_AC2 = 0xCC009622 | trap_AC2;
940 break;
941 case AST_DRAM_4Gx16:
942 param->reg_AC2 = 0xCC00963F | trap_AC2;
943 break;
944 }
945 break;
946
947 case 408:
948 ast_moutdwm(ast, 0x1E6E2020, 0x01F0);
949 param->wodt = 1;
950 param->reg_AC1 = 0x33302825;
951 param->reg_AC2 = 0xCC009617 | trap_AC2;
952 param->reg_DQSIC = 0x000000E2;
953 param->reg_MRS = 0x04001600 | trap_MRS;
954 param->reg_EMRS = 0x00000000;
955 param->reg_IOZ = 0x00000023;
956 param->reg_DRV = 0x000000FA;
957 param->reg_DQIDLY = 0x00000089;
958 param->reg_FREQ = 0x000050C0;
959 param->madj_max = 96;
960 param->dll2_finetune_step = 4;
961
962 switch (param->dram_chipid) {
963 default:
964 case AST_DRAM_512Mx16:
965 case AST_DRAM_1Gx16:
966 param->reg_AC2 = 0xCC009617 | trap_AC2;
967 break;
968 case AST_DRAM_2Gx16:
969 param->reg_AC2 = 0xCC009622 | trap_AC2;
970 break;
971 case AST_DRAM_4Gx16:
972 param->reg_AC2 = 0xCC00963F | trap_AC2;
973 break;
974 }
975
976 break;
977 case 456:
978 ast_moutdwm(ast, 0x1E6E2020, 0x0230);
979 param->wodt = 0;
980 param->reg_AC1 = 0x33302926;
981 param->reg_AC2 = 0xCD44961A;
982 param->reg_DQSIC = 0x000000FC;
983 param->reg_MRS = 0x00081830;
984 param->reg_EMRS = 0x00000000;
985 param->reg_IOZ = 0x00000045;
986 param->reg_DQIDLY = 0x00000097;
987 param->reg_FREQ = 0x000052C0;
988 param->madj_max = 88;
989 param->dll2_finetune_step = 4;
990 break;
991 case 504:
992 ast_moutdwm(ast, 0x1E6E2020, 0x0270);
993 param->wodt = 1;
994 param->reg_AC1 = 0x33302926;
995 param->reg_AC2 = 0xDE44A61D;
996 param->reg_DQSIC = 0x00000117;
997 param->reg_MRS = 0x00081A30;
998 param->reg_EMRS = 0x00000000;
999 param->reg_IOZ = 0x070000BB;
1000 param->reg_DQIDLY = 0x000000A0;
1001 param->reg_FREQ = 0x000054C0;
1002 param->madj_max = 79;
1003 param->dll2_finetune_step = 4;
1004 break;
1005 case 528:
1006 ast_moutdwm(ast, 0x1E6E2020, 0x0290);
1007 param->wodt = 1;
1008 param->rodt = 1;
1009 param->reg_AC1 = 0x33302926;
1010 param->reg_AC2 = 0xEF44B61E;
1011 param->reg_DQSIC = 0x00000125;
1012 param->reg_MRS = 0x00081A30;
1013 param->reg_EMRS = 0x00000040;
1014 param->reg_DRV = 0x000000F5;
1015 param->reg_IOZ = 0x00000023;
1016 param->reg_DQIDLY = 0x00000088;
1017 param->reg_FREQ = 0x000055C0;
1018 param->madj_max = 76;
1019 param->dll2_finetune_step = 3;
1020 break;
1021 case 576:
1022 ast_moutdwm(ast, 0x1E6E2020, 0x0140);
1023 param->reg_MADJ = 0x00136868;
1024 param->reg_SADJ = 0x00004534;
1025 param->wodt = 1;
1026 param->rodt = 1;
1027 param->reg_AC1 = 0x33302A37;
1028 param->reg_AC2 = 0xEF56B61E;
1029 param->reg_DQSIC = 0x0000013F;
1030 param->reg_MRS = 0x00101A50;
1031 param->reg_EMRS = 0x00000040;
1032 param->reg_DRV = 0x000000FA;
1033 param->reg_IOZ = 0x00000023;
1034 param->reg_DQIDLY = 0x00000078;
1035 param->reg_FREQ = 0x000057C0;
1036 param->madj_max = 136;
1037 param->dll2_finetune_step = 3;
1038 break;
1039 case 600:
1040 ast_moutdwm(ast, 0x1E6E2020, 0x02E1);
1041 param->reg_MADJ = 0x00136868;
1042 param->reg_SADJ = 0x00004534;
1043 param->wodt = 1;
1044 param->rodt = 1;
1045 param->reg_AC1 = 0x32302A37;
1046 param->reg_AC2 = 0xDF56B61F;
1047 param->reg_DQSIC = 0x0000014D;
1048 param->reg_MRS = 0x00101A50;
1049 param->reg_EMRS = 0x00000004;
1050 param->reg_DRV = 0x000000F5;
1051 param->reg_IOZ = 0x00000023;
1052 param->reg_DQIDLY = 0x00000078;
1053 param->reg_FREQ = 0x000058C0;
1054 param->madj_max = 132;
1055 param->dll2_finetune_step = 3;
1056 break;
1057 case 624:
1058 ast_moutdwm(ast, 0x1E6E2020, 0x0160);
1059 param->reg_MADJ = 0x00136868;
1060 param->reg_SADJ = 0x00004534;
1061 param->wodt = 1;
1062 param->rodt = 1;
1063 param->reg_AC1 = 0x32302A37;
1064 param->reg_AC2 = 0xEF56B621;
1065 param->reg_DQSIC = 0x0000015A;
1066 param->reg_MRS = 0x02101A50;
1067 param->reg_EMRS = 0x00000004;
1068 param->reg_DRV = 0x000000F5;
1069 param->reg_IOZ = 0x00000034;
1070 param->reg_DQIDLY = 0x00000078;
1071 param->reg_FREQ = 0x000059C0;
1072 param->madj_max = 128;
1073 param->dll2_finetune_step = 3;
1074 break;
1075 } /* switch freq */
1076
1077 switch (param->dram_chipid) {
1078 case AST_DRAM_512Mx16:
1079 param->dram_config = 0x130;
1080 break;
1081 default:
1082 case AST_DRAM_1Gx16:
1083 param->dram_config = 0x131;
1084 break;
1085 case AST_DRAM_2Gx16:
1086 param->dram_config = 0x132;
1087 break;
1088 case AST_DRAM_4Gx16:
1089 param->dram_config = 0x133;
1090 break;
1091 } /* switch size */
1092
1093 switch (param->vram_size) {
1094 default:
1095 case AST_VIDMEM_SIZE_8M:
1096 param->dram_config |= 0x00;
1097 break;
1098 case AST_VIDMEM_SIZE_16M:
1099 param->dram_config |= 0x04;
1100 break;
1101 case AST_VIDMEM_SIZE_32M:
1102 param->dram_config |= 0x08;
1103 break;
1104 case AST_VIDMEM_SIZE_64M:
1105 param->dram_config |= 0x0c;
1106 break;
1107 }
1108
1109}
1110
1111static void ddr3_init(struct ast_private *ast, struct ast2300_dram_param *param)
1112{
1113 u32 data, data2, retry = 0;
1114
1115ddr3_init_start:
1116 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1117 ast_moutdwm(ast, 0x1E6E0018, 0x00000100);
1118 ast_moutdwm(ast, 0x1E6E0024, 0x00000000);
1119 ast_moutdwm(ast, 0x1E6E0034, 0x00000000);
1120 udelay(10);
1121 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ);
1122 ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ);
1123 udelay(10);
1124 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000);
1125 udelay(10);
1126
1127 ast_moutdwm(ast, 0x1E6E0004, param->dram_config);
1128 ast_moutdwm(ast, 0x1E6E0008, 0x90040f);
1129 ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1);
1130 ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2);
1131 ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC);
1132 ast_moutdwm(ast, 0x1E6E0080, 0x00000000);
1133 ast_moutdwm(ast, 0x1E6E0084, 0x00000000);
1134 ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY);
1135 ast_moutdwm(ast, 0x1E6E0018, 0x4000A170);
1136 ast_moutdwm(ast, 0x1E6E0018, 0x00002370);
1137 ast_moutdwm(ast, 0x1E6E0038, 0x00000000);
1138 ast_moutdwm(ast, 0x1E6E0040, 0xFF444444);
1139 ast_moutdwm(ast, 0x1E6E0044, 0x22222222);
1140 ast_moutdwm(ast, 0x1E6E0048, 0x22222222);
1141 ast_moutdwm(ast, 0x1E6E004C, 0x00000002);
1142 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1143 ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1144 ast_moutdwm(ast, 0x1E6E0054, 0);
1145 ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV);
1146 ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ);
1147 ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1148 ast_moutdwm(ast, 0x1E6E0074, 0x00000000);
1149 ast_moutdwm(ast, 0x1E6E0078, 0x00000000);
1150 ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1151 /* Wait MCLK2X lock to MCLK */
1152 do {
1153 data = ast_mindwm(ast, 0x1E6E001C);
1154 } while (!(data & 0x08000000));
1155 data = ast_mindwm(ast, 0x1E6E001C);
1156 data = (data >> 8) & 0xff;
1157 while ((data & 0x08) || ((data & 0x7) < 2) || (data < 4)) {
1158 data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4;
1159 if ((data2 & 0xff) > param->madj_max) {
1160 break;
1161 }
1162 ast_moutdwm(ast, 0x1E6E0064, data2);
1163 if (data2 & 0x00100000) {
1164 data2 = ((data2 & 0xff) >> 3) + 3;
1165 } else {
1166 data2 = ((data2 & 0xff) >> 2) + 5;
1167 }
1168 data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff;
1169 data2 += data & 0xff;
1170 data = data | (data2 << 8);
1171 ast_moutdwm(ast, 0x1E6E0068, data);
1172 udelay(10);
1173 ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000);
1174 udelay(10);
1175 data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff;
1176 ast_moutdwm(ast, 0x1E6E0018, data);
1177 data = data | 0x200;
1178 ast_moutdwm(ast, 0x1E6E0018, data);
1179 do {
1180 data = ast_mindwm(ast, 0x1E6E001C);
1181 } while (!(data & 0x08000000));
1182
1183 data = ast_mindwm(ast, 0x1E6E001C);
1184 data = (data >> 8) & 0xff;
1185 }
1186 ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0068) & 0xffff);
1187 data = ast_mindwm(ast, 0x1E6E0018) | 0xC00;
1188 ast_moutdwm(ast, 0x1E6E0018, data);
1189
1190 ast_moutdwm(ast, 0x1E6E0034, 0x00000001);
1191 ast_moutdwm(ast, 0x1E6E000C, 0x00000040);
1192 udelay(50);
1193 /* Mode Register Setting */
1194 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100);
1195 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1196 ast_moutdwm(ast, 0x1E6E0028, 0x00000005);
1197 ast_moutdwm(ast, 0x1E6E0028, 0x00000007);
1198 ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1199 ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1200 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS);
1201 ast_moutdwm(ast, 0x1E6E000C, 0x00005C08);
1202 ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1203
1204 ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
1205 data = 0;
1206 if (param->wodt) {
1207 data = 0x300;
1208 }
1209 if (param->rodt) {
1210 data = data | 0x3000 | ((param->reg_AC2 & 0x60000) >> 3);
1211 }
1212 ast_moutdwm(ast, 0x1E6E0034, data | 0x3);
1213
1214 /* Calibrate the DQSI delay */
1215 if ((cbr_dll2(ast, param) == false) && (retry++ < 10))
1216 goto ddr3_init_start;
1217
1218 ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ);
1219 /* ECC Memory Initialization */
1220#ifdef ECC
1221 ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1222 ast_moutdwm(ast, 0x1E6E0070, 0x221);
1223 do {
1224 data = ast_mindwm(ast, 0x1E6E0070);
1225 } while (!(data & 0x00001000));
1226 ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1227 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1228 ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1229#endif
1230
1231
1232}
1233
1234static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *param)
1235{
1236 u32 trap, trap_AC2, trap_MRS;
1237
1238 ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
1239
1240 /* Ger trap info */
1241 trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3;
1242 trap_AC2 = (trap << 20) | (trap << 16);
1243 trap_AC2 += 0x00110000;
1244 trap_MRS = 0x00000040 | (trap << 4);
1245
1246
1247 param->reg_MADJ = 0x00034C4C;
1248 param->reg_SADJ = 0x00001800;
1249 param->reg_DRV = 0x000000F0;
1250 param->reg_PERIOD = param->dram_freq;
1251 param->rodt = 0;
1252
1253 switch (param->dram_freq) {
1254 case 264:
1255 ast_moutdwm(ast, 0x1E6E2020, 0x0130);
1256 param->wodt = 0;
1257 param->reg_AC1 = 0x11101513;
1258 param->reg_AC2 = 0x78117011;
1259 param->reg_DQSIC = 0x00000092;
1260 param->reg_MRS = 0x00000842;
1261 param->reg_EMRS = 0x00000000;
1262 param->reg_DRV = 0x000000F0;
1263 param->reg_IOZ = 0x00000034;
1264 param->reg_DQIDLY = 0x0000005A;
1265 param->reg_FREQ = 0x00004AC0;
1266 param->madj_max = 138;
1267 param->dll2_finetune_step = 3;
1268 break;
1269 case 336:
1270 ast_moutdwm(ast, 0x1E6E2020, 0x0190);
1271 param->wodt = 1;
1272 param->reg_AC1 = 0x22202613;
1273 param->reg_AC2 = 0xAA009016 | trap_AC2;
1274 param->reg_DQSIC = 0x000000BA;
1275 param->reg_MRS = 0x00000A02 | trap_MRS;
1276 param->reg_EMRS = 0x00000040;
1277 param->reg_DRV = 0x000000FA;
1278 param->reg_IOZ = 0x00000034;
1279 param->reg_DQIDLY = 0x00000074;
1280 param->reg_FREQ = 0x00004DC0;
1281 param->madj_max = 96;
1282 param->dll2_finetune_step = 3;
1283 switch (param->dram_chipid) {
1284 default:
1285 case AST_DRAM_512Mx16:
1286 param->reg_AC2 = 0xAA009012 | trap_AC2;
1287 break;
1288 case AST_DRAM_1Gx16:
1289 param->reg_AC2 = 0xAA009016 | trap_AC2;
1290 break;
1291 case AST_DRAM_2Gx16:
1292 param->reg_AC2 = 0xAA009023 | trap_AC2;
1293 break;
1294 case AST_DRAM_4Gx16:
1295 param->reg_AC2 = 0xAA00903B | trap_AC2;
1296 break;
1297 }
1298 break;
1299 default:
1300 case 396:
1301 ast_moutdwm(ast, 0x1E6E2020, 0x03F1);
1302 param->wodt = 1;
1303 param->rodt = 0;
1304 param->reg_AC1 = 0x33302714;
1305 param->reg_AC2 = 0xCC00B01B | trap_AC2;
1306 param->reg_DQSIC = 0x000000E2;
1307 param->reg_MRS = 0x00000C02 | trap_MRS;
1308 param->reg_EMRS = 0x00000040;
1309 param->reg_DRV = 0x000000FA;
1310 param->reg_IOZ = 0x00000034;
1311 param->reg_DQIDLY = 0x00000089;
1312 param->reg_FREQ = 0x00005040;
1313 param->madj_max = 96;
1314 param->dll2_finetune_step = 4;
1315
1316 switch (param->dram_chipid) {
1317 case AST_DRAM_512Mx16:
1318 param->reg_AC2 = 0xCC00B016 | trap_AC2;
1319 break;
1320 default:
1321 case AST_DRAM_1Gx16:
1322 param->reg_AC2 = 0xCC00B01B | trap_AC2;
1323 break;
1324 case AST_DRAM_2Gx16:
1325 param->reg_AC2 = 0xCC00B02B | trap_AC2;
1326 break;
1327 case AST_DRAM_4Gx16:
1328 param->reg_AC2 = 0xCC00B03F | trap_AC2;
1329 break;
1330 }
1331
1332 break;
1333
1334 case 408:
1335 ast_moutdwm(ast, 0x1E6E2020, 0x01F0);
1336 param->wodt = 1;
1337 param->rodt = 0;
1338 param->reg_AC1 = 0x33302714;
1339 param->reg_AC2 = 0xCC00B01B | trap_AC2;
1340 param->reg_DQSIC = 0x000000E2;
1341 param->reg_MRS = 0x00000C02 | trap_MRS;
1342 param->reg_EMRS = 0x00000040;
1343 param->reg_DRV = 0x000000FA;
1344 param->reg_IOZ = 0x00000034;
1345 param->reg_DQIDLY = 0x00000089;
1346 param->reg_FREQ = 0x000050C0;
1347 param->madj_max = 96;
1348 param->dll2_finetune_step = 4;
1349
1350 switch (param->dram_chipid) {
1351 case AST_DRAM_512Mx16:
1352 param->reg_AC2 = 0xCC00B016 | trap_AC2;
1353 break;
1354 default:
1355 case AST_DRAM_1Gx16:
1356 param->reg_AC2 = 0xCC00B01B | trap_AC2;
1357 break;
1358 case AST_DRAM_2Gx16:
1359 param->reg_AC2 = 0xCC00B02B | trap_AC2;
1360 break;
1361 case AST_DRAM_4Gx16:
1362 param->reg_AC2 = 0xCC00B03F | trap_AC2;
1363 break;
1364 }
1365
1366 break;
1367 case 456:
1368 ast_moutdwm(ast, 0x1E6E2020, 0x0230);
1369 param->wodt = 0;
1370 param->reg_AC1 = 0x33302815;
1371 param->reg_AC2 = 0xCD44B01E;
1372 param->reg_DQSIC = 0x000000FC;
1373 param->reg_MRS = 0x00000E72;
1374 param->reg_EMRS = 0x00000000;
1375 param->reg_DRV = 0x00000000;
1376 param->reg_IOZ = 0x00000034;
1377 param->reg_DQIDLY = 0x00000097;
1378 param->reg_FREQ = 0x000052C0;
1379 param->madj_max = 88;
1380 param->dll2_finetune_step = 3;
1381 break;
1382 case 504:
1383 ast_moutdwm(ast, 0x1E6E2020, 0x0261);
1384 param->wodt = 1;
1385 param->rodt = 1;
1386 param->reg_AC1 = 0x33302815;
1387 param->reg_AC2 = 0xDE44C022;
1388 param->reg_DQSIC = 0x00000117;
1389 param->reg_MRS = 0x00000E72;
1390 param->reg_EMRS = 0x00000040;
1391 param->reg_DRV = 0x0000000A;
1392 param->reg_IOZ = 0x00000045;
1393 param->reg_DQIDLY = 0x000000A0;
1394 param->reg_FREQ = 0x000054C0;
1395 param->madj_max = 79;
1396 param->dll2_finetune_step = 3;
1397 break;
1398 case 528:
1399 ast_moutdwm(ast, 0x1E6E2020, 0x0120);
1400 param->wodt = 1;
1401 param->rodt = 1;
1402 param->reg_AC1 = 0x33302815;
1403 param->reg_AC2 = 0xEF44D024;
1404 param->reg_DQSIC = 0x00000125;
1405 param->reg_MRS = 0x00000E72;
1406 param->reg_EMRS = 0x00000004;
1407 param->reg_DRV = 0x000000F9;
1408 param->reg_IOZ = 0x00000045;
1409 param->reg_DQIDLY = 0x000000A7;
1410 param->reg_FREQ = 0x000055C0;
1411 param->madj_max = 76;
1412 param->dll2_finetune_step = 3;
1413 break;
1414 case 552:
1415 ast_moutdwm(ast, 0x1E6E2020, 0x02A1);
1416 param->wodt = 1;
1417 param->rodt = 1;
1418 param->reg_AC1 = 0x43402915;
1419 param->reg_AC2 = 0xFF44E025;
1420 param->reg_DQSIC = 0x00000132;
1421 param->reg_MRS = 0x00000E72;
1422 param->reg_EMRS = 0x00000040;
1423 param->reg_DRV = 0x0000000A;
1424 param->reg_IOZ = 0x00000045;
1425 param->reg_DQIDLY = 0x000000AD;
1426 param->reg_FREQ = 0x000056C0;
1427 param->madj_max = 76;
1428 param->dll2_finetune_step = 3;
1429 break;
1430 case 576:
1431 ast_moutdwm(ast, 0x1E6E2020, 0x0140);
1432 param->wodt = 1;
1433 param->rodt = 1;
1434 param->reg_AC1 = 0x43402915;
1435 param->reg_AC2 = 0xFF44E027;
1436 param->reg_DQSIC = 0x0000013F;
1437 param->reg_MRS = 0x00000E72;
1438 param->reg_EMRS = 0x00000004;
1439 param->reg_DRV = 0x000000F5;
1440 param->reg_IOZ = 0x00000045;
1441 param->reg_DQIDLY = 0x000000B3;
1442 param->reg_FREQ = 0x000057C0;
1443 param->madj_max = 76;
1444 param->dll2_finetune_step = 3;
1445 break;
1446 }
1447
1448 switch (param->dram_chipid) {
1449 case AST_DRAM_512Mx16:
1450 param->dram_config = 0x100;
1451 break;
1452 default:
1453 case AST_DRAM_1Gx16:
1454 param->dram_config = 0x121;
1455 break;
1456 case AST_DRAM_2Gx16:
1457 param->dram_config = 0x122;
1458 break;
1459 case AST_DRAM_4Gx16:
1460 param->dram_config = 0x123;
1461 break;
1462 } /* switch size */
1463
1464 switch (param->vram_size) {
1465 default:
1466 case AST_VIDMEM_SIZE_8M:
1467 param->dram_config |= 0x00;
1468 break;
1469 case AST_VIDMEM_SIZE_16M:
1470 param->dram_config |= 0x04;
1471 break;
1472 case AST_VIDMEM_SIZE_32M:
1473 param->dram_config |= 0x08;
1474 break;
1475 case AST_VIDMEM_SIZE_64M:
1476 param->dram_config |= 0x0c;
1477 break;
1478 }
1479}
1480
1481static void ddr2_init(struct ast_private *ast, struct ast2300_dram_param *param)
1482{
1483 u32 data, data2, retry = 0;
1484
1485ddr2_init_start:
1486 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1487 ast_moutdwm(ast, 0x1E6E0018, 0x00000100);
1488 ast_moutdwm(ast, 0x1E6E0024, 0x00000000);
1489 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ);
1490 ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ);
1491 udelay(10);
1492 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000);
1493 udelay(10);
1494
1495 ast_moutdwm(ast, 0x1E6E0004, param->dram_config);
1496 ast_moutdwm(ast, 0x1E6E0008, 0x90040f);
1497 ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1);
1498 ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2);
1499 ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC);
1500 ast_moutdwm(ast, 0x1E6E0080, 0x00000000);
1501 ast_moutdwm(ast, 0x1E6E0084, 0x00000000);
1502 ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY);
1503 ast_moutdwm(ast, 0x1E6E0018, 0x4000A130);
1504 ast_moutdwm(ast, 0x1E6E0018, 0x00002330);
1505 ast_moutdwm(ast, 0x1E6E0038, 0x00000000);
1506 ast_moutdwm(ast, 0x1E6E0040, 0xFF808000);
1507 ast_moutdwm(ast, 0x1E6E0044, 0x88848466);
1508 ast_moutdwm(ast, 0x1E6E0048, 0x44440008);
1509 ast_moutdwm(ast, 0x1E6E004C, 0x00000000);
1510 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1511 ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1512 ast_moutdwm(ast, 0x1E6E0054, 0);
1513 ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV);
1514 ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ);
1515 ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1516 ast_moutdwm(ast, 0x1E6E0074, 0x00000000);
1517 ast_moutdwm(ast, 0x1E6E0078, 0x00000000);
1518 ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1519
1520 /* Wait MCLK2X lock to MCLK */
1521 do {
1522 data = ast_mindwm(ast, 0x1E6E001C);
1523 } while (!(data & 0x08000000));
1524 data = ast_mindwm(ast, 0x1E6E001C);
1525 data = (data >> 8) & 0xff;
1526 while ((data & 0x08) || ((data & 0x7) < 2) || (data < 4)) {
1527 data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4;
1528 if ((data2 & 0xff) > param->madj_max) {
1529 break;
1530 }
1531 ast_moutdwm(ast, 0x1E6E0064, data2);
1532 if (data2 & 0x00100000) {
1533 data2 = ((data2 & 0xff) >> 3) + 3;
1534 } else {
1535 data2 = ((data2 & 0xff) >> 2) + 5;
1536 }
1537 data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff;
1538 data2 += data & 0xff;
1539 data = data | (data2 << 8);
1540 ast_moutdwm(ast, 0x1E6E0068, data);
1541 udelay(10);
1542 ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000);
1543 udelay(10);
1544 data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff;
1545 ast_moutdwm(ast, 0x1E6E0018, data);
1546 data = data | 0x200;
1547 ast_moutdwm(ast, 0x1E6E0018, data);
1548 do {
1549 data = ast_mindwm(ast, 0x1E6E001C);
1550 } while (!(data & 0x08000000));
1551
1552 data = ast_mindwm(ast, 0x1E6E001C);
1553 data = (data >> 8) & 0xff;
1554 }
1555 ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0008) & 0xffff);
1556 data = ast_mindwm(ast, 0x1E6E0018) | 0xC00;
1557 ast_moutdwm(ast, 0x1E6E0018, data);
1558
1559 ast_moutdwm(ast, 0x1E6E0034, 0x00000001);
1560 ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1561 udelay(50);
1562 /* Mode Register Setting */
1563 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100);
1564 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1565 ast_moutdwm(ast, 0x1E6E0028, 0x00000005);
1566 ast_moutdwm(ast, 0x1E6E0028, 0x00000007);
1567 ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1568 ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1569
1570 ast_moutdwm(ast, 0x1E6E000C, 0x00005C08);
1571 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS);
1572 ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1573 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS | 0x380);
1574 ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1575 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1576 ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1577
1578 ast_moutdwm(ast, 0x1E6E000C, 0x7FFF5C01);
1579 data = 0;
1580 if (param->wodt) {
1581 data = 0x500;
1582 }
1583 if (param->rodt) {
1584 data = data | 0x3000 | ((param->reg_AC2 & 0x60000) >> 3);
1585 }
1586 ast_moutdwm(ast, 0x1E6E0034, data | 0x3);
1587 ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ);
1588
1589 /* Calibrate the DQSI delay */
1590 if ((cbr_dll2(ast, param) == false) && (retry++ < 10))
1591 goto ddr2_init_start;
1592
1593 /* ECC Memory Initialization */
1594#ifdef ECC
1595 ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1596 ast_moutdwm(ast, 0x1E6E0070, 0x221);
1597 do {
1598 data = ast_mindwm(ast, 0x1E6E0070);
1599 } while (!(data & 0x00001000));
1600 ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1601 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1602 ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1603#endif
1604
1605}
1606
1607static void ast_init_dram_2300(struct drm_device *dev)
1608{
1609 struct ast_private *ast = dev->dev_private;
1610 struct ast2300_dram_param param;
1611 u32 temp;
1612 u8 reg;
1613
1614 reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
1615 if ((reg & 0x80) == 0) {/* vga only */
1616 ast_write32(ast, 0xf004, 0x1e6e0000);
1617 ast_write32(ast, 0xf000, 0x1);
1618 ast_write32(ast, 0x12000, 0x1688a8a8);
1619 do {
1620 ;
1621 } while (ast_read32(ast, 0x12000) != 0x1);
1622
1623 ast_write32(ast, 0x10000, 0xfc600309);
1624 do {
1625 ;
1626 } while (ast_read32(ast, 0x10000) != 0x1);
1627
1628 /* Slow down CPU/AHB CLK in VGA only mode */
1629 temp = ast_read32(ast, 0x12008);
1630 temp |= 0x73;
1631 ast_write32(ast, 0x12008, temp);
1632
1633 param.dram_type = AST_DDR3;
1634 if (temp & 0x01000000)
1635 param.dram_type = AST_DDR2;
1636 param.dram_chipid = ast->dram_type;
1637 param.dram_freq = ast->mclk;
1638 param.vram_size = ast->vram_size;
1639
1640 if (param.dram_type == AST_DDR3) {
1641 get_ddr3_info(ast, ¶m);
1642 ddr3_init(ast, ¶m);
1643 } else {
1644 get_ddr2_info(ast, ¶m);
1645 ddr2_init(ast, ¶m);
1646 }
1647
1648 temp = ast_mindwm(ast, 0x1e6e2040);
1649 ast_moutdwm(ast, 0x1e6e2040, temp | 0x40);
1650 }
1651
1652 /* wait ready */
1653 do {
1654 reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
1655 } while ((reg & 0x40) == 0);
1656}
1657
1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
16 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
17 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
18 * USE OR OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * The above copyright notice and this permission notice (including the
21 * next paragraph) shall be included in all copies or substantial portions
22 * of the Software.
23 *
24 */
25/*
26 * Authors: Dave Airlie <airlied@redhat.com>
27 */
28
29#include <linux/delay.h>
30#include <linux/pci.h>
31
32#include <drm/drm_print.h>
33
34#include "ast_dram_tables.h"
35#include "ast_drv.h"
36
37static void ast_post_chip_2300(struct ast_device *ast);
38static void ast_post_chip_2500(struct ast_device *ast);
39
40static const u8 extreginfo[] = { 0x0f, 0x04, 0x1c, 0xff };
41static const u8 extreginfo_ast2300[] = { 0x0f, 0x04, 0x1f, 0xff };
42
43static void ast_set_def_ext_reg(struct ast_device *ast)
44{
45 u8 i, index, reg;
46 const u8 *ext_reg_info;
47
48 /* reset scratch */
49 for (i = 0x81; i <= 0x9f; i++)
50 ast_set_index_reg(ast, AST_IO_VGACRI, i, 0x00);
51
52 if (IS_AST_GEN4(ast) || IS_AST_GEN5(ast) || IS_AST_GEN6(ast))
53 ext_reg_info = extreginfo_ast2300;
54 else
55 ext_reg_info = extreginfo;
56
57 index = 0xa0;
58 while (*ext_reg_info != 0xff) {
59 ast_set_index_reg_mask(ast, AST_IO_VGACRI, index, 0x00, *ext_reg_info);
60 index++;
61 ext_reg_info++;
62 }
63
64 /* disable standard IO/MEM decode if secondary */
65 /* ast_set_index_reg-mask(ast, AST_IO_VGACRI, 0xa1, 0xff, 0x3); */
66
67 /* Set Ext. Default */
68 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x8c, 0x00, 0x01);
69 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb7, 0x00, 0x00);
70
71 /* Enable RAMDAC for A1 */
72 reg = 0x04;
73 if (IS_AST_GEN4(ast) || IS_AST_GEN5(ast) || IS_AST_GEN6(ast))
74 reg |= 0x20;
75 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb6, 0xff, reg);
76}
77
78static u32 __ast_mindwm(void __iomem *regs, u32 r)
79{
80 u32 data;
81
82 __ast_write32(regs, 0xf004, r & 0xffff0000);
83 __ast_write32(regs, 0xf000, 0x1);
84
85 do {
86 data = __ast_read32(regs, 0xf004) & 0xffff0000;
87 } while (data != (r & 0xffff0000));
88
89 return __ast_read32(regs, 0x10000 + (r & 0x0000ffff));
90}
91
92static void __ast_moutdwm(void __iomem *regs, u32 r, u32 v)
93{
94 u32 data;
95
96 __ast_write32(regs, 0xf004, r & 0xffff0000);
97 __ast_write32(regs, 0xf000, 0x1);
98
99 do {
100 data = __ast_read32(regs, 0xf004) & 0xffff0000;
101 } while (data != (r & 0xffff0000));
102
103 __ast_write32(regs, 0x10000 + (r & 0x0000ffff), v);
104}
105
106u32 ast_mindwm(struct ast_device *ast, u32 r)
107{
108 return __ast_mindwm(ast->regs, r);
109}
110
111void ast_moutdwm(struct ast_device *ast, u32 r, u32 v)
112{
113 __ast_moutdwm(ast->regs, r, v);
114}
115
116/*
117 * AST2100/2150 DLL CBR Setting
118 */
119#define CBR_SIZE_AST2150 ((16 << 10) - 1)
120#define CBR_PASSNUM_AST2150 5
121#define CBR_THRESHOLD_AST2150 10
122#define CBR_THRESHOLD2_AST2150 10
123#define TIMEOUT_AST2150 5000000
124
125#define CBR_PATNUM_AST2150 8
126
127static const u32 pattern_AST2150[14] = {
128 0xFF00FF00,
129 0xCC33CC33,
130 0xAA55AA55,
131 0xFFFE0001,
132 0x683501FE,
133 0x0F1929B0,
134 0x2D0B4346,
135 0x60767F02,
136 0x6FBE36A6,
137 0x3A253035,
138 0x3019686D,
139 0x41C6167E,
140 0x620152BF,
141 0x20F050E0
142};
143
144static u32 mmctestburst2_ast2150(struct ast_device *ast, u32 datagen)
145{
146 u32 data, timeout;
147
148 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
149 ast_moutdwm(ast, 0x1e6e0070, 0x00000001 | (datagen << 3));
150 timeout = 0;
151 do {
152 data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
153 if (++timeout > TIMEOUT_AST2150) {
154 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
155 return 0xffffffff;
156 }
157 } while (!data);
158 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
159 ast_moutdwm(ast, 0x1e6e0070, 0x00000003 | (datagen << 3));
160 timeout = 0;
161 do {
162 data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
163 if (++timeout > TIMEOUT_AST2150) {
164 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
165 return 0xffffffff;
166 }
167 } while (!data);
168 data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7;
169 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
170 return data;
171}
172
173#if 0 /* unused in DDX driver - here for completeness */
174static u32 mmctestsingle2_ast2150(struct ast_device *ast, u32 datagen)
175{
176 u32 data, timeout;
177
178 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
179 ast_moutdwm(ast, 0x1e6e0070, 0x00000005 | (datagen << 3));
180 timeout = 0;
181 do {
182 data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
183 if (++timeout > TIMEOUT_AST2150) {
184 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
185 return 0xffffffff;
186 }
187 } while (!data);
188 data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7;
189 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
190 return data;
191}
192#endif
193
194static int cbrtest_ast2150(struct ast_device *ast)
195{
196 int i;
197
198 for (i = 0; i < 8; i++)
199 if (mmctestburst2_ast2150(ast, i))
200 return 0;
201 return 1;
202}
203
204static int cbrscan_ast2150(struct ast_device *ast, int busw)
205{
206 u32 patcnt, loop;
207
208 for (patcnt = 0; patcnt < CBR_PATNUM_AST2150; patcnt++) {
209 ast_moutdwm(ast, 0x1e6e007c, pattern_AST2150[patcnt]);
210 for (loop = 0; loop < CBR_PASSNUM_AST2150; loop++) {
211 if (cbrtest_ast2150(ast))
212 break;
213 }
214 if (loop == CBR_PASSNUM_AST2150)
215 return 0;
216 }
217 return 1;
218}
219
220
221static void cbrdlli_ast2150(struct ast_device *ast, int busw)
222{
223 u32 dll_min[4], dll_max[4], dlli, data, passcnt;
224
225cbr_start:
226 dll_min[0] = dll_min[1] = dll_min[2] = dll_min[3] = 0xff;
227 dll_max[0] = dll_max[1] = dll_max[2] = dll_max[3] = 0x0;
228 passcnt = 0;
229
230 for (dlli = 0; dlli < 100; dlli++) {
231 ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24));
232 data = cbrscan_ast2150(ast, busw);
233 if (data != 0) {
234 if (data & 0x1) {
235 if (dll_min[0] > dlli)
236 dll_min[0] = dlli;
237 if (dll_max[0] < dlli)
238 dll_max[0] = dlli;
239 }
240 passcnt++;
241 } else if (passcnt >= CBR_THRESHOLD_AST2150)
242 goto cbr_start;
243 }
244 if (dll_max[0] == 0 || (dll_max[0]-dll_min[0]) < CBR_THRESHOLD_AST2150)
245 goto cbr_start;
246
247 dlli = dll_min[0] + (((dll_max[0] - dll_min[0]) * 7) >> 4);
248 ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24));
249}
250
251
252
253static void ast_init_dram_reg(struct ast_device *ast)
254{
255 u8 j;
256 u32 data, temp, i;
257 const struct ast_dramstruct *dram_reg_info;
258
259 j = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
260
261 if ((j & 0x80) == 0) { /* VGA only */
262 if (IS_AST_GEN1(ast)) {
263 dram_reg_info = ast2000_dram_table_data;
264 ast_write32(ast, 0xf004, 0x1e6e0000);
265 ast_write32(ast, 0xf000, 0x1);
266 ast_write32(ast, 0x10100, 0xa8);
267
268 do {
269 ;
270 } while (ast_read32(ast, 0x10100) != 0xa8);
271 } else { /* GEN2/GEN3 */
272 if (ast->chip == AST2100 || ast->chip == AST2200)
273 dram_reg_info = ast2100_dram_table_data;
274 else
275 dram_reg_info = ast1100_dram_table_data;
276
277 ast_write32(ast, 0xf004, 0x1e6e0000);
278 ast_write32(ast, 0xf000, 0x1);
279 ast_write32(ast, 0x12000, 0x1688A8A8);
280 do {
281 ;
282 } while (ast_read32(ast, 0x12000) != 0x01);
283
284 ast_write32(ast, 0x10000, 0xfc600309);
285 do {
286 ;
287 } while (ast_read32(ast, 0x10000) != 0x01);
288 }
289
290 while (dram_reg_info->index != 0xffff) {
291 if (dram_reg_info->index == 0xff00) {/* delay fn */
292 for (i = 0; i < 15; i++)
293 udelay(dram_reg_info->data);
294 } else if (dram_reg_info->index == 0x4 && !IS_AST_GEN1(ast)) {
295 data = dram_reg_info->data;
296 if (ast->dram_type == AST_DRAM_1Gx16)
297 data = 0x00000d89;
298 else if (ast->dram_type == AST_DRAM_1Gx32)
299 data = 0x00000c8d;
300
301 temp = ast_read32(ast, 0x12070);
302 temp &= 0xc;
303 temp <<= 2;
304 ast_write32(ast, 0x10000 + dram_reg_info->index, data | temp);
305 } else
306 ast_write32(ast, 0x10000 + dram_reg_info->index, dram_reg_info->data);
307 dram_reg_info++;
308 }
309
310 /* AST 2100/2150 DRAM calibration */
311 data = ast_read32(ast, 0x10120);
312 if (data == 0x5061) { /* 266Mhz */
313 data = ast_read32(ast, 0x10004);
314 if (data & 0x40)
315 cbrdlli_ast2150(ast, 16); /* 16 bits */
316 else
317 cbrdlli_ast2150(ast, 32); /* 32 bits */
318 }
319
320 switch (AST_GEN(ast)) {
321 case 1:
322 temp = ast_read32(ast, 0x10140);
323 ast_write32(ast, 0x10140, temp | 0x40);
324 break;
325 case 2:
326 case 3:
327 temp = ast_read32(ast, 0x1200c);
328 ast_write32(ast, 0x1200c, temp & 0xfffffffd);
329 temp = ast_read32(ast, 0x12040);
330 ast_write32(ast, 0x12040, temp | 0x40);
331 break;
332 default:
333 break;
334 }
335 }
336
337 /* wait ready */
338 do {
339 j = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
340 } while ((j & 0x40) == 0);
341}
342
343void ast_post_gpu(struct ast_device *ast)
344{
345 ast_set_def_ext_reg(ast);
346
347 if (IS_AST_GEN7(ast)) {
348 if (ast->tx_chip == AST_TX_ASTDP)
349 ast_dp_launch(ast);
350 } else if (ast->config_mode == ast_use_p2a) {
351 if (IS_AST_GEN6(ast))
352 ast_post_chip_2500(ast);
353 else if (IS_AST_GEN5(ast) || IS_AST_GEN4(ast))
354 ast_post_chip_2300(ast);
355 else
356 ast_init_dram_reg(ast);
357
358 ast_init_3rdtx(ast);
359 } else {
360 if (ast->tx_chip == AST_TX_SIL164)
361 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xcf, 0x80); /* Enable DVO */
362 }
363}
364
365/* AST 2300 DRAM settings */
366#define AST_DDR3 0
367#define AST_DDR2 1
368
369struct ast2300_dram_param {
370 u32 dram_type;
371 u32 dram_chipid;
372 u32 dram_freq;
373 u32 vram_size;
374 u32 odt;
375 u32 wodt;
376 u32 rodt;
377 u32 dram_config;
378 u32 reg_PERIOD;
379 u32 reg_MADJ;
380 u32 reg_SADJ;
381 u32 reg_MRS;
382 u32 reg_EMRS;
383 u32 reg_AC1;
384 u32 reg_AC2;
385 u32 reg_DQSIC;
386 u32 reg_DRV;
387 u32 reg_IOZ;
388 u32 reg_DQIDLY;
389 u32 reg_FREQ;
390 u32 madj_max;
391 u32 dll2_finetune_step;
392};
393
394/*
395 * DQSI DLL CBR Setting
396 */
397#define CBR_SIZE0 ((1 << 10) - 1)
398#define CBR_SIZE1 ((4 << 10) - 1)
399#define CBR_SIZE2 ((64 << 10) - 1)
400#define CBR_PASSNUM 5
401#define CBR_PASSNUM2 5
402#define CBR_THRESHOLD 10
403#define CBR_THRESHOLD2 10
404#define TIMEOUT 5000000
405#define CBR_PATNUM 8
406
407static const u32 pattern[8] = {
408 0xFF00FF00,
409 0xCC33CC33,
410 0xAA55AA55,
411 0x88778877,
412 0x92CC4D6E,
413 0x543D3CDE,
414 0xF1E843C7,
415 0x7C61D253
416};
417
418static bool mmc_test(struct ast_device *ast, u32 datagen, u8 test_ctl)
419{
420 u32 data, timeout;
421
422 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
423 ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl);
424 timeout = 0;
425 do {
426 data = ast_mindwm(ast, 0x1e6e0070) & 0x3000;
427 if (data & 0x2000)
428 return false;
429 if (++timeout > TIMEOUT) {
430 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
431 return false;
432 }
433 } while (!data);
434 ast_moutdwm(ast, 0x1e6e0070, 0x0);
435 return true;
436}
437
438static u32 mmc_test2(struct ast_device *ast, u32 datagen, u8 test_ctl)
439{
440 u32 data, timeout;
441
442 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
443 ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl);
444 timeout = 0;
445 do {
446 data = ast_mindwm(ast, 0x1e6e0070) & 0x1000;
447 if (++timeout > TIMEOUT) {
448 ast_moutdwm(ast, 0x1e6e0070, 0x0);
449 return 0xffffffff;
450 }
451 } while (!data);
452 data = ast_mindwm(ast, 0x1e6e0078);
453 data = (data | (data >> 16)) & 0xffff;
454 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
455 return data;
456}
457
458
459static bool mmc_test_burst(struct ast_device *ast, u32 datagen)
460{
461 return mmc_test(ast, datagen, 0xc1);
462}
463
464static u32 mmc_test_burst2(struct ast_device *ast, u32 datagen)
465{
466 return mmc_test2(ast, datagen, 0x41);
467}
468
469static bool mmc_test_single(struct ast_device *ast, u32 datagen)
470{
471 return mmc_test(ast, datagen, 0xc5);
472}
473
474static u32 mmc_test_single2(struct ast_device *ast, u32 datagen)
475{
476 return mmc_test2(ast, datagen, 0x05);
477}
478
479static bool mmc_test_single_2500(struct ast_device *ast, u32 datagen)
480{
481 return mmc_test(ast, datagen, 0x85);
482}
483
484static int cbr_test(struct ast_device *ast)
485{
486 u32 data;
487 int i;
488 data = mmc_test_single2(ast, 0);
489 if ((data & 0xff) && (data & 0xff00))
490 return 0;
491 for (i = 0; i < 8; i++) {
492 data = mmc_test_burst2(ast, i);
493 if ((data & 0xff) && (data & 0xff00))
494 return 0;
495 }
496 if (!data)
497 return 3;
498 else if (data & 0xff)
499 return 2;
500 return 1;
501}
502
503static int cbr_scan(struct ast_device *ast)
504{
505 u32 data, data2, patcnt, loop;
506
507 data2 = 3;
508 for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) {
509 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
510 for (loop = 0; loop < CBR_PASSNUM2; loop++) {
511 if ((data = cbr_test(ast)) != 0) {
512 data2 &= data;
513 if (!data2)
514 return 0;
515 break;
516 }
517 }
518 if (loop == CBR_PASSNUM2)
519 return 0;
520 }
521 return data2;
522}
523
524static u32 cbr_test2(struct ast_device *ast)
525{
526 u32 data;
527
528 data = mmc_test_burst2(ast, 0);
529 if (data == 0xffff)
530 return 0;
531 data |= mmc_test_single2(ast, 0);
532 if (data == 0xffff)
533 return 0;
534
535 return ~data & 0xffff;
536}
537
538static u32 cbr_scan2(struct ast_device *ast)
539{
540 u32 data, data2, patcnt, loop;
541
542 data2 = 0xffff;
543 for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) {
544 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
545 for (loop = 0; loop < CBR_PASSNUM2; loop++) {
546 if ((data = cbr_test2(ast)) != 0) {
547 data2 &= data;
548 if (!data2)
549 return 0;
550 break;
551 }
552 }
553 if (loop == CBR_PASSNUM2)
554 return 0;
555 }
556 return data2;
557}
558
559static bool cbr_test3(struct ast_device *ast)
560{
561 if (!mmc_test_burst(ast, 0))
562 return false;
563 if (!mmc_test_single(ast, 0))
564 return false;
565 return true;
566}
567
568static bool cbr_scan3(struct ast_device *ast)
569{
570 u32 patcnt, loop;
571
572 for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) {
573 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
574 for (loop = 0; loop < 2; loop++) {
575 if (cbr_test3(ast))
576 break;
577 }
578 if (loop == 2)
579 return false;
580 }
581 return true;
582}
583
584static bool finetuneDQI_L(struct ast_device *ast, struct ast2300_dram_param *param)
585{
586 u32 gold_sadj[2], dllmin[16], dllmax[16], dlli, data, cnt, mask, passcnt, retry = 0;
587 bool status = false;
588FINETUNE_START:
589 for (cnt = 0; cnt < 16; cnt++) {
590 dllmin[cnt] = 0xff;
591 dllmax[cnt] = 0x0;
592 }
593 passcnt = 0;
594 for (dlli = 0; dlli < 76; dlli++) {
595 ast_moutdwm(ast, 0x1E6E0068, 0x00001400 | (dlli << 16) | (dlli << 24));
596 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE1);
597 data = cbr_scan2(ast);
598 if (data != 0) {
599 mask = 0x00010001;
600 for (cnt = 0; cnt < 16; cnt++) {
601 if (data & mask) {
602 if (dllmin[cnt] > dlli) {
603 dllmin[cnt] = dlli;
604 }
605 if (dllmax[cnt] < dlli) {
606 dllmax[cnt] = dlli;
607 }
608 }
609 mask <<= 1;
610 }
611 passcnt++;
612 } else if (passcnt >= CBR_THRESHOLD2) {
613 break;
614 }
615 }
616 gold_sadj[0] = 0x0;
617 passcnt = 0;
618 for (cnt = 0; cnt < 16; cnt++) {
619 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) {
620 gold_sadj[0] += dllmin[cnt];
621 passcnt++;
622 }
623 }
624 if (retry++ > 10)
625 goto FINETUNE_DONE;
626 if (passcnt != 16) {
627 goto FINETUNE_START;
628 }
629 status = true;
630FINETUNE_DONE:
631 gold_sadj[0] = gold_sadj[0] >> 4;
632 gold_sadj[1] = gold_sadj[0];
633
634 data = 0;
635 for (cnt = 0; cnt < 8; cnt++) {
636 data >>= 3;
637 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) {
638 dlli = dllmin[cnt];
639 if (gold_sadj[0] >= dlli) {
640 dlli = ((gold_sadj[0] - dlli) * 19) >> 5;
641 if (dlli > 3) {
642 dlli = 3;
643 }
644 } else {
645 dlli = ((dlli - gold_sadj[0]) * 19) >> 5;
646 if (dlli > 4) {
647 dlli = 4;
648 }
649 dlli = (8 - dlli) & 0x7;
650 }
651 data |= dlli << 21;
652 }
653 }
654 ast_moutdwm(ast, 0x1E6E0080, data);
655
656 data = 0;
657 for (cnt = 8; cnt < 16; cnt++) {
658 data >>= 3;
659 if ((dllmax[cnt] > dllmin[cnt]) && ((dllmax[cnt] - dllmin[cnt]) >= CBR_THRESHOLD2)) {
660 dlli = dllmin[cnt];
661 if (gold_sadj[1] >= dlli) {
662 dlli = ((gold_sadj[1] - dlli) * 19) >> 5;
663 if (dlli > 3) {
664 dlli = 3;
665 } else {
666 dlli = (dlli - 1) & 0x7;
667 }
668 } else {
669 dlli = ((dlli - gold_sadj[1]) * 19) >> 5;
670 dlli += 1;
671 if (dlli > 4) {
672 dlli = 4;
673 }
674 dlli = (8 - dlli) & 0x7;
675 }
676 data |= dlli << 21;
677 }
678 }
679 ast_moutdwm(ast, 0x1E6E0084, data);
680 return status;
681} /* finetuneDQI_L */
682
683static void finetuneDQSI(struct ast_device *ast)
684{
685 u32 dlli, dqsip, dqidly;
686 u32 reg_mcr18, reg_mcr0c, passcnt[2], diff;
687 u32 g_dqidly, g_dqsip, g_margin, g_side;
688 u16 pass[32][2][2];
689 char tag[2][76];
690
691 /* Disable DQI CBR */
692 reg_mcr0c = ast_mindwm(ast, 0x1E6E000C);
693 reg_mcr18 = ast_mindwm(ast, 0x1E6E0018);
694 reg_mcr18 &= 0x0000ffff;
695 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18);
696
697 for (dlli = 0; dlli < 76; dlli++) {
698 tag[0][dlli] = 0x0;
699 tag[1][dlli] = 0x0;
700 }
701 for (dqidly = 0; dqidly < 32; dqidly++) {
702 pass[dqidly][0][0] = 0xff;
703 pass[dqidly][0][1] = 0x0;
704 pass[dqidly][1][0] = 0xff;
705 pass[dqidly][1][1] = 0x0;
706 }
707 for (dqidly = 0; dqidly < 32; dqidly++) {
708 passcnt[0] = passcnt[1] = 0;
709 for (dqsip = 0; dqsip < 2; dqsip++) {
710 ast_moutdwm(ast, 0x1E6E000C, 0);
711 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18 | (dqidly << 16) | (dqsip << 23));
712 ast_moutdwm(ast, 0x1E6E000C, reg_mcr0c);
713 for (dlli = 0; dlli < 76; dlli++) {
714 ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24));
715 ast_moutdwm(ast, 0x1E6E0070, 0);
716 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE0);
717 if (cbr_scan3(ast)) {
718 if (dlli == 0)
719 break;
720 passcnt[dqsip]++;
721 tag[dqsip][dlli] = 'P';
722 if (dlli < pass[dqidly][dqsip][0])
723 pass[dqidly][dqsip][0] = (u16) dlli;
724 if (dlli > pass[dqidly][dqsip][1])
725 pass[dqidly][dqsip][1] = (u16) dlli;
726 } else if (passcnt[dqsip] >= 5)
727 break;
728 else {
729 pass[dqidly][dqsip][0] = 0xff;
730 pass[dqidly][dqsip][1] = 0x0;
731 }
732 }
733 }
734 if (passcnt[0] == 0 && passcnt[1] == 0)
735 dqidly++;
736 }
737 /* Search margin */
738 g_dqidly = g_dqsip = g_margin = g_side = 0;
739
740 for (dqidly = 0; dqidly < 32; dqidly++) {
741 for (dqsip = 0; dqsip < 2; dqsip++) {
742 if (pass[dqidly][dqsip][0] > pass[dqidly][dqsip][1])
743 continue;
744 diff = pass[dqidly][dqsip][1] - pass[dqidly][dqsip][0];
745 if ((diff+2) < g_margin)
746 continue;
747 passcnt[0] = passcnt[1] = 0;
748 for (dlli = pass[dqidly][dqsip][0]; dlli > 0 && tag[dqsip][dlli] != 0; dlli--, passcnt[0]++);
749 for (dlli = pass[dqidly][dqsip][1]; dlli < 76 && tag[dqsip][dlli] != 0; dlli++, passcnt[1]++);
750 if (passcnt[0] > passcnt[1])
751 passcnt[0] = passcnt[1];
752 passcnt[1] = 0;
753 if (passcnt[0] > g_side)
754 passcnt[1] = passcnt[0] - g_side;
755 if (diff > (g_margin+1) && (passcnt[1] > 0 || passcnt[0] > 8)) {
756 g_margin = diff;
757 g_dqidly = dqidly;
758 g_dqsip = dqsip;
759 g_side = passcnt[0];
760 } else if (passcnt[1] > 1 && g_side < 8) {
761 if (diff > g_margin)
762 g_margin = diff;
763 g_dqidly = dqidly;
764 g_dqsip = dqsip;
765 g_side = passcnt[0];
766 }
767 }
768 }
769 reg_mcr18 = reg_mcr18 | (g_dqidly << 16) | (g_dqsip << 23);
770 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18);
771
772}
773static bool cbr_dll2(struct ast_device *ast, struct ast2300_dram_param *param)
774{
775 u32 dllmin[2], dllmax[2], dlli, data, passcnt, retry = 0;
776 bool status = false;
777
778 finetuneDQSI(ast);
779 if (finetuneDQI_L(ast, param) == false)
780 return status;
781
782CBR_START2:
783 dllmin[0] = dllmin[1] = 0xff;
784 dllmax[0] = dllmax[1] = 0x0;
785 passcnt = 0;
786 for (dlli = 0; dlli < 76; dlli++) {
787 ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24));
788 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE2);
789 data = cbr_scan(ast);
790 if (data != 0) {
791 if (data & 0x1) {
792 if (dllmin[0] > dlli) {
793 dllmin[0] = dlli;
794 }
795 if (dllmax[0] < dlli) {
796 dllmax[0] = dlli;
797 }
798 }
799 if (data & 0x2) {
800 if (dllmin[1] > dlli) {
801 dllmin[1] = dlli;
802 }
803 if (dllmax[1] < dlli) {
804 dllmax[1] = dlli;
805 }
806 }
807 passcnt++;
808 } else if (passcnt >= CBR_THRESHOLD) {
809 break;
810 }
811 }
812 if (retry++ > 10)
813 goto CBR_DONE2;
814 if (dllmax[0] == 0 || (dllmax[0]-dllmin[0]) < CBR_THRESHOLD) {
815 goto CBR_START2;
816 }
817 if (dllmax[1] == 0 || (dllmax[1]-dllmin[1]) < CBR_THRESHOLD) {
818 goto CBR_START2;
819 }
820 status = true;
821CBR_DONE2:
822 dlli = (dllmin[1] + dllmax[1]) >> 1;
823 dlli <<= 8;
824 dlli += (dllmin[0] + dllmax[0]) >> 1;
825 ast_moutdwm(ast, 0x1E6E0068, ast_mindwm(ast, 0x1E720058) | (dlli << 16));
826 return status;
827} /* CBRDLL2 */
828
829static void get_ddr3_info(struct ast_device *ast, struct ast2300_dram_param *param)
830{
831 u32 trap, trap_AC2, trap_MRS;
832
833 ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
834
835 /* Ger trap info */
836 trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3;
837 trap_AC2 = 0x00020000 + (trap << 16);
838 trap_AC2 |= 0x00300000 + ((trap & 0x2) << 19);
839 trap_MRS = 0x00000010 + (trap << 4);
840 trap_MRS |= ((trap & 0x2) << 18);
841
842 param->reg_MADJ = 0x00034C4C;
843 param->reg_SADJ = 0x00001800;
844 param->reg_DRV = 0x000000F0;
845 param->reg_PERIOD = param->dram_freq;
846 param->rodt = 0;
847
848 switch (param->dram_freq) {
849 case 336:
850 ast_moutdwm(ast, 0x1E6E2020, 0x0190);
851 param->wodt = 0;
852 param->reg_AC1 = 0x22202725;
853 param->reg_AC2 = 0xAA007613 | trap_AC2;
854 param->reg_DQSIC = 0x000000BA;
855 param->reg_MRS = 0x04001400 | trap_MRS;
856 param->reg_EMRS = 0x00000000;
857 param->reg_IOZ = 0x00000023;
858 param->reg_DQIDLY = 0x00000074;
859 param->reg_FREQ = 0x00004DC0;
860 param->madj_max = 96;
861 param->dll2_finetune_step = 3;
862 switch (param->dram_chipid) {
863 default:
864 case AST_DRAM_512Mx16:
865 case AST_DRAM_1Gx16:
866 param->reg_AC2 = 0xAA007613 | trap_AC2;
867 break;
868 case AST_DRAM_2Gx16:
869 param->reg_AC2 = 0xAA00761C | trap_AC2;
870 break;
871 case AST_DRAM_4Gx16:
872 param->reg_AC2 = 0xAA007636 | trap_AC2;
873 break;
874 }
875 break;
876 default:
877 case 396:
878 ast_moutdwm(ast, 0x1E6E2020, 0x03F1);
879 param->wodt = 1;
880 param->reg_AC1 = 0x33302825;
881 param->reg_AC2 = 0xCC009617 | trap_AC2;
882 param->reg_DQSIC = 0x000000E2;
883 param->reg_MRS = 0x04001600 | trap_MRS;
884 param->reg_EMRS = 0x00000000;
885 param->reg_IOZ = 0x00000034;
886 param->reg_DRV = 0x000000FA;
887 param->reg_DQIDLY = 0x00000089;
888 param->reg_FREQ = 0x00005040;
889 param->madj_max = 96;
890 param->dll2_finetune_step = 4;
891
892 switch (param->dram_chipid) {
893 default:
894 case AST_DRAM_512Mx16:
895 case AST_DRAM_1Gx16:
896 param->reg_AC2 = 0xCC009617 | trap_AC2;
897 break;
898 case AST_DRAM_2Gx16:
899 param->reg_AC2 = 0xCC009622 | trap_AC2;
900 break;
901 case AST_DRAM_4Gx16:
902 param->reg_AC2 = 0xCC00963F | trap_AC2;
903 break;
904 }
905 break;
906
907 case 408:
908 ast_moutdwm(ast, 0x1E6E2020, 0x01F0);
909 param->wodt = 1;
910 param->reg_AC1 = 0x33302825;
911 param->reg_AC2 = 0xCC009617 | trap_AC2;
912 param->reg_DQSIC = 0x000000E2;
913 param->reg_MRS = 0x04001600 | trap_MRS;
914 param->reg_EMRS = 0x00000000;
915 param->reg_IOZ = 0x00000023;
916 param->reg_DRV = 0x000000FA;
917 param->reg_DQIDLY = 0x00000089;
918 param->reg_FREQ = 0x000050C0;
919 param->madj_max = 96;
920 param->dll2_finetune_step = 4;
921
922 switch (param->dram_chipid) {
923 default:
924 case AST_DRAM_512Mx16:
925 case AST_DRAM_1Gx16:
926 param->reg_AC2 = 0xCC009617 | trap_AC2;
927 break;
928 case AST_DRAM_2Gx16:
929 param->reg_AC2 = 0xCC009622 | trap_AC2;
930 break;
931 case AST_DRAM_4Gx16:
932 param->reg_AC2 = 0xCC00963F | trap_AC2;
933 break;
934 }
935
936 break;
937 case 456:
938 ast_moutdwm(ast, 0x1E6E2020, 0x0230);
939 param->wodt = 0;
940 param->reg_AC1 = 0x33302926;
941 param->reg_AC2 = 0xCD44961A;
942 param->reg_DQSIC = 0x000000FC;
943 param->reg_MRS = 0x00081830;
944 param->reg_EMRS = 0x00000000;
945 param->reg_IOZ = 0x00000045;
946 param->reg_DQIDLY = 0x00000097;
947 param->reg_FREQ = 0x000052C0;
948 param->madj_max = 88;
949 param->dll2_finetune_step = 4;
950 break;
951 case 504:
952 ast_moutdwm(ast, 0x1E6E2020, 0x0270);
953 param->wodt = 1;
954 param->reg_AC1 = 0x33302926;
955 param->reg_AC2 = 0xDE44A61D;
956 param->reg_DQSIC = 0x00000117;
957 param->reg_MRS = 0x00081A30;
958 param->reg_EMRS = 0x00000000;
959 param->reg_IOZ = 0x070000BB;
960 param->reg_DQIDLY = 0x000000A0;
961 param->reg_FREQ = 0x000054C0;
962 param->madj_max = 79;
963 param->dll2_finetune_step = 4;
964 break;
965 case 528:
966 ast_moutdwm(ast, 0x1E6E2020, 0x0290);
967 param->wodt = 1;
968 param->rodt = 1;
969 param->reg_AC1 = 0x33302926;
970 param->reg_AC2 = 0xEF44B61E;
971 param->reg_DQSIC = 0x00000125;
972 param->reg_MRS = 0x00081A30;
973 param->reg_EMRS = 0x00000040;
974 param->reg_DRV = 0x000000F5;
975 param->reg_IOZ = 0x00000023;
976 param->reg_DQIDLY = 0x00000088;
977 param->reg_FREQ = 0x000055C0;
978 param->madj_max = 76;
979 param->dll2_finetune_step = 3;
980 break;
981 case 576:
982 ast_moutdwm(ast, 0x1E6E2020, 0x0140);
983 param->reg_MADJ = 0x00136868;
984 param->reg_SADJ = 0x00004534;
985 param->wodt = 1;
986 param->rodt = 1;
987 param->reg_AC1 = 0x33302A37;
988 param->reg_AC2 = 0xEF56B61E;
989 param->reg_DQSIC = 0x0000013F;
990 param->reg_MRS = 0x00101A50;
991 param->reg_EMRS = 0x00000040;
992 param->reg_DRV = 0x000000FA;
993 param->reg_IOZ = 0x00000023;
994 param->reg_DQIDLY = 0x00000078;
995 param->reg_FREQ = 0x000057C0;
996 param->madj_max = 136;
997 param->dll2_finetune_step = 3;
998 break;
999 case 600:
1000 ast_moutdwm(ast, 0x1E6E2020, 0x02E1);
1001 param->reg_MADJ = 0x00136868;
1002 param->reg_SADJ = 0x00004534;
1003 param->wodt = 1;
1004 param->rodt = 1;
1005 param->reg_AC1 = 0x32302A37;
1006 param->reg_AC2 = 0xDF56B61F;
1007 param->reg_DQSIC = 0x0000014D;
1008 param->reg_MRS = 0x00101A50;
1009 param->reg_EMRS = 0x00000004;
1010 param->reg_DRV = 0x000000F5;
1011 param->reg_IOZ = 0x00000023;
1012 param->reg_DQIDLY = 0x00000078;
1013 param->reg_FREQ = 0x000058C0;
1014 param->madj_max = 132;
1015 param->dll2_finetune_step = 3;
1016 break;
1017 case 624:
1018 ast_moutdwm(ast, 0x1E6E2020, 0x0160);
1019 param->reg_MADJ = 0x00136868;
1020 param->reg_SADJ = 0x00004534;
1021 param->wodt = 1;
1022 param->rodt = 1;
1023 param->reg_AC1 = 0x32302A37;
1024 param->reg_AC2 = 0xEF56B621;
1025 param->reg_DQSIC = 0x0000015A;
1026 param->reg_MRS = 0x02101A50;
1027 param->reg_EMRS = 0x00000004;
1028 param->reg_DRV = 0x000000F5;
1029 param->reg_IOZ = 0x00000034;
1030 param->reg_DQIDLY = 0x00000078;
1031 param->reg_FREQ = 0x000059C0;
1032 param->madj_max = 128;
1033 param->dll2_finetune_step = 3;
1034 break;
1035 } /* switch freq */
1036
1037 switch (param->dram_chipid) {
1038 case AST_DRAM_512Mx16:
1039 param->dram_config = 0x130;
1040 break;
1041 default:
1042 case AST_DRAM_1Gx16:
1043 param->dram_config = 0x131;
1044 break;
1045 case AST_DRAM_2Gx16:
1046 param->dram_config = 0x132;
1047 break;
1048 case AST_DRAM_4Gx16:
1049 param->dram_config = 0x133;
1050 break;
1051 } /* switch size */
1052
1053 switch (param->vram_size) {
1054 default:
1055 case AST_VIDMEM_SIZE_8M:
1056 param->dram_config |= 0x00;
1057 break;
1058 case AST_VIDMEM_SIZE_16M:
1059 param->dram_config |= 0x04;
1060 break;
1061 case AST_VIDMEM_SIZE_32M:
1062 param->dram_config |= 0x08;
1063 break;
1064 case AST_VIDMEM_SIZE_64M:
1065 param->dram_config |= 0x0c;
1066 break;
1067 }
1068
1069}
1070
1071static void ddr3_init(struct ast_device *ast, struct ast2300_dram_param *param)
1072{
1073 u32 data, data2, retry = 0;
1074
1075ddr3_init_start:
1076 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1077 ast_moutdwm(ast, 0x1E6E0018, 0x00000100);
1078 ast_moutdwm(ast, 0x1E6E0024, 0x00000000);
1079 ast_moutdwm(ast, 0x1E6E0034, 0x00000000);
1080 udelay(10);
1081 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ);
1082 ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ);
1083 udelay(10);
1084 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000);
1085 udelay(10);
1086
1087 ast_moutdwm(ast, 0x1E6E0004, param->dram_config);
1088 ast_moutdwm(ast, 0x1E6E0008, 0x90040f);
1089 ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1);
1090 ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2);
1091 ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC);
1092 ast_moutdwm(ast, 0x1E6E0080, 0x00000000);
1093 ast_moutdwm(ast, 0x1E6E0084, 0x00000000);
1094 ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY);
1095 ast_moutdwm(ast, 0x1E6E0018, 0x4000A170);
1096 ast_moutdwm(ast, 0x1E6E0018, 0x00002370);
1097 ast_moutdwm(ast, 0x1E6E0038, 0x00000000);
1098 ast_moutdwm(ast, 0x1E6E0040, 0xFF444444);
1099 ast_moutdwm(ast, 0x1E6E0044, 0x22222222);
1100 ast_moutdwm(ast, 0x1E6E0048, 0x22222222);
1101 ast_moutdwm(ast, 0x1E6E004C, 0x00000002);
1102 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1103 ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1104 ast_moutdwm(ast, 0x1E6E0054, 0);
1105 ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV);
1106 ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ);
1107 ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1108 ast_moutdwm(ast, 0x1E6E0074, 0x00000000);
1109 ast_moutdwm(ast, 0x1E6E0078, 0x00000000);
1110 ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1111 /* Wait MCLK2X lock to MCLK */
1112 do {
1113 data = ast_mindwm(ast, 0x1E6E001C);
1114 } while (!(data & 0x08000000));
1115 data = ast_mindwm(ast, 0x1E6E001C);
1116 data = (data >> 8) & 0xff;
1117 while ((data & 0x08) || ((data & 0x7) < 2) || (data < 4)) {
1118 data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4;
1119 if ((data2 & 0xff) > param->madj_max) {
1120 break;
1121 }
1122 ast_moutdwm(ast, 0x1E6E0064, data2);
1123 if (data2 & 0x00100000) {
1124 data2 = ((data2 & 0xff) >> 3) + 3;
1125 } else {
1126 data2 = ((data2 & 0xff) >> 2) + 5;
1127 }
1128 data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff;
1129 data2 += data & 0xff;
1130 data = data | (data2 << 8);
1131 ast_moutdwm(ast, 0x1E6E0068, data);
1132 udelay(10);
1133 ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000);
1134 udelay(10);
1135 data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff;
1136 ast_moutdwm(ast, 0x1E6E0018, data);
1137 data = data | 0x200;
1138 ast_moutdwm(ast, 0x1E6E0018, data);
1139 do {
1140 data = ast_mindwm(ast, 0x1E6E001C);
1141 } while (!(data & 0x08000000));
1142
1143 data = ast_mindwm(ast, 0x1E6E001C);
1144 data = (data >> 8) & 0xff;
1145 }
1146 ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0068) & 0xffff);
1147 data = ast_mindwm(ast, 0x1E6E0018) | 0xC00;
1148 ast_moutdwm(ast, 0x1E6E0018, data);
1149
1150 ast_moutdwm(ast, 0x1E6E0034, 0x00000001);
1151 ast_moutdwm(ast, 0x1E6E000C, 0x00000040);
1152 udelay(50);
1153 /* Mode Register Setting */
1154 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100);
1155 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1156 ast_moutdwm(ast, 0x1E6E0028, 0x00000005);
1157 ast_moutdwm(ast, 0x1E6E0028, 0x00000007);
1158 ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1159 ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1160 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS);
1161 ast_moutdwm(ast, 0x1E6E000C, 0x00005C08);
1162 ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1163
1164 ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
1165 data = 0;
1166 if (param->wodt) {
1167 data = 0x300;
1168 }
1169 if (param->rodt) {
1170 data = data | 0x3000 | ((param->reg_AC2 & 0x60000) >> 3);
1171 }
1172 ast_moutdwm(ast, 0x1E6E0034, data | 0x3);
1173
1174 /* Calibrate the DQSI delay */
1175 if ((cbr_dll2(ast, param) == false) && (retry++ < 10))
1176 goto ddr3_init_start;
1177
1178 ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ);
1179 /* ECC Memory Initialization */
1180#ifdef ECC
1181 ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1182 ast_moutdwm(ast, 0x1E6E0070, 0x221);
1183 do {
1184 data = ast_mindwm(ast, 0x1E6E0070);
1185 } while (!(data & 0x00001000));
1186 ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1187 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1188 ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1189#endif
1190
1191
1192}
1193
1194static void get_ddr2_info(struct ast_device *ast, struct ast2300_dram_param *param)
1195{
1196 u32 trap, trap_AC2, trap_MRS;
1197
1198 ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
1199
1200 /* Ger trap info */
1201 trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3;
1202 trap_AC2 = (trap << 20) | (trap << 16);
1203 trap_AC2 += 0x00110000;
1204 trap_MRS = 0x00000040 | (trap << 4);
1205
1206
1207 param->reg_MADJ = 0x00034C4C;
1208 param->reg_SADJ = 0x00001800;
1209 param->reg_DRV = 0x000000F0;
1210 param->reg_PERIOD = param->dram_freq;
1211 param->rodt = 0;
1212
1213 switch (param->dram_freq) {
1214 case 264:
1215 ast_moutdwm(ast, 0x1E6E2020, 0x0130);
1216 param->wodt = 0;
1217 param->reg_AC1 = 0x11101513;
1218 param->reg_AC2 = 0x78117011;
1219 param->reg_DQSIC = 0x00000092;
1220 param->reg_MRS = 0x00000842;
1221 param->reg_EMRS = 0x00000000;
1222 param->reg_DRV = 0x000000F0;
1223 param->reg_IOZ = 0x00000034;
1224 param->reg_DQIDLY = 0x0000005A;
1225 param->reg_FREQ = 0x00004AC0;
1226 param->madj_max = 138;
1227 param->dll2_finetune_step = 3;
1228 break;
1229 case 336:
1230 ast_moutdwm(ast, 0x1E6E2020, 0x0190);
1231 param->wodt = 1;
1232 param->reg_AC1 = 0x22202613;
1233 param->reg_AC2 = 0xAA009016 | trap_AC2;
1234 param->reg_DQSIC = 0x000000BA;
1235 param->reg_MRS = 0x00000A02 | trap_MRS;
1236 param->reg_EMRS = 0x00000040;
1237 param->reg_DRV = 0x000000FA;
1238 param->reg_IOZ = 0x00000034;
1239 param->reg_DQIDLY = 0x00000074;
1240 param->reg_FREQ = 0x00004DC0;
1241 param->madj_max = 96;
1242 param->dll2_finetune_step = 3;
1243 switch (param->dram_chipid) {
1244 default:
1245 case AST_DRAM_512Mx16:
1246 param->reg_AC2 = 0xAA009012 | trap_AC2;
1247 break;
1248 case AST_DRAM_1Gx16:
1249 param->reg_AC2 = 0xAA009016 | trap_AC2;
1250 break;
1251 case AST_DRAM_2Gx16:
1252 param->reg_AC2 = 0xAA009023 | trap_AC2;
1253 break;
1254 case AST_DRAM_4Gx16:
1255 param->reg_AC2 = 0xAA00903B | trap_AC2;
1256 break;
1257 }
1258 break;
1259 default:
1260 case 396:
1261 ast_moutdwm(ast, 0x1E6E2020, 0x03F1);
1262 param->wodt = 1;
1263 param->rodt = 0;
1264 param->reg_AC1 = 0x33302714;
1265 param->reg_AC2 = 0xCC00B01B | trap_AC2;
1266 param->reg_DQSIC = 0x000000E2;
1267 param->reg_MRS = 0x00000C02 | trap_MRS;
1268 param->reg_EMRS = 0x00000040;
1269 param->reg_DRV = 0x000000FA;
1270 param->reg_IOZ = 0x00000034;
1271 param->reg_DQIDLY = 0x00000089;
1272 param->reg_FREQ = 0x00005040;
1273 param->madj_max = 96;
1274 param->dll2_finetune_step = 4;
1275
1276 switch (param->dram_chipid) {
1277 case AST_DRAM_512Mx16:
1278 param->reg_AC2 = 0xCC00B016 | trap_AC2;
1279 break;
1280 default:
1281 case AST_DRAM_1Gx16:
1282 param->reg_AC2 = 0xCC00B01B | trap_AC2;
1283 break;
1284 case AST_DRAM_2Gx16:
1285 param->reg_AC2 = 0xCC00B02B | trap_AC2;
1286 break;
1287 case AST_DRAM_4Gx16:
1288 param->reg_AC2 = 0xCC00B03F | trap_AC2;
1289 break;
1290 }
1291
1292 break;
1293
1294 case 408:
1295 ast_moutdwm(ast, 0x1E6E2020, 0x01F0);
1296 param->wodt = 1;
1297 param->rodt = 0;
1298 param->reg_AC1 = 0x33302714;
1299 param->reg_AC2 = 0xCC00B01B | trap_AC2;
1300 param->reg_DQSIC = 0x000000E2;
1301 param->reg_MRS = 0x00000C02 | trap_MRS;
1302 param->reg_EMRS = 0x00000040;
1303 param->reg_DRV = 0x000000FA;
1304 param->reg_IOZ = 0x00000034;
1305 param->reg_DQIDLY = 0x00000089;
1306 param->reg_FREQ = 0x000050C0;
1307 param->madj_max = 96;
1308 param->dll2_finetune_step = 4;
1309
1310 switch (param->dram_chipid) {
1311 case AST_DRAM_512Mx16:
1312 param->reg_AC2 = 0xCC00B016 | trap_AC2;
1313 break;
1314 default:
1315 case AST_DRAM_1Gx16:
1316 param->reg_AC2 = 0xCC00B01B | trap_AC2;
1317 break;
1318 case AST_DRAM_2Gx16:
1319 param->reg_AC2 = 0xCC00B02B | trap_AC2;
1320 break;
1321 case AST_DRAM_4Gx16:
1322 param->reg_AC2 = 0xCC00B03F | trap_AC2;
1323 break;
1324 }
1325
1326 break;
1327 case 456:
1328 ast_moutdwm(ast, 0x1E6E2020, 0x0230);
1329 param->wodt = 0;
1330 param->reg_AC1 = 0x33302815;
1331 param->reg_AC2 = 0xCD44B01E;
1332 param->reg_DQSIC = 0x000000FC;
1333 param->reg_MRS = 0x00000E72;
1334 param->reg_EMRS = 0x00000000;
1335 param->reg_DRV = 0x00000000;
1336 param->reg_IOZ = 0x00000034;
1337 param->reg_DQIDLY = 0x00000097;
1338 param->reg_FREQ = 0x000052C0;
1339 param->madj_max = 88;
1340 param->dll2_finetune_step = 3;
1341 break;
1342 case 504:
1343 ast_moutdwm(ast, 0x1E6E2020, 0x0261);
1344 param->wodt = 1;
1345 param->rodt = 1;
1346 param->reg_AC1 = 0x33302815;
1347 param->reg_AC2 = 0xDE44C022;
1348 param->reg_DQSIC = 0x00000117;
1349 param->reg_MRS = 0x00000E72;
1350 param->reg_EMRS = 0x00000040;
1351 param->reg_DRV = 0x0000000A;
1352 param->reg_IOZ = 0x00000045;
1353 param->reg_DQIDLY = 0x000000A0;
1354 param->reg_FREQ = 0x000054C0;
1355 param->madj_max = 79;
1356 param->dll2_finetune_step = 3;
1357 break;
1358 case 528:
1359 ast_moutdwm(ast, 0x1E6E2020, 0x0120);
1360 param->wodt = 1;
1361 param->rodt = 1;
1362 param->reg_AC1 = 0x33302815;
1363 param->reg_AC2 = 0xEF44D024;
1364 param->reg_DQSIC = 0x00000125;
1365 param->reg_MRS = 0x00000E72;
1366 param->reg_EMRS = 0x00000004;
1367 param->reg_DRV = 0x000000F9;
1368 param->reg_IOZ = 0x00000045;
1369 param->reg_DQIDLY = 0x000000A7;
1370 param->reg_FREQ = 0x000055C0;
1371 param->madj_max = 76;
1372 param->dll2_finetune_step = 3;
1373 break;
1374 case 552:
1375 ast_moutdwm(ast, 0x1E6E2020, 0x02A1);
1376 param->wodt = 1;
1377 param->rodt = 1;
1378 param->reg_AC1 = 0x43402915;
1379 param->reg_AC2 = 0xFF44E025;
1380 param->reg_DQSIC = 0x00000132;
1381 param->reg_MRS = 0x00000E72;
1382 param->reg_EMRS = 0x00000040;
1383 param->reg_DRV = 0x0000000A;
1384 param->reg_IOZ = 0x00000045;
1385 param->reg_DQIDLY = 0x000000AD;
1386 param->reg_FREQ = 0x000056C0;
1387 param->madj_max = 76;
1388 param->dll2_finetune_step = 3;
1389 break;
1390 case 576:
1391 ast_moutdwm(ast, 0x1E6E2020, 0x0140);
1392 param->wodt = 1;
1393 param->rodt = 1;
1394 param->reg_AC1 = 0x43402915;
1395 param->reg_AC2 = 0xFF44E027;
1396 param->reg_DQSIC = 0x0000013F;
1397 param->reg_MRS = 0x00000E72;
1398 param->reg_EMRS = 0x00000004;
1399 param->reg_DRV = 0x000000F5;
1400 param->reg_IOZ = 0x00000045;
1401 param->reg_DQIDLY = 0x000000B3;
1402 param->reg_FREQ = 0x000057C0;
1403 param->madj_max = 76;
1404 param->dll2_finetune_step = 3;
1405 break;
1406 }
1407
1408 switch (param->dram_chipid) {
1409 case AST_DRAM_512Mx16:
1410 param->dram_config = 0x100;
1411 break;
1412 default:
1413 case AST_DRAM_1Gx16:
1414 param->dram_config = 0x121;
1415 break;
1416 case AST_DRAM_2Gx16:
1417 param->dram_config = 0x122;
1418 break;
1419 case AST_DRAM_4Gx16:
1420 param->dram_config = 0x123;
1421 break;
1422 } /* switch size */
1423
1424 switch (param->vram_size) {
1425 default:
1426 case AST_VIDMEM_SIZE_8M:
1427 param->dram_config |= 0x00;
1428 break;
1429 case AST_VIDMEM_SIZE_16M:
1430 param->dram_config |= 0x04;
1431 break;
1432 case AST_VIDMEM_SIZE_32M:
1433 param->dram_config |= 0x08;
1434 break;
1435 case AST_VIDMEM_SIZE_64M:
1436 param->dram_config |= 0x0c;
1437 break;
1438 }
1439}
1440
1441static void ddr2_init(struct ast_device *ast, struct ast2300_dram_param *param)
1442{
1443 u32 data, data2, retry = 0;
1444
1445ddr2_init_start:
1446 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1447 ast_moutdwm(ast, 0x1E6E0018, 0x00000100);
1448 ast_moutdwm(ast, 0x1E6E0024, 0x00000000);
1449 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ);
1450 ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ);
1451 udelay(10);
1452 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000);
1453 udelay(10);
1454
1455 ast_moutdwm(ast, 0x1E6E0004, param->dram_config);
1456 ast_moutdwm(ast, 0x1E6E0008, 0x90040f);
1457 ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1);
1458 ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2);
1459 ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC);
1460 ast_moutdwm(ast, 0x1E6E0080, 0x00000000);
1461 ast_moutdwm(ast, 0x1E6E0084, 0x00000000);
1462 ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY);
1463 ast_moutdwm(ast, 0x1E6E0018, 0x4000A130);
1464 ast_moutdwm(ast, 0x1E6E0018, 0x00002330);
1465 ast_moutdwm(ast, 0x1E6E0038, 0x00000000);
1466 ast_moutdwm(ast, 0x1E6E0040, 0xFF808000);
1467 ast_moutdwm(ast, 0x1E6E0044, 0x88848466);
1468 ast_moutdwm(ast, 0x1E6E0048, 0x44440008);
1469 ast_moutdwm(ast, 0x1E6E004C, 0x00000000);
1470 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1471 ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1472 ast_moutdwm(ast, 0x1E6E0054, 0);
1473 ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV);
1474 ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ);
1475 ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1476 ast_moutdwm(ast, 0x1E6E0074, 0x00000000);
1477 ast_moutdwm(ast, 0x1E6E0078, 0x00000000);
1478 ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1479
1480 /* Wait MCLK2X lock to MCLK */
1481 do {
1482 data = ast_mindwm(ast, 0x1E6E001C);
1483 } while (!(data & 0x08000000));
1484 data = ast_mindwm(ast, 0x1E6E001C);
1485 data = (data >> 8) & 0xff;
1486 while ((data & 0x08) || ((data & 0x7) < 2) || (data < 4)) {
1487 data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4;
1488 if ((data2 & 0xff) > param->madj_max) {
1489 break;
1490 }
1491 ast_moutdwm(ast, 0x1E6E0064, data2);
1492 if (data2 & 0x00100000) {
1493 data2 = ((data2 & 0xff) >> 3) + 3;
1494 } else {
1495 data2 = ((data2 & 0xff) >> 2) + 5;
1496 }
1497 data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff;
1498 data2 += data & 0xff;
1499 data = data | (data2 << 8);
1500 ast_moutdwm(ast, 0x1E6E0068, data);
1501 udelay(10);
1502 ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000);
1503 udelay(10);
1504 data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff;
1505 ast_moutdwm(ast, 0x1E6E0018, data);
1506 data = data | 0x200;
1507 ast_moutdwm(ast, 0x1E6E0018, data);
1508 do {
1509 data = ast_mindwm(ast, 0x1E6E001C);
1510 } while (!(data & 0x08000000));
1511
1512 data = ast_mindwm(ast, 0x1E6E001C);
1513 data = (data >> 8) & 0xff;
1514 }
1515 ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0008) & 0xffff);
1516 data = ast_mindwm(ast, 0x1E6E0018) | 0xC00;
1517 ast_moutdwm(ast, 0x1E6E0018, data);
1518
1519 ast_moutdwm(ast, 0x1E6E0034, 0x00000001);
1520 ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1521 udelay(50);
1522 /* Mode Register Setting */
1523 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100);
1524 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1525 ast_moutdwm(ast, 0x1E6E0028, 0x00000005);
1526 ast_moutdwm(ast, 0x1E6E0028, 0x00000007);
1527 ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1528 ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1529
1530 ast_moutdwm(ast, 0x1E6E000C, 0x00005C08);
1531 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS);
1532 ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1533 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS | 0x380);
1534 ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1535 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1536 ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1537
1538 ast_moutdwm(ast, 0x1E6E000C, 0x7FFF5C01);
1539 data = 0;
1540 if (param->wodt) {
1541 data = 0x500;
1542 }
1543 if (param->rodt) {
1544 data = data | 0x3000 | ((param->reg_AC2 & 0x60000) >> 3);
1545 }
1546 ast_moutdwm(ast, 0x1E6E0034, data | 0x3);
1547 ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ);
1548
1549 /* Calibrate the DQSI delay */
1550 if ((cbr_dll2(ast, param) == false) && (retry++ < 10))
1551 goto ddr2_init_start;
1552
1553 /* ECC Memory Initialization */
1554#ifdef ECC
1555 ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1556 ast_moutdwm(ast, 0x1E6E0070, 0x221);
1557 do {
1558 data = ast_mindwm(ast, 0x1E6E0070);
1559 } while (!(data & 0x00001000));
1560 ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1561 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1562 ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1563#endif
1564
1565}
1566
1567static void ast_post_chip_2300(struct ast_device *ast)
1568{
1569 struct ast2300_dram_param param;
1570 u32 temp;
1571 u8 reg;
1572
1573 reg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
1574 if ((reg & 0x80) == 0) {/* vga only */
1575 ast_write32(ast, 0xf004, 0x1e6e0000);
1576 ast_write32(ast, 0xf000, 0x1);
1577 ast_write32(ast, 0x12000, 0x1688a8a8);
1578 do {
1579 ;
1580 } while (ast_read32(ast, 0x12000) != 0x1);
1581
1582 ast_write32(ast, 0x10000, 0xfc600309);
1583 do {
1584 ;
1585 } while (ast_read32(ast, 0x10000) != 0x1);
1586
1587 /* Slow down CPU/AHB CLK in VGA only mode */
1588 temp = ast_read32(ast, 0x12008);
1589 temp |= 0x73;
1590 ast_write32(ast, 0x12008, temp);
1591
1592 param.dram_freq = 396;
1593 param.dram_type = AST_DDR3;
1594 temp = ast_mindwm(ast, 0x1e6e2070);
1595 if (temp & 0x01000000)
1596 param.dram_type = AST_DDR2;
1597 switch (temp & 0x18000000) {
1598 case 0:
1599 param.dram_chipid = AST_DRAM_512Mx16;
1600 break;
1601 default:
1602 case 0x08000000:
1603 param.dram_chipid = AST_DRAM_1Gx16;
1604 break;
1605 case 0x10000000:
1606 param.dram_chipid = AST_DRAM_2Gx16;
1607 break;
1608 case 0x18000000:
1609 param.dram_chipid = AST_DRAM_4Gx16;
1610 break;
1611 }
1612 switch (temp & 0x0c) {
1613 default:
1614 case 0x00:
1615 param.vram_size = AST_VIDMEM_SIZE_8M;
1616 break;
1617
1618 case 0x04:
1619 param.vram_size = AST_VIDMEM_SIZE_16M;
1620 break;
1621
1622 case 0x08:
1623 param.vram_size = AST_VIDMEM_SIZE_32M;
1624 break;
1625
1626 case 0x0c:
1627 param.vram_size = AST_VIDMEM_SIZE_64M;
1628 break;
1629 }
1630
1631 if (param.dram_type == AST_DDR3) {
1632 get_ddr3_info(ast, ¶m);
1633 ddr3_init(ast, ¶m);
1634 } else {
1635 get_ddr2_info(ast, ¶m);
1636 ddr2_init(ast, ¶m);
1637 }
1638
1639 temp = ast_mindwm(ast, 0x1e6e2040);
1640 ast_moutdwm(ast, 0x1e6e2040, temp | 0x40);
1641 }
1642
1643 /* wait ready */
1644 do {
1645 reg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
1646 } while ((reg & 0x40) == 0);
1647}
1648
1649static bool cbr_test_2500(struct ast_device *ast)
1650{
1651 ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF);
1652 ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00);
1653 if (!mmc_test_burst(ast, 0))
1654 return false;
1655 if (!mmc_test_single_2500(ast, 0))
1656 return false;
1657 return true;
1658}
1659
1660static bool ddr_test_2500(struct ast_device *ast)
1661{
1662 ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF);
1663 ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00);
1664 if (!mmc_test_burst(ast, 0))
1665 return false;
1666 if (!mmc_test_burst(ast, 1))
1667 return false;
1668 if (!mmc_test_burst(ast, 2))
1669 return false;
1670 if (!mmc_test_burst(ast, 3))
1671 return false;
1672 if (!mmc_test_single_2500(ast, 0))
1673 return false;
1674 return true;
1675}
1676
1677static void ddr_init_common_2500(struct ast_device *ast)
1678{
1679 ast_moutdwm(ast, 0x1E6E0034, 0x00020080);
1680 ast_moutdwm(ast, 0x1E6E0008, 0x2003000F);
1681 ast_moutdwm(ast, 0x1E6E0038, 0x00000FFF);
1682 ast_moutdwm(ast, 0x1E6E0040, 0x88448844);
1683 ast_moutdwm(ast, 0x1E6E0044, 0x24422288);
1684 ast_moutdwm(ast, 0x1E6E0048, 0x22222222);
1685 ast_moutdwm(ast, 0x1E6E004C, 0x22222222);
1686 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1687 ast_moutdwm(ast, 0x1E6E0208, 0x00000000);
1688 ast_moutdwm(ast, 0x1E6E0218, 0x00000000);
1689 ast_moutdwm(ast, 0x1E6E0220, 0x00000000);
1690 ast_moutdwm(ast, 0x1E6E0228, 0x00000000);
1691 ast_moutdwm(ast, 0x1E6E0230, 0x00000000);
1692 ast_moutdwm(ast, 0x1E6E02A8, 0x00000000);
1693 ast_moutdwm(ast, 0x1E6E02B0, 0x00000000);
1694 ast_moutdwm(ast, 0x1E6E0240, 0x86000000);
1695 ast_moutdwm(ast, 0x1E6E0244, 0x00008600);
1696 ast_moutdwm(ast, 0x1E6E0248, 0x80000000);
1697 ast_moutdwm(ast, 0x1E6E024C, 0x80808080);
1698}
1699
1700static void ddr_phy_init_2500(struct ast_device *ast)
1701{
1702 u32 data, pass, timecnt;
1703
1704 pass = 0;
1705 ast_moutdwm(ast, 0x1E6E0060, 0x00000005);
1706 while (!pass) {
1707 for (timecnt = 0; timecnt < TIMEOUT; timecnt++) {
1708 data = ast_mindwm(ast, 0x1E6E0060) & 0x1;
1709 if (!data)
1710 break;
1711 }
1712 if (timecnt != TIMEOUT) {
1713 data = ast_mindwm(ast, 0x1E6E0300) & 0x000A0000;
1714 if (!data)
1715 pass = 1;
1716 }
1717 if (!pass) {
1718 ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
1719 udelay(10); /* delay 10 us */
1720 ast_moutdwm(ast, 0x1E6E0060, 0x00000005);
1721 }
1722 }
1723
1724 ast_moutdwm(ast, 0x1E6E0060, 0x00000006);
1725}
1726
1727/*
1728 * Check DRAM Size
1729 * 1Gb : 0x80000000 ~ 0x87FFFFFF
1730 * 2Gb : 0x80000000 ~ 0x8FFFFFFF
1731 * 4Gb : 0x80000000 ~ 0x9FFFFFFF
1732 * 8Gb : 0x80000000 ~ 0xBFFFFFFF
1733 */
1734static void check_dram_size_2500(struct ast_device *ast, u32 tRFC)
1735{
1736 u32 reg_04, reg_14;
1737
1738 reg_04 = ast_mindwm(ast, 0x1E6E0004) & 0xfffffffc;
1739 reg_14 = ast_mindwm(ast, 0x1E6E0014) & 0xffffff00;
1740
1741 ast_moutdwm(ast, 0xA0100000, 0x41424344);
1742 ast_moutdwm(ast, 0x90100000, 0x35363738);
1743 ast_moutdwm(ast, 0x88100000, 0x292A2B2C);
1744 ast_moutdwm(ast, 0x80100000, 0x1D1E1F10);
1745
1746 /* Check 8Gbit */
1747 if (ast_mindwm(ast, 0xA0100000) == 0x41424344) {
1748 reg_04 |= 0x03;
1749 reg_14 |= (tRFC >> 24) & 0xFF;
1750 /* Check 4Gbit */
1751 } else if (ast_mindwm(ast, 0x90100000) == 0x35363738) {
1752 reg_04 |= 0x02;
1753 reg_14 |= (tRFC >> 16) & 0xFF;
1754 /* Check 2Gbit */
1755 } else if (ast_mindwm(ast, 0x88100000) == 0x292A2B2C) {
1756 reg_04 |= 0x01;
1757 reg_14 |= (tRFC >> 8) & 0xFF;
1758 } else {
1759 reg_14 |= tRFC & 0xFF;
1760 }
1761 ast_moutdwm(ast, 0x1E6E0004, reg_04);
1762 ast_moutdwm(ast, 0x1E6E0014, reg_14);
1763}
1764
1765static void enable_cache_2500(struct ast_device *ast)
1766{
1767 u32 reg_04, data;
1768
1769 reg_04 = ast_mindwm(ast, 0x1E6E0004);
1770 ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x1000);
1771
1772 do
1773 data = ast_mindwm(ast, 0x1E6E0004);
1774 while (!(data & 0x80000));
1775 ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x400);
1776}
1777
1778static void set_mpll_2500(struct ast_device *ast)
1779{
1780 u32 addr, data, param;
1781
1782 /* Reset MMC */
1783 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1784 ast_moutdwm(ast, 0x1E6E0034, 0x00020080);
1785 for (addr = 0x1e6e0004; addr < 0x1e6e0090;) {
1786 ast_moutdwm(ast, addr, 0x0);
1787 addr += 4;
1788 }
1789 ast_moutdwm(ast, 0x1E6E0034, 0x00020000);
1790
1791 ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
1792 data = ast_mindwm(ast, 0x1E6E2070) & 0x00800000;
1793 if (data) {
1794 /* CLKIN = 25MHz */
1795 param = 0x930023E0;
1796 ast_moutdwm(ast, 0x1E6E2160, 0x00011320);
1797 } else {
1798 /* CLKIN = 24MHz */
1799 param = 0x93002400;
1800 }
1801 ast_moutdwm(ast, 0x1E6E2020, param);
1802 udelay(100);
1803}
1804
1805static void reset_mmc_2500(struct ast_device *ast)
1806{
1807 ast_moutdwm(ast, 0x1E78505C, 0x00000004);
1808 ast_moutdwm(ast, 0x1E785044, 0x00000001);
1809 ast_moutdwm(ast, 0x1E785048, 0x00004755);
1810 ast_moutdwm(ast, 0x1E78504C, 0x00000013);
1811 mdelay(100);
1812 ast_moutdwm(ast, 0x1E785054, 0x00000077);
1813 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1814}
1815
1816static void ddr3_init_2500(struct ast_device *ast, const u32 *ddr_table)
1817{
1818
1819 ast_moutdwm(ast, 0x1E6E0004, 0x00000303);
1820 ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]);
1821 ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]);
1822 ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]);
1823 ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]); /* MODEREG4/6 */
1824 ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]); /* MODEREG5 */
1825 ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */
1826 ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]); /* MODEREG1/3 */
1827
1828 /* DDR PHY Setting */
1829 ast_moutdwm(ast, 0x1E6E0200, 0x02492AAE);
1830 ast_moutdwm(ast, 0x1E6E0204, 0x00001001);
1831 ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B);
1832 ast_moutdwm(ast, 0x1E6E0210, 0x20000000);
1833 ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]);
1834 ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]);
1835 ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]);
1836 ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]);
1837 ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]);
1838 ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]);
1839 ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]);
1840 ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]);
1841 ast_moutdwm(ast, 0x1E6E0290, 0x00100008);
1842 ast_moutdwm(ast, 0x1E6E02C0, 0x00000006);
1843
1844 /* Controller Setting */
1845 ast_moutdwm(ast, 0x1E6E0034, 0x00020091);
1846
1847 /* Wait DDR PHY init done */
1848 ddr_phy_init_2500(ast);
1849
1850 ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]);
1851 ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81);
1852 ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93);
1853
1854 check_dram_size_2500(ast, ddr_table[REGIDX_RFC]);
1855 enable_cache_2500(ast);
1856 ast_moutdwm(ast, 0x1E6E001C, 0x00000008);
1857 ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00);
1858}
1859
1860static void ddr4_init_2500(struct ast_device *ast, const u32 *ddr_table)
1861{
1862 u32 data, data2, pass, retrycnt;
1863 u32 ddr_vref, phy_vref;
1864 u32 min_ddr_vref = 0, min_phy_vref = 0;
1865 u32 max_ddr_vref = 0, max_phy_vref = 0;
1866
1867 ast_moutdwm(ast, 0x1E6E0004, 0x00000313);
1868 ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]);
1869 ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]);
1870 ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]);
1871 ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]); /* MODEREG4/6 */
1872 ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]); /* MODEREG5 */
1873 ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */
1874 ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]); /* MODEREG1/3 */
1875
1876 /* DDR PHY Setting */
1877 ast_moutdwm(ast, 0x1E6E0200, 0x42492AAE);
1878 ast_moutdwm(ast, 0x1E6E0204, 0x09002000);
1879 ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B);
1880 ast_moutdwm(ast, 0x1E6E0210, 0x20000000);
1881 ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]);
1882 ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]);
1883 ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]);
1884 ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]);
1885 ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]);
1886 ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]);
1887 ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]);
1888 ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]);
1889 ast_moutdwm(ast, 0x1E6E0290, 0x00100008);
1890 ast_moutdwm(ast, 0x1E6E02C4, 0x3C183C3C);
1891 ast_moutdwm(ast, 0x1E6E02C8, 0x00631E0E);
1892
1893 /* Controller Setting */
1894 ast_moutdwm(ast, 0x1E6E0034, 0x0001A991);
1895
1896 /* Train PHY Vref first */
1897 pass = 0;
1898
1899 for (retrycnt = 0; retrycnt < 4 && pass == 0; retrycnt++) {
1900 max_phy_vref = 0x0;
1901 pass = 0;
1902 ast_moutdwm(ast, 0x1E6E02C0, 0x00001C06);
1903 for (phy_vref = 0x40; phy_vref < 0x80; phy_vref++) {
1904 ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1905 ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
1906 ast_moutdwm(ast, 0x1E6E02CC, phy_vref | (phy_vref << 8));
1907 /* Fire DFI Init */
1908 ddr_phy_init_2500(ast);
1909 ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
1910 if (cbr_test_2500(ast)) {
1911 pass++;
1912 data = ast_mindwm(ast, 0x1E6E03D0);
1913 data2 = data >> 8;
1914 data = data & 0xff;
1915 if (data > data2)
1916 data = data2;
1917 if (max_phy_vref < data) {
1918 max_phy_vref = data;
1919 min_phy_vref = phy_vref;
1920 }
1921 } else if (pass > 0)
1922 break;
1923 }
1924 }
1925 ast_moutdwm(ast, 0x1E6E02CC, min_phy_vref | (min_phy_vref << 8));
1926
1927 /* Train DDR Vref next */
1928 pass = 0;
1929
1930 for (retrycnt = 0; retrycnt < 4 && pass == 0; retrycnt++) {
1931 min_ddr_vref = 0xFF;
1932 max_ddr_vref = 0x0;
1933 pass = 0;
1934 for (ddr_vref = 0x00; ddr_vref < 0x40; ddr_vref++) {
1935 ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1936 ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
1937 ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8));
1938 /* Fire DFI Init */
1939 ddr_phy_init_2500(ast);
1940 ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
1941 if (cbr_test_2500(ast)) {
1942 pass++;
1943 if (min_ddr_vref > ddr_vref)
1944 min_ddr_vref = ddr_vref;
1945 if (max_ddr_vref < ddr_vref)
1946 max_ddr_vref = ddr_vref;
1947 } else if (pass != 0)
1948 break;
1949 }
1950 }
1951
1952 ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1953 ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
1954 ddr_vref = (min_ddr_vref + max_ddr_vref + 1) >> 1;
1955 ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8));
1956
1957 /* Wait DDR PHY init done */
1958 ddr_phy_init_2500(ast);
1959
1960 ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]);
1961 ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81);
1962 ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93);
1963
1964 check_dram_size_2500(ast, ddr_table[REGIDX_RFC]);
1965 enable_cache_2500(ast);
1966 ast_moutdwm(ast, 0x1E6E001C, 0x00000008);
1967 ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00);
1968}
1969
1970static bool ast_dram_init_2500(struct ast_device *ast)
1971{
1972 u32 data;
1973 u32 max_tries = 5;
1974
1975 do {
1976 if (max_tries-- == 0)
1977 return false;
1978 set_mpll_2500(ast);
1979 reset_mmc_2500(ast);
1980 ddr_init_common_2500(ast);
1981
1982 data = ast_mindwm(ast, 0x1E6E2070);
1983 if (data & 0x01000000)
1984 ddr4_init_2500(ast, ast2500_ddr4_1600_timing_table);
1985 else
1986 ddr3_init_2500(ast, ast2500_ddr3_1600_timing_table);
1987 } while (!ddr_test_2500(ast));
1988
1989 ast_moutdwm(ast, 0x1E6E2040, ast_mindwm(ast, 0x1E6E2040) | 0x41);
1990
1991 /* Patch code */
1992 data = ast_mindwm(ast, 0x1E6E200C) & 0xF9FFFFFF;
1993 ast_moutdwm(ast, 0x1E6E200C, data | 0x10000000);
1994
1995 return true;
1996}
1997
1998void ast_patch_ahb_2500(void __iomem *regs)
1999{
2000 u32 data;
2001
2002 /* Clear bus lock condition */
2003 __ast_moutdwm(regs, 0x1e600000, 0xAEED1A03);
2004 __ast_moutdwm(regs, 0x1e600084, 0x00010000);
2005 __ast_moutdwm(regs, 0x1e600088, 0x00000000);
2006 __ast_moutdwm(regs, 0x1e6e2000, 0x1688A8A8);
2007
2008 data = __ast_mindwm(regs, 0x1e6e2070);
2009 if (data & 0x08000000) { /* check fast reset */
2010 /*
2011 * If "Fast restet" is enabled for ARM-ICE debugger,
2012 * then WDT needs to enable, that
2013 * WDT04 is WDT#1 Reload reg.
2014 * WDT08 is WDT#1 counter restart reg to avoid system deadlock
2015 * WDT0C is WDT#1 control reg
2016 * [6:5]:= 01:Full chip
2017 * [4]:= 1:1MHz clock source
2018 * [1]:= 1:WDT will be cleeared and disabled after timeout occurs
2019 * [0]:= 1:WDT enable
2020 */
2021 __ast_moutdwm(regs, 0x1E785004, 0x00000010);
2022 __ast_moutdwm(regs, 0x1E785008, 0x00004755);
2023 __ast_moutdwm(regs, 0x1E78500c, 0x00000033);
2024 udelay(1000);
2025 }
2026
2027 do {
2028 __ast_moutdwm(regs, 0x1e6e2000, 0x1688A8A8);
2029 data = __ast_mindwm(regs, 0x1e6e2000);
2030 } while (data != 1);
2031
2032 __ast_moutdwm(regs, 0x1e6e207c, 0x08000000); /* clear fast reset */
2033}
2034
2035void ast_post_chip_2500(struct ast_device *ast)
2036{
2037 struct drm_device *dev = &ast->base;
2038 u32 temp;
2039 u8 reg;
2040
2041 reg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
2042 if ((reg & AST_VRAM_INIT_STATUS_MASK) == 0) {/* vga only */
2043 /* Clear bus lock condition */
2044 ast_patch_ahb_2500(ast->regs);
2045
2046 /* Disable watchdog */
2047 ast_moutdwm(ast, 0x1E78502C, 0x00000000);
2048 ast_moutdwm(ast, 0x1E78504C, 0x00000000);
2049
2050 /*
2051 * Reset USB port to patch USB unknown device issue
2052 * SCU90 is Multi-function Pin Control #5
2053 * [29]:= 1:Enable USB2.0 Host port#1 (that the mutually shared USB2.0 Hub
2054 * port).
2055 * SCU94 is Multi-function Pin Control #6
2056 * [14:13]:= 1x:USB2.0 Host2 controller
2057 * SCU70 is Hardware Strap reg
2058 * [23]:= 1:CLKIN is 25MHz and USBCK1 = 24/48 MHz (determined by
2059 * [18]: 0(24)/1(48) MHz)
2060 * SCU7C is Write clear reg to SCU70
2061 * [23]:= write 1 and then SCU70[23] will be clear as 0b.
2062 */
2063 ast_moutdwm(ast, 0x1E6E2090, 0x20000000);
2064 ast_moutdwm(ast, 0x1E6E2094, 0x00004000);
2065 if (ast_mindwm(ast, 0x1E6E2070) & 0x00800000) {
2066 ast_moutdwm(ast, 0x1E6E207C, 0x00800000);
2067 mdelay(100);
2068 ast_moutdwm(ast, 0x1E6E2070, 0x00800000);
2069 }
2070 /* Modify eSPI reset pin */
2071 temp = ast_mindwm(ast, 0x1E6E2070);
2072 if (temp & 0x02000000)
2073 ast_moutdwm(ast, 0x1E6E207C, 0x00004000);
2074
2075 /* Slow down CPU/AHB CLK in VGA only mode */
2076 temp = ast_read32(ast, 0x12008);
2077 temp |= 0x73;
2078 ast_write32(ast, 0x12008, temp);
2079
2080 if (!ast_dram_init_2500(ast))
2081 drm_err(dev, "DRAM init failed !\n");
2082
2083 temp = ast_mindwm(ast, 0x1e6e2040);
2084 ast_moutdwm(ast, 0x1e6e2040, temp | 0x40);
2085 }
2086
2087 /* wait ready */
2088 do {
2089 reg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd0, 0xff);
2090 } while ((reg & 0x40) == 0);
2091}