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1/*
2 * SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs
3 *
4 * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * This driver has been based on the spi-gpio.c:
7 * Copyright (C) 2006,2008 David Brownell
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 */
14
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/delay.h>
18#include <linux/spinlock.h>
19#include <linux/platform_device.h>
20#include <linux/io.h>
21#include <linux/spi/spi.h>
22#include <linux/spi/spi_bitbang.h>
23#include <linux/bitops.h>
24#include <linux/gpio.h>
25#include <linux/clk.h>
26#include <linux/err.h>
27
28#include <asm/mach-ath79/ar71xx_regs.h>
29#include <asm/mach-ath79/ath79_spi_platform.h>
30
31#define DRV_NAME "ath79-spi"
32
33#define ATH79_SPI_RRW_DELAY_FACTOR 12000
34#define MHZ (1000 * 1000)
35
36struct ath79_spi {
37 struct spi_bitbang bitbang;
38 u32 ioc_base;
39 u32 reg_ctrl;
40 void __iomem *base;
41 struct clk *clk;
42 unsigned rrw_delay;
43};
44
45static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned reg)
46{
47 return ioread32(sp->base + reg);
48}
49
50static inline void ath79_spi_wr(struct ath79_spi *sp, unsigned reg, u32 val)
51{
52 iowrite32(val, sp->base + reg);
53}
54
55static inline struct ath79_spi *ath79_spidev_to_sp(struct spi_device *spi)
56{
57 return spi_master_get_devdata(spi->master);
58}
59
60static inline void ath79_spi_delay(struct ath79_spi *sp, unsigned nsecs)
61{
62 if (nsecs > sp->rrw_delay)
63 ndelay(nsecs - sp->rrw_delay);
64}
65
66static void ath79_spi_chipselect(struct spi_device *spi, int is_active)
67{
68 struct ath79_spi *sp = ath79_spidev_to_sp(spi);
69 int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active;
70
71 if (is_active) {
72 /* set initial clock polarity */
73 if (spi->mode & SPI_CPOL)
74 sp->ioc_base |= AR71XX_SPI_IOC_CLK;
75 else
76 sp->ioc_base &= ~AR71XX_SPI_IOC_CLK;
77
78 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
79 }
80
81 if (spi->chip_select) {
82 /* SPI is normally active-low */
83 gpio_set_value(spi->cs_gpio, cs_high);
84 } else {
85 if (cs_high)
86 sp->ioc_base |= AR71XX_SPI_IOC_CS0;
87 else
88 sp->ioc_base &= ~AR71XX_SPI_IOC_CS0;
89
90 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
91 }
92
93}
94
95static void ath79_spi_enable(struct ath79_spi *sp)
96{
97 /* enable GPIO mode */
98 ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
99
100 /* save CTRL register */
101 sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL);
102 sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC);
103
104 /* TODO: setup speed? */
105 ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
106}
107
108static void ath79_spi_disable(struct ath79_spi *sp)
109{
110 /* restore CTRL register */
111 ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl);
112 /* disable GPIO mode */
113 ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
114}
115
116static int ath79_spi_setup_cs(struct spi_device *spi)
117{
118 struct ath79_spi *sp = ath79_spidev_to_sp(spi);
119 int status;
120
121 if (spi->chip_select && !gpio_is_valid(spi->cs_gpio))
122 return -EINVAL;
123
124 status = 0;
125 if (spi->chip_select) {
126 unsigned long flags;
127
128 flags = GPIOF_DIR_OUT;
129 if (spi->mode & SPI_CS_HIGH)
130 flags |= GPIOF_INIT_LOW;
131 else
132 flags |= GPIOF_INIT_HIGH;
133
134 status = gpio_request_one(spi->cs_gpio, flags,
135 dev_name(&spi->dev));
136 } else {
137 if (spi->mode & SPI_CS_HIGH)
138 sp->ioc_base &= ~AR71XX_SPI_IOC_CS0;
139 else
140 sp->ioc_base |= AR71XX_SPI_IOC_CS0;
141
142 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
143 }
144
145 return status;
146}
147
148static void ath79_spi_cleanup_cs(struct spi_device *spi)
149{
150 if (spi->chip_select) {
151 gpio_free(spi->cs_gpio);
152 }
153}
154
155static int ath79_spi_setup(struct spi_device *spi)
156{
157 int status = 0;
158
159 if (!spi->controller_state) {
160 status = ath79_spi_setup_cs(spi);
161 if (status)
162 return status;
163 }
164
165 status = spi_bitbang_setup(spi);
166 if (status && !spi->controller_state)
167 ath79_spi_cleanup_cs(spi);
168
169 return status;
170}
171
172static void ath79_spi_cleanup(struct spi_device *spi)
173{
174 ath79_spi_cleanup_cs(spi);
175 spi_bitbang_cleanup(spi);
176}
177
178static u32 ath79_spi_txrx_mode0(struct spi_device *spi, unsigned nsecs,
179 u32 word, u8 bits)
180{
181 struct ath79_spi *sp = ath79_spidev_to_sp(spi);
182 u32 ioc = sp->ioc_base;
183
184 /* clock starts at inactive polarity */
185 for (word <<= (32 - bits); likely(bits); bits--) {
186 u32 out;
187
188 if (word & (1 << 31))
189 out = ioc | AR71XX_SPI_IOC_DO;
190 else
191 out = ioc & ~AR71XX_SPI_IOC_DO;
192
193 /* setup MSB (to slave) on trailing edge */
194 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
195 ath79_spi_delay(sp, nsecs);
196 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK);
197 ath79_spi_delay(sp, nsecs);
198 if (bits == 1)
199 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
200
201 word <<= 1;
202 }
203
204 return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS);
205}
206
207static int ath79_spi_probe(struct platform_device *pdev)
208{
209 struct spi_master *master;
210 struct ath79_spi *sp;
211 struct ath79_spi_platform_data *pdata;
212 struct resource *r;
213 unsigned long rate;
214 int ret;
215
216 master = spi_alloc_master(&pdev->dev, sizeof(*sp));
217 if (master == NULL) {
218 dev_err(&pdev->dev, "failed to allocate spi master\n");
219 return -ENOMEM;
220 }
221
222 sp = spi_master_get_devdata(master);
223 master->dev.of_node = pdev->dev.of_node;
224 platform_set_drvdata(pdev, sp);
225
226 pdata = dev_get_platdata(&pdev->dev);
227
228 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
229 master->setup = ath79_spi_setup;
230 master->cleanup = ath79_spi_cleanup;
231 if (pdata) {
232 master->bus_num = pdata->bus_num;
233 master->num_chipselect = pdata->num_chipselect;
234 }
235
236 sp->bitbang.master = master;
237 sp->bitbang.chipselect = ath79_spi_chipselect;
238 sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0;
239 sp->bitbang.setup_transfer = spi_bitbang_setup_transfer;
240 sp->bitbang.flags = SPI_CS_HIGH;
241
242 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
243 sp->base = devm_ioremap_resource(&pdev->dev, r);
244 if (IS_ERR(sp->base)) {
245 ret = PTR_ERR(sp->base);
246 goto err_put_master;
247 }
248
249 sp->clk = devm_clk_get(&pdev->dev, "ahb");
250 if (IS_ERR(sp->clk)) {
251 ret = PTR_ERR(sp->clk);
252 goto err_put_master;
253 }
254
255 ret = clk_prepare_enable(sp->clk);
256 if (ret)
257 goto err_put_master;
258
259 rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ);
260 if (!rate) {
261 ret = -EINVAL;
262 goto err_clk_disable;
263 }
264
265 sp->rrw_delay = ATH79_SPI_RRW_DELAY_FACTOR / rate;
266 dev_dbg(&pdev->dev, "register read/write delay is %u nsecs\n",
267 sp->rrw_delay);
268
269 ath79_spi_enable(sp);
270 ret = spi_bitbang_start(&sp->bitbang);
271 if (ret)
272 goto err_disable;
273
274 return 0;
275
276err_disable:
277 ath79_spi_disable(sp);
278err_clk_disable:
279 clk_disable_unprepare(sp->clk);
280err_put_master:
281 spi_master_put(sp->bitbang.master);
282
283 return ret;
284}
285
286static int ath79_spi_remove(struct platform_device *pdev)
287{
288 struct ath79_spi *sp = platform_get_drvdata(pdev);
289
290 spi_bitbang_stop(&sp->bitbang);
291 ath79_spi_disable(sp);
292 clk_disable_unprepare(sp->clk);
293 spi_master_put(sp->bitbang.master);
294
295 return 0;
296}
297
298static void ath79_spi_shutdown(struct platform_device *pdev)
299{
300 ath79_spi_remove(pdev);
301}
302
303static const struct of_device_id ath79_spi_of_match[] = {
304 { .compatible = "qca,ar7100-spi", },
305 { },
306};
307
308static struct platform_driver ath79_spi_driver = {
309 .probe = ath79_spi_probe,
310 .remove = ath79_spi_remove,
311 .shutdown = ath79_spi_shutdown,
312 .driver = {
313 .name = DRV_NAME,
314 .of_match_table = ath79_spi_of_match,
315 },
316};
317module_platform_driver(ath79_spi_driver);
318
319MODULE_DESCRIPTION("SPI controller driver for Atheros AR71XX/AR724X/AR913X");
320MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
321MODULE_LICENSE("GPL v2");
322MODULE_ALIAS("platform:" DRV_NAME);
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs
4 *
5 * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
6 *
7 * This driver has been based on the spi-gpio.c:
8 * Copyright (C) 2006,2008 David Brownell
9 */
10
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/delay.h>
14#include <linux/spinlock.h>
15#include <linux/platform_device.h>
16#include <linux/io.h>
17#include <linux/spi/spi.h>
18#include <linux/spi/spi_bitbang.h>
19#include <linux/bitops.h>
20#include <linux/clk.h>
21#include <linux/err.h>
22#include <linux/platform_data/spi-ath79.h>
23
24#define DRV_NAME "ath79-spi"
25
26#define ATH79_SPI_RRW_DELAY_FACTOR 12000
27#define MHZ (1000 * 1000)
28
29#define AR71XX_SPI_REG_FS 0x00 /* Function Select */
30#define AR71XX_SPI_REG_CTRL 0x04 /* SPI Control */
31#define AR71XX_SPI_REG_IOC 0x08 /* SPI I/O Control */
32#define AR71XX_SPI_REG_RDS 0x0c /* Read Data Shift */
33
34#define AR71XX_SPI_FS_GPIO BIT(0) /* Enable GPIO mode */
35
36#define AR71XX_SPI_IOC_DO BIT(0) /* Data Out pin */
37#define AR71XX_SPI_IOC_CLK BIT(8) /* CLK pin */
38#define AR71XX_SPI_IOC_CS(n) BIT(16 + (n))
39
40struct ath79_spi {
41 struct spi_bitbang bitbang;
42 u32 ioc_base;
43 u32 reg_ctrl;
44 void __iomem *base;
45 struct clk *clk;
46 unsigned int rrw_delay;
47};
48
49static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned int reg)
50{
51 return ioread32(sp->base + reg);
52}
53
54static inline void ath79_spi_wr(struct ath79_spi *sp, unsigned int reg, u32 val)
55{
56 iowrite32(val, sp->base + reg);
57}
58
59static inline struct ath79_spi *ath79_spidev_to_sp(struct spi_device *spi)
60{
61 return spi_master_get_devdata(spi->master);
62}
63
64static inline void ath79_spi_delay(struct ath79_spi *sp, unsigned int nsecs)
65{
66 if (nsecs > sp->rrw_delay)
67 ndelay(nsecs - sp->rrw_delay);
68}
69
70static void ath79_spi_chipselect(struct spi_device *spi, int is_active)
71{
72 struct ath79_spi *sp = ath79_spidev_to_sp(spi);
73 int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active;
74 u32 cs_bit = AR71XX_SPI_IOC_CS(spi->chip_select);
75
76 if (cs_high)
77 sp->ioc_base |= cs_bit;
78 else
79 sp->ioc_base &= ~cs_bit;
80
81 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
82}
83
84static void ath79_spi_enable(struct ath79_spi *sp)
85{
86 /* enable GPIO mode */
87 ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
88
89 /* save CTRL register */
90 sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL);
91 sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC);
92
93 /* clear clk and mosi in the base state */
94 sp->ioc_base &= ~(AR71XX_SPI_IOC_DO | AR71XX_SPI_IOC_CLK);
95
96 /* TODO: setup speed? */
97 ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
98}
99
100static void ath79_spi_disable(struct ath79_spi *sp)
101{
102 /* restore CTRL register */
103 ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl);
104 /* disable GPIO mode */
105 ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
106}
107
108static u32 ath79_spi_txrx_mode0(struct spi_device *spi, unsigned int nsecs,
109 u32 word, u8 bits, unsigned flags)
110{
111 struct ath79_spi *sp = ath79_spidev_to_sp(spi);
112 u32 ioc = sp->ioc_base;
113
114 /* clock starts at inactive polarity */
115 for (word <<= (32 - bits); likely(bits); bits--) {
116 u32 out;
117
118 if (word & (1 << 31))
119 out = ioc | AR71XX_SPI_IOC_DO;
120 else
121 out = ioc & ~AR71XX_SPI_IOC_DO;
122
123 /* setup MSB (to slave) on trailing edge */
124 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
125 ath79_spi_delay(sp, nsecs);
126 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK);
127 ath79_spi_delay(sp, nsecs);
128 if (bits == 1)
129 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
130
131 word <<= 1;
132 }
133
134 return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS);
135}
136
137static int ath79_spi_probe(struct platform_device *pdev)
138{
139 struct spi_master *master;
140 struct ath79_spi *sp;
141 struct ath79_spi_platform_data *pdata;
142 unsigned long rate;
143 int ret;
144
145 master = spi_alloc_master(&pdev->dev, sizeof(*sp));
146 if (master == NULL) {
147 dev_err(&pdev->dev, "failed to allocate spi master\n");
148 return -ENOMEM;
149 }
150
151 sp = spi_master_get_devdata(master);
152 master->dev.of_node = pdev->dev.of_node;
153 platform_set_drvdata(pdev, sp);
154
155 pdata = dev_get_platdata(&pdev->dev);
156
157 master->use_gpio_descriptors = true;
158 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
159 master->setup = spi_bitbang_setup;
160 master->cleanup = spi_bitbang_cleanup;
161 if (pdata) {
162 master->bus_num = pdata->bus_num;
163 master->num_chipselect = pdata->num_chipselect;
164 }
165
166 sp->bitbang.master = master;
167 sp->bitbang.chipselect = ath79_spi_chipselect;
168 sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0;
169 sp->bitbang.flags = SPI_CS_HIGH;
170
171 sp->base = devm_platform_ioremap_resource(pdev, 0);
172 if (IS_ERR(sp->base)) {
173 ret = PTR_ERR(sp->base);
174 goto err_put_master;
175 }
176
177 sp->clk = devm_clk_get(&pdev->dev, "ahb");
178 if (IS_ERR(sp->clk)) {
179 ret = PTR_ERR(sp->clk);
180 goto err_put_master;
181 }
182
183 ret = clk_prepare_enable(sp->clk);
184 if (ret)
185 goto err_put_master;
186
187 rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ);
188 if (!rate) {
189 ret = -EINVAL;
190 goto err_clk_disable;
191 }
192
193 sp->rrw_delay = ATH79_SPI_RRW_DELAY_FACTOR / rate;
194 dev_dbg(&pdev->dev, "register read/write delay is %u nsecs\n",
195 sp->rrw_delay);
196
197 ath79_spi_enable(sp);
198 ret = spi_bitbang_start(&sp->bitbang);
199 if (ret)
200 goto err_disable;
201
202 return 0;
203
204err_disable:
205 ath79_spi_disable(sp);
206err_clk_disable:
207 clk_disable_unprepare(sp->clk);
208err_put_master:
209 spi_master_put(sp->bitbang.master);
210
211 return ret;
212}
213
214static int ath79_spi_remove(struct platform_device *pdev)
215{
216 struct ath79_spi *sp = platform_get_drvdata(pdev);
217
218 spi_bitbang_stop(&sp->bitbang);
219 ath79_spi_disable(sp);
220 clk_disable_unprepare(sp->clk);
221 spi_master_put(sp->bitbang.master);
222
223 return 0;
224}
225
226static void ath79_spi_shutdown(struct platform_device *pdev)
227{
228 ath79_spi_remove(pdev);
229}
230
231static const struct of_device_id ath79_spi_of_match[] = {
232 { .compatible = "qca,ar7100-spi", },
233 { },
234};
235MODULE_DEVICE_TABLE(of, ath79_spi_of_match);
236
237static struct platform_driver ath79_spi_driver = {
238 .probe = ath79_spi_probe,
239 .remove = ath79_spi_remove,
240 .shutdown = ath79_spi_shutdown,
241 .driver = {
242 .name = DRV_NAME,
243 .of_match_table = ath79_spi_of_match,
244 },
245};
246module_platform_driver(ath79_spi_driver);
247
248MODULE_DESCRIPTION("SPI controller driver for Atheros AR71XX/AR724X/AR913X");
249MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
250MODULE_LICENSE("GPL v2");
251MODULE_ALIAS("platform:" DRV_NAME);