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1/*
2 * SiRFSoC Real Time Clock interface for Linux
3 *
4 * Copyright (c) 2013 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#include <linux/module.h>
10#include <linux/err.h>
11#include <linux/rtc.h>
12#include <linux/platform_device.h>
13#include <linux/slab.h>
14#include <linux/io.h>
15#include <linux/of.h>
16#include <linux/regmap.h>
17#include <linux/rtc/sirfsoc_rtciobrg.h>
18
19
20#define RTC_CN 0x00
21#define RTC_ALARM0 0x04
22#define RTC_ALARM1 0x18
23#define RTC_STATUS 0x08
24#define RTC_SW_VALUE 0x40
25#define SIRFSOC_RTC_AL1E (1<<6)
26#define SIRFSOC_RTC_AL1 (1<<4)
27#define SIRFSOC_RTC_HZE (1<<3)
28#define SIRFSOC_RTC_AL0E (1<<2)
29#define SIRFSOC_RTC_HZ (1<<1)
30#define SIRFSOC_RTC_AL0 (1<<0)
31#define RTC_DIV 0x0c
32#define RTC_DEEP_CTRL 0x14
33#define RTC_CLOCK_SWITCH 0x1c
34#define SIRFSOC_RTC_CLK 0x03 /* others are reserved */
35
36/* Refer to RTC DIV switch */
37#define RTC_HZ 16
38
39/* This macro is also defined in arch/arm/plat-sirfsoc/cpu.c */
40#define RTC_SHIFT 4
41
42#define INTR_SYSRTC_CN 0x48
43
44struct sirfsoc_rtc_drv {
45 struct rtc_device *rtc;
46 u32 rtc_base;
47 u32 irq;
48 unsigned irq_wake;
49 /* Overflow for every 8 years extra time */
50 u32 overflow_rtc;
51 spinlock_t lock;
52 struct regmap *regmap;
53#ifdef CONFIG_PM
54 u32 saved_counter;
55 u32 saved_overflow_rtc;
56#endif
57};
58
59static u32 sirfsoc_rtc_readl(struct sirfsoc_rtc_drv *rtcdrv, u32 offset)
60{
61 u32 val;
62
63 regmap_read(rtcdrv->regmap, rtcdrv->rtc_base + offset, &val);
64 return val;
65}
66
67static void sirfsoc_rtc_writel(struct sirfsoc_rtc_drv *rtcdrv,
68 u32 offset, u32 val)
69{
70 regmap_write(rtcdrv->regmap, rtcdrv->rtc_base + offset, val);
71}
72
73static int sirfsoc_rtc_read_alarm(struct device *dev,
74 struct rtc_wkalrm *alrm)
75{
76 unsigned long rtc_alarm, rtc_count;
77 struct sirfsoc_rtc_drv *rtcdrv;
78
79 rtcdrv = dev_get_drvdata(dev);
80
81 spin_lock_irq(&rtcdrv->lock);
82
83 rtc_count = sirfsoc_rtc_readl(rtcdrv, RTC_CN);
84
85 rtc_alarm = sirfsoc_rtc_readl(rtcdrv, RTC_ALARM0);
86 memset(alrm, 0, sizeof(struct rtc_wkalrm));
87
88 /*
89 * assume alarm interval not beyond one round counter overflow_rtc:
90 * 0->0xffffffff
91 */
92 /* if alarm is in next overflow cycle */
93 if (rtc_count > rtc_alarm)
94 rtc_time_to_tm((rtcdrv->overflow_rtc + 1)
95 << (BITS_PER_LONG - RTC_SHIFT)
96 | rtc_alarm >> RTC_SHIFT, &(alrm->time));
97 else
98 rtc_time_to_tm(rtcdrv->overflow_rtc
99 << (BITS_PER_LONG - RTC_SHIFT)
100 | rtc_alarm >> RTC_SHIFT, &(alrm->time));
101 if (sirfsoc_rtc_readl(rtcdrv, RTC_STATUS) & SIRFSOC_RTC_AL0E)
102 alrm->enabled = 1;
103
104 spin_unlock_irq(&rtcdrv->lock);
105
106 return 0;
107}
108
109static int sirfsoc_rtc_set_alarm(struct device *dev,
110 struct rtc_wkalrm *alrm)
111{
112 unsigned long rtc_status_reg, rtc_alarm;
113 struct sirfsoc_rtc_drv *rtcdrv;
114 rtcdrv = dev_get_drvdata(dev);
115
116 if (alrm->enabled) {
117 rtc_tm_to_time(&(alrm->time), &rtc_alarm);
118
119 spin_lock_irq(&rtcdrv->lock);
120
121 rtc_status_reg = sirfsoc_rtc_readl(rtcdrv, RTC_STATUS);
122 if (rtc_status_reg & SIRFSOC_RTC_AL0E) {
123 /*
124 * An ongoing alarm in progress - ingore it and not
125 * to return EBUSY
126 */
127 dev_info(dev, "An old alarm was set, will be replaced by a new one\n");
128 }
129
130 sirfsoc_rtc_writel(rtcdrv, RTC_ALARM0, rtc_alarm << RTC_SHIFT);
131 rtc_status_reg &= ~0x07; /* mask out the lower status bits */
132 /*
133 * This bit RTC_AL sets it as a wake-up source for Sleep Mode
134 * Writing 1 into this bit will clear it
135 */
136 rtc_status_reg |= SIRFSOC_RTC_AL0;
137 /* enable the RTC alarm interrupt */
138 rtc_status_reg |= SIRFSOC_RTC_AL0E;
139 sirfsoc_rtc_writel(rtcdrv, RTC_STATUS, rtc_status_reg);
140
141 spin_unlock_irq(&rtcdrv->lock);
142 } else {
143 /*
144 * if this function was called with enabled=0
145 * then it could mean that the application is
146 * trying to cancel an ongoing alarm
147 */
148 spin_lock_irq(&rtcdrv->lock);
149
150 rtc_status_reg = sirfsoc_rtc_readl(rtcdrv, RTC_STATUS);
151 if (rtc_status_reg & SIRFSOC_RTC_AL0E) {
152 /* clear the RTC status register's alarm bit */
153 rtc_status_reg &= ~0x07;
154 /* write 1 into SIRFSOC_RTC_AL0 to force a clear */
155 rtc_status_reg |= (SIRFSOC_RTC_AL0);
156 /* Clear the Alarm enable bit */
157 rtc_status_reg &= ~(SIRFSOC_RTC_AL0E);
158
159 sirfsoc_rtc_writel(rtcdrv, RTC_STATUS,
160 rtc_status_reg);
161 }
162
163 spin_unlock_irq(&rtcdrv->lock);
164 }
165
166 return 0;
167}
168
169static int sirfsoc_rtc_read_time(struct device *dev,
170 struct rtc_time *tm)
171{
172 unsigned long tmp_rtc = 0;
173 struct sirfsoc_rtc_drv *rtcdrv;
174 rtcdrv = dev_get_drvdata(dev);
175 /*
176 * This patch is taken from WinCE - Need to validate this for
177 * correctness. To work around sirfsoc RTC counter double sync logic
178 * fail, read several times to make sure get stable value.
179 */
180 do {
181 tmp_rtc = sirfsoc_rtc_readl(rtcdrv, RTC_CN);
182 cpu_relax();
183 } while (tmp_rtc != sirfsoc_rtc_readl(rtcdrv, RTC_CN));
184
185 rtc_time_to_tm(rtcdrv->overflow_rtc << (BITS_PER_LONG - RTC_SHIFT) |
186 tmp_rtc >> RTC_SHIFT, tm);
187 return 0;
188}
189
190static int sirfsoc_rtc_set_time(struct device *dev,
191 struct rtc_time *tm)
192{
193 unsigned long rtc_time;
194 struct sirfsoc_rtc_drv *rtcdrv;
195 rtcdrv = dev_get_drvdata(dev);
196
197 rtc_tm_to_time(tm, &rtc_time);
198
199 rtcdrv->overflow_rtc = rtc_time >> (BITS_PER_LONG - RTC_SHIFT);
200
201 sirfsoc_rtc_writel(rtcdrv, RTC_SW_VALUE, rtcdrv->overflow_rtc);
202 sirfsoc_rtc_writel(rtcdrv, RTC_CN, rtc_time << RTC_SHIFT);
203
204 return 0;
205}
206
207static int sirfsoc_rtc_ioctl(struct device *dev, unsigned int cmd,
208 unsigned long arg)
209{
210 switch (cmd) {
211 case RTC_PIE_ON:
212 case RTC_PIE_OFF:
213 case RTC_UIE_ON:
214 case RTC_UIE_OFF:
215 case RTC_AIE_ON:
216 case RTC_AIE_OFF:
217 return 0;
218
219 default:
220 return -ENOIOCTLCMD;
221 }
222}
223
224static int sirfsoc_rtc_alarm_irq_enable(struct device *dev,
225 unsigned int enabled)
226{
227 unsigned long rtc_status_reg = 0x0;
228 struct sirfsoc_rtc_drv *rtcdrv;
229
230 rtcdrv = dev_get_drvdata(dev);
231
232 spin_lock_irq(&rtcdrv->lock);
233
234 rtc_status_reg = sirfsoc_rtc_readl(rtcdrv, RTC_STATUS);
235 if (enabled)
236 rtc_status_reg |= SIRFSOC_RTC_AL0E;
237 else
238 rtc_status_reg &= ~SIRFSOC_RTC_AL0E;
239
240 sirfsoc_rtc_writel(rtcdrv, RTC_STATUS, rtc_status_reg);
241
242 spin_unlock_irq(&rtcdrv->lock);
243
244 return 0;
245
246}
247
248static const struct rtc_class_ops sirfsoc_rtc_ops = {
249 .read_time = sirfsoc_rtc_read_time,
250 .set_time = sirfsoc_rtc_set_time,
251 .read_alarm = sirfsoc_rtc_read_alarm,
252 .set_alarm = sirfsoc_rtc_set_alarm,
253 .ioctl = sirfsoc_rtc_ioctl,
254 .alarm_irq_enable = sirfsoc_rtc_alarm_irq_enable
255};
256
257static irqreturn_t sirfsoc_rtc_irq_handler(int irq, void *pdata)
258{
259 struct sirfsoc_rtc_drv *rtcdrv = pdata;
260 unsigned long rtc_status_reg = 0x0;
261 unsigned long events = 0x0;
262
263 spin_lock(&rtcdrv->lock);
264
265 rtc_status_reg = sirfsoc_rtc_readl(rtcdrv, RTC_STATUS);
266 /* this bit will be set ONLY if an alarm was active
267 * and it expired NOW
268 * So this is being used as an ASSERT
269 */
270 if (rtc_status_reg & SIRFSOC_RTC_AL0) {
271 /*
272 * clear the RTC status register's alarm bit
273 * mask out the lower status bits
274 */
275 rtc_status_reg &= ~0x07;
276 /* write 1 into SIRFSOC_RTC_AL0 to ACK the alarm interrupt */
277 rtc_status_reg |= (SIRFSOC_RTC_AL0);
278 /* Clear the Alarm enable bit */
279 rtc_status_reg &= ~(SIRFSOC_RTC_AL0E);
280 }
281
282 sirfsoc_rtc_writel(rtcdrv, RTC_STATUS, rtc_status_reg);
283
284 spin_unlock(&rtcdrv->lock);
285
286 /* this should wake up any apps polling/waiting on the read
287 * after setting the alarm
288 */
289 events |= RTC_IRQF | RTC_AF;
290 rtc_update_irq(rtcdrv->rtc, 1, events);
291
292 return IRQ_HANDLED;
293}
294
295static const struct of_device_id sirfsoc_rtc_of_match[] = {
296 { .compatible = "sirf,prima2-sysrtc"},
297 {},
298};
299
300const struct regmap_config sysrtc_regmap_config = {
301 .reg_bits = 32,
302 .val_bits = 32,
303 .fast_io = true,
304};
305
306MODULE_DEVICE_TABLE(of, sirfsoc_rtc_of_match);
307
308static int sirfsoc_rtc_probe(struct platform_device *pdev)
309{
310 int err;
311 unsigned long rtc_div;
312 struct sirfsoc_rtc_drv *rtcdrv;
313 struct device_node *np = pdev->dev.of_node;
314
315 rtcdrv = devm_kzalloc(&pdev->dev,
316 sizeof(struct sirfsoc_rtc_drv), GFP_KERNEL);
317 if (rtcdrv == NULL)
318 return -ENOMEM;
319
320 spin_lock_init(&rtcdrv->lock);
321
322 err = of_property_read_u32(np, "reg", &rtcdrv->rtc_base);
323 if (err) {
324 dev_err(&pdev->dev, "unable to find base address of rtc node in dtb\n");
325 return err;
326 }
327
328 platform_set_drvdata(pdev, rtcdrv);
329
330 /* Register rtc alarm as a wakeup source */
331 device_init_wakeup(&pdev->dev, 1);
332
333 rtcdrv->regmap = devm_regmap_init_iobg(&pdev->dev,
334 &sysrtc_regmap_config);
335 if (IS_ERR(rtcdrv->regmap)) {
336 err = PTR_ERR(rtcdrv->regmap);
337 dev_err(&pdev->dev, "Failed to allocate register map: %d\n",
338 err);
339 return err;
340 }
341
342 /*
343 * Set SYS_RTC counter in RTC_HZ HZ Units
344 * We are using 32K RTC crystal (32768 / RTC_HZ / 2) -1
345 * If 16HZ, therefore RTC_DIV = 1023;
346 */
347 rtc_div = ((32768 / RTC_HZ) / 2) - 1;
348 sirfsoc_rtc_writel(rtcdrv, RTC_DIV, rtc_div);
349
350 /* 0x3 -> RTC_CLK */
351 sirfsoc_rtc_writel(rtcdrv, RTC_CLOCK_SWITCH, SIRFSOC_RTC_CLK);
352
353 /* reset SYS RTC ALARM0 */
354 sirfsoc_rtc_writel(rtcdrv, RTC_ALARM0, 0x0);
355
356 /* reset SYS RTC ALARM1 */
357 sirfsoc_rtc_writel(rtcdrv, RTC_ALARM1, 0x0);
358
359 /* Restore RTC Overflow From Register After Command Reboot */
360 rtcdrv->overflow_rtc =
361 sirfsoc_rtc_readl(rtcdrv, RTC_SW_VALUE);
362
363 rtcdrv->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
364 &sirfsoc_rtc_ops, THIS_MODULE);
365 if (IS_ERR(rtcdrv->rtc)) {
366 err = PTR_ERR(rtcdrv->rtc);
367 dev_err(&pdev->dev, "can't register RTC device\n");
368 return err;
369 }
370
371 rtcdrv->irq = platform_get_irq(pdev, 0);
372 err = devm_request_irq(
373 &pdev->dev,
374 rtcdrv->irq,
375 sirfsoc_rtc_irq_handler,
376 IRQF_SHARED,
377 pdev->name,
378 rtcdrv);
379 if (err) {
380 dev_err(&pdev->dev, "Unable to register for the SiRF SOC RTC IRQ\n");
381 return err;
382 }
383
384 return 0;
385}
386
387static int sirfsoc_rtc_remove(struct platform_device *pdev)
388{
389 device_init_wakeup(&pdev->dev, 0);
390
391 return 0;
392}
393
394#ifdef CONFIG_PM_SLEEP
395static int sirfsoc_rtc_suspend(struct device *dev)
396{
397 struct sirfsoc_rtc_drv *rtcdrv = dev_get_drvdata(dev);
398 rtcdrv->overflow_rtc =
399 sirfsoc_rtc_readl(rtcdrv, RTC_SW_VALUE);
400
401 rtcdrv->saved_counter =
402 sirfsoc_rtc_readl(rtcdrv, RTC_CN);
403 rtcdrv->saved_overflow_rtc = rtcdrv->overflow_rtc;
404 if (device_may_wakeup(dev) && !enable_irq_wake(rtcdrv->irq))
405 rtcdrv->irq_wake = 1;
406
407 return 0;
408}
409
410static int sirfsoc_rtc_resume(struct device *dev)
411{
412 u32 tmp;
413 struct sirfsoc_rtc_drv *rtcdrv = dev_get_drvdata(dev);
414
415 /*
416 * if resume from snapshot and the rtc power is lost,
417 * restroe the rtc settings
418 */
419 if (SIRFSOC_RTC_CLK != sirfsoc_rtc_readl(rtcdrv, RTC_CLOCK_SWITCH)) {
420 u32 rtc_div;
421 /* 0x3 -> RTC_CLK */
422 sirfsoc_rtc_writel(rtcdrv, RTC_CLOCK_SWITCH, SIRFSOC_RTC_CLK);
423 /*
424 * Set SYS_RTC counter in RTC_HZ HZ Units
425 * We are using 32K RTC crystal (32768 / RTC_HZ / 2) -1
426 * If 16HZ, therefore RTC_DIV = 1023;
427 */
428 rtc_div = ((32768 / RTC_HZ) / 2) - 1;
429
430 sirfsoc_rtc_writel(rtcdrv, RTC_DIV, rtc_div);
431
432 /* reset SYS RTC ALARM0 */
433 sirfsoc_rtc_writel(rtcdrv, RTC_ALARM0, 0x0);
434
435 /* reset SYS RTC ALARM1 */
436 sirfsoc_rtc_writel(rtcdrv, RTC_ALARM1, 0x0);
437 }
438 rtcdrv->overflow_rtc = rtcdrv->saved_overflow_rtc;
439
440 /*
441 * if current counter is small than previous,
442 * it means overflow in sleep
443 */
444 tmp = sirfsoc_rtc_readl(rtcdrv, RTC_CN);
445 if (tmp <= rtcdrv->saved_counter)
446 rtcdrv->overflow_rtc++;
447 /*
448 *PWRC Value Be Changed When Suspend, Restore Overflow
449 * In Memory To Register
450 */
451 sirfsoc_rtc_writel(rtcdrv, RTC_SW_VALUE, rtcdrv->overflow_rtc);
452
453 if (device_may_wakeup(dev) && rtcdrv->irq_wake) {
454 disable_irq_wake(rtcdrv->irq);
455 rtcdrv->irq_wake = 0;
456 }
457
458 return 0;
459}
460#endif
461
462static SIMPLE_DEV_PM_OPS(sirfsoc_rtc_pm_ops,
463 sirfsoc_rtc_suspend, sirfsoc_rtc_resume);
464
465static struct platform_driver sirfsoc_rtc_driver = {
466 .driver = {
467 .name = "sirfsoc-rtc",
468 .pm = &sirfsoc_rtc_pm_ops,
469 .of_match_table = sirfsoc_rtc_of_match,
470 },
471 .probe = sirfsoc_rtc_probe,
472 .remove = sirfsoc_rtc_remove,
473};
474module_platform_driver(sirfsoc_rtc_driver);
475
476MODULE_DESCRIPTION("SiRF SoC rtc driver");
477MODULE_AUTHOR("Xianglong Du <Xianglong.Du@csr.com>");
478MODULE_LICENSE("GPL v2");
479MODULE_ALIAS("platform:sirfsoc-rtc");
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * SiRFSoC Real Time Clock interface for Linux
4 *
5 * Copyright (c) 2013 Cambridge Silicon Radio Limited, a CSR plc group company.
6 */
7
8#include <linux/module.h>
9#include <linux/err.h>
10#include <linux/rtc.h>
11#include <linux/platform_device.h>
12#include <linux/slab.h>
13#include <linux/io.h>
14#include <linux/of.h>
15#include <linux/regmap.h>
16#include <linux/rtc/sirfsoc_rtciobrg.h>
17
18
19#define RTC_CN 0x00
20#define RTC_ALARM0 0x04
21#define RTC_ALARM1 0x18
22#define RTC_STATUS 0x08
23#define RTC_SW_VALUE 0x40
24#define SIRFSOC_RTC_AL1E (1<<6)
25#define SIRFSOC_RTC_AL1 (1<<4)
26#define SIRFSOC_RTC_HZE (1<<3)
27#define SIRFSOC_RTC_AL0E (1<<2)
28#define SIRFSOC_RTC_HZ (1<<1)
29#define SIRFSOC_RTC_AL0 (1<<0)
30#define RTC_DIV 0x0c
31#define RTC_DEEP_CTRL 0x14
32#define RTC_CLOCK_SWITCH 0x1c
33#define SIRFSOC_RTC_CLK 0x03 /* others are reserved */
34
35/* Refer to RTC DIV switch */
36#define RTC_HZ 16
37
38/* This macro is also defined in arch/arm/plat-sirfsoc/cpu.c */
39#define RTC_SHIFT 4
40
41#define INTR_SYSRTC_CN 0x48
42
43struct sirfsoc_rtc_drv {
44 struct rtc_device *rtc;
45 u32 rtc_base;
46 u32 irq;
47 unsigned irq_wake;
48 /* Overflow for every 8 years extra time */
49 u32 overflow_rtc;
50 spinlock_t lock;
51 struct regmap *regmap;
52#ifdef CONFIG_PM
53 u32 saved_counter;
54 u32 saved_overflow_rtc;
55#endif
56};
57
58static u32 sirfsoc_rtc_readl(struct sirfsoc_rtc_drv *rtcdrv, u32 offset)
59{
60 u32 val;
61
62 regmap_read(rtcdrv->regmap, rtcdrv->rtc_base + offset, &val);
63 return val;
64}
65
66static void sirfsoc_rtc_writel(struct sirfsoc_rtc_drv *rtcdrv,
67 u32 offset, u32 val)
68{
69 regmap_write(rtcdrv->regmap, rtcdrv->rtc_base + offset, val);
70}
71
72static int sirfsoc_rtc_read_alarm(struct device *dev,
73 struct rtc_wkalrm *alrm)
74{
75 unsigned long rtc_alarm, rtc_count;
76 struct sirfsoc_rtc_drv *rtcdrv;
77
78 rtcdrv = dev_get_drvdata(dev);
79
80 spin_lock_irq(&rtcdrv->lock);
81
82 rtc_count = sirfsoc_rtc_readl(rtcdrv, RTC_CN);
83
84 rtc_alarm = sirfsoc_rtc_readl(rtcdrv, RTC_ALARM0);
85 memset(alrm, 0, sizeof(struct rtc_wkalrm));
86
87 /*
88 * assume alarm interval not beyond one round counter overflow_rtc:
89 * 0->0xffffffff
90 */
91 /* if alarm is in next overflow cycle */
92 if (rtc_count > rtc_alarm)
93 rtc_time64_to_tm((rtcdrv->overflow_rtc + 1)
94 << (BITS_PER_LONG - RTC_SHIFT)
95 | rtc_alarm >> RTC_SHIFT, &alrm->time);
96 else
97 rtc_time64_to_tm(rtcdrv->overflow_rtc
98 << (BITS_PER_LONG - RTC_SHIFT)
99 | rtc_alarm >> RTC_SHIFT, &alrm->time);
100 if (sirfsoc_rtc_readl(rtcdrv, RTC_STATUS) & SIRFSOC_RTC_AL0E)
101 alrm->enabled = 1;
102
103 spin_unlock_irq(&rtcdrv->lock);
104
105 return 0;
106}
107
108static int sirfsoc_rtc_set_alarm(struct device *dev,
109 struct rtc_wkalrm *alrm)
110{
111 unsigned long rtc_status_reg, rtc_alarm;
112 struct sirfsoc_rtc_drv *rtcdrv;
113 rtcdrv = dev_get_drvdata(dev);
114
115 if (alrm->enabled) {
116 rtc_alarm = rtc_tm_to_time64(&alrm->time);
117
118 spin_lock_irq(&rtcdrv->lock);
119
120 rtc_status_reg = sirfsoc_rtc_readl(rtcdrv, RTC_STATUS);
121 if (rtc_status_reg & SIRFSOC_RTC_AL0E) {
122 /*
123 * An ongoing alarm in progress - ingore it and not
124 * to return EBUSY
125 */
126 dev_info(dev, "An old alarm was set, will be replaced by a new one\n");
127 }
128
129 sirfsoc_rtc_writel(rtcdrv, RTC_ALARM0, rtc_alarm << RTC_SHIFT);
130 rtc_status_reg &= ~0x07; /* mask out the lower status bits */
131 /*
132 * This bit RTC_AL sets it as a wake-up source for Sleep Mode
133 * Writing 1 into this bit will clear it
134 */
135 rtc_status_reg |= SIRFSOC_RTC_AL0;
136 /* enable the RTC alarm interrupt */
137 rtc_status_reg |= SIRFSOC_RTC_AL0E;
138 sirfsoc_rtc_writel(rtcdrv, RTC_STATUS, rtc_status_reg);
139
140 spin_unlock_irq(&rtcdrv->lock);
141 } else {
142 /*
143 * if this function was called with enabled=0
144 * then it could mean that the application is
145 * trying to cancel an ongoing alarm
146 */
147 spin_lock_irq(&rtcdrv->lock);
148
149 rtc_status_reg = sirfsoc_rtc_readl(rtcdrv, RTC_STATUS);
150 if (rtc_status_reg & SIRFSOC_RTC_AL0E) {
151 /* clear the RTC status register's alarm bit */
152 rtc_status_reg &= ~0x07;
153 /* write 1 into SIRFSOC_RTC_AL0 to force a clear */
154 rtc_status_reg |= (SIRFSOC_RTC_AL0);
155 /* Clear the Alarm enable bit */
156 rtc_status_reg &= ~(SIRFSOC_RTC_AL0E);
157
158 sirfsoc_rtc_writel(rtcdrv, RTC_STATUS,
159 rtc_status_reg);
160 }
161
162 spin_unlock_irq(&rtcdrv->lock);
163 }
164
165 return 0;
166}
167
168static int sirfsoc_rtc_read_time(struct device *dev,
169 struct rtc_time *tm)
170{
171 unsigned long tmp_rtc = 0;
172 struct sirfsoc_rtc_drv *rtcdrv;
173 rtcdrv = dev_get_drvdata(dev);
174 /*
175 * This patch is taken from WinCE - Need to validate this for
176 * correctness. To work around sirfsoc RTC counter double sync logic
177 * fail, read several times to make sure get stable value.
178 */
179 do {
180 tmp_rtc = sirfsoc_rtc_readl(rtcdrv, RTC_CN);
181 cpu_relax();
182 } while (tmp_rtc != sirfsoc_rtc_readl(rtcdrv, RTC_CN));
183
184 rtc_time64_to_tm(rtcdrv->overflow_rtc << (BITS_PER_LONG - RTC_SHIFT)
185 | tmp_rtc >> RTC_SHIFT, tm);
186 return 0;
187}
188
189static int sirfsoc_rtc_set_time(struct device *dev,
190 struct rtc_time *tm)
191{
192 unsigned long rtc_time;
193 struct sirfsoc_rtc_drv *rtcdrv;
194 rtcdrv = dev_get_drvdata(dev);
195
196 rtc_time = rtc_tm_to_time64(tm);
197
198 rtcdrv->overflow_rtc = rtc_time >> (BITS_PER_LONG - RTC_SHIFT);
199
200 sirfsoc_rtc_writel(rtcdrv, RTC_SW_VALUE, rtcdrv->overflow_rtc);
201 sirfsoc_rtc_writel(rtcdrv, RTC_CN, rtc_time << RTC_SHIFT);
202
203 return 0;
204}
205
206static int sirfsoc_rtc_alarm_irq_enable(struct device *dev,
207 unsigned int enabled)
208{
209 unsigned long rtc_status_reg = 0x0;
210 struct sirfsoc_rtc_drv *rtcdrv;
211
212 rtcdrv = dev_get_drvdata(dev);
213
214 spin_lock_irq(&rtcdrv->lock);
215
216 rtc_status_reg = sirfsoc_rtc_readl(rtcdrv, RTC_STATUS);
217 if (enabled)
218 rtc_status_reg |= SIRFSOC_RTC_AL0E;
219 else
220 rtc_status_reg &= ~SIRFSOC_RTC_AL0E;
221
222 sirfsoc_rtc_writel(rtcdrv, RTC_STATUS, rtc_status_reg);
223
224 spin_unlock_irq(&rtcdrv->lock);
225
226 return 0;
227
228}
229
230static const struct rtc_class_ops sirfsoc_rtc_ops = {
231 .read_time = sirfsoc_rtc_read_time,
232 .set_time = sirfsoc_rtc_set_time,
233 .read_alarm = sirfsoc_rtc_read_alarm,
234 .set_alarm = sirfsoc_rtc_set_alarm,
235 .alarm_irq_enable = sirfsoc_rtc_alarm_irq_enable
236};
237
238static irqreturn_t sirfsoc_rtc_irq_handler(int irq, void *pdata)
239{
240 struct sirfsoc_rtc_drv *rtcdrv = pdata;
241 unsigned long rtc_status_reg = 0x0;
242 unsigned long events = 0x0;
243
244 spin_lock(&rtcdrv->lock);
245
246 rtc_status_reg = sirfsoc_rtc_readl(rtcdrv, RTC_STATUS);
247 /* this bit will be set ONLY if an alarm was active
248 * and it expired NOW
249 * So this is being used as an ASSERT
250 */
251 if (rtc_status_reg & SIRFSOC_RTC_AL0) {
252 /*
253 * clear the RTC status register's alarm bit
254 * mask out the lower status bits
255 */
256 rtc_status_reg &= ~0x07;
257 /* write 1 into SIRFSOC_RTC_AL0 to ACK the alarm interrupt */
258 rtc_status_reg |= (SIRFSOC_RTC_AL0);
259 /* Clear the Alarm enable bit */
260 rtc_status_reg &= ~(SIRFSOC_RTC_AL0E);
261 }
262
263 sirfsoc_rtc_writel(rtcdrv, RTC_STATUS, rtc_status_reg);
264
265 spin_unlock(&rtcdrv->lock);
266
267 /* this should wake up any apps polling/waiting on the read
268 * after setting the alarm
269 */
270 events |= RTC_IRQF | RTC_AF;
271 rtc_update_irq(rtcdrv->rtc, 1, events);
272
273 return IRQ_HANDLED;
274}
275
276static const struct of_device_id sirfsoc_rtc_of_match[] = {
277 { .compatible = "sirf,prima2-sysrtc"},
278 {},
279};
280
281static const struct regmap_config sysrtc_regmap_config = {
282 .reg_bits = 32,
283 .val_bits = 32,
284 .fast_io = true,
285};
286
287MODULE_DEVICE_TABLE(of, sirfsoc_rtc_of_match);
288
289static int sirfsoc_rtc_probe(struct platform_device *pdev)
290{
291 int err;
292 unsigned long rtc_div;
293 struct sirfsoc_rtc_drv *rtcdrv;
294 struct device_node *np = pdev->dev.of_node;
295
296 rtcdrv = devm_kzalloc(&pdev->dev,
297 sizeof(struct sirfsoc_rtc_drv), GFP_KERNEL);
298 if (rtcdrv == NULL)
299 return -ENOMEM;
300
301 spin_lock_init(&rtcdrv->lock);
302
303 err = of_property_read_u32(np, "reg", &rtcdrv->rtc_base);
304 if (err) {
305 dev_err(&pdev->dev, "unable to find base address of rtc node in dtb\n");
306 return err;
307 }
308
309 platform_set_drvdata(pdev, rtcdrv);
310
311 /* Register rtc alarm as a wakeup source */
312 device_init_wakeup(&pdev->dev, 1);
313
314 rtcdrv->regmap = devm_regmap_init_iobg(&pdev->dev,
315 &sysrtc_regmap_config);
316 if (IS_ERR(rtcdrv->regmap)) {
317 err = PTR_ERR(rtcdrv->regmap);
318 dev_err(&pdev->dev, "Failed to allocate register map: %d\n",
319 err);
320 return err;
321 }
322
323 /*
324 * Set SYS_RTC counter in RTC_HZ HZ Units
325 * We are using 32K RTC crystal (32768 / RTC_HZ / 2) -1
326 * If 16HZ, therefore RTC_DIV = 1023;
327 */
328 rtc_div = ((32768 / RTC_HZ) / 2) - 1;
329 sirfsoc_rtc_writel(rtcdrv, RTC_DIV, rtc_div);
330
331 /* 0x3 -> RTC_CLK */
332 sirfsoc_rtc_writel(rtcdrv, RTC_CLOCK_SWITCH, SIRFSOC_RTC_CLK);
333
334 /* reset SYS RTC ALARM0 */
335 sirfsoc_rtc_writel(rtcdrv, RTC_ALARM0, 0x0);
336
337 /* reset SYS RTC ALARM1 */
338 sirfsoc_rtc_writel(rtcdrv, RTC_ALARM1, 0x0);
339
340 /* Restore RTC Overflow From Register After Command Reboot */
341 rtcdrv->overflow_rtc =
342 sirfsoc_rtc_readl(rtcdrv, RTC_SW_VALUE);
343
344 rtcdrv->rtc = devm_rtc_allocate_device(&pdev->dev);
345 if (IS_ERR(rtcdrv->rtc))
346 return PTR_ERR(rtcdrv->rtc);
347
348 rtcdrv->rtc->ops = &sirfsoc_rtc_ops;
349 rtcdrv->rtc->range_max = (1ULL << 60) - 1;
350
351 rtcdrv->irq = platform_get_irq(pdev, 0);
352 err = devm_request_irq(&pdev->dev, rtcdrv->irq, sirfsoc_rtc_irq_handler,
353 IRQF_SHARED, pdev->name, rtcdrv);
354 if (err) {
355 dev_err(&pdev->dev, "Unable to register for the SiRF SOC RTC IRQ\n");
356 return err;
357 }
358
359 return rtc_register_device(rtcdrv->rtc);
360}
361
362#ifdef CONFIG_PM_SLEEP
363static int sirfsoc_rtc_suspend(struct device *dev)
364{
365 struct sirfsoc_rtc_drv *rtcdrv = dev_get_drvdata(dev);
366 rtcdrv->overflow_rtc =
367 sirfsoc_rtc_readl(rtcdrv, RTC_SW_VALUE);
368
369 rtcdrv->saved_counter =
370 sirfsoc_rtc_readl(rtcdrv, RTC_CN);
371 rtcdrv->saved_overflow_rtc = rtcdrv->overflow_rtc;
372 if (device_may_wakeup(dev) && !enable_irq_wake(rtcdrv->irq))
373 rtcdrv->irq_wake = 1;
374
375 return 0;
376}
377
378static int sirfsoc_rtc_resume(struct device *dev)
379{
380 u32 tmp;
381 struct sirfsoc_rtc_drv *rtcdrv = dev_get_drvdata(dev);
382
383 /*
384 * if resume from snapshot and the rtc power is lost,
385 * restroe the rtc settings
386 */
387 if (SIRFSOC_RTC_CLK != sirfsoc_rtc_readl(rtcdrv, RTC_CLOCK_SWITCH)) {
388 u32 rtc_div;
389 /* 0x3 -> RTC_CLK */
390 sirfsoc_rtc_writel(rtcdrv, RTC_CLOCK_SWITCH, SIRFSOC_RTC_CLK);
391 /*
392 * Set SYS_RTC counter in RTC_HZ HZ Units
393 * We are using 32K RTC crystal (32768 / RTC_HZ / 2) -1
394 * If 16HZ, therefore RTC_DIV = 1023;
395 */
396 rtc_div = ((32768 / RTC_HZ) / 2) - 1;
397
398 sirfsoc_rtc_writel(rtcdrv, RTC_DIV, rtc_div);
399
400 /* reset SYS RTC ALARM0 */
401 sirfsoc_rtc_writel(rtcdrv, RTC_ALARM0, 0x0);
402
403 /* reset SYS RTC ALARM1 */
404 sirfsoc_rtc_writel(rtcdrv, RTC_ALARM1, 0x0);
405 }
406 rtcdrv->overflow_rtc = rtcdrv->saved_overflow_rtc;
407
408 /*
409 * if current counter is small than previous,
410 * it means overflow in sleep
411 */
412 tmp = sirfsoc_rtc_readl(rtcdrv, RTC_CN);
413 if (tmp <= rtcdrv->saved_counter)
414 rtcdrv->overflow_rtc++;
415 /*
416 *PWRC Value Be Changed When Suspend, Restore Overflow
417 * In Memory To Register
418 */
419 sirfsoc_rtc_writel(rtcdrv, RTC_SW_VALUE, rtcdrv->overflow_rtc);
420
421 if (device_may_wakeup(dev) && rtcdrv->irq_wake) {
422 disable_irq_wake(rtcdrv->irq);
423 rtcdrv->irq_wake = 0;
424 }
425
426 return 0;
427}
428#endif
429
430static SIMPLE_DEV_PM_OPS(sirfsoc_rtc_pm_ops,
431 sirfsoc_rtc_suspend, sirfsoc_rtc_resume);
432
433static struct platform_driver sirfsoc_rtc_driver = {
434 .driver = {
435 .name = "sirfsoc-rtc",
436 .pm = &sirfsoc_rtc_pm_ops,
437 .of_match_table = sirfsoc_rtc_of_match,
438 },
439 .probe = sirfsoc_rtc_probe,
440};
441module_platform_driver(sirfsoc_rtc_driver);
442
443MODULE_DESCRIPTION("SiRF SoC rtc driver");
444MODULE_AUTHOR("Xianglong Du <Xianglong.Du@csr.com>");
445MODULE_LICENSE("GPL v2");
446MODULE_ALIAS("platform:sirfsoc-rtc");