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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Intel Core SoC Power Management Controller Header File
4 *
5 * Copyright (c) 2016, Intel Corporation.
6 * All Rights Reserved.
7 *
8 * Authors: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
9 * Vishwanath Somayaji <vishwanath.somayaji@intel.com>
10 */
11
12#ifndef PMC_CORE_H
13#define PMC_CORE_H
14
15#include <linux/bits.h>
16
17#define PMC_BASE_ADDR_DEFAULT 0xFE000000
18
19/* Sunrise Point Power Management Controller PCI Device ID */
20#define SPT_PMC_PCI_DEVICE_ID 0x9d21
21#define SPT_PMC_BASE_ADDR_OFFSET 0x48
22#define SPT_PMC_SLP_S0_RES_COUNTER_OFFSET 0x13c
23#define SPT_PMC_PM_CFG_OFFSET 0x18
24#define SPT_PMC_PM_STS_OFFSET 0x1c
25#define SPT_PMC_MTPMC_OFFSET 0x20
26#define SPT_PMC_MFPMC_OFFSET 0x38
27#define SPT_PMC_LTR_IGNORE_OFFSET 0x30C
28#define SPT_PMC_VRIC1_OFFSET 0x31c
29#define SPT_PMC_MPHY_CORE_STS_0 0x1143
30#define SPT_PMC_MPHY_CORE_STS_1 0x1142
31#define SPT_PMC_MPHY_COM_STS_0 0x1155
32#define SPT_PMC_MMIO_REG_LEN 0x1000
33#define SPT_PMC_SLP_S0_RES_COUNTER_STEP 0x64
34#define PMC_BASE_ADDR_MASK ~(SPT_PMC_MMIO_REG_LEN - 1)
35#define MTPMC_MASK 0xffff0000
36#define PPFEAR_MAX_NUM_ENTRIES 12
37#define SPT_PPFEAR_NUM_ENTRIES 5
38#define SPT_PMC_READ_DISABLE_BIT 0x16
39#define SPT_PMC_MSG_FULL_STS_BIT 0x18
40#define NUM_RETRIES 100
41#define SPT_NUM_IP_IGN_ALLOWED 17
42
43#define SPT_PMC_LTR_CUR_PLT 0x350
44#define SPT_PMC_LTR_CUR_ASLT 0x354
45#define SPT_PMC_LTR_SPA 0x360
46#define SPT_PMC_LTR_SPB 0x364
47#define SPT_PMC_LTR_SATA 0x368
48#define SPT_PMC_LTR_GBE 0x36C
49#define SPT_PMC_LTR_XHCI 0x370
50#define SPT_PMC_LTR_RESERVED 0x374
51#define SPT_PMC_LTR_ME 0x378
52#define SPT_PMC_LTR_EVA 0x37C
53#define SPT_PMC_LTR_SPC 0x380
54#define SPT_PMC_LTR_AZ 0x384
55#define SPT_PMC_LTR_LPSS 0x38C
56#define SPT_PMC_LTR_CAM 0x390
57#define SPT_PMC_LTR_SPD 0x394
58#define SPT_PMC_LTR_SPE 0x398
59#define SPT_PMC_LTR_ESPI 0x39C
60#define SPT_PMC_LTR_SCC 0x3A0
61#define SPT_PMC_LTR_ISH 0x3A4
62
63/* Sunrise Point: PGD PFET Enable Ack Status Registers */
64enum ppfear_regs {
65 SPT_PMC_XRAM_PPFEAR0A = 0x590,
66 SPT_PMC_XRAM_PPFEAR0B,
67 SPT_PMC_XRAM_PPFEAR0C,
68 SPT_PMC_XRAM_PPFEAR0D,
69 SPT_PMC_XRAM_PPFEAR1A,
70};
71
72#define SPT_PMC_BIT_PMC BIT(0)
73#define SPT_PMC_BIT_OPI BIT(1)
74#define SPT_PMC_BIT_SPI BIT(2)
75#define SPT_PMC_BIT_XHCI BIT(3)
76#define SPT_PMC_BIT_SPA BIT(4)
77#define SPT_PMC_BIT_SPB BIT(5)
78#define SPT_PMC_BIT_SPC BIT(6)
79#define SPT_PMC_BIT_GBE BIT(7)
80
81#define SPT_PMC_BIT_SATA BIT(0)
82#define SPT_PMC_BIT_HDA_PGD0 BIT(1)
83#define SPT_PMC_BIT_HDA_PGD1 BIT(2)
84#define SPT_PMC_BIT_HDA_PGD2 BIT(3)
85#define SPT_PMC_BIT_HDA_PGD3 BIT(4)
86#define SPT_PMC_BIT_RSVD_0B BIT(5)
87#define SPT_PMC_BIT_LPSS BIT(6)
88#define SPT_PMC_BIT_LPC BIT(7)
89
90#define SPT_PMC_BIT_SMB BIT(0)
91#define SPT_PMC_BIT_ISH BIT(1)
92#define SPT_PMC_BIT_P2SB BIT(2)
93#define SPT_PMC_BIT_DFX BIT(3)
94#define SPT_PMC_BIT_SCC BIT(4)
95#define SPT_PMC_BIT_RSVD_0C BIT(5)
96#define SPT_PMC_BIT_FUSE BIT(6)
97#define SPT_PMC_BIT_CAMREA BIT(7)
98
99#define SPT_PMC_BIT_RSVD_0D BIT(0)
100#define SPT_PMC_BIT_USB3_OTG BIT(1)
101#define SPT_PMC_BIT_EXI BIT(2)
102#define SPT_PMC_BIT_CSE BIT(3)
103#define SPT_PMC_BIT_CSME_KVM BIT(4)
104#define SPT_PMC_BIT_CSME_PMT BIT(5)
105#define SPT_PMC_BIT_CSME_CLINK BIT(6)
106#define SPT_PMC_BIT_CSME_PTIO BIT(7)
107
108#define SPT_PMC_BIT_CSME_USBR BIT(0)
109#define SPT_PMC_BIT_CSME_SUSRAM BIT(1)
110#define SPT_PMC_BIT_CSME_SMT BIT(2)
111#define SPT_PMC_BIT_RSVD_1A BIT(3)
112#define SPT_PMC_BIT_CSME_SMS2 BIT(4)
113#define SPT_PMC_BIT_CSME_SMS1 BIT(5)
114#define SPT_PMC_BIT_CSME_RTC BIT(6)
115#define SPT_PMC_BIT_CSME_PSF BIT(7)
116
117#define SPT_PMC_BIT_MPHY_LANE0 BIT(0)
118#define SPT_PMC_BIT_MPHY_LANE1 BIT(1)
119#define SPT_PMC_BIT_MPHY_LANE2 BIT(2)
120#define SPT_PMC_BIT_MPHY_LANE3 BIT(3)
121#define SPT_PMC_BIT_MPHY_LANE4 BIT(4)
122#define SPT_PMC_BIT_MPHY_LANE5 BIT(5)
123#define SPT_PMC_BIT_MPHY_LANE6 BIT(6)
124#define SPT_PMC_BIT_MPHY_LANE7 BIT(7)
125
126#define SPT_PMC_BIT_MPHY_LANE8 BIT(0)
127#define SPT_PMC_BIT_MPHY_LANE9 BIT(1)
128#define SPT_PMC_BIT_MPHY_LANE10 BIT(2)
129#define SPT_PMC_BIT_MPHY_LANE11 BIT(3)
130#define SPT_PMC_BIT_MPHY_LANE12 BIT(4)
131#define SPT_PMC_BIT_MPHY_LANE13 BIT(5)
132#define SPT_PMC_BIT_MPHY_LANE14 BIT(6)
133#define SPT_PMC_BIT_MPHY_LANE15 BIT(7)
134
135#define SPT_PMC_BIT_MPHY_CMN_LANE0 BIT(0)
136#define SPT_PMC_BIT_MPHY_CMN_LANE1 BIT(1)
137#define SPT_PMC_BIT_MPHY_CMN_LANE2 BIT(2)
138#define SPT_PMC_BIT_MPHY_CMN_LANE3 BIT(3)
139
140#define SPT_PMC_VRIC1_SLPS0LVEN BIT(13)
141#define SPT_PMC_VRIC1_XTALSDQDIS BIT(22)
142
143/* Cannonlake Power Management Controller register offsets */
144#define CNP_PMC_SLPS0_DBG_OFFSET 0x10B4
145#define CNP_PMC_PM_CFG_OFFSET 0x1818
146#define CNP_PMC_SLP_S0_RES_COUNTER_OFFSET 0x193C
147#define CNP_PMC_LTR_IGNORE_OFFSET 0x1B0C
148/* Cannonlake: PGD PFET Enable Ack Status Register(s) start */
149#define CNP_PMC_HOST_PPFEAR0A 0x1D90
150
151#define CNP_PMC_LATCH_SLPS0_EVENTS BIT(31)
152
153#define CNP_PMC_MMIO_REG_LEN 0x2000
154#define CNP_PPFEAR_NUM_ENTRIES 8
155#define CNP_PMC_READ_DISABLE_BIT 22
156#define CNP_NUM_IP_IGN_ALLOWED 19
157#define CNP_PMC_LTR_CUR_PLT 0x1B50
158#define CNP_PMC_LTR_CUR_ASLT 0x1B54
159#define CNP_PMC_LTR_SPA 0x1B60
160#define CNP_PMC_LTR_SPB 0x1B64
161#define CNP_PMC_LTR_SATA 0x1B68
162#define CNP_PMC_LTR_GBE 0x1B6C
163#define CNP_PMC_LTR_XHCI 0x1B70
164#define CNP_PMC_LTR_RESERVED 0x1B74
165#define CNP_PMC_LTR_ME 0x1B78
166#define CNP_PMC_LTR_EVA 0x1B7C
167#define CNP_PMC_LTR_SPC 0x1B80
168#define CNP_PMC_LTR_AZ 0x1B84
169#define CNP_PMC_LTR_LPSS 0x1B8C
170#define CNP_PMC_LTR_CAM 0x1B90
171#define CNP_PMC_LTR_SPD 0x1B94
172#define CNP_PMC_LTR_SPE 0x1B98
173#define CNP_PMC_LTR_ESPI 0x1B9C
174#define CNP_PMC_LTR_SCC 0x1BA0
175#define CNP_PMC_LTR_ISH 0x1BA4
176#define CNP_PMC_LTR_CNV 0x1BF0
177#define CNP_PMC_LTR_EMMC 0x1BF4
178#define CNP_PMC_LTR_UFSX2 0x1BF8
179
180#define LTR_DECODED_VAL GENMASK(9, 0)
181#define LTR_DECODED_SCALE GENMASK(12, 10)
182#define LTR_REQ_SNOOP BIT(15)
183#define LTR_REQ_NONSNOOP BIT(31)
184
185#define ICL_PPFEAR_NUM_ENTRIES 9
186#define ICL_NUM_IP_IGN_ALLOWED 20
187#define ICL_PMC_LTR_WIGIG 0x1BFC
188
189#define TGL_NUM_IP_IGN_ALLOWED 22
190
191/*
192 * Tigerlake Power Management Controller register offsets
193 */
194#define TGL_LPM_EN_OFFSET 0x1C78
195#define TGL_LPM_RESIDENCY_OFFSET 0x1C80
196
197/* Tigerlake Low Power Mode debug registers */
198#define TGL_LPM_STATUS_OFFSET 0x1C3C
199#define TGL_LPM_LIVE_STATUS_OFFSET 0x1C5C
200
201const char *tgl_lpm_modes[] = {
202 "S0i2.0",
203 "S0i2.1",
204 "S0i2.2",
205 "S0i3.0",
206 "S0i3.1",
207 "S0i3.2",
208 "S0i3.3",
209 "S0i3.4",
210 NULL
211};
212
213struct pmc_bit_map {
214 const char *name;
215 u32 bit_mask;
216};
217
218/**
219 * struct pmc_reg_map - Structure used to define parameter unique to a
220 PCH family
221 * @pfear_sts: Maps name of IP block to PPFEAR* bit
222 * @mphy_sts: Maps name of MPHY lane to MPHY status lane status bit
223 * @pll_sts: Maps name of PLL to corresponding bit status
224 * @slps0_dbg_maps: Array of SLP_S0_DBG* registers containing debug info
225 * @ltr_show_sts: Maps PCH IP Names to their MMIO register offsets
226 * @slp_s0_offset: PWRMBASE offset to read SLP_S0 residency
227 * @ltr_ignore_offset: PWRMBASE offset to read/write LTR ignore bit
228 * @regmap_length: Length of memory to map from PWRMBASE address to access
229 * @ppfear0_offset: PWRMBASE offset to to read PPFEAR*
230 * @ppfear_buckets: Number of 8 bits blocks to read all IP blocks from
231 * PPFEAR
232 * @pm_cfg_offset: PWRMBASE offset to PM_CFG register
233 * @pm_read_disable_bit: Bit index to read PMC_READ_DISABLE
234 * @slps0_dbg_offset: PWRMBASE offset to SLP_S0_DEBUG_REG*
235 *
236 * Each PCH has unique set of register offsets and bit indexes. This structure
237 * captures them to have a common implementation.
238 */
239struct pmc_reg_map {
240 const struct pmc_bit_map **pfear_sts;
241 const struct pmc_bit_map *mphy_sts;
242 const struct pmc_bit_map *pll_sts;
243 const struct pmc_bit_map **slps0_dbg_maps;
244 const struct pmc_bit_map *ltr_show_sts;
245 const struct pmc_bit_map *msr_sts;
246 const struct pmc_bit_map **lpm_sts;
247 const u32 slp_s0_offset;
248 const u32 ltr_ignore_offset;
249 const int regmap_length;
250 const u32 ppfear0_offset;
251 const int ppfear_buckets;
252 const u32 pm_cfg_offset;
253 const int pm_read_disable_bit;
254 const u32 slps0_dbg_offset;
255 const u32 ltr_ignore_max;
256 const u32 pm_vric1_offset;
257 /* Low Power Mode registers */
258 const char **lpm_modes;
259 const u32 lpm_en_offset;
260 const u32 lpm_residency_offset;
261 const u32 lpm_status_offset;
262 const u32 lpm_live_status_offset;
263};
264
265/**
266 * struct pmc_dev - pmc device structure
267 * @base_addr: contains pmc base address
268 * @regbase: pointer to io-remapped memory location
269 * @map: pointer to pmc_reg_map struct that contains platform
270 * specific attributes
271 * @dbgfs_dir: path to debugfs interface
272 * @pmc_xram_read_bit: flag to indicate whether PMC XRAM shadow registers
273 * used to read MPHY PG and PLL status are available
274 * @mutex_lock: mutex to complete one transcation
275 * @check_counters: On resume, check if counters are getting incremented
276 * @pc10_counter: PC10 residency counter
277 * @s0ix_counter: S0ix residency (step adjusted)
278 *
279 * pmc_dev contains info about power management controller device.
280 */
281struct pmc_dev {
282 u32 base_addr;
283 void __iomem *regbase;
284 const struct pmc_reg_map *map;
285 struct dentry *dbgfs_dir;
286 int pmc_xram_read_bit;
287 struct mutex lock; /* generic mutex lock for PMC Core */
288
289 bool check_counters; /* Check for counter increments on resume */
290 u64 pc10_counter;
291 u64 s0ix_counter;
292};
293
294#endif /* PMC_CORE_H */