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1/*
2 * Atmel MultiMedia Card Interface driver
3 *
4 * Copyright (C) 2004-2008 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/blkdev.h>
11#include <linux/clk.h>
12#include <linux/debugfs.h>
13#include <linux/device.h>
14#include <linux/dmaengine.h>
15#include <linux/dma-mapping.h>
16#include <linux/err.h>
17#include <linux/gpio.h>
18#include <linux/init.h>
19#include <linux/interrupt.h>
20#include <linux/io.h>
21#include <linux/ioport.h>
22#include <linux/module.h>
23#include <linux/of.h>
24#include <linux/of_device.h>
25#include <linux/of_gpio.h>
26#include <linux/platform_device.h>
27#include <linux/scatterlist.h>
28#include <linux/seq_file.h>
29#include <linux/slab.h>
30#include <linux/stat.h>
31#include <linux/types.h>
32
33#include <linux/mmc/host.h>
34#include <linux/mmc/sdio.h>
35
36#include <linux/atmel-mci.h>
37#include <linux/atmel_pdc.h>
38#include <linux/pm.h>
39#include <linux/pm_runtime.h>
40#include <linux/pinctrl/consumer.h>
41
42#include <asm/cacheflush.h>
43#include <asm/io.h>
44#include <asm/unaligned.h>
45
46/*
47 * Superset of MCI IP registers integrated in Atmel AVR32 and AT91 Processors
48 * Registers and bitfields marked with [2] are only available in MCI2
49 */
50
51/* MCI Register Definitions */
52#define ATMCI_CR 0x0000 /* Control */
53#define ATMCI_CR_MCIEN BIT(0) /* MCI Enable */
54#define ATMCI_CR_MCIDIS BIT(1) /* MCI Disable */
55#define ATMCI_CR_PWSEN BIT(2) /* Power Save Enable */
56#define ATMCI_CR_PWSDIS BIT(3) /* Power Save Disable */
57#define ATMCI_CR_SWRST BIT(7) /* Software Reset */
58#define ATMCI_MR 0x0004 /* Mode */
59#define ATMCI_MR_CLKDIV(x) ((x) << 0) /* Clock Divider */
60#define ATMCI_MR_PWSDIV(x) ((x) << 8) /* Power Saving Divider */
61#define ATMCI_MR_RDPROOF BIT(11) /* Read Proof */
62#define ATMCI_MR_WRPROOF BIT(12) /* Write Proof */
63#define ATMCI_MR_PDCFBYTE BIT(13) /* Force Byte Transfer */
64#define ATMCI_MR_PDCPADV BIT(14) /* Padding Value */
65#define ATMCI_MR_PDCMODE BIT(15) /* PDC-oriented Mode */
66#define ATMCI_MR_CLKODD(x) ((x) << 16) /* LSB of Clock Divider */
67#define ATMCI_DTOR 0x0008 /* Data Timeout */
68#define ATMCI_DTOCYC(x) ((x) << 0) /* Data Timeout Cycles */
69#define ATMCI_DTOMUL(x) ((x) << 4) /* Data Timeout Multiplier */
70#define ATMCI_SDCR 0x000c /* SD Card / SDIO */
71#define ATMCI_SDCSEL_SLOT_A (0 << 0) /* Select SD slot A */
72#define ATMCI_SDCSEL_SLOT_B (1 << 0) /* Select SD slot A */
73#define ATMCI_SDCSEL_MASK (3 << 0)
74#define ATMCI_SDCBUS_1BIT (0 << 6) /* 1-bit data bus */
75#define ATMCI_SDCBUS_4BIT (2 << 6) /* 4-bit data bus */
76#define ATMCI_SDCBUS_8BIT (3 << 6) /* 8-bit data bus[2] */
77#define ATMCI_SDCBUS_MASK (3 << 6)
78#define ATMCI_ARGR 0x0010 /* Command Argument */
79#define ATMCI_CMDR 0x0014 /* Command */
80#define ATMCI_CMDR_CMDNB(x) ((x) << 0) /* Command Opcode */
81#define ATMCI_CMDR_RSPTYP_NONE (0 << 6) /* No response */
82#define ATMCI_CMDR_RSPTYP_48BIT (1 << 6) /* 48-bit response */
83#define ATMCI_CMDR_RSPTYP_136BIT (2 << 6) /* 136-bit response */
84#define ATMCI_CMDR_SPCMD_INIT (1 << 8) /* Initialization command */
85#define ATMCI_CMDR_SPCMD_SYNC (2 << 8) /* Synchronized command */
86#define ATMCI_CMDR_SPCMD_INT (4 << 8) /* Interrupt command */
87#define ATMCI_CMDR_SPCMD_INTRESP (5 << 8) /* Interrupt response */
88#define ATMCI_CMDR_OPDCMD (1 << 11) /* Open Drain */
89#define ATMCI_CMDR_MAXLAT_5CYC (0 << 12) /* Max latency 5 cycles */
90#define ATMCI_CMDR_MAXLAT_64CYC (1 << 12) /* Max latency 64 cycles */
91#define ATMCI_CMDR_START_XFER (1 << 16) /* Start data transfer */
92#define ATMCI_CMDR_STOP_XFER (2 << 16) /* Stop data transfer */
93#define ATMCI_CMDR_TRDIR_WRITE (0 << 18) /* Write data */
94#define ATMCI_CMDR_TRDIR_READ (1 << 18) /* Read data */
95#define ATMCI_CMDR_BLOCK (0 << 19) /* Single-block transfer */
96#define ATMCI_CMDR_MULTI_BLOCK (1 << 19) /* Multi-block transfer */
97#define ATMCI_CMDR_STREAM (2 << 19) /* MMC Stream transfer */
98#define ATMCI_CMDR_SDIO_BYTE (4 << 19) /* SDIO Byte transfer */
99#define ATMCI_CMDR_SDIO_BLOCK (5 << 19) /* SDIO Block transfer */
100#define ATMCI_CMDR_SDIO_SUSPEND (1 << 24) /* SDIO Suspend Command */
101#define ATMCI_CMDR_SDIO_RESUME (2 << 24) /* SDIO Resume Command */
102#define ATMCI_BLKR 0x0018 /* Block */
103#define ATMCI_BCNT(x) ((x) << 0) /* Data Block Count */
104#define ATMCI_BLKLEN(x) ((x) << 16) /* Data Block Length */
105#define ATMCI_CSTOR 0x001c /* Completion Signal Timeout[2] */
106#define ATMCI_CSTOCYC(x) ((x) << 0) /* CST cycles */
107#define ATMCI_CSTOMUL(x) ((x) << 4) /* CST multiplier */
108#define ATMCI_RSPR 0x0020 /* Response 0 */
109#define ATMCI_RSPR1 0x0024 /* Response 1 */
110#define ATMCI_RSPR2 0x0028 /* Response 2 */
111#define ATMCI_RSPR3 0x002c /* Response 3 */
112#define ATMCI_RDR 0x0030 /* Receive Data */
113#define ATMCI_TDR 0x0034 /* Transmit Data */
114#define ATMCI_SR 0x0040 /* Status */
115#define ATMCI_IER 0x0044 /* Interrupt Enable */
116#define ATMCI_IDR 0x0048 /* Interrupt Disable */
117#define ATMCI_IMR 0x004c /* Interrupt Mask */
118#define ATMCI_CMDRDY BIT(0) /* Command Ready */
119#define ATMCI_RXRDY BIT(1) /* Receiver Ready */
120#define ATMCI_TXRDY BIT(2) /* Transmitter Ready */
121#define ATMCI_BLKE BIT(3) /* Data Block Ended */
122#define ATMCI_DTIP BIT(4) /* Data Transfer In Progress */
123#define ATMCI_NOTBUSY BIT(5) /* Data Not Busy */
124#define ATMCI_ENDRX BIT(6) /* End of RX Buffer */
125#define ATMCI_ENDTX BIT(7) /* End of TX Buffer */
126#define ATMCI_SDIOIRQA BIT(8) /* SDIO IRQ in slot A */
127#define ATMCI_SDIOIRQB BIT(9) /* SDIO IRQ in slot B */
128#define ATMCI_SDIOWAIT BIT(12) /* SDIO Read Wait Operation Status */
129#define ATMCI_CSRCV BIT(13) /* CE-ATA Completion Signal Received */
130#define ATMCI_RXBUFF BIT(14) /* RX Buffer Full */
131#define ATMCI_TXBUFE BIT(15) /* TX Buffer Empty */
132#define ATMCI_RINDE BIT(16) /* Response Index Error */
133#define ATMCI_RDIRE BIT(17) /* Response Direction Error */
134#define ATMCI_RCRCE BIT(18) /* Response CRC Error */
135#define ATMCI_RENDE BIT(19) /* Response End Bit Error */
136#define ATMCI_RTOE BIT(20) /* Response Time-Out Error */
137#define ATMCI_DCRCE BIT(21) /* Data CRC Error */
138#define ATMCI_DTOE BIT(22) /* Data Time-Out Error */
139#define ATMCI_CSTOE BIT(23) /* Completion Signal Time-out Error */
140#define ATMCI_BLKOVRE BIT(24) /* DMA Block Overrun Error */
141#define ATMCI_DMADONE BIT(25) /* DMA Transfer Done */
142#define ATMCI_FIFOEMPTY BIT(26) /* FIFO Empty Flag */
143#define ATMCI_XFRDONE BIT(27) /* Transfer Done Flag */
144#define ATMCI_ACKRCV BIT(28) /* Boot Operation Acknowledge Received */
145#define ATMCI_ACKRCVE BIT(29) /* Boot Operation Acknowledge Error */
146#define ATMCI_OVRE BIT(30) /* RX Overrun Error */
147#define ATMCI_UNRE BIT(31) /* TX Underrun Error */
148#define ATMCI_DMA 0x0050 /* DMA Configuration[2] */
149#define ATMCI_DMA_OFFSET(x) ((x) << 0) /* DMA Write Buffer Offset */
150#define ATMCI_DMA_CHKSIZE(x) ((x) << 4) /* DMA Channel Read and Write Chunk Size */
151#define ATMCI_DMAEN BIT(8) /* DMA Hardware Handshaking Enable */
152#define ATMCI_CFG 0x0054 /* Configuration[2] */
153#define ATMCI_CFG_FIFOMODE_1DATA BIT(0) /* MCI Internal FIFO control mode */
154#define ATMCI_CFG_FERRCTRL_COR BIT(4) /* Flow Error flag reset control mode */
155#define ATMCI_CFG_HSMODE BIT(8) /* High Speed Mode */
156#define ATMCI_CFG_LSYNC BIT(12) /* Synchronize on the last block */
157#define ATMCI_WPMR 0x00e4 /* Write Protection Mode[2] */
158#define ATMCI_WP_EN BIT(0) /* WP Enable */
159#define ATMCI_WP_KEY (0x4d4349 << 8) /* WP Key */
160#define ATMCI_WPSR 0x00e8 /* Write Protection Status[2] */
161#define ATMCI_GET_WP_VS(x) ((x) & 0x0f)
162#define ATMCI_GET_WP_VSRC(x) (((x) >> 8) & 0xffff)
163#define ATMCI_VERSION 0x00FC /* Version */
164#define ATMCI_FIFO_APERTURE 0x0200 /* FIFO Aperture[2] */
165
166/* This is not including the FIFO Aperture on MCI2 */
167#define ATMCI_REGS_SIZE 0x100
168
169/* Register access macros */
170#define atmci_readl(port, reg) \
171 __raw_readl((port)->regs + reg)
172#define atmci_writel(port, reg, value) \
173 __raw_writel((value), (port)->regs + reg)
174
175/* On AVR chips the Peripheral DMA Controller is not connected to MCI. */
176#ifdef CONFIG_AVR32
177# define ATMCI_PDC_CONNECTED 0
178#else
179# define ATMCI_PDC_CONNECTED 1
180#endif
181
182#define AUTOSUSPEND_DELAY 50
183
184#define ATMCI_DATA_ERROR_FLAGS (ATMCI_DCRCE | ATMCI_DTOE | ATMCI_OVRE | ATMCI_UNRE)
185#define ATMCI_DMA_THRESHOLD 16
186
187enum {
188 EVENT_CMD_RDY = 0,
189 EVENT_XFER_COMPLETE,
190 EVENT_NOTBUSY,
191 EVENT_DATA_ERROR,
192};
193
194enum atmel_mci_state {
195 STATE_IDLE = 0,
196 STATE_SENDING_CMD,
197 STATE_DATA_XFER,
198 STATE_WAITING_NOTBUSY,
199 STATE_SENDING_STOP,
200 STATE_END_REQUEST,
201};
202
203enum atmci_xfer_dir {
204 XFER_RECEIVE = 0,
205 XFER_TRANSMIT,
206};
207
208enum atmci_pdc_buf {
209 PDC_FIRST_BUF = 0,
210 PDC_SECOND_BUF,
211};
212
213struct atmel_mci_caps {
214 bool has_dma_conf_reg;
215 bool has_pdc;
216 bool has_cfg_reg;
217 bool has_cstor_reg;
218 bool has_highspeed;
219 bool has_rwproof;
220 bool has_odd_clk_div;
221 bool has_bad_data_ordering;
222 bool need_reset_after_xfer;
223 bool need_blksz_mul_4;
224 bool need_notbusy_for_read_ops;
225};
226
227struct atmel_mci_dma {
228 struct dma_chan *chan;
229 struct dma_async_tx_descriptor *data_desc;
230};
231
232/**
233 * struct atmel_mci - MMC controller state shared between all slots
234 * @lock: Spinlock protecting the queue and associated data.
235 * @regs: Pointer to MMIO registers.
236 * @sg: Scatterlist entry currently being processed by PIO or PDC code.
237 * @pio_offset: Offset into the current scatterlist entry.
238 * @buffer: Buffer used if we don't have the r/w proof capability. We
239 * don't have the time to switch pdc buffers so we have to use only
240 * one buffer for the full transaction.
241 * @buf_size: size of the buffer.
242 * @phys_buf_addr: buffer address needed for pdc.
243 * @cur_slot: The slot which is currently using the controller.
244 * @mrq: The request currently being processed on @cur_slot,
245 * or NULL if the controller is idle.
246 * @cmd: The command currently being sent to the card, or NULL.
247 * @data: The data currently being transferred, or NULL if no data
248 * transfer is in progress.
249 * @data_size: just data->blocks * data->blksz.
250 * @dma: DMA client state.
251 * @data_chan: DMA channel being used for the current data transfer.
252 * @cmd_status: Snapshot of SR taken upon completion of the current
253 * command. Only valid when EVENT_CMD_COMPLETE is pending.
254 * @data_status: Snapshot of SR taken upon completion of the current
255 * data transfer. Only valid when EVENT_DATA_COMPLETE or
256 * EVENT_DATA_ERROR is pending.
257 * @stop_cmdr: Value to be loaded into CMDR when the stop command is
258 * to be sent.
259 * @tasklet: Tasklet running the request state machine.
260 * @pending_events: Bitmask of events flagged by the interrupt handler
261 * to be processed by the tasklet.
262 * @completed_events: Bitmask of events which the state machine has
263 * processed.
264 * @state: Tasklet state.
265 * @queue: List of slots waiting for access to the controller.
266 * @need_clock_update: Update the clock rate before the next request.
267 * @need_reset: Reset controller before next request.
268 * @timer: Timer to balance the data timeout error flag which cannot rise.
269 * @mode_reg: Value of the MR register.
270 * @cfg_reg: Value of the CFG register.
271 * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
272 * rate and timeout calculations.
273 * @mapbase: Physical address of the MMIO registers.
274 * @mck: The peripheral bus clock hooked up to the MMC controller.
275 * @pdev: Platform device associated with the MMC controller.
276 * @slot: Slots sharing this MMC controller.
277 * @caps: MCI capabilities depending on MCI version.
278 * @prepare_data: function to setup MCI before data transfer which
279 * depends on MCI capabilities.
280 * @submit_data: function to start data transfer which depends on MCI
281 * capabilities.
282 * @stop_transfer: function to stop data transfer which depends on MCI
283 * capabilities.
284 *
285 * Locking
286 * =======
287 *
288 * @lock is a softirq-safe spinlock protecting @queue as well as
289 * @cur_slot, @mrq and @state. These must always be updated
290 * at the same time while holding @lock.
291 *
292 * @lock also protects mode_reg and need_clock_update since these are
293 * used to synchronize mode register updates with the queue
294 * processing.
295 *
296 * The @mrq field of struct atmel_mci_slot is also protected by @lock,
297 * and must always be written at the same time as the slot is added to
298 * @queue.
299 *
300 * @pending_events and @completed_events are accessed using atomic bit
301 * operations, so they don't need any locking.
302 *
303 * None of the fields touched by the interrupt handler need any
304 * locking. However, ordering is important: Before EVENT_DATA_ERROR or
305 * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
306 * interrupts must be disabled and @data_status updated with a
307 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
308 * CMDRDY interrupt must be disabled and @cmd_status updated with a
309 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
310 * bytes_xfered field of @data must be written. This is ensured by
311 * using barriers.
312 */
313struct atmel_mci {
314 spinlock_t lock;
315 void __iomem *regs;
316
317 struct scatterlist *sg;
318 unsigned int sg_len;
319 unsigned int pio_offset;
320 unsigned int *buffer;
321 unsigned int buf_size;
322 dma_addr_t buf_phys_addr;
323
324 struct atmel_mci_slot *cur_slot;
325 struct mmc_request *mrq;
326 struct mmc_command *cmd;
327 struct mmc_data *data;
328 unsigned int data_size;
329
330 struct atmel_mci_dma dma;
331 struct dma_chan *data_chan;
332 struct dma_slave_config dma_conf;
333
334 u32 cmd_status;
335 u32 data_status;
336 u32 stop_cmdr;
337
338 struct tasklet_struct tasklet;
339 unsigned long pending_events;
340 unsigned long completed_events;
341 enum atmel_mci_state state;
342 struct list_head queue;
343
344 bool need_clock_update;
345 bool need_reset;
346 struct timer_list timer;
347 u32 mode_reg;
348 u32 cfg_reg;
349 unsigned long bus_hz;
350 unsigned long mapbase;
351 struct clk *mck;
352 struct platform_device *pdev;
353
354 struct atmel_mci_slot *slot[ATMCI_MAX_NR_SLOTS];
355
356 struct atmel_mci_caps caps;
357
358 u32 (*prepare_data)(struct atmel_mci *host, struct mmc_data *data);
359 void (*submit_data)(struct atmel_mci *host, struct mmc_data *data);
360 void (*stop_transfer)(struct atmel_mci *host);
361};
362
363/**
364 * struct atmel_mci_slot - MMC slot state
365 * @mmc: The mmc_host representing this slot.
366 * @host: The MMC controller this slot is using.
367 * @sdc_reg: Value of SDCR to be written before using this slot.
368 * @sdio_irq: SDIO irq mask for this slot.
369 * @mrq: mmc_request currently being processed or waiting to be
370 * processed, or NULL when the slot is idle.
371 * @queue_node: List node for placing this node in the @queue list of
372 * &struct atmel_mci.
373 * @clock: Clock rate configured by set_ios(). Protected by host->lock.
374 * @flags: Random state bits associated with the slot.
375 * @detect_pin: GPIO pin used for card detection, or negative if not
376 * available.
377 * @wp_pin: GPIO pin used for card write protect sending, or negative
378 * if not available.
379 * @detect_is_active_high: The state of the detect pin when it is active.
380 * @detect_timer: Timer used for debouncing @detect_pin interrupts.
381 */
382struct atmel_mci_slot {
383 struct mmc_host *mmc;
384 struct atmel_mci *host;
385
386 u32 sdc_reg;
387 u32 sdio_irq;
388
389 struct mmc_request *mrq;
390 struct list_head queue_node;
391
392 unsigned int clock;
393 unsigned long flags;
394#define ATMCI_CARD_PRESENT 0
395#define ATMCI_CARD_NEED_INIT 1
396#define ATMCI_SHUTDOWN 2
397
398 int detect_pin;
399 int wp_pin;
400 bool detect_is_active_high;
401
402 struct timer_list detect_timer;
403};
404
405#define atmci_test_and_clear_pending(host, event) \
406 test_and_clear_bit(event, &host->pending_events)
407#define atmci_set_completed(host, event) \
408 set_bit(event, &host->completed_events)
409#define atmci_set_pending(host, event) \
410 set_bit(event, &host->pending_events)
411
412/*
413 * The debugfs stuff below is mostly optimized away when
414 * CONFIG_DEBUG_FS is not set.
415 */
416static int atmci_req_show(struct seq_file *s, void *v)
417{
418 struct atmel_mci_slot *slot = s->private;
419 struct mmc_request *mrq;
420 struct mmc_command *cmd;
421 struct mmc_command *stop;
422 struct mmc_data *data;
423
424 /* Make sure we get a consistent snapshot */
425 spin_lock_bh(&slot->host->lock);
426 mrq = slot->mrq;
427
428 if (mrq) {
429 cmd = mrq->cmd;
430 data = mrq->data;
431 stop = mrq->stop;
432
433 if (cmd)
434 seq_printf(s,
435 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
436 cmd->opcode, cmd->arg, cmd->flags,
437 cmd->resp[0], cmd->resp[1], cmd->resp[2],
438 cmd->resp[3], cmd->error);
439 if (data)
440 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
441 data->bytes_xfered, data->blocks,
442 data->blksz, data->flags, data->error);
443 if (stop)
444 seq_printf(s,
445 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
446 stop->opcode, stop->arg, stop->flags,
447 stop->resp[0], stop->resp[1], stop->resp[2],
448 stop->resp[3], stop->error);
449 }
450
451 spin_unlock_bh(&slot->host->lock);
452
453 return 0;
454}
455
456static int atmci_req_open(struct inode *inode, struct file *file)
457{
458 return single_open(file, atmci_req_show, inode->i_private);
459}
460
461static const struct file_operations atmci_req_fops = {
462 .owner = THIS_MODULE,
463 .open = atmci_req_open,
464 .read = seq_read,
465 .llseek = seq_lseek,
466 .release = single_release,
467};
468
469static void atmci_show_status_reg(struct seq_file *s,
470 const char *regname, u32 value)
471{
472 static const char *sr_bit[] = {
473 [0] = "CMDRDY",
474 [1] = "RXRDY",
475 [2] = "TXRDY",
476 [3] = "BLKE",
477 [4] = "DTIP",
478 [5] = "NOTBUSY",
479 [6] = "ENDRX",
480 [7] = "ENDTX",
481 [8] = "SDIOIRQA",
482 [9] = "SDIOIRQB",
483 [12] = "SDIOWAIT",
484 [14] = "RXBUFF",
485 [15] = "TXBUFE",
486 [16] = "RINDE",
487 [17] = "RDIRE",
488 [18] = "RCRCE",
489 [19] = "RENDE",
490 [20] = "RTOE",
491 [21] = "DCRCE",
492 [22] = "DTOE",
493 [23] = "CSTOE",
494 [24] = "BLKOVRE",
495 [25] = "DMADONE",
496 [26] = "FIFOEMPTY",
497 [27] = "XFRDONE",
498 [30] = "OVRE",
499 [31] = "UNRE",
500 };
501 unsigned int i;
502
503 seq_printf(s, "%s:\t0x%08x", regname, value);
504 for (i = 0; i < ARRAY_SIZE(sr_bit); i++) {
505 if (value & (1 << i)) {
506 if (sr_bit[i])
507 seq_printf(s, " %s", sr_bit[i]);
508 else
509 seq_puts(s, " UNKNOWN");
510 }
511 }
512 seq_putc(s, '\n');
513}
514
515static int atmci_regs_show(struct seq_file *s, void *v)
516{
517 struct atmel_mci *host = s->private;
518 u32 *buf;
519 int ret = 0;
520
521
522 buf = kmalloc(ATMCI_REGS_SIZE, GFP_KERNEL);
523 if (!buf)
524 return -ENOMEM;
525
526 pm_runtime_get_sync(&host->pdev->dev);
527
528 /*
529 * Grab a more or less consistent snapshot. Note that we're
530 * not disabling interrupts, so IMR and SR may not be
531 * consistent.
532 */
533 spin_lock_bh(&host->lock);
534 memcpy_fromio(buf, host->regs, ATMCI_REGS_SIZE);
535 spin_unlock_bh(&host->lock);
536
537 pm_runtime_mark_last_busy(&host->pdev->dev);
538 pm_runtime_put_autosuspend(&host->pdev->dev);
539
540 seq_printf(s, "MR:\t0x%08x%s%s ",
541 buf[ATMCI_MR / 4],
542 buf[ATMCI_MR / 4] & ATMCI_MR_RDPROOF ? " RDPROOF" : "",
543 buf[ATMCI_MR / 4] & ATMCI_MR_WRPROOF ? " WRPROOF" : "");
544 if (host->caps.has_odd_clk_div)
545 seq_printf(s, "{CLKDIV,CLKODD}=%u\n",
546 ((buf[ATMCI_MR / 4] & 0xff) << 1)
547 | ((buf[ATMCI_MR / 4] >> 16) & 1));
548 else
549 seq_printf(s, "CLKDIV=%u\n",
550 (buf[ATMCI_MR / 4] & 0xff));
551 seq_printf(s, "DTOR:\t0x%08x\n", buf[ATMCI_DTOR / 4]);
552 seq_printf(s, "SDCR:\t0x%08x\n", buf[ATMCI_SDCR / 4]);
553 seq_printf(s, "ARGR:\t0x%08x\n", buf[ATMCI_ARGR / 4]);
554 seq_printf(s, "BLKR:\t0x%08x BCNT=%u BLKLEN=%u\n",
555 buf[ATMCI_BLKR / 4],
556 buf[ATMCI_BLKR / 4] & 0xffff,
557 (buf[ATMCI_BLKR / 4] >> 16) & 0xffff);
558 if (host->caps.has_cstor_reg)
559 seq_printf(s, "CSTOR:\t0x%08x\n", buf[ATMCI_CSTOR / 4]);
560
561 /* Don't read RSPR and RDR; it will consume the data there */
562
563 atmci_show_status_reg(s, "SR", buf[ATMCI_SR / 4]);
564 atmci_show_status_reg(s, "IMR", buf[ATMCI_IMR / 4]);
565
566 if (host->caps.has_dma_conf_reg) {
567 u32 val;
568
569 val = buf[ATMCI_DMA / 4];
570 seq_printf(s, "DMA:\t0x%08x OFFSET=%u CHKSIZE=%u%s\n",
571 val, val & 3,
572 ((val >> 4) & 3) ?
573 1 << (((val >> 4) & 3) + 1) : 1,
574 val & ATMCI_DMAEN ? " DMAEN" : "");
575 }
576 if (host->caps.has_cfg_reg) {
577 u32 val;
578
579 val = buf[ATMCI_CFG / 4];
580 seq_printf(s, "CFG:\t0x%08x%s%s%s%s\n",
581 val,
582 val & ATMCI_CFG_FIFOMODE_1DATA ? " FIFOMODE_ONE_DATA" : "",
583 val & ATMCI_CFG_FERRCTRL_COR ? " FERRCTRL_CLEAR_ON_READ" : "",
584 val & ATMCI_CFG_HSMODE ? " HSMODE" : "",
585 val & ATMCI_CFG_LSYNC ? " LSYNC" : "");
586 }
587
588 kfree(buf);
589
590 return ret;
591}
592
593static int atmci_regs_open(struct inode *inode, struct file *file)
594{
595 return single_open(file, atmci_regs_show, inode->i_private);
596}
597
598static const struct file_operations atmci_regs_fops = {
599 .owner = THIS_MODULE,
600 .open = atmci_regs_open,
601 .read = seq_read,
602 .llseek = seq_lseek,
603 .release = single_release,
604};
605
606static void atmci_init_debugfs(struct atmel_mci_slot *slot)
607{
608 struct mmc_host *mmc = slot->mmc;
609 struct atmel_mci *host = slot->host;
610 struct dentry *root;
611 struct dentry *node;
612
613 root = mmc->debugfs_root;
614 if (!root)
615 return;
616
617 node = debugfs_create_file("regs", S_IRUSR, root, host,
618 &atmci_regs_fops);
619 if (IS_ERR(node))
620 return;
621 if (!node)
622 goto err;
623
624 node = debugfs_create_file("req", S_IRUSR, root, slot, &atmci_req_fops);
625 if (!node)
626 goto err;
627
628 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
629 if (!node)
630 goto err;
631
632 node = debugfs_create_x32("pending_events", S_IRUSR, root,
633 (u32 *)&host->pending_events);
634 if (!node)
635 goto err;
636
637 node = debugfs_create_x32("completed_events", S_IRUSR, root,
638 (u32 *)&host->completed_events);
639 if (!node)
640 goto err;
641
642 return;
643
644err:
645 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
646}
647
648#if defined(CONFIG_OF)
649static const struct of_device_id atmci_dt_ids[] = {
650 { .compatible = "atmel,hsmci" },
651 { /* sentinel */ }
652};
653
654MODULE_DEVICE_TABLE(of, atmci_dt_ids);
655
656static struct mci_platform_data*
657atmci_of_init(struct platform_device *pdev)
658{
659 struct device_node *np = pdev->dev.of_node;
660 struct device_node *cnp;
661 struct mci_platform_data *pdata;
662 u32 slot_id;
663
664 if (!np) {
665 dev_err(&pdev->dev, "device node not found\n");
666 return ERR_PTR(-EINVAL);
667 }
668
669 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
670 if (!pdata) {
671 dev_err(&pdev->dev, "could not allocate memory for pdata\n");
672 return ERR_PTR(-ENOMEM);
673 }
674
675 for_each_child_of_node(np, cnp) {
676 if (of_property_read_u32(cnp, "reg", &slot_id)) {
677 dev_warn(&pdev->dev, "reg property is missing for %s\n",
678 cnp->full_name);
679 continue;
680 }
681
682 if (slot_id >= ATMCI_MAX_NR_SLOTS) {
683 dev_warn(&pdev->dev, "can't have more than %d slots\n",
684 ATMCI_MAX_NR_SLOTS);
685 break;
686 }
687
688 if (of_property_read_u32(cnp, "bus-width",
689 &pdata->slot[slot_id].bus_width))
690 pdata->slot[slot_id].bus_width = 1;
691
692 pdata->slot[slot_id].detect_pin =
693 of_get_named_gpio(cnp, "cd-gpios", 0);
694
695 pdata->slot[slot_id].detect_is_active_high =
696 of_property_read_bool(cnp, "cd-inverted");
697
698 pdata->slot[slot_id].non_removable =
699 of_property_read_bool(cnp, "non-removable");
700
701 pdata->slot[slot_id].wp_pin =
702 of_get_named_gpio(cnp, "wp-gpios", 0);
703 }
704
705 return pdata;
706}
707#else /* CONFIG_OF */
708static inline struct mci_platform_data*
709atmci_of_init(struct platform_device *dev)
710{
711 return ERR_PTR(-EINVAL);
712}
713#endif
714
715static inline unsigned int atmci_get_version(struct atmel_mci *host)
716{
717 return atmci_readl(host, ATMCI_VERSION) & 0x00000fff;
718}
719
720/*
721 * Fix sconfig's burst size according to atmel MCI. We need to convert them as:
722 * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
723 * With version 0x600, we need to convert them as: 1 -> 0, 2 -> 1, 4 -> 2,
724 * 8 -> 3, 16 -> 4.
725 *
726 * This can be done by finding most significant bit set.
727 */
728static inline unsigned int atmci_convert_chksize(struct atmel_mci *host,
729 unsigned int maxburst)
730{
731 unsigned int version = atmci_get_version(host);
732 unsigned int offset = 2;
733
734 if (version >= 0x600)
735 offset = 1;
736
737 if (maxburst > 1)
738 return fls(maxburst) - offset;
739 else
740 return 0;
741}
742
743static void atmci_timeout_timer(unsigned long data)
744{
745 struct atmel_mci *host;
746
747 host = (struct atmel_mci *)data;
748
749 dev_dbg(&host->pdev->dev, "software timeout\n");
750
751 if (host->mrq->cmd->data) {
752 host->mrq->cmd->data->error = -ETIMEDOUT;
753 host->data = NULL;
754 /*
755 * With some SDIO modules, sometimes DMA transfer hangs. If
756 * stop_transfer() is not called then the DMA request is not
757 * removed, following ones are queued and never computed.
758 */
759 if (host->state == STATE_DATA_XFER)
760 host->stop_transfer(host);
761 } else {
762 host->mrq->cmd->error = -ETIMEDOUT;
763 host->cmd = NULL;
764 }
765 host->need_reset = 1;
766 host->state = STATE_END_REQUEST;
767 smp_wmb();
768 tasklet_schedule(&host->tasklet);
769}
770
771static inline unsigned int atmci_ns_to_clocks(struct atmel_mci *host,
772 unsigned int ns)
773{
774 /*
775 * It is easier here to use us instead of ns for the timeout,
776 * it prevents from overflows during calculation.
777 */
778 unsigned int us = DIV_ROUND_UP(ns, 1000);
779
780 /* Maximum clock frequency is host->bus_hz/2 */
781 return us * (DIV_ROUND_UP(host->bus_hz, 2000000));
782}
783
784static void atmci_set_timeout(struct atmel_mci *host,
785 struct atmel_mci_slot *slot, struct mmc_data *data)
786{
787 static unsigned dtomul_to_shift[] = {
788 0, 4, 7, 8, 10, 12, 16, 20
789 };
790 unsigned timeout;
791 unsigned dtocyc;
792 unsigned dtomul;
793
794 timeout = atmci_ns_to_clocks(host, data->timeout_ns)
795 + data->timeout_clks;
796
797 for (dtomul = 0; dtomul < 8; dtomul++) {
798 unsigned shift = dtomul_to_shift[dtomul];
799 dtocyc = (timeout + (1 << shift) - 1) >> shift;
800 if (dtocyc < 15)
801 break;
802 }
803
804 if (dtomul >= 8) {
805 dtomul = 7;
806 dtocyc = 15;
807 }
808
809 dev_vdbg(&slot->mmc->class_dev, "setting timeout to %u cycles\n",
810 dtocyc << dtomul_to_shift[dtomul]);
811 atmci_writel(host, ATMCI_DTOR, (ATMCI_DTOMUL(dtomul) | ATMCI_DTOCYC(dtocyc)));
812}
813
814/*
815 * Return mask with command flags to be enabled for this command.
816 */
817static u32 atmci_prepare_command(struct mmc_host *mmc,
818 struct mmc_command *cmd)
819{
820 struct mmc_data *data;
821 u32 cmdr;
822
823 cmd->error = -EINPROGRESS;
824
825 cmdr = ATMCI_CMDR_CMDNB(cmd->opcode);
826
827 if (cmd->flags & MMC_RSP_PRESENT) {
828 if (cmd->flags & MMC_RSP_136)
829 cmdr |= ATMCI_CMDR_RSPTYP_136BIT;
830 else
831 cmdr |= ATMCI_CMDR_RSPTYP_48BIT;
832 }
833
834 /*
835 * This should really be MAXLAT_5 for CMD2 and ACMD41, but
836 * it's too difficult to determine whether this is an ACMD or
837 * not. Better make it 64.
838 */
839 cmdr |= ATMCI_CMDR_MAXLAT_64CYC;
840
841 if (mmc->ios.bus_mode == MMC_BUSMODE_OPENDRAIN)
842 cmdr |= ATMCI_CMDR_OPDCMD;
843
844 data = cmd->data;
845 if (data) {
846 cmdr |= ATMCI_CMDR_START_XFER;
847
848 if (cmd->opcode == SD_IO_RW_EXTENDED) {
849 cmdr |= ATMCI_CMDR_SDIO_BLOCK;
850 } else {
851 if (data->blocks > 1)
852 cmdr |= ATMCI_CMDR_MULTI_BLOCK;
853 else
854 cmdr |= ATMCI_CMDR_BLOCK;
855 }
856
857 if (data->flags & MMC_DATA_READ)
858 cmdr |= ATMCI_CMDR_TRDIR_READ;
859 }
860
861 return cmdr;
862}
863
864static void atmci_send_command(struct atmel_mci *host,
865 struct mmc_command *cmd, u32 cmd_flags)
866{
867 WARN_ON(host->cmd);
868 host->cmd = cmd;
869
870 dev_vdbg(&host->pdev->dev,
871 "start command: ARGR=0x%08x CMDR=0x%08x\n",
872 cmd->arg, cmd_flags);
873
874 atmci_writel(host, ATMCI_ARGR, cmd->arg);
875 atmci_writel(host, ATMCI_CMDR, cmd_flags);
876}
877
878static void atmci_send_stop_cmd(struct atmel_mci *host, struct mmc_data *data)
879{
880 dev_dbg(&host->pdev->dev, "send stop command\n");
881 atmci_send_command(host, data->stop, host->stop_cmdr);
882 atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY);
883}
884
885/*
886 * Configure given PDC buffer taking care of alignement issues.
887 * Update host->data_size and host->sg.
888 */
889static void atmci_pdc_set_single_buf(struct atmel_mci *host,
890 enum atmci_xfer_dir dir, enum atmci_pdc_buf buf_nb)
891{
892 u32 pointer_reg, counter_reg;
893 unsigned int buf_size;
894
895 if (dir == XFER_RECEIVE) {
896 pointer_reg = ATMEL_PDC_RPR;
897 counter_reg = ATMEL_PDC_RCR;
898 } else {
899 pointer_reg = ATMEL_PDC_TPR;
900 counter_reg = ATMEL_PDC_TCR;
901 }
902
903 if (buf_nb == PDC_SECOND_BUF) {
904 pointer_reg += ATMEL_PDC_SCND_BUF_OFF;
905 counter_reg += ATMEL_PDC_SCND_BUF_OFF;
906 }
907
908 if (!host->caps.has_rwproof) {
909 buf_size = host->buf_size;
910 atmci_writel(host, pointer_reg, host->buf_phys_addr);
911 } else {
912 buf_size = sg_dma_len(host->sg);
913 atmci_writel(host, pointer_reg, sg_dma_address(host->sg));
914 }
915
916 if (host->data_size <= buf_size) {
917 if (host->data_size & 0x3) {
918 /* If size is different from modulo 4, transfer bytes */
919 atmci_writel(host, counter_reg, host->data_size);
920 atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCFBYTE);
921 } else {
922 /* Else transfer 32-bits words */
923 atmci_writel(host, counter_reg, host->data_size / 4);
924 }
925 host->data_size = 0;
926 } else {
927 /* We assume the size of a page is 32-bits aligned */
928 atmci_writel(host, counter_reg, sg_dma_len(host->sg) / 4);
929 host->data_size -= sg_dma_len(host->sg);
930 if (host->data_size)
931 host->sg = sg_next(host->sg);
932 }
933}
934
935/*
936 * Configure PDC buffer according to the data size ie configuring one or two
937 * buffers. Don't use this function if you want to configure only the second
938 * buffer. In this case, use atmci_pdc_set_single_buf.
939 */
940static void atmci_pdc_set_both_buf(struct atmel_mci *host, int dir)
941{
942 atmci_pdc_set_single_buf(host, dir, PDC_FIRST_BUF);
943 if (host->data_size)
944 atmci_pdc_set_single_buf(host, dir, PDC_SECOND_BUF);
945}
946
947/*
948 * Unmap sg lists, called when transfer is finished.
949 */
950static void atmci_pdc_cleanup(struct atmel_mci *host)
951{
952 struct mmc_data *data = host->data;
953
954 if (data)
955 dma_unmap_sg(&host->pdev->dev,
956 data->sg, data->sg_len,
957 ((data->flags & MMC_DATA_WRITE)
958 ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
959}
960
961/*
962 * Disable PDC transfers. Update pending flags to EVENT_XFER_COMPLETE after
963 * having received ATMCI_TXBUFE or ATMCI_RXBUFF interrupt. Enable ATMCI_NOTBUSY
964 * interrupt needed for both transfer directions.
965 */
966static void atmci_pdc_complete(struct atmel_mci *host)
967{
968 int transfer_size = host->data->blocks * host->data->blksz;
969 int i;
970
971 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
972
973 if ((!host->caps.has_rwproof)
974 && (host->data->flags & MMC_DATA_READ)) {
975 if (host->caps.has_bad_data_ordering)
976 for (i = 0; i < transfer_size; i++)
977 host->buffer[i] = swab32(host->buffer[i]);
978 sg_copy_from_buffer(host->data->sg, host->data->sg_len,
979 host->buffer, transfer_size);
980 }
981
982 atmci_pdc_cleanup(host);
983
984 dev_dbg(&host->pdev->dev, "(%s) set pending xfer complete\n", __func__);
985 atmci_set_pending(host, EVENT_XFER_COMPLETE);
986 tasklet_schedule(&host->tasklet);
987}
988
989static void atmci_dma_cleanup(struct atmel_mci *host)
990{
991 struct mmc_data *data = host->data;
992
993 if (data)
994 dma_unmap_sg(host->dma.chan->device->dev,
995 data->sg, data->sg_len,
996 ((data->flags & MMC_DATA_WRITE)
997 ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
998}
999
1000/*
1001 * This function is called by the DMA driver from tasklet context.
1002 */
1003static void atmci_dma_complete(void *arg)
1004{
1005 struct atmel_mci *host = arg;
1006 struct mmc_data *data = host->data;
1007
1008 dev_vdbg(&host->pdev->dev, "DMA complete\n");
1009
1010 if (host->caps.has_dma_conf_reg)
1011 /* Disable DMA hardware handshaking on MCI */
1012 atmci_writel(host, ATMCI_DMA, atmci_readl(host, ATMCI_DMA) & ~ATMCI_DMAEN);
1013
1014 atmci_dma_cleanup(host);
1015
1016 /*
1017 * If the card was removed, data will be NULL. No point trying
1018 * to send the stop command or waiting for NBUSY in this case.
1019 */
1020 if (data) {
1021 dev_dbg(&host->pdev->dev,
1022 "(%s) set pending xfer complete\n", __func__);
1023 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1024 tasklet_schedule(&host->tasklet);
1025
1026 /*
1027 * Regardless of what the documentation says, we have
1028 * to wait for NOTBUSY even after block read
1029 * operations.
1030 *
1031 * When the DMA transfer is complete, the controller
1032 * may still be reading the CRC from the card, i.e.
1033 * the data transfer is still in progress and we
1034 * haven't seen all the potential error bits yet.
1035 *
1036 * The interrupt handler will schedule a different
1037 * tasklet to finish things up when the data transfer
1038 * is completely done.
1039 *
1040 * We may not complete the mmc request here anyway
1041 * because the mmc layer may call back and cause us to
1042 * violate the "don't submit new operations from the
1043 * completion callback" rule of the dma engine
1044 * framework.
1045 */
1046 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1047 }
1048}
1049
1050/*
1051 * Returns a mask of interrupt flags to be enabled after the whole
1052 * request has been prepared.
1053 */
1054static u32 atmci_prepare_data(struct atmel_mci *host, struct mmc_data *data)
1055{
1056 u32 iflags;
1057
1058 data->error = -EINPROGRESS;
1059
1060 host->sg = data->sg;
1061 host->sg_len = data->sg_len;
1062 host->data = data;
1063 host->data_chan = NULL;
1064
1065 iflags = ATMCI_DATA_ERROR_FLAGS;
1066
1067 /*
1068 * Errata: MMC data write operation with less than 12
1069 * bytes is impossible.
1070 *
1071 * Errata: MCI Transmit Data Register (TDR) FIFO
1072 * corruption when length is not multiple of 4.
1073 */
1074 if (data->blocks * data->blksz < 12
1075 || (data->blocks * data->blksz) & 3)
1076 host->need_reset = true;
1077
1078 host->pio_offset = 0;
1079 if (data->flags & MMC_DATA_READ)
1080 iflags |= ATMCI_RXRDY;
1081 else
1082 iflags |= ATMCI_TXRDY;
1083
1084 return iflags;
1085}
1086
1087/*
1088 * Set interrupt flags and set block length into the MCI mode register even
1089 * if this value is also accessible in the MCI block register. It seems to be
1090 * necessary before the High Speed MCI version. It also map sg and configure
1091 * PDC registers.
1092 */
1093static u32
1094atmci_prepare_data_pdc(struct atmel_mci *host, struct mmc_data *data)
1095{
1096 u32 iflags, tmp;
1097 unsigned int sg_len;
1098 enum dma_data_direction dir;
1099 int i;
1100
1101 data->error = -EINPROGRESS;
1102
1103 host->data = data;
1104 host->sg = data->sg;
1105 iflags = ATMCI_DATA_ERROR_FLAGS;
1106
1107 /* Enable pdc mode */
1108 atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCMODE);
1109
1110 if (data->flags & MMC_DATA_READ) {
1111 dir = DMA_FROM_DEVICE;
1112 iflags |= ATMCI_ENDRX | ATMCI_RXBUFF;
1113 } else {
1114 dir = DMA_TO_DEVICE;
1115 iflags |= ATMCI_ENDTX | ATMCI_TXBUFE | ATMCI_BLKE;
1116 }
1117
1118 /* Set BLKLEN */
1119 tmp = atmci_readl(host, ATMCI_MR);
1120 tmp &= 0x0000ffff;
1121 tmp |= ATMCI_BLKLEN(data->blksz);
1122 atmci_writel(host, ATMCI_MR, tmp);
1123
1124 /* Configure PDC */
1125 host->data_size = data->blocks * data->blksz;
1126 sg_len = dma_map_sg(&host->pdev->dev, data->sg, data->sg_len, dir);
1127
1128 if ((!host->caps.has_rwproof)
1129 && (host->data->flags & MMC_DATA_WRITE)) {
1130 sg_copy_to_buffer(host->data->sg, host->data->sg_len,
1131 host->buffer, host->data_size);
1132 if (host->caps.has_bad_data_ordering)
1133 for (i = 0; i < host->data_size; i++)
1134 host->buffer[i] = swab32(host->buffer[i]);
1135 }
1136
1137 if (host->data_size)
1138 atmci_pdc_set_both_buf(host,
1139 ((dir == DMA_FROM_DEVICE) ? XFER_RECEIVE : XFER_TRANSMIT));
1140
1141 return iflags;
1142}
1143
1144static u32
1145atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data)
1146{
1147 struct dma_chan *chan;
1148 struct dma_async_tx_descriptor *desc;
1149 struct scatterlist *sg;
1150 unsigned int i;
1151 enum dma_data_direction direction;
1152 enum dma_transfer_direction slave_dirn;
1153 unsigned int sglen;
1154 u32 maxburst;
1155 u32 iflags;
1156
1157 data->error = -EINPROGRESS;
1158
1159 WARN_ON(host->data);
1160 host->sg = NULL;
1161 host->data = data;
1162
1163 iflags = ATMCI_DATA_ERROR_FLAGS;
1164
1165 /*
1166 * We don't do DMA on "complex" transfers, i.e. with
1167 * non-word-aligned buffers or lengths. Also, we don't bother
1168 * with all the DMA setup overhead for short transfers.
1169 */
1170 if (data->blocks * data->blksz < ATMCI_DMA_THRESHOLD)
1171 return atmci_prepare_data(host, data);
1172 if (data->blksz & 3)
1173 return atmci_prepare_data(host, data);
1174
1175 for_each_sg(data->sg, sg, data->sg_len, i) {
1176 if (sg->offset & 3 || sg->length & 3)
1177 return atmci_prepare_data(host, data);
1178 }
1179
1180 /* If we don't have a channel, we can't do DMA */
1181 chan = host->dma.chan;
1182 if (chan)
1183 host->data_chan = chan;
1184
1185 if (!chan)
1186 return -ENODEV;
1187
1188 if (data->flags & MMC_DATA_READ) {
1189 direction = DMA_FROM_DEVICE;
1190 host->dma_conf.direction = slave_dirn = DMA_DEV_TO_MEM;
1191 maxburst = atmci_convert_chksize(host,
1192 host->dma_conf.src_maxburst);
1193 } else {
1194 direction = DMA_TO_DEVICE;
1195 host->dma_conf.direction = slave_dirn = DMA_MEM_TO_DEV;
1196 maxburst = atmci_convert_chksize(host,
1197 host->dma_conf.dst_maxburst);
1198 }
1199
1200 if (host->caps.has_dma_conf_reg)
1201 atmci_writel(host, ATMCI_DMA, ATMCI_DMA_CHKSIZE(maxburst) |
1202 ATMCI_DMAEN);
1203
1204 sglen = dma_map_sg(chan->device->dev, data->sg,
1205 data->sg_len, direction);
1206
1207 dmaengine_slave_config(chan, &host->dma_conf);
1208 desc = dmaengine_prep_slave_sg(chan,
1209 data->sg, sglen, slave_dirn,
1210 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1211 if (!desc)
1212 goto unmap_exit;
1213
1214 host->dma.data_desc = desc;
1215 desc->callback = atmci_dma_complete;
1216 desc->callback_param = host;
1217
1218 return iflags;
1219unmap_exit:
1220 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, direction);
1221 return -ENOMEM;
1222}
1223
1224static void
1225atmci_submit_data(struct atmel_mci *host, struct mmc_data *data)
1226{
1227 return;
1228}
1229
1230/*
1231 * Start PDC according to transfer direction.
1232 */
1233static void
1234atmci_submit_data_pdc(struct atmel_mci *host, struct mmc_data *data)
1235{
1236 if (data->flags & MMC_DATA_READ)
1237 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
1238 else
1239 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
1240}
1241
1242static void
1243atmci_submit_data_dma(struct atmel_mci *host, struct mmc_data *data)
1244{
1245 struct dma_chan *chan = host->data_chan;
1246 struct dma_async_tx_descriptor *desc = host->dma.data_desc;
1247
1248 if (chan) {
1249 dmaengine_submit(desc);
1250 dma_async_issue_pending(chan);
1251 }
1252}
1253
1254static void atmci_stop_transfer(struct atmel_mci *host)
1255{
1256 dev_dbg(&host->pdev->dev,
1257 "(%s) set pending xfer complete\n", __func__);
1258 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1259 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1260}
1261
1262/*
1263 * Stop data transfer because error(s) occurred.
1264 */
1265static void atmci_stop_transfer_pdc(struct atmel_mci *host)
1266{
1267 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
1268}
1269
1270static void atmci_stop_transfer_dma(struct atmel_mci *host)
1271{
1272 struct dma_chan *chan = host->data_chan;
1273
1274 if (chan) {
1275 dmaengine_terminate_all(chan);
1276 atmci_dma_cleanup(host);
1277 } else {
1278 /* Data transfer was stopped by the interrupt handler */
1279 dev_dbg(&host->pdev->dev,
1280 "(%s) set pending xfer complete\n", __func__);
1281 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1282 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1283 }
1284}
1285
1286/*
1287 * Start a request: prepare data if needed, prepare the command and activate
1288 * interrupts.
1289 */
1290static void atmci_start_request(struct atmel_mci *host,
1291 struct atmel_mci_slot *slot)
1292{
1293 struct mmc_request *mrq;
1294 struct mmc_command *cmd;
1295 struct mmc_data *data;
1296 u32 iflags;
1297 u32 cmdflags;
1298
1299 mrq = slot->mrq;
1300 host->cur_slot = slot;
1301 host->mrq = mrq;
1302
1303 host->pending_events = 0;
1304 host->completed_events = 0;
1305 host->cmd_status = 0;
1306 host->data_status = 0;
1307
1308 dev_dbg(&host->pdev->dev, "start request: cmd %u\n", mrq->cmd->opcode);
1309
1310 if (host->need_reset || host->caps.need_reset_after_xfer) {
1311 iflags = atmci_readl(host, ATMCI_IMR);
1312 iflags &= (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB);
1313 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1314 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1315 atmci_writel(host, ATMCI_MR, host->mode_reg);
1316 if (host->caps.has_cfg_reg)
1317 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1318 atmci_writel(host, ATMCI_IER, iflags);
1319 host->need_reset = false;
1320 }
1321 atmci_writel(host, ATMCI_SDCR, slot->sdc_reg);
1322
1323 iflags = atmci_readl(host, ATMCI_IMR);
1324 if (iflags & ~(ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
1325 dev_dbg(&slot->mmc->class_dev, "WARNING: IMR=0x%08x\n",
1326 iflags);
1327
1328 if (unlikely(test_and_clear_bit(ATMCI_CARD_NEED_INIT, &slot->flags))) {
1329 /* Send init sequence (74 clock cycles) */
1330 atmci_writel(host, ATMCI_CMDR, ATMCI_CMDR_SPCMD_INIT);
1331 while (!(atmci_readl(host, ATMCI_SR) & ATMCI_CMDRDY))
1332 cpu_relax();
1333 }
1334 iflags = 0;
1335 data = mrq->data;
1336 if (data) {
1337 atmci_set_timeout(host, slot, data);
1338
1339 /* Must set block count/size before sending command */
1340 atmci_writel(host, ATMCI_BLKR, ATMCI_BCNT(data->blocks)
1341 | ATMCI_BLKLEN(data->blksz));
1342 dev_vdbg(&slot->mmc->class_dev, "BLKR=0x%08x\n",
1343 ATMCI_BCNT(data->blocks) | ATMCI_BLKLEN(data->blksz));
1344
1345 iflags |= host->prepare_data(host, data);
1346 }
1347
1348 iflags |= ATMCI_CMDRDY;
1349 cmd = mrq->cmd;
1350 cmdflags = atmci_prepare_command(slot->mmc, cmd);
1351
1352 /*
1353 * DMA transfer should be started before sending the command to avoid
1354 * unexpected errors especially for read operations in SDIO mode.
1355 * Unfortunately, in PDC mode, command has to be sent before starting
1356 * the transfer.
1357 */
1358 if (host->submit_data != &atmci_submit_data_dma)
1359 atmci_send_command(host, cmd, cmdflags);
1360
1361 if (data)
1362 host->submit_data(host, data);
1363
1364 if (host->submit_data == &atmci_submit_data_dma)
1365 atmci_send_command(host, cmd, cmdflags);
1366
1367 if (mrq->stop) {
1368 host->stop_cmdr = atmci_prepare_command(slot->mmc, mrq->stop);
1369 host->stop_cmdr |= ATMCI_CMDR_STOP_XFER;
1370 if (!(data->flags & MMC_DATA_WRITE))
1371 host->stop_cmdr |= ATMCI_CMDR_TRDIR_READ;
1372 host->stop_cmdr |= ATMCI_CMDR_MULTI_BLOCK;
1373 }
1374
1375 /*
1376 * We could have enabled interrupts earlier, but I suspect
1377 * that would open up a nice can of interesting race
1378 * conditions (e.g. command and data complete, but stop not
1379 * prepared yet.)
1380 */
1381 atmci_writel(host, ATMCI_IER, iflags);
1382
1383 mod_timer(&host->timer, jiffies + msecs_to_jiffies(2000));
1384}
1385
1386static void atmci_queue_request(struct atmel_mci *host,
1387 struct atmel_mci_slot *slot, struct mmc_request *mrq)
1388{
1389 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1390 host->state);
1391
1392 spin_lock_bh(&host->lock);
1393 slot->mrq = mrq;
1394 if (host->state == STATE_IDLE) {
1395 host->state = STATE_SENDING_CMD;
1396 atmci_start_request(host, slot);
1397 } else {
1398 dev_dbg(&host->pdev->dev, "queue request\n");
1399 list_add_tail(&slot->queue_node, &host->queue);
1400 }
1401 spin_unlock_bh(&host->lock);
1402}
1403
1404static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1405{
1406 struct atmel_mci_slot *slot = mmc_priv(mmc);
1407 struct atmel_mci *host = slot->host;
1408 struct mmc_data *data;
1409
1410 WARN_ON(slot->mrq);
1411 dev_dbg(&host->pdev->dev, "MRQ: cmd %u\n", mrq->cmd->opcode);
1412
1413 pm_runtime_get_sync(&host->pdev->dev);
1414
1415 /*
1416 * We may "know" the card is gone even though there's still an
1417 * electrical connection. If so, we really need to communicate
1418 * this to the MMC core since there won't be any more
1419 * interrupts as the card is completely removed. Otherwise,
1420 * the MMC core might believe the card is still there even
1421 * though the card was just removed very slowly.
1422 */
1423 if (!test_bit(ATMCI_CARD_PRESENT, &slot->flags)) {
1424 mrq->cmd->error = -ENOMEDIUM;
1425 mmc_request_done(mmc, mrq);
1426 return;
1427 }
1428
1429 /* We don't support multiple blocks of weird lengths. */
1430 data = mrq->data;
1431 if (data && data->blocks > 1 && data->blksz & 3) {
1432 mrq->cmd->error = -EINVAL;
1433 mmc_request_done(mmc, mrq);
1434 }
1435
1436 atmci_queue_request(host, slot, mrq);
1437}
1438
1439static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1440{
1441 struct atmel_mci_slot *slot = mmc_priv(mmc);
1442 struct atmel_mci *host = slot->host;
1443 unsigned int i;
1444
1445 pm_runtime_get_sync(&host->pdev->dev);
1446
1447 slot->sdc_reg &= ~ATMCI_SDCBUS_MASK;
1448 switch (ios->bus_width) {
1449 case MMC_BUS_WIDTH_1:
1450 slot->sdc_reg |= ATMCI_SDCBUS_1BIT;
1451 break;
1452 case MMC_BUS_WIDTH_4:
1453 slot->sdc_reg |= ATMCI_SDCBUS_4BIT;
1454 break;
1455 }
1456
1457 if (ios->clock) {
1458 unsigned int clock_min = ~0U;
1459 int clkdiv;
1460
1461 spin_lock_bh(&host->lock);
1462 if (!host->mode_reg) {
1463 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1464 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1465 if (host->caps.has_cfg_reg)
1466 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1467 }
1468
1469 /*
1470 * Use mirror of ios->clock to prevent race with mmc
1471 * core ios update when finding the minimum.
1472 */
1473 slot->clock = ios->clock;
1474 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1475 if (host->slot[i] && host->slot[i]->clock
1476 && host->slot[i]->clock < clock_min)
1477 clock_min = host->slot[i]->clock;
1478 }
1479
1480 /* Calculate clock divider */
1481 if (host->caps.has_odd_clk_div) {
1482 clkdiv = DIV_ROUND_UP(host->bus_hz, clock_min) - 2;
1483 if (clkdiv < 0) {
1484 dev_warn(&mmc->class_dev,
1485 "clock %u too fast; using %lu\n",
1486 clock_min, host->bus_hz / 2);
1487 clkdiv = 0;
1488 } else if (clkdiv > 511) {
1489 dev_warn(&mmc->class_dev,
1490 "clock %u too slow; using %lu\n",
1491 clock_min, host->bus_hz / (511 + 2));
1492 clkdiv = 511;
1493 }
1494 host->mode_reg = ATMCI_MR_CLKDIV(clkdiv >> 1)
1495 | ATMCI_MR_CLKODD(clkdiv & 1);
1496 } else {
1497 clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * clock_min) - 1;
1498 if (clkdiv > 255) {
1499 dev_warn(&mmc->class_dev,
1500 "clock %u too slow; using %lu\n",
1501 clock_min, host->bus_hz / (2 * 256));
1502 clkdiv = 255;
1503 }
1504 host->mode_reg = ATMCI_MR_CLKDIV(clkdiv);
1505 }
1506
1507 /*
1508 * WRPROOF and RDPROOF prevent overruns/underruns by
1509 * stopping the clock when the FIFO is full/empty.
1510 * This state is not expected to last for long.
1511 */
1512 if (host->caps.has_rwproof)
1513 host->mode_reg |= (ATMCI_MR_WRPROOF | ATMCI_MR_RDPROOF);
1514
1515 if (host->caps.has_cfg_reg) {
1516 /* setup High Speed mode in relation with card capacity */
1517 if (ios->timing == MMC_TIMING_SD_HS)
1518 host->cfg_reg |= ATMCI_CFG_HSMODE;
1519 else
1520 host->cfg_reg &= ~ATMCI_CFG_HSMODE;
1521 }
1522
1523 if (list_empty(&host->queue)) {
1524 atmci_writel(host, ATMCI_MR, host->mode_reg);
1525 if (host->caps.has_cfg_reg)
1526 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1527 } else {
1528 host->need_clock_update = true;
1529 }
1530
1531 spin_unlock_bh(&host->lock);
1532 } else {
1533 bool any_slot_active = false;
1534
1535 spin_lock_bh(&host->lock);
1536 slot->clock = 0;
1537 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1538 if (host->slot[i] && host->slot[i]->clock) {
1539 any_slot_active = true;
1540 break;
1541 }
1542 }
1543 if (!any_slot_active) {
1544 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
1545 if (host->mode_reg) {
1546 atmci_readl(host, ATMCI_MR);
1547 }
1548 host->mode_reg = 0;
1549 }
1550 spin_unlock_bh(&host->lock);
1551 }
1552
1553 switch (ios->power_mode) {
1554 case MMC_POWER_OFF:
1555 if (!IS_ERR(mmc->supply.vmmc))
1556 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1557 break;
1558 case MMC_POWER_UP:
1559 set_bit(ATMCI_CARD_NEED_INIT, &slot->flags);
1560 if (!IS_ERR(mmc->supply.vmmc))
1561 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
1562 break;
1563 default:
1564 /*
1565 * TODO: None of the currently available AVR32-based
1566 * boards allow MMC power to be turned off. Implement
1567 * power control when this can be tested properly.
1568 *
1569 * We also need to hook this into the clock management
1570 * somehow so that newly inserted cards aren't
1571 * subjected to a fast clock before we have a chance
1572 * to figure out what the maximum rate is. Currently,
1573 * there's no way to avoid this, and there never will
1574 * be for boards that don't support power control.
1575 */
1576 break;
1577 }
1578
1579 pm_runtime_mark_last_busy(&host->pdev->dev);
1580 pm_runtime_put_autosuspend(&host->pdev->dev);
1581}
1582
1583static int atmci_get_ro(struct mmc_host *mmc)
1584{
1585 int read_only = -ENOSYS;
1586 struct atmel_mci_slot *slot = mmc_priv(mmc);
1587
1588 if (gpio_is_valid(slot->wp_pin)) {
1589 read_only = gpio_get_value(slot->wp_pin);
1590 dev_dbg(&mmc->class_dev, "card is %s\n",
1591 read_only ? "read-only" : "read-write");
1592 }
1593
1594 return read_only;
1595}
1596
1597static int atmci_get_cd(struct mmc_host *mmc)
1598{
1599 int present = -ENOSYS;
1600 struct atmel_mci_slot *slot = mmc_priv(mmc);
1601
1602 if (gpio_is_valid(slot->detect_pin)) {
1603 present = !(gpio_get_value(slot->detect_pin) ^
1604 slot->detect_is_active_high);
1605 dev_dbg(&mmc->class_dev, "card is %spresent\n",
1606 present ? "" : "not ");
1607 }
1608
1609 return present;
1610}
1611
1612static void atmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1613{
1614 struct atmel_mci_slot *slot = mmc_priv(mmc);
1615 struct atmel_mci *host = slot->host;
1616
1617 if (enable)
1618 atmci_writel(host, ATMCI_IER, slot->sdio_irq);
1619 else
1620 atmci_writel(host, ATMCI_IDR, slot->sdio_irq);
1621}
1622
1623static const struct mmc_host_ops atmci_ops = {
1624 .request = atmci_request,
1625 .set_ios = atmci_set_ios,
1626 .get_ro = atmci_get_ro,
1627 .get_cd = atmci_get_cd,
1628 .enable_sdio_irq = atmci_enable_sdio_irq,
1629};
1630
1631/* Called with host->lock held */
1632static void atmci_request_end(struct atmel_mci *host, struct mmc_request *mrq)
1633 __releases(&host->lock)
1634 __acquires(&host->lock)
1635{
1636 struct atmel_mci_slot *slot = NULL;
1637 struct mmc_host *prev_mmc = host->cur_slot->mmc;
1638
1639 WARN_ON(host->cmd || host->data);
1640
1641 /*
1642 * Update the MMC clock rate if necessary. This may be
1643 * necessary if set_ios() is called when a different slot is
1644 * busy transferring data.
1645 */
1646 if (host->need_clock_update) {
1647 atmci_writel(host, ATMCI_MR, host->mode_reg);
1648 if (host->caps.has_cfg_reg)
1649 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1650 }
1651
1652 host->cur_slot->mrq = NULL;
1653 host->mrq = NULL;
1654 if (!list_empty(&host->queue)) {
1655 slot = list_entry(host->queue.next,
1656 struct atmel_mci_slot, queue_node);
1657 list_del(&slot->queue_node);
1658 dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n",
1659 mmc_hostname(slot->mmc));
1660 host->state = STATE_SENDING_CMD;
1661 atmci_start_request(host, slot);
1662 } else {
1663 dev_vdbg(&host->pdev->dev, "list empty\n");
1664 host->state = STATE_IDLE;
1665 }
1666
1667 del_timer(&host->timer);
1668
1669 spin_unlock(&host->lock);
1670 mmc_request_done(prev_mmc, mrq);
1671 spin_lock(&host->lock);
1672
1673 pm_runtime_mark_last_busy(&host->pdev->dev);
1674 pm_runtime_put_autosuspend(&host->pdev->dev);
1675}
1676
1677static void atmci_command_complete(struct atmel_mci *host,
1678 struct mmc_command *cmd)
1679{
1680 u32 status = host->cmd_status;
1681
1682 /* Read the response from the card (up to 16 bytes) */
1683 cmd->resp[0] = atmci_readl(host, ATMCI_RSPR);
1684 cmd->resp[1] = atmci_readl(host, ATMCI_RSPR);
1685 cmd->resp[2] = atmci_readl(host, ATMCI_RSPR);
1686 cmd->resp[3] = atmci_readl(host, ATMCI_RSPR);
1687
1688 if (status & ATMCI_RTOE)
1689 cmd->error = -ETIMEDOUT;
1690 else if ((cmd->flags & MMC_RSP_CRC) && (status & ATMCI_RCRCE))
1691 cmd->error = -EILSEQ;
1692 else if (status & (ATMCI_RINDE | ATMCI_RDIRE | ATMCI_RENDE))
1693 cmd->error = -EIO;
1694 else if (host->mrq->data && (host->mrq->data->blksz & 3)) {
1695 if (host->caps.need_blksz_mul_4) {
1696 cmd->error = -EINVAL;
1697 host->need_reset = 1;
1698 }
1699 } else
1700 cmd->error = 0;
1701}
1702
1703static void atmci_detect_change(unsigned long data)
1704{
1705 struct atmel_mci_slot *slot = (struct atmel_mci_slot *)data;
1706 bool present;
1707 bool present_old;
1708
1709 /*
1710 * atmci_cleanup_slot() sets the ATMCI_SHUTDOWN flag before
1711 * freeing the interrupt. We must not re-enable the interrupt
1712 * if it has been freed, and if we're shutting down, it
1713 * doesn't really matter whether the card is present or not.
1714 */
1715 smp_rmb();
1716 if (test_bit(ATMCI_SHUTDOWN, &slot->flags))
1717 return;
1718
1719 enable_irq(gpio_to_irq(slot->detect_pin));
1720 present = !(gpio_get_value(slot->detect_pin) ^
1721 slot->detect_is_active_high);
1722 present_old = test_bit(ATMCI_CARD_PRESENT, &slot->flags);
1723
1724 dev_vdbg(&slot->mmc->class_dev, "detect change: %d (was %d)\n",
1725 present, present_old);
1726
1727 if (present != present_old) {
1728 struct atmel_mci *host = slot->host;
1729 struct mmc_request *mrq;
1730
1731 dev_dbg(&slot->mmc->class_dev, "card %s\n",
1732 present ? "inserted" : "removed");
1733
1734 spin_lock(&host->lock);
1735
1736 if (!present)
1737 clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
1738 else
1739 set_bit(ATMCI_CARD_PRESENT, &slot->flags);
1740
1741 /* Clean up queue if present */
1742 mrq = slot->mrq;
1743 if (mrq) {
1744 if (mrq == host->mrq) {
1745 /*
1746 * Reset controller to terminate any ongoing
1747 * commands or data transfers.
1748 */
1749 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1750 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1751 atmci_writel(host, ATMCI_MR, host->mode_reg);
1752 if (host->caps.has_cfg_reg)
1753 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1754
1755 host->data = NULL;
1756 host->cmd = NULL;
1757
1758 switch (host->state) {
1759 case STATE_IDLE:
1760 break;
1761 case STATE_SENDING_CMD:
1762 mrq->cmd->error = -ENOMEDIUM;
1763 if (mrq->data)
1764 host->stop_transfer(host);
1765 break;
1766 case STATE_DATA_XFER:
1767 mrq->data->error = -ENOMEDIUM;
1768 host->stop_transfer(host);
1769 break;
1770 case STATE_WAITING_NOTBUSY:
1771 mrq->data->error = -ENOMEDIUM;
1772 break;
1773 case STATE_SENDING_STOP:
1774 mrq->stop->error = -ENOMEDIUM;
1775 break;
1776 case STATE_END_REQUEST:
1777 break;
1778 }
1779
1780 atmci_request_end(host, mrq);
1781 } else {
1782 list_del(&slot->queue_node);
1783 mrq->cmd->error = -ENOMEDIUM;
1784 if (mrq->data)
1785 mrq->data->error = -ENOMEDIUM;
1786 if (mrq->stop)
1787 mrq->stop->error = -ENOMEDIUM;
1788
1789 spin_unlock(&host->lock);
1790 mmc_request_done(slot->mmc, mrq);
1791 spin_lock(&host->lock);
1792 }
1793 }
1794 spin_unlock(&host->lock);
1795
1796 mmc_detect_change(slot->mmc, 0);
1797 }
1798}
1799
1800static void atmci_tasklet_func(unsigned long priv)
1801{
1802 struct atmel_mci *host = (struct atmel_mci *)priv;
1803 struct mmc_request *mrq = host->mrq;
1804 struct mmc_data *data = host->data;
1805 enum atmel_mci_state state = host->state;
1806 enum atmel_mci_state prev_state;
1807 u32 status;
1808
1809 spin_lock(&host->lock);
1810
1811 state = host->state;
1812
1813 dev_vdbg(&host->pdev->dev,
1814 "tasklet: state %u pending/completed/mask %lx/%lx/%x\n",
1815 state, host->pending_events, host->completed_events,
1816 atmci_readl(host, ATMCI_IMR));
1817
1818 do {
1819 prev_state = state;
1820 dev_dbg(&host->pdev->dev, "FSM: state=%d\n", state);
1821
1822 switch (state) {
1823 case STATE_IDLE:
1824 break;
1825
1826 case STATE_SENDING_CMD:
1827 /*
1828 * Command has been sent, we are waiting for command
1829 * ready. Then we have three next states possible:
1830 * END_REQUEST by default, WAITING_NOTBUSY if it's a
1831 * command needing it or DATA_XFER if there is data.
1832 */
1833 dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n");
1834 if (!atmci_test_and_clear_pending(host,
1835 EVENT_CMD_RDY))
1836 break;
1837
1838 dev_dbg(&host->pdev->dev, "set completed cmd ready\n");
1839 host->cmd = NULL;
1840 atmci_set_completed(host, EVENT_CMD_RDY);
1841 atmci_command_complete(host, mrq->cmd);
1842 if (mrq->data) {
1843 dev_dbg(&host->pdev->dev,
1844 "command with data transfer");
1845 /*
1846 * If there is a command error don't start
1847 * data transfer.
1848 */
1849 if (mrq->cmd->error) {
1850 host->stop_transfer(host);
1851 host->data = NULL;
1852 atmci_writel(host, ATMCI_IDR,
1853 ATMCI_TXRDY | ATMCI_RXRDY
1854 | ATMCI_DATA_ERROR_FLAGS);
1855 state = STATE_END_REQUEST;
1856 } else
1857 state = STATE_DATA_XFER;
1858 } else if ((!mrq->data) && (mrq->cmd->flags & MMC_RSP_BUSY)) {
1859 dev_dbg(&host->pdev->dev,
1860 "command response need waiting notbusy");
1861 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1862 state = STATE_WAITING_NOTBUSY;
1863 } else
1864 state = STATE_END_REQUEST;
1865
1866 break;
1867
1868 case STATE_DATA_XFER:
1869 if (atmci_test_and_clear_pending(host,
1870 EVENT_DATA_ERROR)) {
1871 dev_dbg(&host->pdev->dev, "set completed data error\n");
1872 atmci_set_completed(host, EVENT_DATA_ERROR);
1873 state = STATE_END_REQUEST;
1874 break;
1875 }
1876
1877 /*
1878 * A data transfer is in progress. The event expected
1879 * to move to the next state depends of data transfer
1880 * type (PDC or DMA). Once transfer done we can move
1881 * to the next step which is WAITING_NOTBUSY in write
1882 * case and directly SENDING_STOP in read case.
1883 */
1884 dev_dbg(&host->pdev->dev, "FSM: xfer complete?\n");
1885 if (!atmci_test_and_clear_pending(host,
1886 EVENT_XFER_COMPLETE))
1887 break;
1888
1889 dev_dbg(&host->pdev->dev,
1890 "(%s) set completed xfer complete\n",
1891 __func__);
1892 atmci_set_completed(host, EVENT_XFER_COMPLETE);
1893
1894 if (host->caps.need_notbusy_for_read_ops ||
1895 (host->data->flags & MMC_DATA_WRITE)) {
1896 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1897 state = STATE_WAITING_NOTBUSY;
1898 } else if (host->mrq->stop) {
1899 atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY);
1900 atmci_send_stop_cmd(host, data);
1901 state = STATE_SENDING_STOP;
1902 } else {
1903 host->data = NULL;
1904 data->bytes_xfered = data->blocks * data->blksz;
1905 data->error = 0;
1906 state = STATE_END_REQUEST;
1907 }
1908 break;
1909
1910 case STATE_WAITING_NOTBUSY:
1911 /*
1912 * We can be in the state for two reasons: a command
1913 * requiring waiting not busy signal (stop command
1914 * included) or a write operation. In the latest case,
1915 * we need to send a stop command.
1916 */
1917 dev_dbg(&host->pdev->dev, "FSM: not busy?\n");
1918 if (!atmci_test_and_clear_pending(host,
1919 EVENT_NOTBUSY))
1920 break;
1921
1922 dev_dbg(&host->pdev->dev, "set completed not busy\n");
1923 atmci_set_completed(host, EVENT_NOTBUSY);
1924
1925 if (host->data) {
1926 /*
1927 * For some commands such as CMD53, even if
1928 * there is data transfer, there is no stop
1929 * command to send.
1930 */
1931 if (host->mrq->stop) {
1932 atmci_writel(host, ATMCI_IER,
1933 ATMCI_CMDRDY);
1934 atmci_send_stop_cmd(host, data);
1935 state = STATE_SENDING_STOP;
1936 } else {
1937 host->data = NULL;
1938 data->bytes_xfered = data->blocks
1939 * data->blksz;
1940 data->error = 0;
1941 state = STATE_END_REQUEST;
1942 }
1943 } else
1944 state = STATE_END_REQUEST;
1945 break;
1946
1947 case STATE_SENDING_STOP:
1948 /*
1949 * In this state, it is important to set host->data to
1950 * NULL (which is tested in the waiting notbusy state)
1951 * in order to go to the end request state instead of
1952 * sending stop again.
1953 */
1954 dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n");
1955 if (!atmci_test_and_clear_pending(host,
1956 EVENT_CMD_RDY))
1957 break;
1958
1959 dev_dbg(&host->pdev->dev, "FSM: cmd ready\n");
1960 host->cmd = NULL;
1961 data->bytes_xfered = data->blocks * data->blksz;
1962 data->error = 0;
1963 atmci_command_complete(host, mrq->stop);
1964 if (mrq->stop->error) {
1965 host->stop_transfer(host);
1966 atmci_writel(host, ATMCI_IDR,
1967 ATMCI_TXRDY | ATMCI_RXRDY
1968 | ATMCI_DATA_ERROR_FLAGS);
1969 state = STATE_END_REQUEST;
1970 } else {
1971 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1972 state = STATE_WAITING_NOTBUSY;
1973 }
1974 host->data = NULL;
1975 break;
1976
1977 case STATE_END_REQUEST:
1978 atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY | ATMCI_RXRDY
1979 | ATMCI_DATA_ERROR_FLAGS);
1980 status = host->data_status;
1981 if (unlikely(status)) {
1982 host->stop_transfer(host);
1983 host->data = NULL;
1984 if (data) {
1985 if (status & ATMCI_DTOE) {
1986 data->error = -ETIMEDOUT;
1987 } else if (status & ATMCI_DCRCE) {
1988 data->error = -EILSEQ;
1989 } else {
1990 data->error = -EIO;
1991 }
1992 }
1993 }
1994
1995 atmci_request_end(host, host->mrq);
1996 state = STATE_IDLE;
1997 break;
1998 }
1999 } while (state != prev_state);
2000
2001 host->state = state;
2002
2003 spin_unlock(&host->lock);
2004}
2005
2006static void atmci_read_data_pio(struct atmel_mci *host)
2007{
2008 struct scatterlist *sg = host->sg;
2009 void *buf = sg_virt(sg);
2010 unsigned int offset = host->pio_offset;
2011 struct mmc_data *data = host->data;
2012 u32 value;
2013 u32 status;
2014 unsigned int nbytes = 0;
2015
2016 do {
2017 value = atmci_readl(host, ATMCI_RDR);
2018 if (likely(offset + 4 <= sg->length)) {
2019 put_unaligned(value, (u32 *)(buf + offset));
2020
2021 offset += 4;
2022 nbytes += 4;
2023
2024 if (offset == sg->length) {
2025 flush_dcache_page(sg_page(sg));
2026 host->sg = sg = sg_next(sg);
2027 host->sg_len--;
2028 if (!sg || !host->sg_len)
2029 goto done;
2030
2031 offset = 0;
2032 buf = sg_virt(sg);
2033 }
2034 } else {
2035 unsigned int remaining = sg->length - offset;
2036 memcpy(buf + offset, &value, remaining);
2037 nbytes += remaining;
2038
2039 flush_dcache_page(sg_page(sg));
2040 host->sg = sg = sg_next(sg);
2041 host->sg_len--;
2042 if (!sg || !host->sg_len)
2043 goto done;
2044
2045 offset = 4 - remaining;
2046 buf = sg_virt(sg);
2047 memcpy(buf, (u8 *)&value + remaining, offset);
2048 nbytes += offset;
2049 }
2050
2051 status = atmci_readl(host, ATMCI_SR);
2052 if (status & ATMCI_DATA_ERROR_FLAGS) {
2053 atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_RXRDY
2054 | ATMCI_DATA_ERROR_FLAGS));
2055 host->data_status = status;
2056 data->bytes_xfered += nbytes;
2057 return;
2058 }
2059 } while (status & ATMCI_RXRDY);
2060
2061 host->pio_offset = offset;
2062 data->bytes_xfered += nbytes;
2063
2064 return;
2065
2066done:
2067 atmci_writel(host, ATMCI_IDR, ATMCI_RXRDY);
2068 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
2069 data->bytes_xfered += nbytes;
2070 smp_wmb();
2071 atmci_set_pending(host, EVENT_XFER_COMPLETE);
2072}
2073
2074static void atmci_write_data_pio(struct atmel_mci *host)
2075{
2076 struct scatterlist *sg = host->sg;
2077 void *buf = sg_virt(sg);
2078 unsigned int offset = host->pio_offset;
2079 struct mmc_data *data = host->data;
2080 u32 value;
2081 u32 status;
2082 unsigned int nbytes = 0;
2083
2084 do {
2085 if (likely(offset + 4 <= sg->length)) {
2086 value = get_unaligned((u32 *)(buf + offset));
2087 atmci_writel(host, ATMCI_TDR, value);
2088
2089 offset += 4;
2090 nbytes += 4;
2091 if (offset == sg->length) {
2092 host->sg = sg = sg_next(sg);
2093 host->sg_len--;
2094 if (!sg || !host->sg_len)
2095 goto done;
2096
2097 offset = 0;
2098 buf = sg_virt(sg);
2099 }
2100 } else {
2101 unsigned int remaining = sg->length - offset;
2102
2103 value = 0;
2104 memcpy(&value, buf + offset, remaining);
2105 nbytes += remaining;
2106
2107 host->sg = sg = sg_next(sg);
2108 host->sg_len--;
2109 if (!sg || !host->sg_len) {
2110 atmci_writel(host, ATMCI_TDR, value);
2111 goto done;
2112 }
2113
2114 offset = 4 - remaining;
2115 buf = sg_virt(sg);
2116 memcpy((u8 *)&value + remaining, buf, offset);
2117 atmci_writel(host, ATMCI_TDR, value);
2118 nbytes += offset;
2119 }
2120
2121 status = atmci_readl(host, ATMCI_SR);
2122 if (status & ATMCI_DATA_ERROR_FLAGS) {
2123 atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_TXRDY
2124 | ATMCI_DATA_ERROR_FLAGS));
2125 host->data_status = status;
2126 data->bytes_xfered += nbytes;
2127 return;
2128 }
2129 } while (status & ATMCI_TXRDY);
2130
2131 host->pio_offset = offset;
2132 data->bytes_xfered += nbytes;
2133
2134 return;
2135
2136done:
2137 atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY);
2138 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
2139 data->bytes_xfered += nbytes;
2140 smp_wmb();
2141 atmci_set_pending(host, EVENT_XFER_COMPLETE);
2142}
2143
2144static void atmci_sdio_interrupt(struct atmel_mci *host, u32 status)
2145{
2146 int i;
2147
2148 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2149 struct atmel_mci_slot *slot = host->slot[i];
2150 if (slot && (status & slot->sdio_irq)) {
2151 mmc_signal_sdio_irq(slot->mmc);
2152 }
2153 }
2154}
2155
2156
2157static irqreturn_t atmci_interrupt(int irq, void *dev_id)
2158{
2159 struct atmel_mci *host = dev_id;
2160 u32 status, mask, pending;
2161 unsigned int pass_count = 0;
2162
2163 do {
2164 status = atmci_readl(host, ATMCI_SR);
2165 mask = atmci_readl(host, ATMCI_IMR);
2166 pending = status & mask;
2167 if (!pending)
2168 break;
2169
2170 if (pending & ATMCI_DATA_ERROR_FLAGS) {
2171 dev_dbg(&host->pdev->dev, "IRQ: data error\n");
2172 atmci_writel(host, ATMCI_IDR, ATMCI_DATA_ERROR_FLAGS
2173 | ATMCI_RXRDY | ATMCI_TXRDY
2174 | ATMCI_ENDRX | ATMCI_ENDTX
2175 | ATMCI_RXBUFF | ATMCI_TXBUFE);
2176
2177 host->data_status = status;
2178 dev_dbg(&host->pdev->dev, "set pending data error\n");
2179 smp_wmb();
2180 atmci_set_pending(host, EVENT_DATA_ERROR);
2181 tasklet_schedule(&host->tasklet);
2182 }
2183
2184 if (pending & ATMCI_TXBUFE) {
2185 dev_dbg(&host->pdev->dev, "IRQ: tx buffer empty\n");
2186 atmci_writel(host, ATMCI_IDR, ATMCI_TXBUFE);
2187 atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
2188 /*
2189 * We can receive this interruption before having configured
2190 * the second pdc buffer, so we need to reconfigure first and
2191 * second buffers again
2192 */
2193 if (host->data_size) {
2194 atmci_pdc_set_both_buf(host, XFER_TRANSMIT);
2195 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
2196 atmci_writel(host, ATMCI_IER, ATMCI_TXBUFE);
2197 } else {
2198 atmci_pdc_complete(host);
2199 }
2200 } else if (pending & ATMCI_ENDTX) {
2201 dev_dbg(&host->pdev->dev, "IRQ: end of tx buffer\n");
2202 atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
2203
2204 if (host->data_size) {
2205 atmci_pdc_set_single_buf(host,
2206 XFER_TRANSMIT, PDC_SECOND_BUF);
2207 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
2208 }
2209 }
2210
2211 if (pending & ATMCI_RXBUFF) {
2212 dev_dbg(&host->pdev->dev, "IRQ: rx buffer full\n");
2213 atmci_writel(host, ATMCI_IDR, ATMCI_RXBUFF);
2214 atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
2215 /*
2216 * We can receive this interruption before having configured
2217 * the second pdc buffer, so we need to reconfigure first and
2218 * second buffers again
2219 */
2220 if (host->data_size) {
2221 atmci_pdc_set_both_buf(host, XFER_RECEIVE);
2222 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
2223 atmci_writel(host, ATMCI_IER, ATMCI_RXBUFF);
2224 } else {
2225 atmci_pdc_complete(host);
2226 }
2227 } else if (pending & ATMCI_ENDRX) {
2228 dev_dbg(&host->pdev->dev, "IRQ: end of rx buffer\n");
2229 atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
2230
2231 if (host->data_size) {
2232 atmci_pdc_set_single_buf(host,
2233 XFER_RECEIVE, PDC_SECOND_BUF);
2234 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
2235 }
2236 }
2237
2238 /*
2239 * First mci IPs, so mainly the ones having pdc, have some
2240 * issues with the notbusy signal. You can't get it after
2241 * data transmission if you have not sent a stop command.
2242 * The appropriate workaround is to use the BLKE signal.
2243 */
2244 if (pending & ATMCI_BLKE) {
2245 dev_dbg(&host->pdev->dev, "IRQ: blke\n");
2246 atmci_writel(host, ATMCI_IDR, ATMCI_BLKE);
2247 smp_wmb();
2248 dev_dbg(&host->pdev->dev, "set pending notbusy\n");
2249 atmci_set_pending(host, EVENT_NOTBUSY);
2250 tasklet_schedule(&host->tasklet);
2251 }
2252
2253 if (pending & ATMCI_NOTBUSY) {
2254 dev_dbg(&host->pdev->dev, "IRQ: not_busy\n");
2255 atmci_writel(host, ATMCI_IDR, ATMCI_NOTBUSY);
2256 smp_wmb();
2257 dev_dbg(&host->pdev->dev, "set pending notbusy\n");
2258 atmci_set_pending(host, EVENT_NOTBUSY);
2259 tasklet_schedule(&host->tasklet);
2260 }
2261
2262 if (pending & ATMCI_RXRDY)
2263 atmci_read_data_pio(host);
2264 if (pending & ATMCI_TXRDY)
2265 atmci_write_data_pio(host);
2266
2267 if (pending & ATMCI_CMDRDY) {
2268 dev_dbg(&host->pdev->dev, "IRQ: cmd ready\n");
2269 atmci_writel(host, ATMCI_IDR, ATMCI_CMDRDY);
2270 host->cmd_status = status;
2271 smp_wmb();
2272 dev_dbg(&host->pdev->dev, "set pending cmd rdy\n");
2273 atmci_set_pending(host, EVENT_CMD_RDY);
2274 tasklet_schedule(&host->tasklet);
2275 }
2276
2277 if (pending & (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
2278 atmci_sdio_interrupt(host, status);
2279
2280 } while (pass_count++ < 5);
2281
2282 return pass_count ? IRQ_HANDLED : IRQ_NONE;
2283}
2284
2285static irqreturn_t atmci_detect_interrupt(int irq, void *dev_id)
2286{
2287 struct atmel_mci_slot *slot = dev_id;
2288
2289 /*
2290 * Disable interrupts until the pin has stabilized and check
2291 * the state then. Use mod_timer() since we may be in the
2292 * middle of the timer routine when this interrupt triggers.
2293 */
2294 disable_irq_nosync(irq);
2295 mod_timer(&slot->detect_timer, jiffies + msecs_to_jiffies(20));
2296
2297 return IRQ_HANDLED;
2298}
2299
2300static int atmci_init_slot(struct atmel_mci *host,
2301 struct mci_slot_pdata *slot_data, unsigned int id,
2302 u32 sdc_reg, u32 sdio_irq)
2303{
2304 struct mmc_host *mmc;
2305 struct atmel_mci_slot *slot;
2306
2307 mmc = mmc_alloc_host(sizeof(struct atmel_mci_slot), &host->pdev->dev);
2308 if (!mmc)
2309 return -ENOMEM;
2310
2311 slot = mmc_priv(mmc);
2312 slot->mmc = mmc;
2313 slot->host = host;
2314 slot->detect_pin = slot_data->detect_pin;
2315 slot->wp_pin = slot_data->wp_pin;
2316 slot->detect_is_active_high = slot_data->detect_is_active_high;
2317 slot->sdc_reg = sdc_reg;
2318 slot->sdio_irq = sdio_irq;
2319
2320 dev_dbg(&mmc->class_dev,
2321 "slot[%u]: bus_width=%u, detect_pin=%d, "
2322 "detect_is_active_high=%s, wp_pin=%d\n",
2323 id, slot_data->bus_width, slot_data->detect_pin,
2324 slot_data->detect_is_active_high ? "true" : "false",
2325 slot_data->wp_pin);
2326
2327 mmc->ops = &atmci_ops;
2328 mmc->f_min = DIV_ROUND_UP(host->bus_hz, 512);
2329 mmc->f_max = host->bus_hz / 2;
2330 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
2331 if (sdio_irq)
2332 mmc->caps |= MMC_CAP_SDIO_IRQ;
2333 if (host->caps.has_highspeed)
2334 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
2335 /*
2336 * Without the read/write proof capability, it is strongly suggested to
2337 * use only one bit for data to prevent fifo underruns and overruns
2338 * which will corrupt data.
2339 */
2340 if ((slot_data->bus_width >= 4) && host->caps.has_rwproof)
2341 mmc->caps |= MMC_CAP_4_BIT_DATA;
2342
2343 if (atmci_get_version(host) < 0x200) {
2344 mmc->max_segs = 256;
2345 mmc->max_blk_size = 4095;
2346 mmc->max_blk_count = 256;
2347 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2348 mmc->max_seg_size = mmc->max_blk_size * mmc->max_segs;
2349 } else {
2350 mmc->max_segs = 64;
2351 mmc->max_req_size = 32768 * 512;
2352 mmc->max_blk_size = 32768;
2353 mmc->max_blk_count = 512;
2354 }
2355
2356 /* Assume card is present initially */
2357 set_bit(ATMCI_CARD_PRESENT, &slot->flags);
2358 if (gpio_is_valid(slot->detect_pin)) {
2359 if (devm_gpio_request(&host->pdev->dev, slot->detect_pin,
2360 "mmc_detect")) {
2361 dev_dbg(&mmc->class_dev, "no detect pin available\n");
2362 slot->detect_pin = -EBUSY;
2363 } else if (gpio_get_value(slot->detect_pin) ^
2364 slot->detect_is_active_high) {
2365 clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
2366 }
2367 }
2368
2369 if (!gpio_is_valid(slot->detect_pin)) {
2370 if (slot_data->non_removable)
2371 mmc->caps |= MMC_CAP_NONREMOVABLE;
2372 else
2373 mmc->caps |= MMC_CAP_NEEDS_POLL;
2374 }
2375
2376 if (gpio_is_valid(slot->wp_pin)) {
2377 if (devm_gpio_request(&host->pdev->dev, slot->wp_pin,
2378 "mmc_wp")) {
2379 dev_dbg(&mmc->class_dev, "no WP pin available\n");
2380 slot->wp_pin = -EBUSY;
2381 }
2382 }
2383
2384 host->slot[id] = slot;
2385 mmc_regulator_get_supply(mmc);
2386 mmc_add_host(mmc);
2387
2388 if (gpio_is_valid(slot->detect_pin)) {
2389 int ret;
2390
2391 setup_timer(&slot->detect_timer, atmci_detect_change,
2392 (unsigned long)slot);
2393
2394 ret = request_irq(gpio_to_irq(slot->detect_pin),
2395 atmci_detect_interrupt,
2396 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
2397 "mmc-detect", slot);
2398 if (ret) {
2399 dev_dbg(&mmc->class_dev,
2400 "could not request IRQ %d for detect pin\n",
2401 gpio_to_irq(slot->detect_pin));
2402 slot->detect_pin = -EBUSY;
2403 }
2404 }
2405
2406 atmci_init_debugfs(slot);
2407
2408 return 0;
2409}
2410
2411static void atmci_cleanup_slot(struct atmel_mci_slot *slot,
2412 unsigned int id)
2413{
2414 /* Debugfs stuff is cleaned up by mmc core */
2415
2416 set_bit(ATMCI_SHUTDOWN, &slot->flags);
2417 smp_wmb();
2418
2419 mmc_remove_host(slot->mmc);
2420
2421 if (gpio_is_valid(slot->detect_pin)) {
2422 int pin = slot->detect_pin;
2423
2424 free_irq(gpio_to_irq(pin), slot);
2425 del_timer_sync(&slot->detect_timer);
2426 }
2427
2428 slot->host->slot[id] = NULL;
2429 mmc_free_host(slot->mmc);
2430}
2431
2432static int atmci_configure_dma(struct atmel_mci *host)
2433{
2434 host->dma.chan = dma_request_slave_channel_reason(&host->pdev->dev,
2435 "rxtx");
2436
2437 if (PTR_ERR(host->dma.chan) == -ENODEV) {
2438 struct mci_platform_data *pdata = host->pdev->dev.platform_data;
2439 dma_cap_mask_t mask;
2440
2441 if (!pdata || !pdata->dma_filter)
2442 return -ENODEV;
2443
2444 dma_cap_zero(mask);
2445 dma_cap_set(DMA_SLAVE, mask);
2446
2447 host->dma.chan = dma_request_channel(mask, pdata->dma_filter,
2448 pdata->dma_slave);
2449 if (!host->dma.chan)
2450 host->dma.chan = ERR_PTR(-ENODEV);
2451 }
2452
2453 if (IS_ERR(host->dma.chan))
2454 return PTR_ERR(host->dma.chan);
2455
2456 dev_info(&host->pdev->dev, "using %s for DMA transfers\n",
2457 dma_chan_name(host->dma.chan));
2458
2459 host->dma_conf.src_addr = host->mapbase + ATMCI_RDR;
2460 host->dma_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2461 host->dma_conf.src_maxburst = 1;
2462 host->dma_conf.dst_addr = host->mapbase + ATMCI_TDR;
2463 host->dma_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2464 host->dma_conf.dst_maxburst = 1;
2465 host->dma_conf.device_fc = false;
2466
2467 return 0;
2468}
2469
2470/*
2471 * HSMCI (High Speed MCI) module is not fully compatible with MCI module.
2472 * HSMCI provides DMA support and a new config register but no more supports
2473 * PDC.
2474 */
2475static void atmci_get_cap(struct atmel_mci *host)
2476{
2477 unsigned int version;
2478
2479 version = atmci_get_version(host);
2480 dev_info(&host->pdev->dev,
2481 "version: 0x%x\n", version);
2482
2483 host->caps.has_dma_conf_reg = 0;
2484 host->caps.has_pdc = ATMCI_PDC_CONNECTED;
2485 host->caps.has_cfg_reg = 0;
2486 host->caps.has_cstor_reg = 0;
2487 host->caps.has_highspeed = 0;
2488 host->caps.has_rwproof = 0;
2489 host->caps.has_odd_clk_div = 0;
2490 host->caps.has_bad_data_ordering = 1;
2491 host->caps.need_reset_after_xfer = 1;
2492 host->caps.need_blksz_mul_4 = 1;
2493 host->caps.need_notbusy_for_read_ops = 0;
2494
2495 /* keep only major version number */
2496 switch (version & 0xf00) {
2497 case 0x600:
2498 case 0x500:
2499 host->caps.has_odd_clk_div = 1;
2500 case 0x400:
2501 case 0x300:
2502 host->caps.has_dma_conf_reg = 1;
2503 host->caps.has_pdc = 0;
2504 host->caps.has_cfg_reg = 1;
2505 host->caps.has_cstor_reg = 1;
2506 host->caps.has_highspeed = 1;
2507 case 0x200:
2508 host->caps.has_rwproof = 1;
2509 host->caps.need_blksz_mul_4 = 0;
2510 host->caps.need_notbusy_for_read_ops = 1;
2511 case 0x100:
2512 host->caps.has_bad_data_ordering = 0;
2513 host->caps.need_reset_after_xfer = 0;
2514 case 0x0:
2515 break;
2516 default:
2517 host->caps.has_pdc = 0;
2518 dev_warn(&host->pdev->dev,
2519 "Unmanaged mci version, set minimum capabilities\n");
2520 break;
2521 }
2522}
2523
2524static int atmci_probe(struct platform_device *pdev)
2525{
2526 struct mci_platform_data *pdata;
2527 struct atmel_mci *host;
2528 struct resource *regs;
2529 unsigned int nr_slots;
2530 int irq;
2531 int ret, i;
2532
2533 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2534 if (!regs)
2535 return -ENXIO;
2536 pdata = pdev->dev.platform_data;
2537 if (!pdata) {
2538 pdata = atmci_of_init(pdev);
2539 if (IS_ERR(pdata)) {
2540 dev_err(&pdev->dev, "platform data not available\n");
2541 return PTR_ERR(pdata);
2542 }
2543 }
2544
2545 irq = platform_get_irq(pdev, 0);
2546 if (irq < 0)
2547 return irq;
2548
2549 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
2550 if (!host)
2551 return -ENOMEM;
2552
2553 host->pdev = pdev;
2554 spin_lock_init(&host->lock);
2555 INIT_LIST_HEAD(&host->queue);
2556
2557 host->mck = devm_clk_get(&pdev->dev, "mci_clk");
2558 if (IS_ERR(host->mck))
2559 return PTR_ERR(host->mck);
2560
2561 host->regs = devm_ioremap(&pdev->dev, regs->start, resource_size(regs));
2562 if (!host->regs)
2563 return -ENOMEM;
2564
2565 ret = clk_prepare_enable(host->mck);
2566 if (ret)
2567 return ret;
2568
2569 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
2570 host->bus_hz = clk_get_rate(host->mck);
2571
2572 host->mapbase = regs->start;
2573
2574 tasklet_init(&host->tasklet, atmci_tasklet_func, (unsigned long)host);
2575
2576 ret = request_irq(irq, atmci_interrupt, 0, dev_name(&pdev->dev), host);
2577 if (ret) {
2578 clk_disable_unprepare(host->mck);
2579 return ret;
2580 }
2581
2582 /* Get MCI capabilities and set operations according to it */
2583 atmci_get_cap(host);
2584 ret = atmci_configure_dma(host);
2585 if (ret == -EPROBE_DEFER)
2586 goto err_dma_probe_defer;
2587 if (ret == 0) {
2588 host->prepare_data = &atmci_prepare_data_dma;
2589 host->submit_data = &atmci_submit_data_dma;
2590 host->stop_transfer = &atmci_stop_transfer_dma;
2591 } else if (host->caps.has_pdc) {
2592 dev_info(&pdev->dev, "using PDC\n");
2593 host->prepare_data = &atmci_prepare_data_pdc;
2594 host->submit_data = &atmci_submit_data_pdc;
2595 host->stop_transfer = &atmci_stop_transfer_pdc;
2596 } else {
2597 dev_info(&pdev->dev, "using PIO\n");
2598 host->prepare_data = &atmci_prepare_data;
2599 host->submit_data = &atmci_submit_data;
2600 host->stop_transfer = &atmci_stop_transfer;
2601 }
2602
2603 platform_set_drvdata(pdev, host);
2604
2605 setup_timer(&host->timer, atmci_timeout_timer, (unsigned long)host);
2606
2607 pm_runtime_get_noresume(&pdev->dev);
2608 pm_runtime_set_active(&pdev->dev);
2609 pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_DELAY);
2610 pm_runtime_use_autosuspend(&pdev->dev);
2611 pm_runtime_enable(&pdev->dev);
2612
2613 /* We need at least one slot to succeed */
2614 nr_slots = 0;
2615 ret = -ENODEV;
2616 if (pdata->slot[0].bus_width) {
2617 ret = atmci_init_slot(host, &pdata->slot[0],
2618 0, ATMCI_SDCSEL_SLOT_A, ATMCI_SDIOIRQA);
2619 if (!ret) {
2620 nr_slots++;
2621 host->buf_size = host->slot[0]->mmc->max_req_size;
2622 }
2623 }
2624 if (pdata->slot[1].bus_width) {
2625 ret = atmci_init_slot(host, &pdata->slot[1],
2626 1, ATMCI_SDCSEL_SLOT_B, ATMCI_SDIOIRQB);
2627 if (!ret) {
2628 nr_slots++;
2629 if (host->slot[1]->mmc->max_req_size > host->buf_size)
2630 host->buf_size =
2631 host->slot[1]->mmc->max_req_size;
2632 }
2633 }
2634
2635 if (!nr_slots) {
2636 dev_err(&pdev->dev, "init failed: no slot defined\n");
2637 goto err_init_slot;
2638 }
2639
2640 if (!host->caps.has_rwproof) {
2641 host->buffer = dma_alloc_coherent(&pdev->dev, host->buf_size,
2642 &host->buf_phys_addr,
2643 GFP_KERNEL);
2644 if (!host->buffer) {
2645 ret = -ENOMEM;
2646 dev_err(&pdev->dev, "buffer allocation failed\n");
2647 goto err_dma_alloc;
2648 }
2649 }
2650
2651 dev_info(&pdev->dev,
2652 "Atmel MCI controller at 0x%08lx irq %d, %u slots\n",
2653 host->mapbase, irq, nr_slots);
2654
2655 pm_runtime_mark_last_busy(&host->pdev->dev);
2656 pm_runtime_put_autosuspend(&pdev->dev);
2657
2658 return 0;
2659
2660err_dma_alloc:
2661 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2662 if (host->slot[i])
2663 atmci_cleanup_slot(host->slot[i], i);
2664 }
2665err_init_slot:
2666 clk_disable_unprepare(host->mck);
2667
2668 pm_runtime_disable(&pdev->dev);
2669 pm_runtime_put_noidle(&pdev->dev);
2670
2671 del_timer_sync(&host->timer);
2672 if (!IS_ERR(host->dma.chan))
2673 dma_release_channel(host->dma.chan);
2674err_dma_probe_defer:
2675 free_irq(irq, host);
2676 return ret;
2677}
2678
2679static int atmci_remove(struct platform_device *pdev)
2680{
2681 struct atmel_mci *host = platform_get_drvdata(pdev);
2682 unsigned int i;
2683
2684 pm_runtime_get_sync(&pdev->dev);
2685
2686 if (host->buffer)
2687 dma_free_coherent(&pdev->dev, host->buf_size,
2688 host->buffer, host->buf_phys_addr);
2689
2690 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2691 if (host->slot[i])
2692 atmci_cleanup_slot(host->slot[i], i);
2693 }
2694
2695 atmci_writel(host, ATMCI_IDR, ~0UL);
2696 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
2697 atmci_readl(host, ATMCI_SR);
2698
2699 del_timer_sync(&host->timer);
2700 if (!IS_ERR(host->dma.chan))
2701 dma_release_channel(host->dma.chan);
2702
2703 free_irq(platform_get_irq(pdev, 0), host);
2704
2705 clk_disable_unprepare(host->mck);
2706
2707 pm_runtime_disable(&pdev->dev);
2708 pm_runtime_put_noidle(&pdev->dev);
2709
2710 return 0;
2711}
2712
2713#ifdef CONFIG_PM
2714static int atmci_runtime_suspend(struct device *dev)
2715{
2716 struct atmel_mci *host = dev_get_drvdata(dev);
2717
2718 clk_disable_unprepare(host->mck);
2719
2720 pinctrl_pm_select_sleep_state(dev);
2721
2722 return 0;
2723}
2724
2725static int atmci_runtime_resume(struct device *dev)
2726{
2727 struct atmel_mci *host = dev_get_drvdata(dev);
2728
2729 pinctrl_pm_select_default_state(dev);
2730
2731 return clk_prepare_enable(host->mck);
2732}
2733#endif
2734
2735static const struct dev_pm_ops atmci_dev_pm_ops = {
2736 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
2737 pm_runtime_force_resume)
2738 SET_RUNTIME_PM_OPS(atmci_runtime_suspend, atmci_runtime_resume, NULL)
2739};
2740
2741static struct platform_driver atmci_driver = {
2742 .probe = atmci_probe,
2743 .remove = atmci_remove,
2744 .driver = {
2745 .name = "atmel_mci",
2746 .of_match_table = of_match_ptr(atmci_dt_ids),
2747 .pm = &atmci_dev_pm_ops,
2748 },
2749};
2750module_platform_driver(atmci_driver);
2751
2752MODULE_DESCRIPTION("Atmel Multimedia Card Interface driver");
2753MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
2754MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Atmel MultiMedia Card Interface driver
4 *
5 * Copyright (C) 2004-2008 Atmel Corporation
6 */
7#include <linux/blkdev.h>
8#include <linux/clk.h>
9#include <linux/debugfs.h>
10#include <linux/device.h>
11#include <linux/dmaengine.h>
12#include <linux/dma-mapping.h>
13#include <linux/err.h>
14#include <linux/gpio.h>
15#include <linux/init.h>
16#include <linux/interrupt.h>
17#include <linux/io.h>
18#include <linux/ioport.h>
19#include <linux/module.h>
20#include <linux/of.h>
21#include <linux/of_device.h>
22#include <linux/of_gpio.h>
23#include <linux/platform_device.h>
24#include <linux/scatterlist.h>
25#include <linux/seq_file.h>
26#include <linux/slab.h>
27#include <linux/stat.h>
28#include <linux/types.h>
29
30#include <linux/mmc/host.h>
31#include <linux/mmc/sdio.h>
32
33#include <linux/atmel-mci.h>
34#include <linux/atmel_pdc.h>
35#include <linux/pm.h>
36#include <linux/pm_runtime.h>
37#include <linux/pinctrl/consumer.h>
38
39#include <asm/cacheflush.h>
40#include <asm/io.h>
41#include <asm/unaligned.h>
42
43/*
44 * Superset of MCI IP registers integrated in Atmel AT91 Processor
45 * Registers and bitfields marked with [2] are only available in MCI2
46 */
47
48/* MCI Register Definitions */
49#define ATMCI_CR 0x0000 /* Control */
50#define ATMCI_CR_MCIEN BIT(0) /* MCI Enable */
51#define ATMCI_CR_MCIDIS BIT(1) /* MCI Disable */
52#define ATMCI_CR_PWSEN BIT(2) /* Power Save Enable */
53#define ATMCI_CR_PWSDIS BIT(3) /* Power Save Disable */
54#define ATMCI_CR_SWRST BIT(7) /* Software Reset */
55#define ATMCI_MR 0x0004 /* Mode */
56#define ATMCI_MR_CLKDIV(x) ((x) << 0) /* Clock Divider */
57#define ATMCI_MR_PWSDIV(x) ((x) << 8) /* Power Saving Divider */
58#define ATMCI_MR_RDPROOF BIT(11) /* Read Proof */
59#define ATMCI_MR_WRPROOF BIT(12) /* Write Proof */
60#define ATMCI_MR_PDCFBYTE BIT(13) /* Force Byte Transfer */
61#define ATMCI_MR_PDCPADV BIT(14) /* Padding Value */
62#define ATMCI_MR_PDCMODE BIT(15) /* PDC-oriented Mode */
63#define ATMCI_MR_CLKODD(x) ((x) << 16) /* LSB of Clock Divider */
64#define ATMCI_DTOR 0x0008 /* Data Timeout */
65#define ATMCI_DTOCYC(x) ((x) << 0) /* Data Timeout Cycles */
66#define ATMCI_DTOMUL(x) ((x) << 4) /* Data Timeout Multiplier */
67#define ATMCI_SDCR 0x000c /* SD Card / SDIO */
68#define ATMCI_SDCSEL_SLOT_A (0 << 0) /* Select SD slot A */
69#define ATMCI_SDCSEL_SLOT_B (1 << 0) /* Select SD slot A */
70#define ATMCI_SDCSEL_MASK (3 << 0)
71#define ATMCI_SDCBUS_1BIT (0 << 6) /* 1-bit data bus */
72#define ATMCI_SDCBUS_4BIT (2 << 6) /* 4-bit data bus */
73#define ATMCI_SDCBUS_8BIT (3 << 6) /* 8-bit data bus[2] */
74#define ATMCI_SDCBUS_MASK (3 << 6)
75#define ATMCI_ARGR 0x0010 /* Command Argument */
76#define ATMCI_CMDR 0x0014 /* Command */
77#define ATMCI_CMDR_CMDNB(x) ((x) << 0) /* Command Opcode */
78#define ATMCI_CMDR_RSPTYP_NONE (0 << 6) /* No response */
79#define ATMCI_CMDR_RSPTYP_48BIT (1 << 6) /* 48-bit response */
80#define ATMCI_CMDR_RSPTYP_136BIT (2 << 6) /* 136-bit response */
81#define ATMCI_CMDR_SPCMD_INIT (1 << 8) /* Initialization command */
82#define ATMCI_CMDR_SPCMD_SYNC (2 << 8) /* Synchronized command */
83#define ATMCI_CMDR_SPCMD_INT (4 << 8) /* Interrupt command */
84#define ATMCI_CMDR_SPCMD_INTRESP (5 << 8) /* Interrupt response */
85#define ATMCI_CMDR_OPDCMD (1 << 11) /* Open Drain */
86#define ATMCI_CMDR_MAXLAT_5CYC (0 << 12) /* Max latency 5 cycles */
87#define ATMCI_CMDR_MAXLAT_64CYC (1 << 12) /* Max latency 64 cycles */
88#define ATMCI_CMDR_START_XFER (1 << 16) /* Start data transfer */
89#define ATMCI_CMDR_STOP_XFER (2 << 16) /* Stop data transfer */
90#define ATMCI_CMDR_TRDIR_WRITE (0 << 18) /* Write data */
91#define ATMCI_CMDR_TRDIR_READ (1 << 18) /* Read data */
92#define ATMCI_CMDR_BLOCK (0 << 19) /* Single-block transfer */
93#define ATMCI_CMDR_MULTI_BLOCK (1 << 19) /* Multi-block transfer */
94#define ATMCI_CMDR_STREAM (2 << 19) /* MMC Stream transfer */
95#define ATMCI_CMDR_SDIO_BYTE (4 << 19) /* SDIO Byte transfer */
96#define ATMCI_CMDR_SDIO_BLOCK (5 << 19) /* SDIO Block transfer */
97#define ATMCI_CMDR_SDIO_SUSPEND (1 << 24) /* SDIO Suspend Command */
98#define ATMCI_CMDR_SDIO_RESUME (2 << 24) /* SDIO Resume Command */
99#define ATMCI_BLKR 0x0018 /* Block */
100#define ATMCI_BCNT(x) ((x) << 0) /* Data Block Count */
101#define ATMCI_BLKLEN(x) ((x) << 16) /* Data Block Length */
102#define ATMCI_CSTOR 0x001c /* Completion Signal Timeout[2] */
103#define ATMCI_CSTOCYC(x) ((x) << 0) /* CST cycles */
104#define ATMCI_CSTOMUL(x) ((x) << 4) /* CST multiplier */
105#define ATMCI_RSPR 0x0020 /* Response 0 */
106#define ATMCI_RSPR1 0x0024 /* Response 1 */
107#define ATMCI_RSPR2 0x0028 /* Response 2 */
108#define ATMCI_RSPR3 0x002c /* Response 3 */
109#define ATMCI_RDR 0x0030 /* Receive Data */
110#define ATMCI_TDR 0x0034 /* Transmit Data */
111#define ATMCI_SR 0x0040 /* Status */
112#define ATMCI_IER 0x0044 /* Interrupt Enable */
113#define ATMCI_IDR 0x0048 /* Interrupt Disable */
114#define ATMCI_IMR 0x004c /* Interrupt Mask */
115#define ATMCI_CMDRDY BIT(0) /* Command Ready */
116#define ATMCI_RXRDY BIT(1) /* Receiver Ready */
117#define ATMCI_TXRDY BIT(2) /* Transmitter Ready */
118#define ATMCI_BLKE BIT(3) /* Data Block Ended */
119#define ATMCI_DTIP BIT(4) /* Data Transfer In Progress */
120#define ATMCI_NOTBUSY BIT(5) /* Data Not Busy */
121#define ATMCI_ENDRX BIT(6) /* End of RX Buffer */
122#define ATMCI_ENDTX BIT(7) /* End of TX Buffer */
123#define ATMCI_SDIOIRQA BIT(8) /* SDIO IRQ in slot A */
124#define ATMCI_SDIOIRQB BIT(9) /* SDIO IRQ in slot B */
125#define ATMCI_SDIOWAIT BIT(12) /* SDIO Read Wait Operation Status */
126#define ATMCI_CSRCV BIT(13) /* CE-ATA Completion Signal Received */
127#define ATMCI_RXBUFF BIT(14) /* RX Buffer Full */
128#define ATMCI_TXBUFE BIT(15) /* TX Buffer Empty */
129#define ATMCI_RINDE BIT(16) /* Response Index Error */
130#define ATMCI_RDIRE BIT(17) /* Response Direction Error */
131#define ATMCI_RCRCE BIT(18) /* Response CRC Error */
132#define ATMCI_RENDE BIT(19) /* Response End Bit Error */
133#define ATMCI_RTOE BIT(20) /* Response Time-Out Error */
134#define ATMCI_DCRCE BIT(21) /* Data CRC Error */
135#define ATMCI_DTOE BIT(22) /* Data Time-Out Error */
136#define ATMCI_CSTOE BIT(23) /* Completion Signal Time-out Error */
137#define ATMCI_BLKOVRE BIT(24) /* DMA Block Overrun Error */
138#define ATMCI_DMADONE BIT(25) /* DMA Transfer Done */
139#define ATMCI_FIFOEMPTY BIT(26) /* FIFO Empty Flag */
140#define ATMCI_XFRDONE BIT(27) /* Transfer Done Flag */
141#define ATMCI_ACKRCV BIT(28) /* Boot Operation Acknowledge Received */
142#define ATMCI_ACKRCVE BIT(29) /* Boot Operation Acknowledge Error */
143#define ATMCI_OVRE BIT(30) /* RX Overrun Error */
144#define ATMCI_UNRE BIT(31) /* TX Underrun Error */
145#define ATMCI_DMA 0x0050 /* DMA Configuration[2] */
146#define ATMCI_DMA_OFFSET(x) ((x) << 0) /* DMA Write Buffer Offset */
147#define ATMCI_DMA_CHKSIZE(x) ((x) << 4) /* DMA Channel Read and Write Chunk Size */
148#define ATMCI_DMAEN BIT(8) /* DMA Hardware Handshaking Enable */
149#define ATMCI_CFG 0x0054 /* Configuration[2] */
150#define ATMCI_CFG_FIFOMODE_1DATA BIT(0) /* MCI Internal FIFO control mode */
151#define ATMCI_CFG_FERRCTRL_COR BIT(4) /* Flow Error flag reset control mode */
152#define ATMCI_CFG_HSMODE BIT(8) /* High Speed Mode */
153#define ATMCI_CFG_LSYNC BIT(12) /* Synchronize on the last block */
154#define ATMCI_WPMR 0x00e4 /* Write Protection Mode[2] */
155#define ATMCI_WP_EN BIT(0) /* WP Enable */
156#define ATMCI_WP_KEY (0x4d4349 << 8) /* WP Key */
157#define ATMCI_WPSR 0x00e8 /* Write Protection Status[2] */
158#define ATMCI_GET_WP_VS(x) ((x) & 0x0f)
159#define ATMCI_GET_WP_VSRC(x) (((x) >> 8) & 0xffff)
160#define ATMCI_VERSION 0x00FC /* Version */
161#define ATMCI_FIFO_APERTURE 0x0200 /* FIFO Aperture[2] */
162
163/* This is not including the FIFO Aperture on MCI2 */
164#define ATMCI_REGS_SIZE 0x100
165
166/* Register access macros */
167#define atmci_readl(port, reg) \
168 __raw_readl((port)->regs + reg)
169#define atmci_writel(port, reg, value) \
170 __raw_writel((value), (port)->regs + reg)
171
172#define ATMCI_CMD_TIMEOUT_MS 2000
173#define AUTOSUSPEND_DELAY 50
174
175#define ATMCI_DATA_ERROR_FLAGS (ATMCI_DCRCE | ATMCI_DTOE | ATMCI_OVRE | ATMCI_UNRE)
176#define ATMCI_DMA_THRESHOLD 16
177
178enum {
179 EVENT_CMD_RDY = 0,
180 EVENT_XFER_COMPLETE,
181 EVENT_NOTBUSY,
182 EVENT_DATA_ERROR,
183};
184
185enum atmel_mci_state {
186 STATE_IDLE = 0,
187 STATE_SENDING_CMD,
188 STATE_DATA_XFER,
189 STATE_WAITING_NOTBUSY,
190 STATE_SENDING_STOP,
191 STATE_END_REQUEST,
192};
193
194enum atmci_xfer_dir {
195 XFER_RECEIVE = 0,
196 XFER_TRANSMIT,
197};
198
199enum atmci_pdc_buf {
200 PDC_FIRST_BUF = 0,
201 PDC_SECOND_BUF,
202};
203
204struct atmel_mci_caps {
205 bool has_dma_conf_reg;
206 bool has_pdc;
207 bool has_cfg_reg;
208 bool has_cstor_reg;
209 bool has_highspeed;
210 bool has_rwproof;
211 bool has_odd_clk_div;
212 bool has_bad_data_ordering;
213 bool need_reset_after_xfer;
214 bool need_blksz_mul_4;
215 bool need_notbusy_for_read_ops;
216};
217
218struct atmel_mci_dma {
219 struct dma_chan *chan;
220 struct dma_async_tx_descriptor *data_desc;
221};
222
223/**
224 * struct atmel_mci - MMC controller state shared between all slots
225 * @lock: Spinlock protecting the queue and associated data.
226 * @regs: Pointer to MMIO registers.
227 * @sg: Scatterlist entry currently being processed by PIO or PDC code.
228 * @sg_len: Size of the scatterlist
229 * @pio_offset: Offset into the current scatterlist entry.
230 * @buffer: Buffer used if we don't have the r/w proof capability. We
231 * don't have the time to switch pdc buffers so we have to use only
232 * one buffer for the full transaction.
233 * @buf_size: size of the buffer.
234 * @buf_phys_addr: buffer address needed for pdc.
235 * @cur_slot: The slot which is currently using the controller.
236 * @mrq: The request currently being processed on @cur_slot,
237 * or NULL if the controller is idle.
238 * @cmd: The command currently being sent to the card, or NULL.
239 * @data: The data currently being transferred, or NULL if no data
240 * transfer is in progress.
241 * @data_size: just data->blocks * data->blksz.
242 * @dma: DMA client state.
243 * @data_chan: DMA channel being used for the current data transfer.
244 * @dma_conf: Configuration for the DMA slave
245 * @cmd_status: Snapshot of SR taken upon completion of the current
246 * command. Only valid when EVENT_CMD_COMPLETE is pending.
247 * @data_status: Snapshot of SR taken upon completion of the current
248 * data transfer. Only valid when EVENT_DATA_COMPLETE or
249 * EVENT_DATA_ERROR is pending.
250 * @stop_cmdr: Value to be loaded into CMDR when the stop command is
251 * to be sent.
252 * @tasklet: Tasklet running the request state machine.
253 * @pending_events: Bitmask of events flagged by the interrupt handler
254 * to be processed by the tasklet.
255 * @completed_events: Bitmask of events which the state machine has
256 * processed.
257 * @state: Tasklet state.
258 * @queue: List of slots waiting for access to the controller.
259 * @need_clock_update: Update the clock rate before the next request.
260 * @need_reset: Reset controller before next request.
261 * @timer: Timer to balance the data timeout error flag which cannot rise.
262 * @mode_reg: Value of the MR register.
263 * @cfg_reg: Value of the CFG register.
264 * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
265 * rate and timeout calculations.
266 * @mapbase: Physical address of the MMIO registers.
267 * @mck: The peripheral bus clock hooked up to the MMC controller.
268 * @pdev: Platform device associated with the MMC controller.
269 * @slot: Slots sharing this MMC controller.
270 * @caps: MCI capabilities depending on MCI version.
271 * @prepare_data: function to setup MCI before data transfer which
272 * depends on MCI capabilities.
273 * @submit_data: function to start data transfer which depends on MCI
274 * capabilities.
275 * @stop_transfer: function to stop data transfer which depends on MCI
276 * capabilities.
277 *
278 * Locking
279 * =======
280 *
281 * @lock is a softirq-safe spinlock protecting @queue as well as
282 * @cur_slot, @mrq and @state. These must always be updated
283 * at the same time while holding @lock.
284 *
285 * @lock also protects mode_reg and need_clock_update since these are
286 * used to synchronize mode register updates with the queue
287 * processing.
288 *
289 * The @mrq field of struct atmel_mci_slot is also protected by @lock,
290 * and must always be written at the same time as the slot is added to
291 * @queue.
292 *
293 * @pending_events and @completed_events are accessed using atomic bit
294 * operations, so they don't need any locking.
295 *
296 * None of the fields touched by the interrupt handler need any
297 * locking. However, ordering is important: Before EVENT_DATA_ERROR or
298 * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
299 * interrupts must be disabled and @data_status updated with a
300 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
301 * CMDRDY interrupt must be disabled and @cmd_status updated with a
302 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
303 * bytes_xfered field of @data must be written. This is ensured by
304 * using barriers.
305 */
306struct atmel_mci {
307 spinlock_t lock;
308 void __iomem *regs;
309
310 struct scatterlist *sg;
311 unsigned int sg_len;
312 unsigned int pio_offset;
313 unsigned int *buffer;
314 unsigned int buf_size;
315 dma_addr_t buf_phys_addr;
316
317 struct atmel_mci_slot *cur_slot;
318 struct mmc_request *mrq;
319 struct mmc_command *cmd;
320 struct mmc_data *data;
321 unsigned int data_size;
322
323 struct atmel_mci_dma dma;
324 struct dma_chan *data_chan;
325 struct dma_slave_config dma_conf;
326
327 u32 cmd_status;
328 u32 data_status;
329 u32 stop_cmdr;
330
331 struct tasklet_struct tasklet;
332 unsigned long pending_events;
333 unsigned long completed_events;
334 enum atmel_mci_state state;
335 struct list_head queue;
336
337 bool need_clock_update;
338 bool need_reset;
339 struct timer_list timer;
340 u32 mode_reg;
341 u32 cfg_reg;
342 unsigned long bus_hz;
343 unsigned long mapbase;
344 struct clk *mck;
345 struct platform_device *pdev;
346
347 struct atmel_mci_slot *slot[ATMCI_MAX_NR_SLOTS];
348
349 struct atmel_mci_caps caps;
350
351 u32 (*prepare_data)(struct atmel_mci *host, struct mmc_data *data);
352 void (*submit_data)(struct atmel_mci *host, struct mmc_data *data);
353 void (*stop_transfer)(struct atmel_mci *host);
354};
355
356/**
357 * struct atmel_mci_slot - MMC slot state
358 * @mmc: The mmc_host representing this slot.
359 * @host: The MMC controller this slot is using.
360 * @sdc_reg: Value of SDCR to be written before using this slot.
361 * @sdio_irq: SDIO irq mask for this slot.
362 * @mrq: mmc_request currently being processed or waiting to be
363 * processed, or NULL when the slot is idle.
364 * @queue_node: List node for placing this node in the @queue list of
365 * &struct atmel_mci.
366 * @clock: Clock rate configured by set_ios(). Protected by host->lock.
367 * @flags: Random state bits associated with the slot.
368 * @detect_pin: GPIO pin used for card detection, or negative if not
369 * available.
370 * @wp_pin: GPIO pin used for card write protect sending, or negative
371 * if not available.
372 * @detect_is_active_high: The state of the detect pin when it is active.
373 * @detect_timer: Timer used for debouncing @detect_pin interrupts.
374 */
375struct atmel_mci_slot {
376 struct mmc_host *mmc;
377 struct atmel_mci *host;
378
379 u32 sdc_reg;
380 u32 sdio_irq;
381
382 struct mmc_request *mrq;
383 struct list_head queue_node;
384
385 unsigned int clock;
386 unsigned long flags;
387#define ATMCI_CARD_PRESENT 0
388#define ATMCI_CARD_NEED_INIT 1
389#define ATMCI_SHUTDOWN 2
390
391 int detect_pin;
392 int wp_pin;
393 bool detect_is_active_high;
394
395 struct timer_list detect_timer;
396};
397
398#define atmci_test_and_clear_pending(host, event) \
399 test_and_clear_bit(event, &host->pending_events)
400#define atmci_set_completed(host, event) \
401 set_bit(event, &host->completed_events)
402#define atmci_set_pending(host, event) \
403 set_bit(event, &host->pending_events)
404
405/*
406 * The debugfs stuff below is mostly optimized away when
407 * CONFIG_DEBUG_FS is not set.
408 */
409static int atmci_req_show(struct seq_file *s, void *v)
410{
411 struct atmel_mci_slot *slot = s->private;
412 struct mmc_request *mrq;
413 struct mmc_command *cmd;
414 struct mmc_command *stop;
415 struct mmc_data *data;
416
417 /* Make sure we get a consistent snapshot */
418 spin_lock_bh(&slot->host->lock);
419 mrq = slot->mrq;
420
421 if (mrq) {
422 cmd = mrq->cmd;
423 data = mrq->data;
424 stop = mrq->stop;
425
426 if (cmd)
427 seq_printf(s,
428 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
429 cmd->opcode, cmd->arg, cmd->flags,
430 cmd->resp[0], cmd->resp[1], cmd->resp[2],
431 cmd->resp[3], cmd->error);
432 if (data)
433 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
434 data->bytes_xfered, data->blocks,
435 data->blksz, data->flags, data->error);
436 if (stop)
437 seq_printf(s,
438 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
439 stop->opcode, stop->arg, stop->flags,
440 stop->resp[0], stop->resp[1], stop->resp[2],
441 stop->resp[3], stop->error);
442 }
443
444 spin_unlock_bh(&slot->host->lock);
445
446 return 0;
447}
448
449DEFINE_SHOW_ATTRIBUTE(atmci_req);
450
451static void atmci_show_status_reg(struct seq_file *s,
452 const char *regname, u32 value)
453{
454 static const char *sr_bit[] = {
455 [0] = "CMDRDY",
456 [1] = "RXRDY",
457 [2] = "TXRDY",
458 [3] = "BLKE",
459 [4] = "DTIP",
460 [5] = "NOTBUSY",
461 [6] = "ENDRX",
462 [7] = "ENDTX",
463 [8] = "SDIOIRQA",
464 [9] = "SDIOIRQB",
465 [12] = "SDIOWAIT",
466 [14] = "RXBUFF",
467 [15] = "TXBUFE",
468 [16] = "RINDE",
469 [17] = "RDIRE",
470 [18] = "RCRCE",
471 [19] = "RENDE",
472 [20] = "RTOE",
473 [21] = "DCRCE",
474 [22] = "DTOE",
475 [23] = "CSTOE",
476 [24] = "BLKOVRE",
477 [25] = "DMADONE",
478 [26] = "FIFOEMPTY",
479 [27] = "XFRDONE",
480 [30] = "OVRE",
481 [31] = "UNRE",
482 };
483 unsigned int i;
484
485 seq_printf(s, "%s:\t0x%08x", regname, value);
486 for (i = 0; i < ARRAY_SIZE(sr_bit); i++) {
487 if (value & (1 << i)) {
488 if (sr_bit[i])
489 seq_printf(s, " %s", sr_bit[i]);
490 else
491 seq_puts(s, " UNKNOWN");
492 }
493 }
494 seq_putc(s, '\n');
495}
496
497static int atmci_regs_show(struct seq_file *s, void *v)
498{
499 struct atmel_mci *host = s->private;
500 u32 *buf;
501 int ret = 0;
502
503
504 buf = kmalloc(ATMCI_REGS_SIZE, GFP_KERNEL);
505 if (!buf)
506 return -ENOMEM;
507
508 pm_runtime_get_sync(&host->pdev->dev);
509
510 /*
511 * Grab a more or less consistent snapshot. Note that we're
512 * not disabling interrupts, so IMR and SR may not be
513 * consistent.
514 */
515 spin_lock_bh(&host->lock);
516 memcpy_fromio(buf, host->regs, ATMCI_REGS_SIZE);
517 spin_unlock_bh(&host->lock);
518
519 pm_runtime_mark_last_busy(&host->pdev->dev);
520 pm_runtime_put_autosuspend(&host->pdev->dev);
521
522 seq_printf(s, "MR:\t0x%08x%s%s ",
523 buf[ATMCI_MR / 4],
524 buf[ATMCI_MR / 4] & ATMCI_MR_RDPROOF ? " RDPROOF" : "",
525 buf[ATMCI_MR / 4] & ATMCI_MR_WRPROOF ? " WRPROOF" : "");
526 if (host->caps.has_odd_clk_div)
527 seq_printf(s, "{CLKDIV,CLKODD}=%u\n",
528 ((buf[ATMCI_MR / 4] & 0xff) << 1)
529 | ((buf[ATMCI_MR / 4] >> 16) & 1));
530 else
531 seq_printf(s, "CLKDIV=%u\n",
532 (buf[ATMCI_MR / 4] & 0xff));
533 seq_printf(s, "DTOR:\t0x%08x\n", buf[ATMCI_DTOR / 4]);
534 seq_printf(s, "SDCR:\t0x%08x\n", buf[ATMCI_SDCR / 4]);
535 seq_printf(s, "ARGR:\t0x%08x\n", buf[ATMCI_ARGR / 4]);
536 seq_printf(s, "BLKR:\t0x%08x BCNT=%u BLKLEN=%u\n",
537 buf[ATMCI_BLKR / 4],
538 buf[ATMCI_BLKR / 4] & 0xffff,
539 (buf[ATMCI_BLKR / 4] >> 16) & 0xffff);
540 if (host->caps.has_cstor_reg)
541 seq_printf(s, "CSTOR:\t0x%08x\n", buf[ATMCI_CSTOR / 4]);
542
543 /* Don't read RSPR and RDR; it will consume the data there */
544
545 atmci_show_status_reg(s, "SR", buf[ATMCI_SR / 4]);
546 atmci_show_status_reg(s, "IMR", buf[ATMCI_IMR / 4]);
547
548 if (host->caps.has_dma_conf_reg) {
549 u32 val;
550
551 val = buf[ATMCI_DMA / 4];
552 seq_printf(s, "DMA:\t0x%08x OFFSET=%u CHKSIZE=%u%s\n",
553 val, val & 3,
554 ((val >> 4) & 3) ?
555 1 << (((val >> 4) & 3) + 1) : 1,
556 val & ATMCI_DMAEN ? " DMAEN" : "");
557 }
558 if (host->caps.has_cfg_reg) {
559 u32 val;
560
561 val = buf[ATMCI_CFG / 4];
562 seq_printf(s, "CFG:\t0x%08x%s%s%s%s\n",
563 val,
564 val & ATMCI_CFG_FIFOMODE_1DATA ? " FIFOMODE_ONE_DATA" : "",
565 val & ATMCI_CFG_FERRCTRL_COR ? " FERRCTRL_CLEAR_ON_READ" : "",
566 val & ATMCI_CFG_HSMODE ? " HSMODE" : "",
567 val & ATMCI_CFG_LSYNC ? " LSYNC" : "");
568 }
569
570 kfree(buf);
571
572 return ret;
573}
574
575DEFINE_SHOW_ATTRIBUTE(atmci_regs);
576
577static void atmci_init_debugfs(struct atmel_mci_slot *slot)
578{
579 struct mmc_host *mmc = slot->mmc;
580 struct atmel_mci *host = slot->host;
581 struct dentry *root;
582
583 root = mmc->debugfs_root;
584 if (!root)
585 return;
586
587 debugfs_create_file("regs", S_IRUSR, root, host, &atmci_regs_fops);
588 debugfs_create_file("req", S_IRUSR, root, slot, &atmci_req_fops);
589 debugfs_create_u32("state", S_IRUSR, root, &host->state);
590 debugfs_create_xul("pending_events", S_IRUSR, root,
591 &host->pending_events);
592 debugfs_create_xul("completed_events", S_IRUSR, root,
593 &host->completed_events);
594}
595
596#if defined(CONFIG_OF)
597static const struct of_device_id atmci_dt_ids[] = {
598 { .compatible = "atmel,hsmci" },
599 { /* sentinel */ }
600};
601
602MODULE_DEVICE_TABLE(of, atmci_dt_ids);
603
604static struct mci_platform_data*
605atmci_of_init(struct platform_device *pdev)
606{
607 struct device_node *np = pdev->dev.of_node;
608 struct device_node *cnp;
609 struct mci_platform_data *pdata;
610 u32 slot_id;
611
612 if (!np) {
613 dev_err(&pdev->dev, "device node not found\n");
614 return ERR_PTR(-EINVAL);
615 }
616
617 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
618 if (!pdata)
619 return ERR_PTR(-ENOMEM);
620
621 for_each_child_of_node(np, cnp) {
622 if (of_property_read_u32(cnp, "reg", &slot_id)) {
623 dev_warn(&pdev->dev, "reg property is missing for %pOF\n",
624 cnp);
625 continue;
626 }
627
628 if (slot_id >= ATMCI_MAX_NR_SLOTS) {
629 dev_warn(&pdev->dev, "can't have more than %d slots\n",
630 ATMCI_MAX_NR_SLOTS);
631 of_node_put(cnp);
632 break;
633 }
634
635 if (of_property_read_u32(cnp, "bus-width",
636 &pdata->slot[slot_id].bus_width))
637 pdata->slot[slot_id].bus_width = 1;
638
639 pdata->slot[slot_id].detect_pin =
640 of_get_named_gpio(cnp, "cd-gpios", 0);
641
642 pdata->slot[slot_id].detect_is_active_high =
643 of_property_read_bool(cnp, "cd-inverted");
644
645 pdata->slot[slot_id].non_removable =
646 of_property_read_bool(cnp, "non-removable");
647
648 pdata->slot[slot_id].wp_pin =
649 of_get_named_gpio(cnp, "wp-gpios", 0);
650 }
651
652 return pdata;
653}
654#else /* CONFIG_OF */
655static inline struct mci_platform_data*
656atmci_of_init(struct platform_device *dev)
657{
658 return ERR_PTR(-EINVAL);
659}
660#endif
661
662static inline unsigned int atmci_get_version(struct atmel_mci *host)
663{
664 return atmci_readl(host, ATMCI_VERSION) & 0x00000fff;
665}
666
667/*
668 * Fix sconfig's burst size according to atmel MCI. We need to convert them as:
669 * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
670 * With version 0x600, we need to convert them as: 1 -> 0, 2 -> 1, 4 -> 2,
671 * 8 -> 3, 16 -> 4.
672 *
673 * This can be done by finding most significant bit set.
674 */
675static inline unsigned int atmci_convert_chksize(struct atmel_mci *host,
676 unsigned int maxburst)
677{
678 unsigned int version = atmci_get_version(host);
679 unsigned int offset = 2;
680
681 if (version >= 0x600)
682 offset = 1;
683
684 if (maxburst > 1)
685 return fls(maxburst) - offset;
686 else
687 return 0;
688}
689
690static void atmci_timeout_timer(struct timer_list *t)
691{
692 struct atmel_mci *host;
693
694 host = from_timer(host, t, timer);
695
696 dev_dbg(&host->pdev->dev, "software timeout\n");
697
698 if (host->mrq->cmd->data) {
699 host->mrq->cmd->data->error = -ETIMEDOUT;
700 host->data = NULL;
701 /*
702 * With some SDIO modules, sometimes DMA transfer hangs. If
703 * stop_transfer() is not called then the DMA request is not
704 * removed, following ones are queued and never computed.
705 */
706 if (host->state == STATE_DATA_XFER)
707 host->stop_transfer(host);
708 } else {
709 host->mrq->cmd->error = -ETIMEDOUT;
710 host->cmd = NULL;
711 }
712 host->need_reset = 1;
713 host->state = STATE_END_REQUEST;
714 smp_wmb();
715 tasklet_schedule(&host->tasklet);
716}
717
718static inline unsigned int atmci_ns_to_clocks(struct atmel_mci *host,
719 unsigned int ns)
720{
721 /*
722 * It is easier here to use us instead of ns for the timeout,
723 * it prevents from overflows during calculation.
724 */
725 unsigned int us = DIV_ROUND_UP(ns, 1000);
726
727 /* Maximum clock frequency is host->bus_hz/2 */
728 return us * (DIV_ROUND_UP(host->bus_hz, 2000000));
729}
730
731static void atmci_set_timeout(struct atmel_mci *host,
732 struct atmel_mci_slot *slot, struct mmc_data *data)
733{
734 static unsigned dtomul_to_shift[] = {
735 0, 4, 7, 8, 10, 12, 16, 20
736 };
737 unsigned timeout;
738 unsigned dtocyc;
739 unsigned dtomul;
740
741 timeout = atmci_ns_to_clocks(host, data->timeout_ns)
742 + data->timeout_clks;
743
744 for (dtomul = 0; dtomul < 8; dtomul++) {
745 unsigned shift = dtomul_to_shift[dtomul];
746 dtocyc = (timeout + (1 << shift) - 1) >> shift;
747 if (dtocyc < 15)
748 break;
749 }
750
751 if (dtomul >= 8) {
752 dtomul = 7;
753 dtocyc = 15;
754 }
755
756 dev_vdbg(&slot->mmc->class_dev, "setting timeout to %u cycles\n",
757 dtocyc << dtomul_to_shift[dtomul]);
758 atmci_writel(host, ATMCI_DTOR, (ATMCI_DTOMUL(dtomul) | ATMCI_DTOCYC(dtocyc)));
759}
760
761/*
762 * Return mask with command flags to be enabled for this command.
763 */
764static u32 atmci_prepare_command(struct mmc_host *mmc,
765 struct mmc_command *cmd)
766{
767 struct mmc_data *data;
768 u32 cmdr;
769
770 cmd->error = -EINPROGRESS;
771
772 cmdr = ATMCI_CMDR_CMDNB(cmd->opcode);
773
774 if (cmd->flags & MMC_RSP_PRESENT) {
775 if (cmd->flags & MMC_RSP_136)
776 cmdr |= ATMCI_CMDR_RSPTYP_136BIT;
777 else
778 cmdr |= ATMCI_CMDR_RSPTYP_48BIT;
779 }
780
781 /*
782 * This should really be MAXLAT_5 for CMD2 and ACMD41, but
783 * it's too difficult to determine whether this is an ACMD or
784 * not. Better make it 64.
785 */
786 cmdr |= ATMCI_CMDR_MAXLAT_64CYC;
787
788 if (mmc->ios.bus_mode == MMC_BUSMODE_OPENDRAIN)
789 cmdr |= ATMCI_CMDR_OPDCMD;
790
791 data = cmd->data;
792 if (data) {
793 cmdr |= ATMCI_CMDR_START_XFER;
794
795 if (cmd->opcode == SD_IO_RW_EXTENDED) {
796 cmdr |= ATMCI_CMDR_SDIO_BLOCK;
797 } else {
798 if (data->blocks > 1)
799 cmdr |= ATMCI_CMDR_MULTI_BLOCK;
800 else
801 cmdr |= ATMCI_CMDR_BLOCK;
802 }
803
804 if (data->flags & MMC_DATA_READ)
805 cmdr |= ATMCI_CMDR_TRDIR_READ;
806 }
807
808 return cmdr;
809}
810
811static void atmci_send_command(struct atmel_mci *host,
812 struct mmc_command *cmd, u32 cmd_flags)
813{
814 unsigned int timeout_ms = cmd->busy_timeout ? cmd->busy_timeout :
815 ATMCI_CMD_TIMEOUT_MS;
816
817 WARN_ON(host->cmd);
818 host->cmd = cmd;
819
820 dev_vdbg(&host->pdev->dev,
821 "start command: ARGR=0x%08x CMDR=0x%08x\n",
822 cmd->arg, cmd_flags);
823
824 atmci_writel(host, ATMCI_ARGR, cmd->arg);
825 atmci_writel(host, ATMCI_CMDR, cmd_flags);
826
827 mod_timer(&host->timer, jiffies + msecs_to_jiffies(timeout_ms));
828}
829
830static void atmci_send_stop_cmd(struct atmel_mci *host, struct mmc_data *data)
831{
832 dev_dbg(&host->pdev->dev, "send stop command\n");
833 atmci_send_command(host, data->stop, host->stop_cmdr);
834 atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY);
835}
836
837/*
838 * Configure given PDC buffer taking care of alignement issues.
839 * Update host->data_size and host->sg.
840 */
841static void atmci_pdc_set_single_buf(struct atmel_mci *host,
842 enum atmci_xfer_dir dir, enum atmci_pdc_buf buf_nb)
843{
844 u32 pointer_reg, counter_reg;
845 unsigned int buf_size;
846
847 if (dir == XFER_RECEIVE) {
848 pointer_reg = ATMEL_PDC_RPR;
849 counter_reg = ATMEL_PDC_RCR;
850 } else {
851 pointer_reg = ATMEL_PDC_TPR;
852 counter_reg = ATMEL_PDC_TCR;
853 }
854
855 if (buf_nb == PDC_SECOND_BUF) {
856 pointer_reg += ATMEL_PDC_SCND_BUF_OFF;
857 counter_reg += ATMEL_PDC_SCND_BUF_OFF;
858 }
859
860 if (!host->caps.has_rwproof) {
861 buf_size = host->buf_size;
862 atmci_writel(host, pointer_reg, host->buf_phys_addr);
863 } else {
864 buf_size = sg_dma_len(host->sg);
865 atmci_writel(host, pointer_reg, sg_dma_address(host->sg));
866 }
867
868 if (host->data_size <= buf_size) {
869 if (host->data_size & 0x3) {
870 /* If size is different from modulo 4, transfer bytes */
871 atmci_writel(host, counter_reg, host->data_size);
872 atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCFBYTE);
873 } else {
874 /* Else transfer 32-bits words */
875 atmci_writel(host, counter_reg, host->data_size / 4);
876 }
877 host->data_size = 0;
878 } else {
879 /* We assume the size of a page is 32-bits aligned */
880 atmci_writel(host, counter_reg, sg_dma_len(host->sg) / 4);
881 host->data_size -= sg_dma_len(host->sg);
882 if (host->data_size)
883 host->sg = sg_next(host->sg);
884 }
885}
886
887/*
888 * Configure PDC buffer according to the data size ie configuring one or two
889 * buffers. Don't use this function if you want to configure only the second
890 * buffer. In this case, use atmci_pdc_set_single_buf.
891 */
892static void atmci_pdc_set_both_buf(struct atmel_mci *host, int dir)
893{
894 atmci_pdc_set_single_buf(host, dir, PDC_FIRST_BUF);
895 if (host->data_size)
896 atmci_pdc_set_single_buf(host, dir, PDC_SECOND_BUF);
897}
898
899/*
900 * Unmap sg lists, called when transfer is finished.
901 */
902static void atmci_pdc_cleanup(struct atmel_mci *host)
903{
904 struct mmc_data *data = host->data;
905
906 if (data)
907 dma_unmap_sg(&host->pdev->dev,
908 data->sg, data->sg_len,
909 mmc_get_dma_dir(data));
910}
911
912/*
913 * Disable PDC transfers. Update pending flags to EVENT_XFER_COMPLETE after
914 * having received ATMCI_TXBUFE or ATMCI_RXBUFF interrupt. Enable ATMCI_NOTBUSY
915 * interrupt needed for both transfer directions.
916 */
917static void atmci_pdc_complete(struct atmel_mci *host)
918{
919 int transfer_size = host->data->blocks * host->data->blksz;
920 int i;
921
922 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
923
924 if ((!host->caps.has_rwproof)
925 && (host->data->flags & MMC_DATA_READ)) {
926 if (host->caps.has_bad_data_ordering)
927 for (i = 0; i < transfer_size; i++)
928 host->buffer[i] = swab32(host->buffer[i]);
929 sg_copy_from_buffer(host->data->sg, host->data->sg_len,
930 host->buffer, transfer_size);
931 }
932
933 atmci_pdc_cleanup(host);
934
935 dev_dbg(&host->pdev->dev, "(%s) set pending xfer complete\n", __func__);
936 atmci_set_pending(host, EVENT_XFER_COMPLETE);
937 tasklet_schedule(&host->tasklet);
938}
939
940static void atmci_dma_cleanup(struct atmel_mci *host)
941{
942 struct mmc_data *data = host->data;
943
944 if (data)
945 dma_unmap_sg(host->dma.chan->device->dev,
946 data->sg, data->sg_len,
947 mmc_get_dma_dir(data));
948}
949
950/*
951 * This function is called by the DMA driver from tasklet context.
952 */
953static void atmci_dma_complete(void *arg)
954{
955 struct atmel_mci *host = arg;
956 struct mmc_data *data = host->data;
957
958 dev_vdbg(&host->pdev->dev, "DMA complete\n");
959
960 if (host->caps.has_dma_conf_reg)
961 /* Disable DMA hardware handshaking on MCI */
962 atmci_writel(host, ATMCI_DMA, atmci_readl(host, ATMCI_DMA) & ~ATMCI_DMAEN);
963
964 atmci_dma_cleanup(host);
965
966 /*
967 * If the card was removed, data will be NULL. No point trying
968 * to send the stop command or waiting for NBUSY in this case.
969 */
970 if (data) {
971 dev_dbg(&host->pdev->dev,
972 "(%s) set pending xfer complete\n", __func__);
973 atmci_set_pending(host, EVENT_XFER_COMPLETE);
974 tasklet_schedule(&host->tasklet);
975
976 /*
977 * Regardless of what the documentation says, we have
978 * to wait for NOTBUSY even after block read
979 * operations.
980 *
981 * When the DMA transfer is complete, the controller
982 * may still be reading the CRC from the card, i.e.
983 * the data transfer is still in progress and we
984 * haven't seen all the potential error bits yet.
985 *
986 * The interrupt handler will schedule a different
987 * tasklet to finish things up when the data transfer
988 * is completely done.
989 *
990 * We may not complete the mmc request here anyway
991 * because the mmc layer may call back and cause us to
992 * violate the "don't submit new operations from the
993 * completion callback" rule of the dma engine
994 * framework.
995 */
996 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
997 }
998}
999
1000/*
1001 * Returns a mask of interrupt flags to be enabled after the whole
1002 * request has been prepared.
1003 */
1004static u32 atmci_prepare_data(struct atmel_mci *host, struct mmc_data *data)
1005{
1006 u32 iflags;
1007
1008 data->error = -EINPROGRESS;
1009
1010 host->sg = data->sg;
1011 host->sg_len = data->sg_len;
1012 host->data = data;
1013 host->data_chan = NULL;
1014
1015 iflags = ATMCI_DATA_ERROR_FLAGS;
1016
1017 /*
1018 * Errata: MMC data write operation with less than 12
1019 * bytes is impossible.
1020 *
1021 * Errata: MCI Transmit Data Register (TDR) FIFO
1022 * corruption when length is not multiple of 4.
1023 */
1024 if (data->blocks * data->blksz < 12
1025 || (data->blocks * data->blksz) & 3)
1026 host->need_reset = true;
1027
1028 host->pio_offset = 0;
1029 if (data->flags & MMC_DATA_READ)
1030 iflags |= ATMCI_RXRDY;
1031 else
1032 iflags |= ATMCI_TXRDY;
1033
1034 return iflags;
1035}
1036
1037/*
1038 * Set interrupt flags and set block length into the MCI mode register even
1039 * if this value is also accessible in the MCI block register. It seems to be
1040 * necessary before the High Speed MCI version. It also map sg and configure
1041 * PDC registers.
1042 */
1043static u32
1044atmci_prepare_data_pdc(struct atmel_mci *host, struct mmc_data *data)
1045{
1046 u32 iflags, tmp;
1047 int i;
1048
1049 data->error = -EINPROGRESS;
1050
1051 host->data = data;
1052 host->sg = data->sg;
1053 iflags = ATMCI_DATA_ERROR_FLAGS;
1054
1055 /* Enable pdc mode */
1056 atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCMODE);
1057
1058 if (data->flags & MMC_DATA_READ)
1059 iflags |= ATMCI_ENDRX | ATMCI_RXBUFF;
1060 else
1061 iflags |= ATMCI_ENDTX | ATMCI_TXBUFE | ATMCI_BLKE;
1062
1063 /* Set BLKLEN */
1064 tmp = atmci_readl(host, ATMCI_MR);
1065 tmp &= 0x0000ffff;
1066 tmp |= ATMCI_BLKLEN(data->blksz);
1067 atmci_writel(host, ATMCI_MR, tmp);
1068
1069 /* Configure PDC */
1070 host->data_size = data->blocks * data->blksz;
1071 dma_map_sg(&host->pdev->dev, data->sg, data->sg_len,
1072 mmc_get_dma_dir(data));
1073
1074 if ((!host->caps.has_rwproof)
1075 && (host->data->flags & MMC_DATA_WRITE)) {
1076 sg_copy_to_buffer(host->data->sg, host->data->sg_len,
1077 host->buffer, host->data_size);
1078 if (host->caps.has_bad_data_ordering)
1079 for (i = 0; i < host->data_size; i++)
1080 host->buffer[i] = swab32(host->buffer[i]);
1081 }
1082
1083 if (host->data_size)
1084 atmci_pdc_set_both_buf(host, data->flags & MMC_DATA_READ ?
1085 XFER_RECEIVE : XFER_TRANSMIT);
1086 return iflags;
1087}
1088
1089static u32
1090atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data)
1091{
1092 struct dma_chan *chan;
1093 struct dma_async_tx_descriptor *desc;
1094 struct scatterlist *sg;
1095 unsigned int i;
1096 enum dma_transfer_direction slave_dirn;
1097 unsigned int sglen;
1098 u32 maxburst;
1099 u32 iflags;
1100
1101 data->error = -EINPROGRESS;
1102
1103 WARN_ON(host->data);
1104 host->sg = NULL;
1105 host->data = data;
1106
1107 iflags = ATMCI_DATA_ERROR_FLAGS;
1108
1109 /*
1110 * We don't do DMA on "complex" transfers, i.e. with
1111 * non-word-aligned buffers or lengths. Also, we don't bother
1112 * with all the DMA setup overhead for short transfers.
1113 */
1114 if (data->blocks * data->blksz < ATMCI_DMA_THRESHOLD)
1115 return atmci_prepare_data(host, data);
1116 if (data->blksz & 3)
1117 return atmci_prepare_data(host, data);
1118
1119 for_each_sg(data->sg, sg, data->sg_len, i) {
1120 if (sg->offset & 3 || sg->length & 3)
1121 return atmci_prepare_data(host, data);
1122 }
1123
1124 /* If we don't have a channel, we can't do DMA */
1125 chan = host->dma.chan;
1126 if (chan)
1127 host->data_chan = chan;
1128
1129 if (!chan)
1130 return -ENODEV;
1131
1132 if (data->flags & MMC_DATA_READ) {
1133 host->dma_conf.direction = slave_dirn = DMA_DEV_TO_MEM;
1134 maxburst = atmci_convert_chksize(host,
1135 host->dma_conf.src_maxburst);
1136 } else {
1137 host->dma_conf.direction = slave_dirn = DMA_MEM_TO_DEV;
1138 maxburst = atmci_convert_chksize(host,
1139 host->dma_conf.dst_maxburst);
1140 }
1141
1142 if (host->caps.has_dma_conf_reg)
1143 atmci_writel(host, ATMCI_DMA, ATMCI_DMA_CHKSIZE(maxburst) |
1144 ATMCI_DMAEN);
1145
1146 sglen = dma_map_sg(chan->device->dev, data->sg,
1147 data->sg_len, mmc_get_dma_dir(data));
1148
1149 dmaengine_slave_config(chan, &host->dma_conf);
1150 desc = dmaengine_prep_slave_sg(chan,
1151 data->sg, sglen, slave_dirn,
1152 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1153 if (!desc)
1154 goto unmap_exit;
1155
1156 host->dma.data_desc = desc;
1157 desc->callback = atmci_dma_complete;
1158 desc->callback_param = host;
1159
1160 return iflags;
1161unmap_exit:
1162 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len,
1163 mmc_get_dma_dir(data));
1164 return -ENOMEM;
1165}
1166
1167static void
1168atmci_submit_data(struct atmel_mci *host, struct mmc_data *data)
1169{
1170 return;
1171}
1172
1173/*
1174 * Start PDC according to transfer direction.
1175 */
1176static void
1177atmci_submit_data_pdc(struct atmel_mci *host, struct mmc_data *data)
1178{
1179 if (data->flags & MMC_DATA_READ)
1180 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
1181 else
1182 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
1183}
1184
1185static void
1186atmci_submit_data_dma(struct atmel_mci *host, struct mmc_data *data)
1187{
1188 struct dma_chan *chan = host->data_chan;
1189 struct dma_async_tx_descriptor *desc = host->dma.data_desc;
1190
1191 if (chan) {
1192 dmaengine_submit(desc);
1193 dma_async_issue_pending(chan);
1194 }
1195}
1196
1197static void atmci_stop_transfer(struct atmel_mci *host)
1198{
1199 dev_dbg(&host->pdev->dev,
1200 "(%s) set pending xfer complete\n", __func__);
1201 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1202 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1203}
1204
1205/*
1206 * Stop data transfer because error(s) occurred.
1207 */
1208static void atmci_stop_transfer_pdc(struct atmel_mci *host)
1209{
1210 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
1211}
1212
1213static void atmci_stop_transfer_dma(struct atmel_mci *host)
1214{
1215 struct dma_chan *chan = host->data_chan;
1216
1217 if (chan) {
1218 dmaengine_terminate_all(chan);
1219 atmci_dma_cleanup(host);
1220 } else {
1221 /* Data transfer was stopped by the interrupt handler */
1222 dev_dbg(&host->pdev->dev,
1223 "(%s) set pending xfer complete\n", __func__);
1224 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1225 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1226 }
1227}
1228
1229/*
1230 * Start a request: prepare data if needed, prepare the command and activate
1231 * interrupts.
1232 */
1233static void atmci_start_request(struct atmel_mci *host,
1234 struct atmel_mci_slot *slot)
1235{
1236 struct mmc_request *mrq;
1237 struct mmc_command *cmd;
1238 struct mmc_data *data;
1239 u32 iflags;
1240 u32 cmdflags;
1241
1242 mrq = slot->mrq;
1243 host->cur_slot = slot;
1244 host->mrq = mrq;
1245
1246 host->pending_events = 0;
1247 host->completed_events = 0;
1248 host->cmd_status = 0;
1249 host->data_status = 0;
1250
1251 dev_dbg(&host->pdev->dev, "start request: cmd %u\n", mrq->cmd->opcode);
1252
1253 if (host->need_reset || host->caps.need_reset_after_xfer) {
1254 iflags = atmci_readl(host, ATMCI_IMR);
1255 iflags &= (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB);
1256 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1257 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1258 atmci_writel(host, ATMCI_MR, host->mode_reg);
1259 if (host->caps.has_cfg_reg)
1260 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1261 atmci_writel(host, ATMCI_IER, iflags);
1262 host->need_reset = false;
1263 }
1264 atmci_writel(host, ATMCI_SDCR, slot->sdc_reg);
1265
1266 iflags = atmci_readl(host, ATMCI_IMR);
1267 if (iflags & ~(ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
1268 dev_dbg(&slot->mmc->class_dev, "WARNING: IMR=0x%08x\n",
1269 iflags);
1270
1271 if (unlikely(test_and_clear_bit(ATMCI_CARD_NEED_INIT, &slot->flags))) {
1272 /* Send init sequence (74 clock cycles) */
1273 atmci_writel(host, ATMCI_CMDR, ATMCI_CMDR_SPCMD_INIT);
1274 while (!(atmci_readl(host, ATMCI_SR) & ATMCI_CMDRDY))
1275 cpu_relax();
1276 }
1277 iflags = 0;
1278 data = mrq->data;
1279 if (data) {
1280 atmci_set_timeout(host, slot, data);
1281
1282 /* Must set block count/size before sending command */
1283 atmci_writel(host, ATMCI_BLKR, ATMCI_BCNT(data->blocks)
1284 | ATMCI_BLKLEN(data->blksz));
1285 dev_vdbg(&slot->mmc->class_dev, "BLKR=0x%08x\n",
1286 ATMCI_BCNT(data->blocks) | ATMCI_BLKLEN(data->blksz));
1287
1288 iflags |= host->prepare_data(host, data);
1289 }
1290
1291 iflags |= ATMCI_CMDRDY;
1292 cmd = mrq->cmd;
1293 cmdflags = atmci_prepare_command(slot->mmc, cmd);
1294
1295 /*
1296 * DMA transfer should be started before sending the command to avoid
1297 * unexpected errors especially for read operations in SDIO mode.
1298 * Unfortunately, in PDC mode, command has to be sent before starting
1299 * the transfer.
1300 */
1301 if (host->submit_data != &atmci_submit_data_dma)
1302 atmci_send_command(host, cmd, cmdflags);
1303
1304 if (data)
1305 host->submit_data(host, data);
1306
1307 if (host->submit_data == &atmci_submit_data_dma)
1308 atmci_send_command(host, cmd, cmdflags);
1309
1310 if (mrq->stop) {
1311 host->stop_cmdr = atmci_prepare_command(slot->mmc, mrq->stop);
1312 host->stop_cmdr |= ATMCI_CMDR_STOP_XFER;
1313 if (!(data->flags & MMC_DATA_WRITE))
1314 host->stop_cmdr |= ATMCI_CMDR_TRDIR_READ;
1315 host->stop_cmdr |= ATMCI_CMDR_MULTI_BLOCK;
1316 }
1317
1318 /*
1319 * We could have enabled interrupts earlier, but I suspect
1320 * that would open up a nice can of interesting race
1321 * conditions (e.g. command and data complete, but stop not
1322 * prepared yet.)
1323 */
1324 atmci_writel(host, ATMCI_IER, iflags);
1325}
1326
1327static void atmci_queue_request(struct atmel_mci *host,
1328 struct atmel_mci_slot *slot, struct mmc_request *mrq)
1329{
1330 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1331 host->state);
1332
1333 spin_lock_bh(&host->lock);
1334 slot->mrq = mrq;
1335 if (host->state == STATE_IDLE) {
1336 host->state = STATE_SENDING_CMD;
1337 atmci_start_request(host, slot);
1338 } else {
1339 dev_dbg(&host->pdev->dev, "queue request\n");
1340 list_add_tail(&slot->queue_node, &host->queue);
1341 }
1342 spin_unlock_bh(&host->lock);
1343}
1344
1345static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1346{
1347 struct atmel_mci_slot *slot = mmc_priv(mmc);
1348 struct atmel_mci *host = slot->host;
1349 struct mmc_data *data;
1350
1351 WARN_ON(slot->mrq);
1352 dev_dbg(&host->pdev->dev, "MRQ: cmd %u\n", mrq->cmd->opcode);
1353
1354 /*
1355 * We may "know" the card is gone even though there's still an
1356 * electrical connection. If so, we really need to communicate
1357 * this to the MMC core since there won't be any more
1358 * interrupts as the card is completely removed. Otherwise,
1359 * the MMC core might believe the card is still there even
1360 * though the card was just removed very slowly.
1361 */
1362 if (!test_bit(ATMCI_CARD_PRESENT, &slot->flags)) {
1363 mrq->cmd->error = -ENOMEDIUM;
1364 mmc_request_done(mmc, mrq);
1365 return;
1366 }
1367
1368 /* We don't support multiple blocks of weird lengths. */
1369 data = mrq->data;
1370 if (data && data->blocks > 1 && data->blksz & 3) {
1371 mrq->cmd->error = -EINVAL;
1372 mmc_request_done(mmc, mrq);
1373 }
1374
1375 atmci_queue_request(host, slot, mrq);
1376}
1377
1378static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1379{
1380 struct atmel_mci_slot *slot = mmc_priv(mmc);
1381 struct atmel_mci *host = slot->host;
1382 unsigned int i;
1383
1384 slot->sdc_reg &= ~ATMCI_SDCBUS_MASK;
1385 switch (ios->bus_width) {
1386 case MMC_BUS_WIDTH_1:
1387 slot->sdc_reg |= ATMCI_SDCBUS_1BIT;
1388 break;
1389 case MMC_BUS_WIDTH_4:
1390 slot->sdc_reg |= ATMCI_SDCBUS_4BIT;
1391 break;
1392 case MMC_BUS_WIDTH_8:
1393 slot->sdc_reg |= ATMCI_SDCBUS_8BIT;
1394 break;
1395 }
1396
1397 if (ios->clock) {
1398 unsigned int clock_min = ~0U;
1399 int clkdiv;
1400
1401 spin_lock_bh(&host->lock);
1402 if (!host->mode_reg) {
1403 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1404 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1405 if (host->caps.has_cfg_reg)
1406 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1407 }
1408
1409 /*
1410 * Use mirror of ios->clock to prevent race with mmc
1411 * core ios update when finding the minimum.
1412 */
1413 slot->clock = ios->clock;
1414 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1415 if (host->slot[i] && host->slot[i]->clock
1416 && host->slot[i]->clock < clock_min)
1417 clock_min = host->slot[i]->clock;
1418 }
1419
1420 /* Calculate clock divider */
1421 if (host->caps.has_odd_clk_div) {
1422 clkdiv = DIV_ROUND_UP(host->bus_hz, clock_min) - 2;
1423 if (clkdiv < 0) {
1424 dev_warn(&mmc->class_dev,
1425 "clock %u too fast; using %lu\n",
1426 clock_min, host->bus_hz / 2);
1427 clkdiv = 0;
1428 } else if (clkdiv > 511) {
1429 dev_warn(&mmc->class_dev,
1430 "clock %u too slow; using %lu\n",
1431 clock_min, host->bus_hz / (511 + 2));
1432 clkdiv = 511;
1433 }
1434 host->mode_reg = ATMCI_MR_CLKDIV(clkdiv >> 1)
1435 | ATMCI_MR_CLKODD(clkdiv & 1);
1436 } else {
1437 clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * clock_min) - 1;
1438 if (clkdiv > 255) {
1439 dev_warn(&mmc->class_dev,
1440 "clock %u too slow; using %lu\n",
1441 clock_min, host->bus_hz / (2 * 256));
1442 clkdiv = 255;
1443 }
1444 host->mode_reg = ATMCI_MR_CLKDIV(clkdiv);
1445 }
1446
1447 /*
1448 * WRPROOF and RDPROOF prevent overruns/underruns by
1449 * stopping the clock when the FIFO is full/empty.
1450 * This state is not expected to last for long.
1451 */
1452 if (host->caps.has_rwproof)
1453 host->mode_reg |= (ATMCI_MR_WRPROOF | ATMCI_MR_RDPROOF);
1454
1455 if (host->caps.has_cfg_reg) {
1456 /* setup High Speed mode in relation with card capacity */
1457 if (ios->timing == MMC_TIMING_SD_HS)
1458 host->cfg_reg |= ATMCI_CFG_HSMODE;
1459 else
1460 host->cfg_reg &= ~ATMCI_CFG_HSMODE;
1461 }
1462
1463 if (list_empty(&host->queue)) {
1464 atmci_writel(host, ATMCI_MR, host->mode_reg);
1465 if (host->caps.has_cfg_reg)
1466 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1467 } else {
1468 host->need_clock_update = true;
1469 }
1470
1471 spin_unlock_bh(&host->lock);
1472 } else {
1473 bool any_slot_active = false;
1474
1475 spin_lock_bh(&host->lock);
1476 slot->clock = 0;
1477 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1478 if (host->slot[i] && host->slot[i]->clock) {
1479 any_slot_active = true;
1480 break;
1481 }
1482 }
1483 if (!any_slot_active) {
1484 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
1485 if (host->mode_reg) {
1486 atmci_readl(host, ATMCI_MR);
1487 }
1488 host->mode_reg = 0;
1489 }
1490 spin_unlock_bh(&host->lock);
1491 }
1492
1493 switch (ios->power_mode) {
1494 case MMC_POWER_OFF:
1495 if (!IS_ERR(mmc->supply.vmmc))
1496 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1497 break;
1498 case MMC_POWER_UP:
1499 set_bit(ATMCI_CARD_NEED_INIT, &slot->flags);
1500 if (!IS_ERR(mmc->supply.vmmc))
1501 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
1502 break;
1503 default:
1504 break;
1505 }
1506}
1507
1508static int atmci_get_ro(struct mmc_host *mmc)
1509{
1510 int read_only = -ENOSYS;
1511 struct atmel_mci_slot *slot = mmc_priv(mmc);
1512
1513 if (gpio_is_valid(slot->wp_pin)) {
1514 read_only = gpio_get_value(slot->wp_pin);
1515 dev_dbg(&mmc->class_dev, "card is %s\n",
1516 read_only ? "read-only" : "read-write");
1517 }
1518
1519 return read_only;
1520}
1521
1522static int atmci_get_cd(struct mmc_host *mmc)
1523{
1524 int present = -ENOSYS;
1525 struct atmel_mci_slot *slot = mmc_priv(mmc);
1526
1527 if (gpio_is_valid(slot->detect_pin)) {
1528 present = !(gpio_get_value(slot->detect_pin) ^
1529 slot->detect_is_active_high);
1530 dev_dbg(&mmc->class_dev, "card is %spresent\n",
1531 present ? "" : "not ");
1532 }
1533
1534 return present;
1535}
1536
1537static void atmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1538{
1539 struct atmel_mci_slot *slot = mmc_priv(mmc);
1540 struct atmel_mci *host = slot->host;
1541
1542 if (enable)
1543 atmci_writel(host, ATMCI_IER, slot->sdio_irq);
1544 else
1545 atmci_writel(host, ATMCI_IDR, slot->sdio_irq);
1546}
1547
1548static const struct mmc_host_ops atmci_ops = {
1549 .request = atmci_request,
1550 .set_ios = atmci_set_ios,
1551 .get_ro = atmci_get_ro,
1552 .get_cd = atmci_get_cd,
1553 .enable_sdio_irq = atmci_enable_sdio_irq,
1554};
1555
1556/* Called with host->lock held */
1557static void atmci_request_end(struct atmel_mci *host, struct mmc_request *mrq)
1558 __releases(&host->lock)
1559 __acquires(&host->lock)
1560{
1561 struct atmel_mci_slot *slot = NULL;
1562 struct mmc_host *prev_mmc = host->cur_slot->mmc;
1563
1564 WARN_ON(host->cmd || host->data);
1565
1566 del_timer(&host->timer);
1567
1568 /*
1569 * Update the MMC clock rate if necessary. This may be
1570 * necessary if set_ios() is called when a different slot is
1571 * busy transferring data.
1572 */
1573 if (host->need_clock_update) {
1574 atmci_writel(host, ATMCI_MR, host->mode_reg);
1575 if (host->caps.has_cfg_reg)
1576 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1577 }
1578
1579 host->cur_slot->mrq = NULL;
1580 host->mrq = NULL;
1581 if (!list_empty(&host->queue)) {
1582 slot = list_entry(host->queue.next,
1583 struct atmel_mci_slot, queue_node);
1584 list_del(&slot->queue_node);
1585 dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n",
1586 mmc_hostname(slot->mmc));
1587 host->state = STATE_SENDING_CMD;
1588 atmci_start_request(host, slot);
1589 } else {
1590 dev_vdbg(&host->pdev->dev, "list empty\n");
1591 host->state = STATE_IDLE;
1592 }
1593
1594 spin_unlock(&host->lock);
1595 mmc_request_done(prev_mmc, mrq);
1596 spin_lock(&host->lock);
1597}
1598
1599static void atmci_command_complete(struct atmel_mci *host,
1600 struct mmc_command *cmd)
1601{
1602 u32 status = host->cmd_status;
1603
1604 /* Read the response from the card (up to 16 bytes) */
1605 cmd->resp[0] = atmci_readl(host, ATMCI_RSPR);
1606 cmd->resp[1] = atmci_readl(host, ATMCI_RSPR);
1607 cmd->resp[2] = atmci_readl(host, ATMCI_RSPR);
1608 cmd->resp[3] = atmci_readl(host, ATMCI_RSPR);
1609
1610 if (status & ATMCI_RTOE)
1611 cmd->error = -ETIMEDOUT;
1612 else if ((cmd->flags & MMC_RSP_CRC) && (status & ATMCI_RCRCE))
1613 cmd->error = -EILSEQ;
1614 else if (status & (ATMCI_RINDE | ATMCI_RDIRE | ATMCI_RENDE))
1615 cmd->error = -EIO;
1616 else if (host->mrq->data && (host->mrq->data->blksz & 3)) {
1617 if (host->caps.need_blksz_mul_4) {
1618 cmd->error = -EINVAL;
1619 host->need_reset = 1;
1620 }
1621 } else
1622 cmd->error = 0;
1623}
1624
1625static void atmci_detect_change(struct timer_list *t)
1626{
1627 struct atmel_mci_slot *slot = from_timer(slot, t, detect_timer);
1628 bool present;
1629 bool present_old;
1630
1631 /*
1632 * atmci_cleanup_slot() sets the ATMCI_SHUTDOWN flag before
1633 * freeing the interrupt. We must not re-enable the interrupt
1634 * if it has been freed, and if we're shutting down, it
1635 * doesn't really matter whether the card is present or not.
1636 */
1637 smp_rmb();
1638 if (test_bit(ATMCI_SHUTDOWN, &slot->flags))
1639 return;
1640
1641 enable_irq(gpio_to_irq(slot->detect_pin));
1642 present = !(gpio_get_value(slot->detect_pin) ^
1643 slot->detect_is_active_high);
1644 present_old = test_bit(ATMCI_CARD_PRESENT, &slot->flags);
1645
1646 dev_vdbg(&slot->mmc->class_dev, "detect change: %d (was %d)\n",
1647 present, present_old);
1648
1649 if (present != present_old) {
1650 struct atmel_mci *host = slot->host;
1651 struct mmc_request *mrq;
1652
1653 dev_dbg(&slot->mmc->class_dev, "card %s\n",
1654 present ? "inserted" : "removed");
1655
1656 spin_lock(&host->lock);
1657
1658 if (!present)
1659 clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
1660 else
1661 set_bit(ATMCI_CARD_PRESENT, &slot->flags);
1662
1663 /* Clean up queue if present */
1664 mrq = slot->mrq;
1665 if (mrq) {
1666 if (mrq == host->mrq) {
1667 /*
1668 * Reset controller to terminate any ongoing
1669 * commands or data transfers.
1670 */
1671 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1672 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1673 atmci_writel(host, ATMCI_MR, host->mode_reg);
1674 if (host->caps.has_cfg_reg)
1675 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1676
1677 host->data = NULL;
1678 host->cmd = NULL;
1679
1680 switch (host->state) {
1681 case STATE_IDLE:
1682 break;
1683 case STATE_SENDING_CMD:
1684 mrq->cmd->error = -ENOMEDIUM;
1685 if (mrq->data)
1686 host->stop_transfer(host);
1687 break;
1688 case STATE_DATA_XFER:
1689 mrq->data->error = -ENOMEDIUM;
1690 host->stop_transfer(host);
1691 break;
1692 case STATE_WAITING_NOTBUSY:
1693 mrq->data->error = -ENOMEDIUM;
1694 break;
1695 case STATE_SENDING_STOP:
1696 mrq->stop->error = -ENOMEDIUM;
1697 break;
1698 case STATE_END_REQUEST:
1699 break;
1700 }
1701
1702 atmci_request_end(host, mrq);
1703 } else {
1704 list_del(&slot->queue_node);
1705 mrq->cmd->error = -ENOMEDIUM;
1706 if (mrq->data)
1707 mrq->data->error = -ENOMEDIUM;
1708 if (mrq->stop)
1709 mrq->stop->error = -ENOMEDIUM;
1710
1711 spin_unlock(&host->lock);
1712 mmc_request_done(slot->mmc, mrq);
1713 spin_lock(&host->lock);
1714 }
1715 }
1716 spin_unlock(&host->lock);
1717
1718 mmc_detect_change(slot->mmc, 0);
1719 }
1720}
1721
1722static void atmci_tasklet_func(unsigned long priv)
1723{
1724 struct atmel_mci *host = (struct atmel_mci *)priv;
1725 struct mmc_request *mrq = host->mrq;
1726 struct mmc_data *data = host->data;
1727 enum atmel_mci_state state = host->state;
1728 enum atmel_mci_state prev_state;
1729 u32 status;
1730
1731 spin_lock(&host->lock);
1732
1733 state = host->state;
1734
1735 dev_vdbg(&host->pdev->dev,
1736 "tasklet: state %u pending/completed/mask %lx/%lx/%x\n",
1737 state, host->pending_events, host->completed_events,
1738 atmci_readl(host, ATMCI_IMR));
1739
1740 do {
1741 prev_state = state;
1742 dev_dbg(&host->pdev->dev, "FSM: state=%d\n", state);
1743
1744 switch (state) {
1745 case STATE_IDLE:
1746 break;
1747
1748 case STATE_SENDING_CMD:
1749 /*
1750 * Command has been sent, we are waiting for command
1751 * ready. Then we have three next states possible:
1752 * END_REQUEST by default, WAITING_NOTBUSY if it's a
1753 * command needing it or DATA_XFER if there is data.
1754 */
1755 dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n");
1756 if (!atmci_test_and_clear_pending(host,
1757 EVENT_CMD_RDY))
1758 break;
1759
1760 dev_dbg(&host->pdev->dev, "set completed cmd ready\n");
1761 host->cmd = NULL;
1762 atmci_set_completed(host, EVENT_CMD_RDY);
1763 atmci_command_complete(host, mrq->cmd);
1764 if (mrq->data) {
1765 dev_dbg(&host->pdev->dev,
1766 "command with data transfer");
1767 /*
1768 * If there is a command error don't start
1769 * data transfer.
1770 */
1771 if (mrq->cmd->error) {
1772 host->stop_transfer(host);
1773 host->data = NULL;
1774 atmci_writel(host, ATMCI_IDR,
1775 ATMCI_TXRDY | ATMCI_RXRDY
1776 | ATMCI_DATA_ERROR_FLAGS);
1777 state = STATE_END_REQUEST;
1778 } else
1779 state = STATE_DATA_XFER;
1780 } else if ((!mrq->data) && (mrq->cmd->flags & MMC_RSP_BUSY)) {
1781 dev_dbg(&host->pdev->dev,
1782 "command response need waiting notbusy");
1783 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1784 state = STATE_WAITING_NOTBUSY;
1785 } else
1786 state = STATE_END_REQUEST;
1787
1788 break;
1789
1790 case STATE_DATA_XFER:
1791 if (atmci_test_and_clear_pending(host,
1792 EVENT_DATA_ERROR)) {
1793 dev_dbg(&host->pdev->dev, "set completed data error\n");
1794 atmci_set_completed(host, EVENT_DATA_ERROR);
1795 state = STATE_END_REQUEST;
1796 break;
1797 }
1798
1799 /*
1800 * A data transfer is in progress. The event expected
1801 * to move to the next state depends of data transfer
1802 * type (PDC or DMA). Once transfer done we can move
1803 * to the next step which is WAITING_NOTBUSY in write
1804 * case and directly SENDING_STOP in read case.
1805 */
1806 dev_dbg(&host->pdev->dev, "FSM: xfer complete?\n");
1807 if (!atmci_test_and_clear_pending(host,
1808 EVENT_XFER_COMPLETE))
1809 break;
1810
1811 dev_dbg(&host->pdev->dev,
1812 "(%s) set completed xfer complete\n",
1813 __func__);
1814 atmci_set_completed(host, EVENT_XFER_COMPLETE);
1815
1816 if (host->caps.need_notbusy_for_read_ops ||
1817 (host->data->flags & MMC_DATA_WRITE)) {
1818 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1819 state = STATE_WAITING_NOTBUSY;
1820 } else if (host->mrq->stop) {
1821 atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY);
1822 atmci_send_stop_cmd(host, data);
1823 state = STATE_SENDING_STOP;
1824 } else {
1825 host->data = NULL;
1826 data->bytes_xfered = data->blocks * data->blksz;
1827 data->error = 0;
1828 state = STATE_END_REQUEST;
1829 }
1830 break;
1831
1832 case STATE_WAITING_NOTBUSY:
1833 /*
1834 * We can be in the state for two reasons: a command
1835 * requiring waiting not busy signal (stop command
1836 * included) or a write operation. In the latest case,
1837 * we need to send a stop command.
1838 */
1839 dev_dbg(&host->pdev->dev, "FSM: not busy?\n");
1840 if (!atmci_test_and_clear_pending(host,
1841 EVENT_NOTBUSY))
1842 break;
1843
1844 dev_dbg(&host->pdev->dev, "set completed not busy\n");
1845 atmci_set_completed(host, EVENT_NOTBUSY);
1846
1847 if (host->data) {
1848 /*
1849 * For some commands such as CMD53, even if
1850 * there is data transfer, there is no stop
1851 * command to send.
1852 */
1853 if (host->mrq->stop) {
1854 atmci_writel(host, ATMCI_IER,
1855 ATMCI_CMDRDY);
1856 atmci_send_stop_cmd(host, data);
1857 state = STATE_SENDING_STOP;
1858 } else {
1859 host->data = NULL;
1860 data->bytes_xfered = data->blocks
1861 * data->blksz;
1862 data->error = 0;
1863 state = STATE_END_REQUEST;
1864 }
1865 } else
1866 state = STATE_END_REQUEST;
1867 break;
1868
1869 case STATE_SENDING_STOP:
1870 /*
1871 * In this state, it is important to set host->data to
1872 * NULL (which is tested in the waiting notbusy state)
1873 * in order to go to the end request state instead of
1874 * sending stop again.
1875 */
1876 dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n");
1877 if (!atmci_test_and_clear_pending(host,
1878 EVENT_CMD_RDY))
1879 break;
1880
1881 dev_dbg(&host->pdev->dev, "FSM: cmd ready\n");
1882 host->cmd = NULL;
1883 data->bytes_xfered = data->blocks * data->blksz;
1884 data->error = 0;
1885 atmci_command_complete(host, mrq->stop);
1886 if (mrq->stop->error) {
1887 host->stop_transfer(host);
1888 atmci_writel(host, ATMCI_IDR,
1889 ATMCI_TXRDY | ATMCI_RXRDY
1890 | ATMCI_DATA_ERROR_FLAGS);
1891 state = STATE_END_REQUEST;
1892 } else {
1893 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1894 state = STATE_WAITING_NOTBUSY;
1895 }
1896 host->data = NULL;
1897 break;
1898
1899 case STATE_END_REQUEST:
1900 atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY | ATMCI_RXRDY
1901 | ATMCI_DATA_ERROR_FLAGS);
1902 status = host->data_status;
1903 if (unlikely(status)) {
1904 host->stop_transfer(host);
1905 host->data = NULL;
1906 if (data) {
1907 if (status & ATMCI_DTOE) {
1908 data->error = -ETIMEDOUT;
1909 } else if (status & ATMCI_DCRCE) {
1910 data->error = -EILSEQ;
1911 } else {
1912 data->error = -EIO;
1913 }
1914 }
1915 }
1916
1917 atmci_request_end(host, host->mrq);
1918 goto unlock; /* atmci_request_end() sets host->state */
1919 break;
1920 }
1921 } while (state != prev_state);
1922
1923 host->state = state;
1924
1925unlock:
1926 spin_unlock(&host->lock);
1927}
1928
1929static void atmci_read_data_pio(struct atmel_mci *host)
1930{
1931 struct scatterlist *sg = host->sg;
1932 unsigned int offset = host->pio_offset;
1933 struct mmc_data *data = host->data;
1934 u32 value;
1935 u32 status;
1936 unsigned int nbytes = 0;
1937
1938 do {
1939 value = atmci_readl(host, ATMCI_RDR);
1940 if (likely(offset + 4 <= sg->length)) {
1941 sg_pcopy_from_buffer(sg, 1, &value, sizeof(u32), offset);
1942
1943 offset += 4;
1944 nbytes += 4;
1945
1946 if (offset == sg->length) {
1947 flush_dcache_page(sg_page(sg));
1948 host->sg = sg = sg_next(sg);
1949 host->sg_len--;
1950 if (!sg || !host->sg_len)
1951 goto done;
1952
1953 offset = 0;
1954 }
1955 } else {
1956 unsigned int remaining = sg->length - offset;
1957
1958 sg_pcopy_from_buffer(sg, 1, &value, remaining, offset);
1959 nbytes += remaining;
1960
1961 flush_dcache_page(sg_page(sg));
1962 host->sg = sg = sg_next(sg);
1963 host->sg_len--;
1964 if (!sg || !host->sg_len)
1965 goto done;
1966
1967 offset = 4 - remaining;
1968 sg_pcopy_from_buffer(sg, 1, (u8 *)&value + remaining,
1969 offset, 0);
1970 nbytes += offset;
1971 }
1972
1973 status = atmci_readl(host, ATMCI_SR);
1974 if (status & ATMCI_DATA_ERROR_FLAGS) {
1975 atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_RXRDY
1976 | ATMCI_DATA_ERROR_FLAGS));
1977 host->data_status = status;
1978 data->bytes_xfered += nbytes;
1979 return;
1980 }
1981 } while (status & ATMCI_RXRDY);
1982
1983 host->pio_offset = offset;
1984 data->bytes_xfered += nbytes;
1985
1986 return;
1987
1988done:
1989 atmci_writel(host, ATMCI_IDR, ATMCI_RXRDY);
1990 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1991 data->bytes_xfered += nbytes;
1992 smp_wmb();
1993 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1994}
1995
1996static void atmci_write_data_pio(struct atmel_mci *host)
1997{
1998 struct scatterlist *sg = host->sg;
1999 unsigned int offset = host->pio_offset;
2000 struct mmc_data *data = host->data;
2001 u32 value;
2002 u32 status;
2003 unsigned int nbytes = 0;
2004
2005 do {
2006 if (likely(offset + 4 <= sg->length)) {
2007 sg_pcopy_to_buffer(sg, 1, &value, sizeof(u32), offset);
2008 atmci_writel(host, ATMCI_TDR, value);
2009
2010 offset += 4;
2011 nbytes += 4;
2012 if (offset == sg->length) {
2013 host->sg = sg = sg_next(sg);
2014 host->sg_len--;
2015 if (!sg || !host->sg_len)
2016 goto done;
2017
2018 offset = 0;
2019 }
2020 } else {
2021 unsigned int remaining = sg->length - offset;
2022
2023 value = 0;
2024 sg_pcopy_to_buffer(sg, 1, &value, remaining, offset);
2025 nbytes += remaining;
2026
2027 host->sg = sg = sg_next(sg);
2028 host->sg_len--;
2029 if (!sg || !host->sg_len) {
2030 atmci_writel(host, ATMCI_TDR, value);
2031 goto done;
2032 }
2033
2034 offset = 4 - remaining;
2035 sg_pcopy_to_buffer(sg, 1, (u8 *)&value + remaining,
2036 offset, 0);
2037 atmci_writel(host, ATMCI_TDR, value);
2038 nbytes += offset;
2039 }
2040
2041 status = atmci_readl(host, ATMCI_SR);
2042 if (status & ATMCI_DATA_ERROR_FLAGS) {
2043 atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_TXRDY
2044 | ATMCI_DATA_ERROR_FLAGS));
2045 host->data_status = status;
2046 data->bytes_xfered += nbytes;
2047 return;
2048 }
2049 } while (status & ATMCI_TXRDY);
2050
2051 host->pio_offset = offset;
2052 data->bytes_xfered += nbytes;
2053
2054 return;
2055
2056done:
2057 atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY);
2058 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
2059 data->bytes_xfered += nbytes;
2060 smp_wmb();
2061 atmci_set_pending(host, EVENT_XFER_COMPLETE);
2062}
2063
2064static void atmci_sdio_interrupt(struct atmel_mci *host, u32 status)
2065{
2066 int i;
2067
2068 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2069 struct atmel_mci_slot *slot = host->slot[i];
2070 if (slot && (status & slot->sdio_irq)) {
2071 mmc_signal_sdio_irq(slot->mmc);
2072 }
2073 }
2074}
2075
2076
2077static irqreturn_t atmci_interrupt(int irq, void *dev_id)
2078{
2079 struct atmel_mci *host = dev_id;
2080 u32 status, mask, pending;
2081 unsigned int pass_count = 0;
2082
2083 do {
2084 status = atmci_readl(host, ATMCI_SR);
2085 mask = atmci_readl(host, ATMCI_IMR);
2086 pending = status & mask;
2087 if (!pending)
2088 break;
2089
2090 if (pending & ATMCI_DATA_ERROR_FLAGS) {
2091 dev_dbg(&host->pdev->dev, "IRQ: data error\n");
2092 atmci_writel(host, ATMCI_IDR, ATMCI_DATA_ERROR_FLAGS
2093 | ATMCI_RXRDY | ATMCI_TXRDY
2094 | ATMCI_ENDRX | ATMCI_ENDTX
2095 | ATMCI_RXBUFF | ATMCI_TXBUFE);
2096
2097 host->data_status = status;
2098 dev_dbg(&host->pdev->dev, "set pending data error\n");
2099 smp_wmb();
2100 atmci_set_pending(host, EVENT_DATA_ERROR);
2101 tasklet_schedule(&host->tasklet);
2102 }
2103
2104 if (pending & ATMCI_TXBUFE) {
2105 dev_dbg(&host->pdev->dev, "IRQ: tx buffer empty\n");
2106 atmci_writel(host, ATMCI_IDR, ATMCI_TXBUFE);
2107 atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
2108 /*
2109 * We can receive this interruption before having configured
2110 * the second pdc buffer, so we need to reconfigure first and
2111 * second buffers again
2112 */
2113 if (host->data_size) {
2114 atmci_pdc_set_both_buf(host, XFER_TRANSMIT);
2115 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
2116 atmci_writel(host, ATMCI_IER, ATMCI_TXBUFE);
2117 } else {
2118 atmci_pdc_complete(host);
2119 }
2120 } else if (pending & ATMCI_ENDTX) {
2121 dev_dbg(&host->pdev->dev, "IRQ: end of tx buffer\n");
2122 atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
2123
2124 if (host->data_size) {
2125 atmci_pdc_set_single_buf(host,
2126 XFER_TRANSMIT, PDC_SECOND_BUF);
2127 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
2128 }
2129 }
2130
2131 if (pending & ATMCI_RXBUFF) {
2132 dev_dbg(&host->pdev->dev, "IRQ: rx buffer full\n");
2133 atmci_writel(host, ATMCI_IDR, ATMCI_RXBUFF);
2134 atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
2135 /*
2136 * We can receive this interruption before having configured
2137 * the second pdc buffer, so we need to reconfigure first and
2138 * second buffers again
2139 */
2140 if (host->data_size) {
2141 atmci_pdc_set_both_buf(host, XFER_RECEIVE);
2142 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
2143 atmci_writel(host, ATMCI_IER, ATMCI_RXBUFF);
2144 } else {
2145 atmci_pdc_complete(host);
2146 }
2147 } else if (pending & ATMCI_ENDRX) {
2148 dev_dbg(&host->pdev->dev, "IRQ: end of rx buffer\n");
2149 atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
2150
2151 if (host->data_size) {
2152 atmci_pdc_set_single_buf(host,
2153 XFER_RECEIVE, PDC_SECOND_BUF);
2154 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
2155 }
2156 }
2157
2158 /*
2159 * First mci IPs, so mainly the ones having pdc, have some
2160 * issues with the notbusy signal. You can't get it after
2161 * data transmission if you have not sent a stop command.
2162 * The appropriate workaround is to use the BLKE signal.
2163 */
2164 if (pending & ATMCI_BLKE) {
2165 dev_dbg(&host->pdev->dev, "IRQ: blke\n");
2166 atmci_writel(host, ATMCI_IDR, ATMCI_BLKE);
2167 smp_wmb();
2168 dev_dbg(&host->pdev->dev, "set pending notbusy\n");
2169 atmci_set_pending(host, EVENT_NOTBUSY);
2170 tasklet_schedule(&host->tasklet);
2171 }
2172
2173 if (pending & ATMCI_NOTBUSY) {
2174 dev_dbg(&host->pdev->dev, "IRQ: not_busy\n");
2175 atmci_writel(host, ATMCI_IDR, ATMCI_NOTBUSY);
2176 smp_wmb();
2177 dev_dbg(&host->pdev->dev, "set pending notbusy\n");
2178 atmci_set_pending(host, EVENT_NOTBUSY);
2179 tasklet_schedule(&host->tasklet);
2180 }
2181
2182 if (pending & ATMCI_RXRDY)
2183 atmci_read_data_pio(host);
2184 if (pending & ATMCI_TXRDY)
2185 atmci_write_data_pio(host);
2186
2187 if (pending & ATMCI_CMDRDY) {
2188 dev_dbg(&host->pdev->dev, "IRQ: cmd ready\n");
2189 atmci_writel(host, ATMCI_IDR, ATMCI_CMDRDY);
2190 host->cmd_status = status;
2191 smp_wmb();
2192 dev_dbg(&host->pdev->dev, "set pending cmd rdy\n");
2193 atmci_set_pending(host, EVENT_CMD_RDY);
2194 tasklet_schedule(&host->tasklet);
2195 }
2196
2197 if (pending & (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
2198 atmci_sdio_interrupt(host, status);
2199
2200 } while (pass_count++ < 5);
2201
2202 return pass_count ? IRQ_HANDLED : IRQ_NONE;
2203}
2204
2205static irqreturn_t atmci_detect_interrupt(int irq, void *dev_id)
2206{
2207 struct atmel_mci_slot *slot = dev_id;
2208
2209 /*
2210 * Disable interrupts until the pin has stabilized and check
2211 * the state then. Use mod_timer() since we may be in the
2212 * middle of the timer routine when this interrupt triggers.
2213 */
2214 disable_irq_nosync(irq);
2215 mod_timer(&slot->detect_timer, jiffies + msecs_to_jiffies(20));
2216
2217 return IRQ_HANDLED;
2218}
2219
2220static int atmci_init_slot(struct atmel_mci *host,
2221 struct mci_slot_pdata *slot_data, unsigned int id,
2222 u32 sdc_reg, u32 sdio_irq)
2223{
2224 struct mmc_host *mmc;
2225 struct atmel_mci_slot *slot;
2226
2227 mmc = mmc_alloc_host(sizeof(struct atmel_mci_slot), &host->pdev->dev);
2228 if (!mmc)
2229 return -ENOMEM;
2230
2231 slot = mmc_priv(mmc);
2232 slot->mmc = mmc;
2233 slot->host = host;
2234 slot->detect_pin = slot_data->detect_pin;
2235 slot->wp_pin = slot_data->wp_pin;
2236 slot->detect_is_active_high = slot_data->detect_is_active_high;
2237 slot->sdc_reg = sdc_reg;
2238 slot->sdio_irq = sdio_irq;
2239
2240 dev_dbg(&mmc->class_dev,
2241 "slot[%u]: bus_width=%u, detect_pin=%d, "
2242 "detect_is_active_high=%s, wp_pin=%d\n",
2243 id, slot_data->bus_width, slot_data->detect_pin,
2244 slot_data->detect_is_active_high ? "true" : "false",
2245 slot_data->wp_pin);
2246
2247 mmc->ops = &atmci_ops;
2248 mmc->f_min = DIV_ROUND_UP(host->bus_hz, 512);
2249 mmc->f_max = host->bus_hz / 2;
2250 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
2251 if (sdio_irq)
2252 mmc->caps |= MMC_CAP_SDIO_IRQ;
2253 if (host->caps.has_highspeed)
2254 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
2255 /*
2256 * Without the read/write proof capability, it is strongly suggested to
2257 * use only one bit for data to prevent fifo underruns and overruns
2258 * which will corrupt data.
2259 */
2260 if ((slot_data->bus_width >= 4) && host->caps.has_rwproof) {
2261 mmc->caps |= MMC_CAP_4_BIT_DATA;
2262 if (slot_data->bus_width >= 8)
2263 mmc->caps |= MMC_CAP_8_BIT_DATA;
2264 }
2265
2266 if (atmci_get_version(host) < 0x200) {
2267 mmc->max_segs = 256;
2268 mmc->max_blk_size = 4095;
2269 mmc->max_blk_count = 256;
2270 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2271 mmc->max_seg_size = mmc->max_blk_size * mmc->max_segs;
2272 } else {
2273 mmc->max_segs = 64;
2274 mmc->max_req_size = 32768 * 512;
2275 mmc->max_blk_size = 32768;
2276 mmc->max_blk_count = 512;
2277 }
2278
2279 /* Assume card is present initially */
2280 set_bit(ATMCI_CARD_PRESENT, &slot->flags);
2281 if (gpio_is_valid(slot->detect_pin)) {
2282 if (devm_gpio_request(&host->pdev->dev, slot->detect_pin,
2283 "mmc_detect")) {
2284 dev_dbg(&mmc->class_dev, "no detect pin available\n");
2285 slot->detect_pin = -EBUSY;
2286 } else if (gpio_get_value(slot->detect_pin) ^
2287 slot->detect_is_active_high) {
2288 clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
2289 }
2290 }
2291
2292 if (!gpio_is_valid(slot->detect_pin)) {
2293 if (slot_data->non_removable)
2294 mmc->caps |= MMC_CAP_NONREMOVABLE;
2295 else
2296 mmc->caps |= MMC_CAP_NEEDS_POLL;
2297 }
2298
2299 if (gpio_is_valid(slot->wp_pin)) {
2300 if (devm_gpio_request(&host->pdev->dev, slot->wp_pin,
2301 "mmc_wp")) {
2302 dev_dbg(&mmc->class_dev, "no WP pin available\n");
2303 slot->wp_pin = -EBUSY;
2304 }
2305 }
2306
2307 host->slot[id] = slot;
2308 mmc_regulator_get_supply(mmc);
2309 mmc_add_host(mmc);
2310
2311 if (gpio_is_valid(slot->detect_pin)) {
2312 int ret;
2313
2314 timer_setup(&slot->detect_timer, atmci_detect_change, 0);
2315
2316 ret = request_irq(gpio_to_irq(slot->detect_pin),
2317 atmci_detect_interrupt,
2318 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
2319 "mmc-detect", slot);
2320 if (ret) {
2321 dev_dbg(&mmc->class_dev,
2322 "could not request IRQ %d for detect pin\n",
2323 gpio_to_irq(slot->detect_pin));
2324 slot->detect_pin = -EBUSY;
2325 }
2326 }
2327
2328 atmci_init_debugfs(slot);
2329
2330 return 0;
2331}
2332
2333static void atmci_cleanup_slot(struct atmel_mci_slot *slot,
2334 unsigned int id)
2335{
2336 /* Debugfs stuff is cleaned up by mmc core */
2337
2338 set_bit(ATMCI_SHUTDOWN, &slot->flags);
2339 smp_wmb();
2340
2341 mmc_remove_host(slot->mmc);
2342
2343 if (gpio_is_valid(slot->detect_pin)) {
2344 int pin = slot->detect_pin;
2345
2346 free_irq(gpio_to_irq(pin), slot);
2347 del_timer_sync(&slot->detect_timer);
2348 }
2349
2350 slot->host->slot[id] = NULL;
2351 mmc_free_host(slot->mmc);
2352}
2353
2354static int atmci_configure_dma(struct atmel_mci *host)
2355{
2356 host->dma.chan = dma_request_chan(&host->pdev->dev, "rxtx");
2357
2358 if (PTR_ERR(host->dma.chan) == -ENODEV) {
2359 struct mci_platform_data *pdata = host->pdev->dev.platform_data;
2360 dma_cap_mask_t mask;
2361
2362 if (!pdata || !pdata->dma_filter)
2363 return -ENODEV;
2364
2365 dma_cap_zero(mask);
2366 dma_cap_set(DMA_SLAVE, mask);
2367
2368 host->dma.chan = dma_request_channel(mask, pdata->dma_filter,
2369 pdata->dma_slave);
2370 if (!host->dma.chan)
2371 host->dma.chan = ERR_PTR(-ENODEV);
2372 }
2373
2374 if (IS_ERR(host->dma.chan))
2375 return PTR_ERR(host->dma.chan);
2376
2377 dev_info(&host->pdev->dev, "using %s for DMA transfers\n",
2378 dma_chan_name(host->dma.chan));
2379
2380 host->dma_conf.src_addr = host->mapbase + ATMCI_RDR;
2381 host->dma_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2382 host->dma_conf.src_maxburst = 1;
2383 host->dma_conf.dst_addr = host->mapbase + ATMCI_TDR;
2384 host->dma_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2385 host->dma_conf.dst_maxburst = 1;
2386 host->dma_conf.device_fc = false;
2387
2388 return 0;
2389}
2390
2391/*
2392 * HSMCI (High Speed MCI) module is not fully compatible with MCI module.
2393 * HSMCI provides DMA support and a new config register but no more supports
2394 * PDC.
2395 */
2396static void atmci_get_cap(struct atmel_mci *host)
2397{
2398 unsigned int version;
2399
2400 version = atmci_get_version(host);
2401 dev_info(&host->pdev->dev,
2402 "version: 0x%x\n", version);
2403
2404 host->caps.has_dma_conf_reg = 0;
2405 host->caps.has_pdc = 1;
2406 host->caps.has_cfg_reg = 0;
2407 host->caps.has_cstor_reg = 0;
2408 host->caps.has_highspeed = 0;
2409 host->caps.has_rwproof = 0;
2410 host->caps.has_odd_clk_div = 0;
2411 host->caps.has_bad_data_ordering = 1;
2412 host->caps.need_reset_after_xfer = 1;
2413 host->caps.need_blksz_mul_4 = 1;
2414 host->caps.need_notbusy_for_read_ops = 0;
2415
2416 /* keep only major version number */
2417 switch (version & 0xf00) {
2418 case 0x600:
2419 case 0x500:
2420 host->caps.has_odd_clk_div = 1;
2421 fallthrough;
2422 case 0x400:
2423 case 0x300:
2424 host->caps.has_dma_conf_reg = 1;
2425 host->caps.has_pdc = 0;
2426 host->caps.has_cfg_reg = 1;
2427 host->caps.has_cstor_reg = 1;
2428 host->caps.has_highspeed = 1;
2429 fallthrough;
2430 case 0x200:
2431 host->caps.has_rwproof = 1;
2432 host->caps.need_blksz_mul_4 = 0;
2433 host->caps.need_notbusy_for_read_ops = 1;
2434 fallthrough;
2435 case 0x100:
2436 host->caps.has_bad_data_ordering = 0;
2437 host->caps.need_reset_after_xfer = 0;
2438 fallthrough;
2439 case 0x0:
2440 break;
2441 default:
2442 host->caps.has_pdc = 0;
2443 dev_warn(&host->pdev->dev,
2444 "Unmanaged mci version, set minimum capabilities\n");
2445 break;
2446 }
2447}
2448
2449static int atmci_probe(struct platform_device *pdev)
2450{
2451 struct mci_platform_data *pdata;
2452 struct atmel_mci *host;
2453 struct resource *regs;
2454 unsigned int nr_slots;
2455 int irq;
2456 int ret, i;
2457
2458 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2459 if (!regs)
2460 return -ENXIO;
2461 pdata = pdev->dev.platform_data;
2462 if (!pdata) {
2463 pdata = atmci_of_init(pdev);
2464 if (IS_ERR(pdata)) {
2465 dev_err(&pdev->dev, "platform data not available\n");
2466 return PTR_ERR(pdata);
2467 }
2468 }
2469
2470 irq = platform_get_irq(pdev, 0);
2471 if (irq < 0)
2472 return irq;
2473
2474 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
2475 if (!host)
2476 return -ENOMEM;
2477
2478 host->pdev = pdev;
2479 spin_lock_init(&host->lock);
2480 INIT_LIST_HEAD(&host->queue);
2481
2482 host->mck = devm_clk_get(&pdev->dev, "mci_clk");
2483 if (IS_ERR(host->mck))
2484 return PTR_ERR(host->mck);
2485
2486 host->regs = devm_ioremap(&pdev->dev, regs->start, resource_size(regs));
2487 if (!host->regs)
2488 return -ENOMEM;
2489
2490 ret = clk_prepare_enable(host->mck);
2491 if (ret)
2492 return ret;
2493
2494 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
2495 host->bus_hz = clk_get_rate(host->mck);
2496
2497 host->mapbase = regs->start;
2498
2499 tasklet_init(&host->tasklet, atmci_tasklet_func, (unsigned long)host);
2500
2501 ret = request_irq(irq, atmci_interrupt, 0, dev_name(&pdev->dev), host);
2502 if (ret) {
2503 clk_disable_unprepare(host->mck);
2504 return ret;
2505 }
2506
2507 /* Get MCI capabilities and set operations according to it */
2508 atmci_get_cap(host);
2509 ret = atmci_configure_dma(host);
2510 if (ret == -EPROBE_DEFER)
2511 goto err_dma_probe_defer;
2512 if (ret == 0) {
2513 host->prepare_data = &atmci_prepare_data_dma;
2514 host->submit_data = &atmci_submit_data_dma;
2515 host->stop_transfer = &atmci_stop_transfer_dma;
2516 } else if (host->caps.has_pdc) {
2517 dev_info(&pdev->dev, "using PDC\n");
2518 host->prepare_data = &atmci_prepare_data_pdc;
2519 host->submit_data = &atmci_submit_data_pdc;
2520 host->stop_transfer = &atmci_stop_transfer_pdc;
2521 } else {
2522 dev_info(&pdev->dev, "using PIO\n");
2523 host->prepare_data = &atmci_prepare_data;
2524 host->submit_data = &atmci_submit_data;
2525 host->stop_transfer = &atmci_stop_transfer;
2526 }
2527
2528 platform_set_drvdata(pdev, host);
2529
2530 timer_setup(&host->timer, atmci_timeout_timer, 0);
2531
2532 pm_runtime_get_noresume(&pdev->dev);
2533 pm_runtime_set_active(&pdev->dev);
2534 pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_DELAY);
2535 pm_runtime_use_autosuspend(&pdev->dev);
2536 pm_runtime_enable(&pdev->dev);
2537
2538 /* We need at least one slot to succeed */
2539 nr_slots = 0;
2540 ret = -ENODEV;
2541 if (pdata->slot[0].bus_width) {
2542 ret = atmci_init_slot(host, &pdata->slot[0],
2543 0, ATMCI_SDCSEL_SLOT_A, ATMCI_SDIOIRQA);
2544 if (!ret) {
2545 nr_slots++;
2546 host->buf_size = host->slot[0]->mmc->max_req_size;
2547 }
2548 }
2549 if (pdata->slot[1].bus_width) {
2550 ret = atmci_init_slot(host, &pdata->slot[1],
2551 1, ATMCI_SDCSEL_SLOT_B, ATMCI_SDIOIRQB);
2552 if (!ret) {
2553 nr_slots++;
2554 if (host->slot[1]->mmc->max_req_size > host->buf_size)
2555 host->buf_size =
2556 host->slot[1]->mmc->max_req_size;
2557 }
2558 }
2559
2560 if (!nr_slots) {
2561 dev_err(&pdev->dev, "init failed: no slot defined\n");
2562 goto err_init_slot;
2563 }
2564
2565 if (!host->caps.has_rwproof) {
2566 host->buffer = dma_alloc_coherent(&pdev->dev, host->buf_size,
2567 &host->buf_phys_addr,
2568 GFP_KERNEL);
2569 if (!host->buffer) {
2570 ret = -ENOMEM;
2571 dev_err(&pdev->dev, "buffer allocation failed\n");
2572 goto err_dma_alloc;
2573 }
2574 }
2575
2576 dev_info(&pdev->dev,
2577 "Atmel MCI controller at 0x%08lx irq %d, %u slots\n",
2578 host->mapbase, irq, nr_slots);
2579
2580 pm_runtime_mark_last_busy(&host->pdev->dev);
2581 pm_runtime_put_autosuspend(&pdev->dev);
2582
2583 return 0;
2584
2585err_dma_alloc:
2586 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2587 if (host->slot[i])
2588 atmci_cleanup_slot(host->slot[i], i);
2589 }
2590err_init_slot:
2591 clk_disable_unprepare(host->mck);
2592
2593 pm_runtime_disable(&pdev->dev);
2594 pm_runtime_put_noidle(&pdev->dev);
2595
2596 del_timer_sync(&host->timer);
2597 if (!IS_ERR(host->dma.chan))
2598 dma_release_channel(host->dma.chan);
2599err_dma_probe_defer:
2600 free_irq(irq, host);
2601 return ret;
2602}
2603
2604static int atmci_remove(struct platform_device *pdev)
2605{
2606 struct atmel_mci *host = platform_get_drvdata(pdev);
2607 unsigned int i;
2608
2609 pm_runtime_get_sync(&pdev->dev);
2610
2611 if (host->buffer)
2612 dma_free_coherent(&pdev->dev, host->buf_size,
2613 host->buffer, host->buf_phys_addr);
2614
2615 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2616 if (host->slot[i])
2617 atmci_cleanup_slot(host->slot[i], i);
2618 }
2619
2620 atmci_writel(host, ATMCI_IDR, ~0UL);
2621 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
2622 atmci_readl(host, ATMCI_SR);
2623
2624 del_timer_sync(&host->timer);
2625 if (!IS_ERR(host->dma.chan))
2626 dma_release_channel(host->dma.chan);
2627
2628 free_irq(platform_get_irq(pdev, 0), host);
2629
2630 clk_disable_unprepare(host->mck);
2631
2632 pm_runtime_disable(&pdev->dev);
2633 pm_runtime_put_noidle(&pdev->dev);
2634
2635 return 0;
2636}
2637
2638#ifdef CONFIG_PM
2639static int atmci_runtime_suspend(struct device *dev)
2640{
2641 struct atmel_mci *host = dev_get_drvdata(dev);
2642
2643 clk_disable_unprepare(host->mck);
2644
2645 pinctrl_pm_select_sleep_state(dev);
2646
2647 return 0;
2648}
2649
2650static int atmci_runtime_resume(struct device *dev)
2651{
2652 struct atmel_mci *host = dev_get_drvdata(dev);
2653
2654 pinctrl_select_default_state(dev);
2655
2656 return clk_prepare_enable(host->mck);
2657}
2658#endif
2659
2660static const struct dev_pm_ops atmci_dev_pm_ops = {
2661 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
2662 pm_runtime_force_resume)
2663 SET_RUNTIME_PM_OPS(atmci_runtime_suspend, atmci_runtime_resume, NULL)
2664};
2665
2666static struct platform_driver atmci_driver = {
2667 .probe = atmci_probe,
2668 .remove = atmci_remove,
2669 .driver = {
2670 .name = "atmel_mci",
2671 .of_match_table = of_match_ptr(atmci_dt_ids),
2672 .pm = &atmci_dev_pm_ops,
2673 },
2674};
2675module_platform_driver(atmci_driver);
2676
2677MODULE_DESCRIPTION("Atmel Multimedia Card Interface driver");
2678MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
2679MODULE_LICENSE("GPL v2");