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1/* linux/drivers/mfd/sm501.c
2 *
3 * Copyright (C) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * Vincent Sanders <vince@simtec.co.uk>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * SM501 MFD driver
12*/
13
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/delay.h>
17#include <linux/init.h>
18#include <linux/list.h>
19#include <linux/device.h>
20#include <linux/platform_device.h>
21#include <linux/pci.h>
22#include <linux/i2c-gpio.h>
23#include <linux/slab.h>
24
25#include <linux/sm501.h>
26#include <linux/sm501-regs.h>
27#include <linux/serial_8250.h>
28
29#include <linux/io.h>
30
31struct sm501_device {
32 struct list_head list;
33 struct platform_device pdev;
34};
35
36struct sm501_gpio;
37
38#ifdef CONFIG_MFD_SM501_GPIO
39#include <linux/gpio.h>
40
41struct sm501_gpio_chip {
42 struct gpio_chip gpio;
43 struct sm501_gpio *ourgpio; /* to get back to parent. */
44 void __iomem *regbase;
45 void __iomem *control; /* address of control reg. */
46};
47
48struct sm501_gpio {
49 struct sm501_gpio_chip low;
50 struct sm501_gpio_chip high;
51 spinlock_t lock;
52
53 unsigned int registered : 1;
54 void __iomem *regs;
55 struct resource *regs_res;
56};
57#else
58struct sm501_gpio {
59 /* no gpio support, empty definition for sm501_devdata. */
60};
61#endif
62
63struct sm501_devdata {
64 spinlock_t reg_lock;
65 struct mutex clock_lock;
66 struct list_head devices;
67 struct sm501_gpio gpio;
68
69 struct device *dev;
70 struct resource *io_res;
71 struct resource *mem_res;
72 struct resource *regs_claim;
73 struct sm501_platdata *platdata;
74
75
76 unsigned int in_suspend;
77 unsigned long pm_misc;
78
79 int unit_power[20];
80 unsigned int pdev_id;
81 unsigned int irq;
82 void __iomem *regs;
83 unsigned int rev;
84};
85
86
87#define MHZ (1000 * 1000)
88
89#ifdef DEBUG
90static const unsigned int div_tab[] = {
91 [0] = 1,
92 [1] = 2,
93 [2] = 4,
94 [3] = 8,
95 [4] = 16,
96 [5] = 32,
97 [6] = 64,
98 [7] = 128,
99 [8] = 3,
100 [9] = 6,
101 [10] = 12,
102 [11] = 24,
103 [12] = 48,
104 [13] = 96,
105 [14] = 192,
106 [15] = 384,
107 [16] = 5,
108 [17] = 10,
109 [18] = 20,
110 [19] = 40,
111 [20] = 80,
112 [21] = 160,
113 [22] = 320,
114 [23] = 604,
115};
116
117static unsigned long decode_div(unsigned long pll2, unsigned long val,
118 unsigned int lshft, unsigned int selbit,
119 unsigned long mask)
120{
121 if (val & selbit)
122 pll2 = 288 * MHZ;
123
124 return pll2 / div_tab[(val >> lshft) & mask];
125}
126
127#define fmt_freq(x) ((x) / MHZ), ((x) % MHZ), (x)
128
129/* sm501_dump_clk
130 *
131 * Print out the current clock configuration for the device
132*/
133
134static void sm501_dump_clk(struct sm501_devdata *sm)
135{
136 unsigned long misct = smc501_readl(sm->regs + SM501_MISC_TIMING);
137 unsigned long pm0 = smc501_readl(sm->regs + SM501_POWER_MODE_0_CLOCK);
138 unsigned long pm1 = smc501_readl(sm->regs + SM501_POWER_MODE_1_CLOCK);
139 unsigned long pmc = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL);
140 unsigned long sdclk0, sdclk1;
141 unsigned long pll2 = 0;
142
143 switch (misct & 0x30) {
144 case 0x00:
145 pll2 = 336 * MHZ;
146 break;
147 case 0x10:
148 pll2 = 288 * MHZ;
149 break;
150 case 0x20:
151 pll2 = 240 * MHZ;
152 break;
153 case 0x30:
154 pll2 = 192 * MHZ;
155 break;
156 }
157
158 sdclk0 = (misct & (1<<12)) ? pll2 : 288 * MHZ;
159 sdclk0 /= div_tab[((misct >> 8) & 0xf)];
160
161 sdclk1 = (misct & (1<<20)) ? pll2 : 288 * MHZ;
162 sdclk1 /= div_tab[((misct >> 16) & 0xf)];
163
164 dev_dbg(sm->dev, "MISCT=%08lx, PM0=%08lx, PM1=%08lx\n",
165 misct, pm0, pm1);
166
167 dev_dbg(sm->dev, "PLL2 = %ld.%ld MHz (%ld), SDCLK0=%08lx, SDCLK1=%08lx\n",
168 fmt_freq(pll2), sdclk0, sdclk1);
169
170 dev_dbg(sm->dev, "SDRAM: PM0=%ld, PM1=%ld\n", sdclk0, sdclk1);
171
172 dev_dbg(sm->dev, "PM0[%c]: "
173 "P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), "
174 "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n",
175 (pmc & 3 ) == 0 ? '*' : '-',
176 fmt_freq(decode_div(pll2, pm0, 24, 1<<29, 31)),
177 fmt_freq(decode_div(pll2, pm0, 16, 1<<20, 15)),
178 fmt_freq(decode_div(pll2, pm0, 8, 1<<12, 15)),
179 fmt_freq(decode_div(pll2, pm0, 0, 1<<4, 15)));
180
181 dev_dbg(sm->dev, "PM1[%c]: "
182 "P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), "
183 "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n",
184 (pmc & 3 ) == 1 ? '*' : '-',
185 fmt_freq(decode_div(pll2, pm1, 24, 1<<29, 31)),
186 fmt_freq(decode_div(pll2, pm1, 16, 1<<20, 15)),
187 fmt_freq(decode_div(pll2, pm1, 8, 1<<12, 15)),
188 fmt_freq(decode_div(pll2, pm1, 0, 1<<4, 15)));
189}
190
191static void sm501_dump_regs(struct sm501_devdata *sm)
192{
193 void __iomem *regs = sm->regs;
194
195 dev_info(sm->dev, "System Control %08x\n",
196 smc501_readl(regs + SM501_SYSTEM_CONTROL));
197 dev_info(sm->dev, "Misc Control %08x\n",
198 smc501_readl(regs + SM501_MISC_CONTROL));
199 dev_info(sm->dev, "GPIO Control Low %08x\n",
200 smc501_readl(regs + SM501_GPIO31_0_CONTROL));
201 dev_info(sm->dev, "GPIO Control Hi %08x\n",
202 smc501_readl(regs + SM501_GPIO63_32_CONTROL));
203 dev_info(sm->dev, "DRAM Control %08x\n",
204 smc501_readl(regs + SM501_DRAM_CONTROL));
205 dev_info(sm->dev, "Arbitration Ctrl %08x\n",
206 smc501_readl(regs + SM501_ARBTRTN_CONTROL));
207 dev_info(sm->dev, "Misc Timing %08x\n",
208 smc501_readl(regs + SM501_MISC_TIMING));
209}
210
211static void sm501_dump_gate(struct sm501_devdata *sm)
212{
213 dev_info(sm->dev, "CurrentGate %08x\n",
214 smc501_readl(sm->regs + SM501_CURRENT_GATE));
215 dev_info(sm->dev, "CurrentClock %08x\n",
216 smc501_readl(sm->regs + SM501_CURRENT_CLOCK));
217 dev_info(sm->dev, "PowerModeControl %08x\n",
218 smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL));
219}
220
221#else
222static inline void sm501_dump_gate(struct sm501_devdata *sm) { }
223static inline void sm501_dump_regs(struct sm501_devdata *sm) { }
224static inline void sm501_dump_clk(struct sm501_devdata *sm) { }
225#endif
226
227/* sm501_sync_regs
228 *
229 * ensure the
230*/
231
232static void sm501_sync_regs(struct sm501_devdata *sm)
233{
234 smc501_readl(sm->regs);
235}
236
237static inline void sm501_mdelay(struct sm501_devdata *sm, unsigned int delay)
238{
239 /* during suspend/resume, we are currently not allowed to sleep,
240 * so change to using mdelay() instead of msleep() if we
241 * are in one of these paths */
242
243 if (sm->in_suspend)
244 mdelay(delay);
245 else
246 msleep(delay);
247}
248
249/* sm501_misc_control
250 *
251 * alters the miscellaneous control parameters
252*/
253
254int sm501_misc_control(struct device *dev,
255 unsigned long set, unsigned long clear)
256{
257 struct sm501_devdata *sm = dev_get_drvdata(dev);
258 unsigned long misc;
259 unsigned long save;
260 unsigned long to;
261
262 spin_lock_irqsave(&sm->reg_lock, save);
263
264 misc = smc501_readl(sm->regs + SM501_MISC_CONTROL);
265 to = (misc & ~clear) | set;
266
267 if (to != misc) {
268 smc501_writel(to, sm->regs + SM501_MISC_CONTROL);
269 sm501_sync_regs(sm);
270
271 dev_dbg(sm->dev, "MISC_CONTROL %08lx\n", misc);
272 }
273
274 spin_unlock_irqrestore(&sm->reg_lock, save);
275 return to;
276}
277
278EXPORT_SYMBOL_GPL(sm501_misc_control);
279
280/* sm501_modify_reg
281 *
282 * Modify a register in the SM501 which may be shared with other
283 * drivers.
284*/
285
286unsigned long sm501_modify_reg(struct device *dev,
287 unsigned long reg,
288 unsigned long set,
289 unsigned long clear)
290{
291 struct sm501_devdata *sm = dev_get_drvdata(dev);
292 unsigned long data;
293 unsigned long save;
294
295 spin_lock_irqsave(&sm->reg_lock, save);
296
297 data = smc501_readl(sm->regs + reg);
298 data |= set;
299 data &= ~clear;
300
301 smc501_writel(data, sm->regs + reg);
302 sm501_sync_regs(sm);
303
304 spin_unlock_irqrestore(&sm->reg_lock, save);
305
306 return data;
307}
308
309EXPORT_SYMBOL_GPL(sm501_modify_reg);
310
311/* sm501_unit_power
312 *
313 * alters the power active gate to set specific units on or off
314 */
315
316int sm501_unit_power(struct device *dev, unsigned int unit, unsigned int to)
317{
318 struct sm501_devdata *sm = dev_get_drvdata(dev);
319 unsigned long mode;
320 unsigned long gate;
321 unsigned long clock;
322
323 mutex_lock(&sm->clock_lock);
324
325 mode = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL);
326 gate = smc501_readl(sm->regs + SM501_CURRENT_GATE);
327 clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK);
328
329 mode &= 3; /* get current power mode */
330
331 if (unit >= ARRAY_SIZE(sm->unit_power)) {
332 dev_err(dev, "%s: bad unit %d\n", __func__, unit);
333 goto already;
334 }
335
336 dev_dbg(sm->dev, "%s: unit %d, cur %d, to %d\n", __func__, unit,
337 sm->unit_power[unit], to);
338
339 if (to == 0 && sm->unit_power[unit] == 0) {
340 dev_err(sm->dev, "unit %d is already shutdown\n", unit);
341 goto already;
342 }
343
344 sm->unit_power[unit] += to ? 1 : -1;
345 to = sm->unit_power[unit] ? 1 : 0;
346
347 if (to) {
348 if (gate & (1 << unit))
349 goto already;
350 gate |= (1 << unit);
351 } else {
352 if (!(gate & (1 << unit)))
353 goto already;
354 gate &= ~(1 << unit);
355 }
356
357 switch (mode) {
358 case 1:
359 smc501_writel(gate, sm->regs + SM501_POWER_MODE_0_GATE);
360 smc501_writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK);
361 mode = 0;
362 break;
363 case 2:
364 case 0:
365 smc501_writel(gate, sm->regs + SM501_POWER_MODE_1_GATE);
366 smc501_writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK);
367 mode = 1;
368 break;
369
370 default:
371 gate = -1;
372 goto already;
373 }
374
375 smc501_writel(mode, sm->regs + SM501_POWER_MODE_CONTROL);
376 sm501_sync_regs(sm);
377
378 dev_dbg(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n",
379 gate, clock, mode);
380
381 sm501_mdelay(sm, 16);
382
383 already:
384 mutex_unlock(&sm->clock_lock);
385 return gate;
386}
387
388EXPORT_SYMBOL_GPL(sm501_unit_power);
389
390/* clock value structure. */
391struct sm501_clock {
392 unsigned long mclk;
393 int divider;
394 int shift;
395 unsigned int m, n, k;
396};
397
398/* sm501_calc_clock
399 *
400 * Calculates the nearest discrete clock frequency that
401 * can be achieved with the specified input clock.
402 * the maximum divisor is 3 or 5
403 */
404
405static int sm501_calc_clock(unsigned long freq,
406 struct sm501_clock *clock,
407 int max_div,
408 unsigned long mclk,
409 long *best_diff)
410{
411 int ret = 0;
412 int divider;
413 int shift;
414 long diff;
415
416 /* try dividers 1 and 3 for CRT and for panel,
417 try divider 5 for panel only.*/
418
419 for (divider = 1; divider <= max_div; divider += 2) {
420 /* try all 8 shift values.*/
421 for (shift = 0; shift < 8; shift++) {
422 /* Calculate difference to requested clock */
423 diff = DIV_ROUND_CLOSEST(mclk, divider << shift) - freq;
424 if (diff < 0)
425 diff = -diff;
426
427 /* If it is less than the current, use it */
428 if (diff < *best_diff) {
429 *best_diff = diff;
430
431 clock->mclk = mclk;
432 clock->divider = divider;
433 clock->shift = shift;
434 ret = 1;
435 }
436 }
437 }
438
439 return ret;
440}
441
442/* sm501_calc_pll
443 *
444 * Calculates the nearest discrete clock frequency that can be
445 * achieved using the programmable PLL.
446 * the maximum divisor is 3 or 5
447 */
448
449static unsigned long sm501_calc_pll(unsigned long freq,
450 struct sm501_clock *clock,
451 int max_div)
452{
453 unsigned long mclk;
454 unsigned int m, n, k;
455 long best_diff = 999999999;
456
457 /*
458 * The SM502 datasheet doesn't specify the min/max values for M and N.
459 * N = 1 at least doesn't work in practice.
460 */
461 for (m = 2; m <= 255; m++) {
462 for (n = 2; n <= 127; n++) {
463 for (k = 0; k <= 1; k++) {
464 mclk = (24000000UL * m / n) >> k;
465
466 if (sm501_calc_clock(freq, clock, max_div,
467 mclk, &best_diff)) {
468 clock->m = m;
469 clock->n = n;
470 clock->k = k;
471 }
472 }
473 }
474 }
475
476 /* Return best clock. */
477 return clock->mclk / (clock->divider << clock->shift);
478}
479
480/* sm501_select_clock
481 *
482 * Calculates the nearest discrete clock frequency that can be
483 * achieved using the 288MHz and 336MHz PLLs.
484 * the maximum divisor is 3 or 5
485 */
486
487static unsigned long sm501_select_clock(unsigned long freq,
488 struct sm501_clock *clock,
489 int max_div)
490{
491 unsigned long mclk;
492 long best_diff = 999999999;
493
494 /* Try 288MHz and 336MHz clocks. */
495 for (mclk = 288000000; mclk <= 336000000; mclk += 48000000) {
496 sm501_calc_clock(freq, clock, max_div, mclk, &best_diff);
497 }
498
499 /* Return best clock. */
500 return clock->mclk / (clock->divider << clock->shift);
501}
502
503/* sm501_set_clock
504 *
505 * set one of the four clock sources to the closest available frequency to
506 * the one specified
507*/
508
509unsigned long sm501_set_clock(struct device *dev,
510 int clksrc,
511 unsigned long req_freq)
512{
513 struct sm501_devdata *sm = dev_get_drvdata(dev);
514 unsigned long mode = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL);
515 unsigned long gate = smc501_readl(sm->regs + SM501_CURRENT_GATE);
516 unsigned long clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK);
517 unsigned int pll_reg = 0;
518 unsigned long sm501_freq; /* the actual frequency achieved */
519 u64 reg;
520
521 struct sm501_clock to;
522
523 /* find achivable discrete frequency and setup register value
524 * accordingly, V2XCLK, MCLK and M1XCLK are the same P2XCLK
525 * has an extra bit for the divider */
526
527 switch (clksrc) {
528 case SM501_CLOCK_P2XCLK:
529 /* This clock is divided in half so to achieve the
530 * requested frequency the value must be multiplied by
531 * 2. This clock also has an additional pre divisor */
532
533 if (sm->rev >= 0xC0) {
534 /* SM502 -> use the programmable PLL */
535 sm501_freq = (sm501_calc_pll(2 * req_freq,
536 &to, 5) / 2);
537 reg = to.shift & 0x07;/* bottom 3 bits are shift */
538 if (to.divider == 3)
539 reg |= 0x08; /* /3 divider required */
540 else if (to.divider == 5)
541 reg |= 0x10; /* /5 divider required */
542 reg |= 0x40; /* select the programmable PLL */
543 pll_reg = 0x20000 | (to.k << 15) | (to.n << 8) | to.m;
544 } else {
545 sm501_freq = (sm501_select_clock(2 * req_freq,
546 &to, 5) / 2);
547 reg = to.shift & 0x07;/* bottom 3 bits are shift */
548 if (to.divider == 3)
549 reg |= 0x08; /* /3 divider required */
550 else if (to.divider == 5)
551 reg |= 0x10; /* /5 divider required */
552 if (to.mclk != 288000000)
553 reg |= 0x20; /* which mclk pll is source */
554 }
555 break;
556
557 case SM501_CLOCK_V2XCLK:
558 /* This clock is divided in half so to achieve the
559 * requested frequency the value must be multiplied by 2. */
560
561 sm501_freq = (sm501_select_clock(2 * req_freq, &to, 3) / 2);
562 reg=to.shift & 0x07; /* bottom 3 bits are shift */
563 if (to.divider == 3)
564 reg |= 0x08; /* /3 divider required */
565 if (to.mclk != 288000000)
566 reg |= 0x10; /* which mclk pll is source */
567 break;
568
569 case SM501_CLOCK_MCLK:
570 case SM501_CLOCK_M1XCLK:
571 /* These clocks are the same and not further divided */
572
573 sm501_freq = sm501_select_clock( req_freq, &to, 3);
574 reg=to.shift & 0x07; /* bottom 3 bits are shift */
575 if (to.divider == 3)
576 reg |= 0x08; /* /3 divider required */
577 if (to.mclk != 288000000)
578 reg |= 0x10; /* which mclk pll is source */
579 break;
580
581 default:
582 return 0; /* this is bad */
583 }
584
585 mutex_lock(&sm->clock_lock);
586
587 mode = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL);
588 gate = smc501_readl(sm->regs + SM501_CURRENT_GATE);
589 clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK);
590
591 clock = clock & ~(0xFF << clksrc);
592 clock |= reg<<clksrc;
593
594 mode &= 3; /* find current mode */
595
596 switch (mode) {
597 case 1:
598 smc501_writel(gate, sm->regs + SM501_POWER_MODE_0_GATE);
599 smc501_writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK);
600 mode = 0;
601 break;
602 case 2:
603 case 0:
604 smc501_writel(gate, sm->regs + SM501_POWER_MODE_1_GATE);
605 smc501_writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK);
606 mode = 1;
607 break;
608
609 default:
610 mutex_unlock(&sm->clock_lock);
611 return -1;
612 }
613
614 smc501_writel(mode, sm->regs + SM501_POWER_MODE_CONTROL);
615
616 if (pll_reg)
617 smc501_writel(pll_reg,
618 sm->regs + SM501_PROGRAMMABLE_PLL_CONTROL);
619
620 sm501_sync_regs(sm);
621
622 dev_dbg(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n",
623 gate, clock, mode);
624
625 sm501_mdelay(sm, 16);
626 mutex_unlock(&sm->clock_lock);
627
628 sm501_dump_clk(sm);
629
630 return sm501_freq;
631}
632
633EXPORT_SYMBOL_GPL(sm501_set_clock);
634
635/* sm501_find_clock
636 *
637 * finds the closest available frequency for a given clock
638*/
639
640unsigned long sm501_find_clock(struct device *dev,
641 int clksrc,
642 unsigned long req_freq)
643{
644 struct sm501_devdata *sm = dev_get_drvdata(dev);
645 unsigned long sm501_freq; /* the frequency achieveable by the 501 */
646 struct sm501_clock to;
647
648 switch (clksrc) {
649 case SM501_CLOCK_P2XCLK:
650 if (sm->rev >= 0xC0) {
651 /* SM502 -> use the programmable PLL */
652 sm501_freq = (sm501_calc_pll(2 * req_freq,
653 &to, 5) / 2);
654 } else {
655 sm501_freq = (sm501_select_clock(2 * req_freq,
656 &to, 5) / 2);
657 }
658 break;
659
660 case SM501_CLOCK_V2XCLK:
661 sm501_freq = (sm501_select_clock(2 * req_freq, &to, 3) / 2);
662 break;
663
664 case SM501_CLOCK_MCLK:
665 case SM501_CLOCK_M1XCLK:
666 sm501_freq = sm501_select_clock(req_freq, &to, 3);
667 break;
668
669 default:
670 sm501_freq = 0; /* error */
671 }
672
673 return sm501_freq;
674}
675
676EXPORT_SYMBOL_GPL(sm501_find_clock);
677
678static struct sm501_device *to_sm_device(struct platform_device *pdev)
679{
680 return container_of(pdev, struct sm501_device, pdev);
681}
682
683/* sm501_device_release
684 *
685 * A release function for the platform devices we create to allow us to
686 * free any items we allocated
687*/
688
689static void sm501_device_release(struct device *dev)
690{
691 kfree(to_sm_device(to_platform_device(dev)));
692}
693
694/* sm501_create_subdev
695 *
696 * Create a skeleton platform device with resources for passing to a
697 * sub-driver
698*/
699
700static struct platform_device *
701sm501_create_subdev(struct sm501_devdata *sm, char *name,
702 unsigned int res_count, unsigned int platform_data_size)
703{
704 struct sm501_device *smdev;
705
706 smdev = kzalloc(sizeof(struct sm501_device) +
707 (sizeof(struct resource) * res_count) +
708 platform_data_size, GFP_KERNEL);
709 if (!smdev)
710 return NULL;
711
712 smdev->pdev.dev.release = sm501_device_release;
713
714 smdev->pdev.name = name;
715 smdev->pdev.id = sm->pdev_id;
716 smdev->pdev.dev.parent = sm->dev;
717
718 if (res_count) {
719 smdev->pdev.resource = (struct resource *)(smdev+1);
720 smdev->pdev.num_resources = res_count;
721 }
722 if (platform_data_size)
723 smdev->pdev.dev.platform_data = (void *)(smdev+1);
724
725 return &smdev->pdev;
726}
727
728/* sm501_register_device
729 *
730 * Register a platform device created with sm501_create_subdev()
731*/
732
733static int sm501_register_device(struct sm501_devdata *sm,
734 struct platform_device *pdev)
735{
736 struct sm501_device *smdev = to_sm_device(pdev);
737 int ptr;
738 int ret;
739
740 for (ptr = 0; ptr < pdev->num_resources; ptr++) {
741 printk(KERN_DEBUG "%s[%d] %pR\n",
742 pdev->name, ptr, &pdev->resource[ptr]);
743 }
744
745 ret = platform_device_register(pdev);
746
747 if (ret >= 0) {
748 dev_dbg(sm->dev, "registered %s\n", pdev->name);
749 list_add_tail(&smdev->list, &sm->devices);
750 } else
751 dev_err(sm->dev, "error registering %s (%d)\n",
752 pdev->name, ret);
753
754 return ret;
755}
756
757/* sm501_create_subio
758 *
759 * Fill in an IO resource for a sub device
760*/
761
762static void sm501_create_subio(struct sm501_devdata *sm,
763 struct resource *res,
764 resource_size_t offs,
765 resource_size_t size)
766{
767 res->flags = IORESOURCE_MEM;
768 res->parent = sm->io_res;
769 res->start = sm->io_res->start + offs;
770 res->end = res->start + size - 1;
771}
772
773/* sm501_create_mem
774 *
775 * Fill in an MEM resource for a sub device
776*/
777
778static void sm501_create_mem(struct sm501_devdata *sm,
779 struct resource *res,
780 resource_size_t *offs,
781 resource_size_t size)
782{
783 *offs -= size; /* adjust memory size */
784
785 res->flags = IORESOURCE_MEM;
786 res->parent = sm->mem_res;
787 res->start = sm->mem_res->start + *offs;
788 res->end = res->start + size - 1;
789}
790
791/* sm501_create_irq
792 *
793 * Fill in an IRQ resource for a sub device
794*/
795
796static void sm501_create_irq(struct sm501_devdata *sm,
797 struct resource *res)
798{
799 res->flags = IORESOURCE_IRQ;
800 res->parent = NULL;
801 res->start = res->end = sm->irq;
802}
803
804static int sm501_register_usbhost(struct sm501_devdata *sm,
805 resource_size_t *mem_avail)
806{
807 struct platform_device *pdev;
808
809 pdev = sm501_create_subdev(sm, "sm501-usb", 3, 0);
810 if (!pdev)
811 return -ENOMEM;
812
813 sm501_create_subio(sm, &pdev->resource[0], 0x40000, 0x20000);
814 sm501_create_mem(sm, &pdev->resource[1], mem_avail, 256*1024);
815 sm501_create_irq(sm, &pdev->resource[2]);
816
817 return sm501_register_device(sm, pdev);
818}
819
820static void sm501_setup_uart_data(struct sm501_devdata *sm,
821 struct plat_serial8250_port *uart_data,
822 unsigned int offset)
823{
824 uart_data->membase = sm->regs + offset;
825 uart_data->mapbase = sm->io_res->start + offset;
826 uart_data->iotype = UPIO_MEM;
827 uart_data->irq = sm->irq;
828 uart_data->flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ;
829 uart_data->regshift = 2;
830 uart_data->uartclk = (9600 * 16);
831}
832
833static int sm501_register_uart(struct sm501_devdata *sm, int devices)
834{
835 struct platform_device *pdev;
836 struct plat_serial8250_port *uart_data;
837
838 pdev = sm501_create_subdev(sm, "serial8250", 0,
839 sizeof(struct plat_serial8250_port) * 3);
840 if (!pdev)
841 return -ENOMEM;
842
843 uart_data = dev_get_platdata(&pdev->dev);
844
845 if (devices & SM501_USE_UART0) {
846 sm501_setup_uart_data(sm, uart_data++, 0x30000);
847 sm501_unit_power(sm->dev, SM501_GATE_UART0, 1);
848 sm501_modify_reg(sm->dev, SM501_IRQ_MASK, 1 << 12, 0);
849 sm501_modify_reg(sm->dev, SM501_GPIO63_32_CONTROL, 0x01e0, 0);
850 }
851 if (devices & SM501_USE_UART1) {
852 sm501_setup_uart_data(sm, uart_data++, 0x30020);
853 sm501_unit_power(sm->dev, SM501_GATE_UART1, 1);
854 sm501_modify_reg(sm->dev, SM501_IRQ_MASK, 1 << 13, 0);
855 sm501_modify_reg(sm->dev, SM501_GPIO63_32_CONTROL, 0x1e00, 0);
856 }
857
858 pdev->id = PLAT8250_DEV_SM501;
859
860 return sm501_register_device(sm, pdev);
861}
862
863static int sm501_register_display(struct sm501_devdata *sm,
864 resource_size_t *mem_avail)
865{
866 struct platform_device *pdev;
867
868 pdev = sm501_create_subdev(sm, "sm501-fb", 4, 0);
869 if (!pdev)
870 return -ENOMEM;
871
872 sm501_create_subio(sm, &pdev->resource[0], 0x80000, 0x10000);
873 sm501_create_subio(sm, &pdev->resource[1], 0x100000, 0x50000);
874 sm501_create_mem(sm, &pdev->resource[2], mem_avail, *mem_avail);
875 sm501_create_irq(sm, &pdev->resource[3]);
876
877 return sm501_register_device(sm, pdev);
878}
879
880#ifdef CONFIG_MFD_SM501_GPIO
881
882static inline struct sm501_gpio_chip *to_sm501_gpio(struct gpio_chip *gc)
883{
884 return container_of(gc, struct sm501_gpio_chip, gpio);
885}
886
887static inline struct sm501_devdata *sm501_gpio_to_dev(struct sm501_gpio *gpio)
888{
889 return container_of(gpio, struct sm501_devdata, gpio);
890}
891
892static int sm501_gpio_get(struct gpio_chip *chip, unsigned offset)
893
894{
895 struct sm501_gpio_chip *smgpio = to_sm501_gpio(chip);
896 unsigned long result;
897
898 result = smc501_readl(smgpio->regbase + SM501_GPIO_DATA_LOW);
899 result >>= offset;
900
901 return result & 1UL;
902}
903
904static void sm501_gpio_ensure_gpio(struct sm501_gpio_chip *smchip,
905 unsigned long bit)
906{
907 unsigned long ctrl;
908
909 /* check and modify if this pin is not set as gpio. */
910
911 if (smc501_readl(smchip->control) & bit) {
912 dev_info(sm501_gpio_to_dev(smchip->ourgpio)->dev,
913 "changing mode of gpio, bit %08lx\n", bit);
914
915 ctrl = smc501_readl(smchip->control);
916 ctrl &= ~bit;
917 smc501_writel(ctrl, smchip->control);
918
919 sm501_sync_regs(sm501_gpio_to_dev(smchip->ourgpio));
920 }
921}
922
923static void sm501_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
924
925{
926 struct sm501_gpio_chip *smchip = to_sm501_gpio(chip);
927 struct sm501_gpio *smgpio = smchip->ourgpio;
928 unsigned long bit = 1 << offset;
929 void __iomem *regs = smchip->regbase;
930 unsigned long save;
931 unsigned long val;
932
933 dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d)\n",
934 __func__, chip, offset);
935
936 spin_lock_irqsave(&smgpio->lock, save);
937
938 val = smc501_readl(regs + SM501_GPIO_DATA_LOW) & ~bit;
939 if (value)
940 val |= bit;
941 smc501_writel(val, regs);
942
943 sm501_sync_regs(sm501_gpio_to_dev(smgpio));
944 sm501_gpio_ensure_gpio(smchip, bit);
945
946 spin_unlock_irqrestore(&smgpio->lock, save);
947}
948
949static int sm501_gpio_input(struct gpio_chip *chip, unsigned offset)
950{
951 struct sm501_gpio_chip *smchip = to_sm501_gpio(chip);
952 struct sm501_gpio *smgpio = smchip->ourgpio;
953 void __iomem *regs = smchip->regbase;
954 unsigned long bit = 1 << offset;
955 unsigned long save;
956 unsigned long ddr;
957
958 dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d)\n",
959 __func__, chip, offset);
960
961 spin_lock_irqsave(&smgpio->lock, save);
962
963 ddr = smc501_readl(regs + SM501_GPIO_DDR_LOW);
964 smc501_writel(ddr & ~bit, regs + SM501_GPIO_DDR_LOW);
965
966 sm501_sync_regs(sm501_gpio_to_dev(smgpio));
967 sm501_gpio_ensure_gpio(smchip, bit);
968
969 spin_unlock_irqrestore(&smgpio->lock, save);
970
971 return 0;
972}
973
974static int sm501_gpio_output(struct gpio_chip *chip,
975 unsigned offset, int value)
976{
977 struct sm501_gpio_chip *smchip = to_sm501_gpio(chip);
978 struct sm501_gpio *smgpio = smchip->ourgpio;
979 unsigned long bit = 1 << offset;
980 void __iomem *regs = smchip->regbase;
981 unsigned long save;
982 unsigned long val;
983 unsigned long ddr;
984
985 dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d,%d)\n",
986 __func__, chip, offset, value);
987
988 spin_lock_irqsave(&smgpio->lock, save);
989
990 val = smc501_readl(regs + SM501_GPIO_DATA_LOW);
991 if (value)
992 val |= bit;
993 else
994 val &= ~bit;
995 smc501_writel(val, regs);
996
997 ddr = smc501_readl(regs + SM501_GPIO_DDR_LOW);
998 smc501_writel(ddr | bit, regs + SM501_GPIO_DDR_LOW);
999
1000 sm501_sync_regs(sm501_gpio_to_dev(smgpio));
1001 smc501_writel(val, regs + SM501_GPIO_DATA_LOW);
1002
1003 sm501_sync_regs(sm501_gpio_to_dev(smgpio));
1004 spin_unlock_irqrestore(&smgpio->lock, save);
1005
1006 return 0;
1007}
1008
1009static struct gpio_chip gpio_chip_template = {
1010 .ngpio = 32,
1011 .direction_input = sm501_gpio_input,
1012 .direction_output = sm501_gpio_output,
1013 .set = sm501_gpio_set,
1014 .get = sm501_gpio_get,
1015};
1016
1017static int sm501_gpio_register_chip(struct sm501_devdata *sm,
1018 struct sm501_gpio *gpio,
1019 struct sm501_gpio_chip *chip)
1020{
1021 struct sm501_platdata *pdata = sm->platdata;
1022 struct gpio_chip *gchip = &chip->gpio;
1023 int base = pdata->gpio_base;
1024
1025 chip->gpio = gpio_chip_template;
1026
1027 if (chip == &gpio->high) {
1028 if (base > 0)
1029 base += 32;
1030 chip->regbase = gpio->regs + SM501_GPIO_DATA_HIGH;
1031 chip->control = sm->regs + SM501_GPIO63_32_CONTROL;
1032 gchip->label = "SM501-HIGH";
1033 } else {
1034 chip->regbase = gpio->regs + SM501_GPIO_DATA_LOW;
1035 chip->control = sm->regs + SM501_GPIO31_0_CONTROL;
1036 gchip->label = "SM501-LOW";
1037 }
1038
1039 gchip->base = base;
1040 chip->ourgpio = gpio;
1041
1042 return gpiochip_add(gchip);
1043}
1044
1045static int sm501_register_gpio(struct sm501_devdata *sm)
1046{
1047 struct sm501_gpio *gpio = &sm->gpio;
1048 resource_size_t iobase = sm->io_res->start + SM501_GPIO;
1049 int ret;
1050
1051 dev_dbg(sm->dev, "registering gpio block %08llx\n",
1052 (unsigned long long)iobase);
1053
1054 spin_lock_init(&gpio->lock);
1055
1056 gpio->regs_res = request_mem_region(iobase, 0x20, "sm501-gpio");
1057 if (gpio->regs_res == NULL) {
1058 dev_err(sm->dev, "gpio: failed to request region\n");
1059 return -ENXIO;
1060 }
1061
1062 gpio->regs = ioremap(iobase, 0x20);
1063 if (gpio->regs == NULL) {
1064 dev_err(sm->dev, "gpio: failed to remap registers\n");
1065 ret = -ENXIO;
1066 goto err_claimed;
1067 }
1068
1069 /* Register both our chips. */
1070
1071 ret = sm501_gpio_register_chip(sm, gpio, &gpio->low);
1072 if (ret) {
1073 dev_err(sm->dev, "failed to add low chip\n");
1074 goto err_mapped;
1075 }
1076
1077 ret = sm501_gpio_register_chip(sm, gpio, &gpio->high);
1078 if (ret) {
1079 dev_err(sm->dev, "failed to add high chip\n");
1080 goto err_low_chip;
1081 }
1082
1083 gpio->registered = 1;
1084
1085 return 0;
1086
1087 err_low_chip:
1088 gpiochip_remove(&gpio->low.gpio);
1089
1090 err_mapped:
1091 iounmap(gpio->regs);
1092
1093 err_claimed:
1094 release_resource(gpio->regs_res);
1095 kfree(gpio->regs_res);
1096
1097 return ret;
1098}
1099
1100static void sm501_gpio_remove(struct sm501_devdata *sm)
1101{
1102 struct sm501_gpio *gpio = &sm->gpio;
1103
1104 if (!sm->gpio.registered)
1105 return;
1106
1107 gpiochip_remove(&gpio->low.gpio);
1108 gpiochip_remove(&gpio->high.gpio);
1109
1110 iounmap(gpio->regs);
1111 release_resource(gpio->regs_res);
1112 kfree(gpio->regs_res);
1113}
1114
1115static inline int sm501_gpio_pin2nr(struct sm501_devdata *sm, unsigned int pin)
1116{
1117 struct sm501_gpio *gpio = &sm->gpio;
1118 int base = (pin < 32) ? gpio->low.gpio.base : gpio->high.gpio.base;
1119
1120 return (pin % 32) + base;
1121}
1122
1123static inline int sm501_gpio_isregistered(struct sm501_devdata *sm)
1124{
1125 return sm->gpio.registered;
1126}
1127#else
1128static inline int sm501_register_gpio(struct sm501_devdata *sm)
1129{
1130 return 0;
1131}
1132
1133static inline void sm501_gpio_remove(struct sm501_devdata *sm)
1134{
1135}
1136
1137static inline int sm501_gpio_pin2nr(struct sm501_devdata *sm, unsigned int pin)
1138{
1139 return -1;
1140}
1141
1142static inline int sm501_gpio_isregistered(struct sm501_devdata *sm)
1143{
1144 return 0;
1145}
1146#endif
1147
1148static int sm501_register_gpio_i2c_instance(struct sm501_devdata *sm,
1149 struct sm501_platdata_gpio_i2c *iic)
1150{
1151 struct i2c_gpio_platform_data *icd;
1152 struct platform_device *pdev;
1153
1154 pdev = sm501_create_subdev(sm, "i2c-gpio", 0,
1155 sizeof(struct i2c_gpio_platform_data));
1156 if (!pdev)
1157 return -ENOMEM;
1158
1159 icd = dev_get_platdata(&pdev->dev);
1160
1161 /* We keep the pin_sda and pin_scl fields relative in case the
1162 * same platform data is passed to >1 SM501.
1163 */
1164
1165 icd->sda_pin = sm501_gpio_pin2nr(sm, iic->pin_sda);
1166 icd->scl_pin = sm501_gpio_pin2nr(sm, iic->pin_scl);
1167 icd->timeout = iic->timeout;
1168 icd->udelay = iic->udelay;
1169
1170 /* note, we can't use either of the pin numbers, as the i2c-gpio
1171 * driver uses the platform.id field to generate the bus number
1172 * to register with the i2c core; The i2c core doesn't have enough
1173 * entries to deal with anything we currently use.
1174 */
1175
1176 pdev->id = iic->bus_num;
1177
1178 dev_info(sm->dev, "registering i2c-%d: sda=%d (%d), scl=%d (%d)\n",
1179 iic->bus_num,
1180 icd->sda_pin, iic->pin_sda, icd->scl_pin, iic->pin_scl);
1181
1182 return sm501_register_device(sm, pdev);
1183}
1184
1185static int sm501_register_gpio_i2c(struct sm501_devdata *sm,
1186 struct sm501_platdata *pdata)
1187{
1188 struct sm501_platdata_gpio_i2c *iic = pdata->gpio_i2c;
1189 int index;
1190 int ret;
1191
1192 for (index = 0; index < pdata->gpio_i2c_nr; index++, iic++) {
1193 ret = sm501_register_gpio_i2c_instance(sm, iic);
1194 if (ret < 0)
1195 return ret;
1196 }
1197
1198 return 0;
1199}
1200
1201/* sm501_dbg_regs
1202 *
1203 * Debug attribute to attach to parent device to show core registers
1204*/
1205
1206static ssize_t sm501_dbg_regs(struct device *dev,
1207 struct device_attribute *attr, char *buff)
1208{
1209 struct sm501_devdata *sm = dev_get_drvdata(dev) ;
1210 unsigned int reg;
1211 char *ptr = buff;
1212 int ret;
1213
1214 for (reg = 0x00; reg < 0x70; reg += 4) {
1215 ret = sprintf(ptr, "%08x = %08x\n",
1216 reg, smc501_readl(sm->regs + reg));
1217 ptr += ret;
1218 }
1219
1220 return ptr - buff;
1221}
1222
1223
1224static DEVICE_ATTR(dbg_regs, 0444, sm501_dbg_regs, NULL);
1225
1226/* sm501_init_reg
1227 *
1228 * Helper function for the init code to setup a register
1229 *
1230 * clear the bits which are set in r->mask, and then set
1231 * the bits set in r->set.
1232*/
1233
1234static inline void sm501_init_reg(struct sm501_devdata *sm,
1235 unsigned long reg,
1236 struct sm501_reg_init *r)
1237{
1238 unsigned long tmp;
1239
1240 tmp = smc501_readl(sm->regs + reg);
1241 tmp &= ~r->mask;
1242 tmp |= r->set;
1243 smc501_writel(tmp, sm->regs + reg);
1244}
1245
1246/* sm501_init_regs
1247 *
1248 * Setup core register values
1249*/
1250
1251static void sm501_init_regs(struct sm501_devdata *sm,
1252 struct sm501_initdata *init)
1253{
1254 sm501_misc_control(sm->dev,
1255 init->misc_control.set,
1256 init->misc_control.mask);
1257
1258 sm501_init_reg(sm, SM501_MISC_TIMING, &init->misc_timing);
1259 sm501_init_reg(sm, SM501_GPIO31_0_CONTROL, &init->gpio_low);
1260 sm501_init_reg(sm, SM501_GPIO63_32_CONTROL, &init->gpio_high);
1261
1262 if (init->m1xclk) {
1263 dev_info(sm->dev, "setting M1XCLK to %ld\n", init->m1xclk);
1264 sm501_set_clock(sm->dev, SM501_CLOCK_M1XCLK, init->m1xclk);
1265 }
1266
1267 if (init->mclk) {
1268 dev_info(sm->dev, "setting MCLK to %ld\n", init->mclk);
1269 sm501_set_clock(sm->dev, SM501_CLOCK_MCLK, init->mclk);
1270 }
1271
1272}
1273
1274/* Check the PLL sources for the M1CLK and M1XCLK
1275 *
1276 * If the M1CLK and M1XCLKs are not sourced from the same PLL, then
1277 * there is a risk (see errata AB-5) that the SM501 will cease proper
1278 * function. If this happens, then it is likely the SM501 will
1279 * hang the system.
1280*/
1281
1282static int sm501_check_clocks(struct sm501_devdata *sm)
1283{
1284 unsigned long pwrmode = smc501_readl(sm->regs + SM501_CURRENT_CLOCK);
1285 unsigned long msrc = (pwrmode & SM501_POWERMODE_M_SRC);
1286 unsigned long m1src = (pwrmode & SM501_POWERMODE_M1_SRC);
1287
1288 return ((msrc == 0 && m1src != 0) || (msrc != 0 && m1src == 0));
1289}
1290
1291static unsigned int sm501_mem_local[] = {
1292 [0] = 4*1024*1024,
1293 [1] = 8*1024*1024,
1294 [2] = 16*1024*1024,
1295 [3] = 32*1024*1024,
1296 [4] = 64*1024*1024,
1297 [5] = 2*1024*1024,
1298};
1299
1300/* sm501_init_dev
1301 *
1302 * Common init code for an SM501
1303*/
1304
1305static int sm501_init_dev(struct sm501_devdata *sm)
1306{
1307 struct sm501_initdata *idata;
1308 struct sm501_platdata *pdata;
1309 resource_size_t mem_avail;
1310 unsigned long dramctrl;
1311 unsigned long devid;
1312 int ret;
1313
1314 mutex_init(&sm->clock_lock);
1315 spin_lock_init(&sm->reg_lock);
1316
1317 INIT_LIST_HEAD(&sm->devices);
1318
1319 devid = smc501_readl(sm->regs + SM501_DEVICEID);
1320
1321 if ((devid & SM501_DEVICEID_IDMASK) != SM501_DEVICEID_SM501) {
1322 dev_err(sm->dev, "incorrect device id %08lx\n", devid);
1323 return -EINVAL;
1324 }
1325
1326 /* disable irqs */
1327 smc501_writel(0, sm->regs + SM501_IRQ_MASK);
1328
1329 dramctrl = smc501_readl(sm->regs + SM501_DRAM_CONTROL);
1330 mem_avail = sm501_mem_local[(dramctrl >> 13) & 0x7];
1331
1332 dev_info(sm->dev, "SM501 At %p: Version %08lx, %ld Mb, IRQ %d\n",
1333 sm->regs, devid, (unsigned long)mem_avail >> 20, sm->irq);
1334
1335 sm->rev = devid & SM501_DEVICEID_REVMASK;
1336
1337 sm501_dump_gate(sm);
1338
1339 ret = device_create_file(sm->dev, &dev_attr_dbg_regs);
1340 if (ret)
1341 dev_err(sm->dev, "failed to create debug regs file\n");
1342
1343 sm501_dump_clk(sm);
1344
1345 /* check to see if we have some device initialisation */
1346
1347 pdata = sm->platdata;
1348 idata = pdata ? pdata->init : NULL;
1349
1350 if (idata) {
1351 sm501_init_regs(sm, idata);
1352
1353 if (idata->devices & SM501_USE_USB_HOST)
1354 sm501_register_usbhost(sm, &mem_avail);
1355 if (idata->devices & (SM501_USE_UART0 | SM501_USE_UART1))
1356 sm501_register_uart(sm, idata->devices);
1357 if (idata->devices & SM501_USE_GPIO)
1358 sm501_register_gpio(sm);
1359 }
1360
1361 if (pdata && pdata->gpio_i2c != NULL && pdata->gpio_i2c_nr > 0) {
1362 if (!sm501_gpio_isregistered(sm))
1363 dev_err(sm->dev, "no gpio available for i2c gpio.\n");
1364 else
1365 sm501_register_gpio_i2c(sm, pdata);
1366 }
1367
1368 ret = sm501_check_clocks(sm);
1369 if (ret) {
1370 dev_err(sm->dev, "M1X and M clocks sourced from different "
1371 "PLLs\n");
1372 return -EINVAL;
1373 }
1374
1375 /* always create a framebuffer */
1376 sm501_register_display(sm, &mem_avail);
1377
1378 return 0;
1379}
1380
1381static int sm501_plat_probe(struct platform_device *dev)
1382{
1383 struct sm501_devdata *sm;
1384 int ret;
1385
1386 sm = kzalloc(sizeof(struct sm501_devdata), GFP_KERNEL);
1387 if (sm == NULL) {
1388 dev_err(&dev->dev, "no memory for device data\n");
1389 ret = -ENOMEM;
1390 goto err1;
1391 }
1392
1393 sm->dev = &dev->dev;
1394 sm->pdev_id = dev->id;
1395 sm->platdata = dev_get_platdata(&dev->dev);
1396
1397 ret = platform_get_irq(dev, 0);
1398 if (ret < 0) {
1399 dev_err(&dev->dev, "failed to get irq resource\n");
1400 goto err_res;
1401 }
1402 sm->irq = ret;
1403
1404 sm->io_res = platform_get_resource(dev, IORESOURCE_MEM, 1);
1405 sm->mem_res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1406
1407 if (sm->io_res == NULL || sm->mem_res == NULL) {
1408 dev_err(&dev->dev, "failed to get IO resource\n");
1409 ret = -ENOENT;
1410 goto err_res;
1411 }
1412
1413 sm->regs_claim = request_mem_region(sm->io_res->start,
1414 0x100, "sm501");
1415
1416 if (sm->regs_claim == NULL) {
1417 dev_err(&dev->dev, "cannot claim registers\n");
1418 ret = -EBUSY;
1419 goto err_res;
1420 }
1421
1422 platform_set_drvdata(dev, sm);
1423
1424 sm->regs = ioremap(sm->io_res->start, resource_size(sm->io_res));
1425
1426 if (sm->regs == NULL) {
1427 dev_err(&dev->dev, "cannot remap registers\n");
1428 ret = -EIO;
1429 goto err_claim;
1430 }
1431
1432 return sm501_init_dev(sm);
1433
1434 err_claim:
1435 release_resource(sm->regs_claim);
1436 kfree(sm->regs_claim);
1437 err_res:
1438 kfree(sm);
1439 err1:
1440 return ret;
1441
1442}
1443
1444#ifdef CONFIG_PM
1445
1446/* power management support */
1447
1448static void sm501_set_power(struct sm501_devdata *sm, int on)
1449{
1450 struct sm501_platdata *pd = sm->platdata;
1451
1452 if (pd == NULL)
1453 return;
1454
1455 if (pd->get_power) {
1456 if (pd->get_power(sm->dev) == on) {
1457 dev_dbg(sm->dev, "is already %d\n", on);
1458 return;
1459 }
1460 }
1461
1462 if (pd->set_power) {
1463 dev_dbg(sm->dev, "setting power to %d\n", on);
1464
1465 pd->set_power(sm->dev, on);
1466 sm501_mdelay(sm, 10);
1467 }
1468}
1469
1470static int sm501_plat_suspend(struct platform_device *pdev, pm_message_t state)
1471{
1472 struct sm501_devdata *sm = platform_get_drvdata(pdev);
1473
1474 sm->in_suspend = 1;
1475 sm->pm_misc = smc501_readl(sm->regs + SM501_MISC_CONTROL);
1476
1477 sm501_dump_regs(sm);
1478
1479 if (sm->platdata) {
1480 if (sm->platdata->flags & SM501_FLAG_SUSPEND_OFF)
1481 sm501_set_power(sm, 0);
1482 }
1483
1484 return 0;
1485}
1486
1487static int sm501_plat_resume(struct platform_device *pdev)
1488{
1489 struct sm501_devdata *sm = platform_get_drvdata(pdev);
1490
1491 sm501_set_power(sm, 1);
1492
1493 sm501_dump_regs(sm);
1494 sm501_dump_gate(sm);
1495 sm501_dump_clk(sm);
1496
1497 /* check to see if we are in the same state as when suspended */
1498
1499 if (smc501_readl(sm->regs + SM501_MISC_CONTROL) != sm->pm_misc) {
1500 dev_info(sm->dev, "SM501_MISC_CONTROL changed over sleep\n");
1501 smc501_writel(sm->pm_misc, sm->regs + SM501_MISC_CONTROL);
1502
1503 /* our suspend causes the controller state to change,
1504 * either by something attempting setup, power loss,
1505 * or an external reset event on power change */
1506
1507 if (sm->platdata && sm->platdata->init) {
1508 sm501_init_regs(sm, sm->platdata->init);
1509 }
1510 }
1511
1512 /* dump our state from resume */
1513
1514 sm501_dump_regs(sm);
1515 sm501_dump_clk(sm);
1516
1517 sm->in_suspend = 0;
1518
1519 return 0;
1520}
1521#else
1522#define sm501_plat_suspend NULL
1523#define sm501_plat_resume NULL
1524#endif
1525
1526/* Initialisation data for PCI devices */
1527
1528static struct sm501_initdata sm501_pci_initdata = {
1529 .gpio_high = {
1530 .set = 0x3F000000, /* 24bit panel */
1531 .mask = 0x0,
1532 },
1533 .misc_timing = {
1534 .set = 0x010100, /* SDRAM timing */
1535 .mask = 0x1F1F00,
1536 },
1537 .misc_control = {
1538 .set = SM501_MISC_PNL_24BIT,
1539 .mask = 0,
1540 },
1541
1542 .devices = SM501_USE_ALL,
1543
1544 /* Errata AB-3 says that 72MHz is the fastest available
1545 * for 33MHZ PCI with proper bus-mastering operation */
1546
1547 .mclk = 72 * MHZ,
1548 .m1xclk = 144 * MHZ,
1549};
1550
1551static struct sm501_platdata_fbsub sm501_pdata_fbsub = {
1552 .flags = (SM501FB_FLAG_USE_INIT_MODE |
1553 SM501FB_FLAG_USE_HWCURSOR |
1554 SM501FB_FLAG_USE_HWACCEL |
1555 SM501FB_FLAG_DISABLE_AT_EXIT),
1556};
1557
1558static struct sm501_platdata_fb sm501_fb_pdata = {
1559 .fb_route = SM501_FB_OWN,
1560 .fb_crt = &sm501_pdata_fbsub,
1561 .fb_pnl = &sm501_pdata_fbsub,
1562};
1563
1564static struct sm501_platdata sm501_pci_platdata = {
1565 .init = &sm501_pci_initdata,
1566 .fb = &sm501_fb_pdata,
1567 .gpio_base = -1,
1568};
1569
1570static int sm501_pci_probe(struct pci_dev *dev,
1571 const struct pci_device_id *id)
1572{
1573 struct sm501_devdata *sm;
1574 int err;
1575
1576 sm = kzalloc(sizeof(struct sm501_devdata), GFP_KERNEL);
1577 if (sm == NULL) {
1578 dev_err(&dev->dev, "no memory for device data\n");
1579 err = -ENOMEM;
1580 goto err1;
1581 }
1582
1583 /* set a default set of platform data */
1584 dev->dev.platform_data = sm->platdata = &sm501_pci_platdata;
1585
1586 /* set a hopefully unique id for our child platform devices */
1587 sm->pdev_id = 32 + dev->devfn;
1588
1589 pci_set_drvdata(dev, sm);
1590
1591 err = pci_enable_device(dev);
1592 if (err) {
1593 dev_err(&dev->dev, "cannot enable device\n");
1594 goto err2;
1595 }
1596
1597 sm->dev = &dev->dev;
1598 sm->irq = dev->irq;
1599
1600#ifdef __BIG_ENDIAN
1601 /* if the system is big-endian, we most probably have a
1602 * translation in the IO layer making the PCI bus little endian
1603 * so make the framebuffer swapped pixels */
1604
1605 sm501_fb_pdata.flags |= SM501_FBPD_SWAP_FB_ENDIAN;
1606#endif
1607
1608 /* check our resources */
1609
1610 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM)) {
1611 dev_err(&dev->dev, "region #0 is not memory?\n");
1612 err = -EINVAL;
1613 goto err3;
1614 }
1615
1616 if (!(pci_resource_flags(dev, 1) & IORESOURCE_MEM)) {
1617 dev_err(&dev->dev, "region #1 is not memory?\n");
1618 err = -EINVAL;
1619 goto err3;
1620 }
1621
1622 /* make our resources ready for sharing */
1623
1624 sm->io_res = &dev->resource[1];
1625 sm->mem_res = &dev->resource[0];
1626
1627 sm->regs_claim = request_mem_region(sm->io_res->start,
1628 0x100, "sm501");
1629 if (sm->regs_claim == NULL) {
1630 dev_err(&dev->dev, "cannot claim registers\n");
1631 err= -EBUSY;
1632 goto err3;
1633 }
1634
1635 sm->regs = pci_ioremap_bar(dev, 1);
1636
1637 if (sm->regs == NULL) {
1638 dev_err(&dev->dev, "cannot remap registers\n");
1639 err = -EIO;
1640 goto err4;
1641 }
1642
1643 sm501_init_dev(sm);
1644 return 0;
1645
1646 err4:
1647 release_resource(sm->regs_claim);
1648 kfree(sm->regs_claim);
1649 err3:
1650 pci_disable_device(dev);
1651 err2:
1652 kfree(sm);
1653 err1:
1654 return err;
1655}
1656
1657static void sm501_remove_sub(struct sm501_devdata *sm,
1658 struct sm501_device *smdev)
1659{
1660 list_del(&smdev->list);
1661 platform_device_unregister(&smdev->pdev);
1662}
1663
1664static void sm501_dev_remove(struct sm501_devdata *sm)
1665{
1666 struct sm501_device *smdev, *tmp;
1667
1668 list_for_each_entry_safe(smdev, tmp, &sm->devices, list)
1669 sm501_remove_sub(sm, smdev);
1670
1671 device_remove_file(sm->dev, &dev_attr_dbg_regs);
1672
1673 sm501_gpio_remove(sm);
1674}
1675
1676static void sm501_pci_remove(struct pci_dev *dev)
1677{
1678 struct sm501_devdata *sm = pci_get_drvdata(dev);
1679
1680 sm501_dev_remove(sm);
1681 iounmap(sm->regs);
1682
1683 release_resource(sm->regs_claim);
1684 kfree(sm->regs_claim);
1685
1686 pci_disable_device(dev);
1687}
1688
1689static int sm501_plat_remove(struct platform_device *dev)
1690{
1691 struct sm501_devdata *sm = platform_get_drvdata(dev);
1692
1693 sm501_dev_remove(sm);
1694 iounmap(sm->regs);
1695
1696 release_resource(sm->regs_claim);
1697 kfree(sm->regs_claim);
1698
1699 return 0;
1700}
1701
1702static const struct pci_device_id sm501_pci_tbl[] = {
1703 { 0x126f, 0x0501, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
1704 { 0, },
1705};
1706
1707MODULE_DEVICE_TABLE(pci, sm501_pci_tbl);
1708
1709static struct pci_driver sm501_pci_driver = {
1710 .name = "sm501",
1711 .id_table = sm501_pci_tbl,
1712 .probe = sm501_pci_probe,
1713 .remove = sm501_pci_remove,
1714};
1715
1716MODULE_ALIAS("platform:sm501");
1717
1718static const struct of_device_id of_sm501_match_tbl[] = {
1719 { .compatible = "smi,sm501", },
1720 { /* end */ }
1721};
1722MODULE_DEVICE_TABLE(of, of_sm501_match_tbl);
1723
1724static struct platform_driver sm501_plat_driver = {
1725 .driver = {
1726 .name = "sm501",
1727 .of_match_table = of_sm501_match_tbl,
1728 },
1729 .probe = sm501_plat_probe,
1730 .remove = sm501_plat_remove,
1731 .suspend = sm501_plat_suspend,
1732 .resume = sm501_plat_resume,
1733};
1734
1735static int __init sm501_base_init(void)
1736{
1737 platform_driver_register(&sm501_plat_driver);
1738 return pci_register_driver(&sm501_pci_driver);
1739}
1740
1741static void __exit sm501_base_exit(void)
1742{
1743 platform_driver_unregister(&sm501_plat_driver);
1744 pci_unregister_driver(&sm501_pci_driver);
1745}
1746
1747module_init(sm501_base_init);
1748module_exit(sm501_base_exit);
1749
1750MODULE_DESCRIPTION("SM501 Core Driver");
1751MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, Vincent Sanders");
1752MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0-only
2/* linux/drivers/mfd/sm501.c
3 *
4 * Copyright (C) 2006 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * Vincent Sanders <vince@simtec.co.uk>
7 *
8 * SM501 MFD driver
9*/
10
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/delay.h>
14#include <linux/init.h>
15#include <linux/list.h>
16#include <linux/device.h>
17#include <linux/platform_device.h>
18#include <linux/pci.h>
19#include <linux/platform_data/i2c-gpio.h>
20#include <linux/gpio/driver.h>
21#include <linux/gpio/machine.h>
22#include <linux/slab.h>
23
24#include <linux/sm501.h>
25#include <linux/sm501-regs.h>
26#include <linux/serial_8250.h>
27
28#include <linux/io.h>
29
30struct sm501_device {
31 struct list_head list;
32 struct platform_device pdev;
33};
34
35struct sm501_gpio;
36
37#ifdef CONFIG_MFD_SM501_GPIO
38#include <linux/gpio.h>
39
40struct sm501_gpio_chip {
41 struct gpio_chip gpio;
42 struct sm501_gpio *ourgpio; /* to get back to parent. */
43 void __iomem *regbase;
44 void __iomem *control; /* address of control reg. */
45};
46
47struct sm501_gpio {
48 struct sm501_gpio_chip low;
49 struct sm501_gpio_chip high;
50 spinlock_t lock;
51
52 unsigned int registered : 1;
53 void __iomem *regs;
54 struct resource *regs_res;
55};
56#else
57struct sm501_gpio {
58 /* no gpio support, empty definition for sm501_devdata. */
59};
60#endif
61
62struct sm501_devdata {
63 spinlock_t reg_lock;
64 struct mutex clock_lock;
65 struct list_head devices;
66 struct sm501_gpio gpio;
67
68 struct device *dev;
69 struct resource *io_res;
70 struct resource *mem_res;
71 struct resource *regs_claim;
72 struct sm501_platdata *platdata;
73
74
75 unsigned int in_suspend;
76 unsigned long pm_misc;
77
78 int unit_power[20];
79 unsigned int pdev_id;
80 unsigned int irq;
81 void __iomem *regs;
82 unsigned int rev;
83};
84
85
86#define MHZ (1000 * 1000)
87
88#ifdef DEBUG
89static const unsigned int div_tab[] = {
90 [0] = 1,
91 [1] = 2,
92 [2] = 4,
93 [3] = 8,
94 [4] = 16,
95 [5] = 32,
96 [6] = 64,
97 [7] = 128,
98 [8] = 3,
99 [9] = 6,
100 [10] = 12,
101 [11] = 24,
102 [12] = 48,
103 [13] = 96,
104 [14] = 192,
105 [15] = 384,
106 [16] = 5,
107 [17] = 10,
108 [18] = 20,
109 [19] = 40,
110 [20] = 80,
111 [21] = 160,
112 [22] = 320,
113 [23] = 604,
114};
115
116static unsigned long decode_div(unsigned long pll2, unsigned long val,
117 unsigned int lshft, unsigned int selbit,
118 unsigned long mask)
119{
120 if (val & selbit)
121 pll2 = 288 * MHZ;
122
123 return pll2 / div_tab[(val >> lshft) & mask];
124}
125
126#define fmt_freq(x) ((x) / MHZ), ((x) % MHZ), (x)
127
128/* sm501_dump_clk
129 *
130 * Print out the current clock configuration for the device
131*/
132
133static void sm501_dump_clk(struct sm501_devdata *sm)
134{
135 unsigned long misct = smc501_readl(sm->regs + SM501_MISC_TIMING);
136 unsigned long pm0 = smc501_readl(sm->regs + SM501_POWER_MODE_0_CLOCK);
137 unsigned long pm1 = smc501_readl(sm->regs + SM501_POWER_MODE_1_CLOCK);
138 unsigned long pmc = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL);
139 unsigned long sdclk0, sdclk1;
140 unsigned long pll2 = 0;
141
142 switch (misct & 0x30) {
143 case 0x00:
144 pll2 = 336 * MHZ;
145 break;
146 case 0x10:
147 pll2 = 288 * MHZ;
148 break;
149 case 0x20:
150 pll2 = 240 * MHZ;
151 break;
152 case 0x30:
153 pll2 = 192 * MHZ;
154 break;
155 }
156
157 sdclk0 = (misct & (1<<12)) ? pll2 : 288 * MHZ;
158 sdclk0 /= div_tab[((misct >> 8) & 0xf)];
159
160 sdclk1 = (misct & (1<<20)) ? pll2 : 288 * MHZ;
161 sdclk1 /= div_tab[((misct >> 16) & 0xf)];
162
163 dev_dbg(sm->dev, "MISCT=%08lx, PM0=%08lx, PM1=%08lx\n",
164 misct, pm0, pm1);
165
166 dev_dbg(sm->dev, "PLL2 = %ld.%ld MHz (%ld), SDCLK0=%08lx, SDCLK1=%08lx\n",
167 fmt_freq(pll2), sdclk0, sdclk1);
168
169 dev_dbg(sm->dev, "SDRAM: PM0=%ld, PM1=%ld\n", sdclk0, sdclk1);
170
171 dev_dbg(sm->dev, "PM0[%c]: "
172 "P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), "
173 "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n",
174 (pmc & 3 ) == 0 ? '*' : '-',
175 fmt_freq(decode_div(pll2, pm0, 24, 1<<29, 31)),
176 fmt_freq(decode_div(pll2, pm0, 16, 1<<20, 15)),
177 fmt_freq(decode_div(pll2, pm0, 8, 1<<12, 15)),
178 fmt_freq(decode_div(pll2, pm0, 0, 1<<4, 15)));
179
180 dev_dbg(sm->dev, "PM1[%c]: "
181 "P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), "
182 "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n",
183 (pmc & 3 ) == 1 ? '*' : '-',
184 fmt_freq(decode_div(pll2, pm1, 24, 1<<29, 31)),
185 fmt_freq(decode_div(pll2, pm1, 16, 1<<20, 15)),
186 fmt_freq(decode_div(pll2, pm1, 8, 1<<12, 15)),
187 fmt_freq(decode_div(pll2, pm1, 0, 1<<4, 15)));
188}
189
190static void sm501_dump_regs(struct sm501_devdata *sm)
191{
192 void __iomem *regs = sm->regs;
193
194 dev_info(sm->dev, "System Control %08x\n",
195 smc501_readl(regs + SM501_SYSTEM_CONTROL));
196 dev_info(sm->dev, "Misc Control %08x\n",
197 smc501_readl(regs + SM501_MISC_CONTROL));
198 dev_info(sm->dev, "GPIO Control Low %08x\n",
199 smc501_readl(regs + SM501_GPIO31_0_CONTROL));
200 dev_info(sm->dev, "GPIO Control Hi %08x\n",
201 smc501_readl(regs + SM501_GPIO63_32_CONTROL));
202 dev_info(sm->dev, "DRAM Control %08x\n",
203 smc501_readl(regs + SM501_DRAM_CONTROL));
204 dev_info(sm->dev, "Arbitration Ctrl %08x\n",
205 smc501_readl(regs + SM501_ARBTRTN_CONTROL));
206 dev_info(sm->dev, "Misc Timing %08x\n",
207 smc501_readl(regs + SM501_MISC_TIMING));
208}
209
210static void sm501_dump_gate(struct sm501_devdata *sm)
211{
212 dev_info(sm->dev, "CurrentGate %08x\n",
213 smc501_readl(sm->regs + SM501_CURRENT_GATE));
214 dev_info(sm->dev, "CurrentClock %08x\n",
215 smc501_readl(sm->regs + SM501_CURRENT_CLOCK));
216 dev_info(sm->dev, "PowerModeControl %08x\n",
217 smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL));
218}
219
220#else
221static inline void sm501_dump_gate(struct sm501_devdata *sm) { }
222static inline void sm501_dump_regs(struct sm501_devdata *sm) { }
223static inline void sm501_dump_clk(struct sm501_devdata *sm) { }
224#endif
225
226/* sm501_sync_regs
227 *
228 * ensure the
229*/
230
231static void sm501_sync_regs(struct sm501_devdata *sm)
232{
233 smc501_readl(sm->regs);
234}
235
236static inline void sm501_mdelay(struct sm501_devdata *sm, unsigned int delay)
237{
238 /* during suspend/resume, we are currently not allowed to sleep,
239 * so change to using mdelay() instead of msleep() if we
240 * are in one of these paths */
241
242 if (sm->in_suspend)
243 mdelay(delay);
244 else
245 msleep(delay);
246}
247
248/* sm501_misc_control
249 *
250 * alters the miscellaneous control parameters
251*/
252
253int sm501_misc_control(struct device *dev,
254 unsigned long set, unsigned long clear)
255{
256 struct sm501_devdata *sm = dev_get_drvdata(dev);
257 unsigned long misc;
258 unsigned long save;
259 unsigned long to;
260
261 spin_lock_irqsave(&sm->reg_lock, save);
262
263 misc = smc501_readl(sm->regs + SM501_MISC_CONTROL);
264 to = (misc & ~clear) | set;
265
266 if (to != misc) {
267 smc501_writel(to, sm->regs + SM501_MISC_CONTROL);
268 sm501_sync_regs(sm);
269
270 dev_dbg(sm->dev, "MISC_CONTROL %08lx\n", misc);
271 }
272
273 spin_unlock_irqrestore(&sm->reg_lock, save);
274 return to;
275}
276
277EXPORT_SYMBOL_GPL(sm501_misc_control);
278
279/* sm501_modify_reg
280 *
281 * Modify a register in the SM501 which may be shared with other
282 * drivers.
283*/
284
285unsigned long sm501_modify_reg(struct device *dev,
286 unsigned long reg,
287 unsigned long set,
288 unsigned long clear)
289{
290 struct sm501_devdata *sm = dev_get_drvdata(dev);
291 unsigned long data;
292 unsigned long save;
293
294 spin_lock_irqsave(&sm->reg_lock, save);
295
296 data = smc501_readl(sm->regs + reg);
297 data |= set;
298 data &= ~clear;
299
300 smc501_writel(data, sm->regs + reg);
301 sm501_sync_regs(sm);
302
303 spin_unlock_irqrestore(&sm->reg_lock, save);
304
305 return data;
306}
307
308EXPORT_SYMBOL_GPL(sm501_modify_reg);
309
310/* sm501_unit_power
311 *
312 * alters the power active gate to set specific units on or off
313 */
314
315int sm501_unit_power(struct device *dev, unsigned int unit, unsigned int to)
316{
317 struct sm501_devdata *sm = dev_get_drvdata(dev);
318 unsigned long mode;
319 unsigned long gate;
320 unsigned long clock;
321
322 mutex_lock(&sm->clock_lock);
323
324 mode = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL);
325 gate = smc501_readl(sm->regs + SM501_CURRENT_GATE);
326 clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK);
327
328 mode &= 3; /* get current power mode */
329
330 if (unit >= ARRAY_SIZE(sm->unit_power)) {
331 dev_err(dev, "%s: bad unit %d\n", __func__, unit);
332 goto already;
333 }
334
335 dev_dbg(sm->dev, "%s: unit %d, cur %d, to %d\n", __func__, unit,
336 sm->unit_power[unit], to);
337
338 if (to == 0 && sm->unit_power[unit] == 0) {
339 dev_err(sm->dev, "unit %d is already shutdown\n", unit);
340 goto already;
341 }
342
343 sm->unit_power[unit] += to ? 1 : -1;
344 to = sm->unit_power[unit] ? 1 : 0;
345
346 if (to) {
347 if (gate & (1 << unit))
348 goto already;
349 gate |= (1 << unit);
350 } else {
351 if (!(gate & (1 << unit)))
352 goto already;
353 gate &= ~(1 << unit);
354 }
355
356 switch (mode) {
357 case 1:
358 smc501_writel(gate, sm->regs + SM501_POWER_MODE_0_GATE);
359 smc501_writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK);
360 mode = 0;
361 break;
362 case 2:
363 case 0:
364 smc501_writel(gate, sm->regs + SM501_POWER_MODE_1_GATE);
365 smc501_writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK);
366 mode = 1;
367 break;
368
369 default:
370 gate = -1;
371 goto already;
372 }
373
374 smc501_writel(mode, sm->regs + SM501_POWER_MODE_CONTROL);
375 sm501_sync_regs(sm);
376
377 dev_dbg(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n",
378 gate, clock, mode);
379
380 sm501_mdelay(sm, 16);
381
382 already:
383 mutex_unlock(&sm->clock_lock);
384 return gate;
385}
386
387EXPORT_SYMBOL_GPL(sm501_unit_power);
388
389/* clock value structure. */
390struct sm501_clock {
391 unsigned long mclk;
392 int divider;
393 int shift;
394 unsigned int m, n, k;
395};
396
397/* sm501_calc_clock
398 *
399 * Calculates the nearest discrete clock frequency that
400 * can be achieved with the specified input clock.
401 * the maximum divisor is 3 or 5
402 */
403
404static int sm501_calc_clock(unsigned long freq,
405 struct sm501_clock *clock,
406 int max_div,
407 unsigned long mclk,
408 long *best_diff)
409{
410 int ret = 0;
411 int divider;
412 int shift;
413 long diff;
414
415 /* try dividers 1 and 3 for CRT and for panel,
416 try divider 5 for panel only.*/
417
418 for (divider = 1; divider <= max_div; divider += 2) {
419 /* try all 8 shift values.*/
420 for (shift = 0; shift < 8; shift++) {
421 /* Calculate difference to requested clock */
422 diff = DIV_ROUND_CLOSEST(mclk, divider << shift) - freq;
423 if (diff < 0)
424 diff = -diff;
425
426 /* If it is less than the current, use it */
427 if (diff < *best_diff) {
428 *best_diff = diff;
429
430 clock->mclk = mclk;
431 clock->divider = divider;
432 clock->shift = shift;
433 ret = 1;
434 }
435 }
436 }
437
438 return ret;
439}
440
441/* sm501_calc_pll
442 *
443 * Calculates the nearest discrete clock frequency that can be
444 * achieved using the programmable PLL.
445 * the maximum divisor is 3 or 5
446 */
447
448static unsigned long sm501_calc_pll(unsigned long freq,
449 struct sm501_clock *clock,
450 int max_div)
451{
452 unsigned long mclk;
453 unsigned int m, n, k;
454 long best_diff = 999999999;
455
456 /*
457 * The SM502 datasheet doesn't specify the min/max values for M and N.
458 * N = 1 at least doesn't work in practice.
459 */
460 for (m = 2; m <= 255; m++) {
461 for (n = 2; n <= 127; n++) {
462 for (k = 0; k <= 1; k++) {
463 mclk = (24000000UL * m / n) >> k;
464
465 if (sm501_calc_clock(freq, clock, max_div,
466 mclk, &best_diff)) {
467 clock->m = m;
468 clock->n = n;
469 clock->k = k;
470 }
471 }
472 }
473 }
474
475 /* Return best clock. */
476 return clock->mclk / (clock->divider << clock->shift);
477}
478
479/* sm501_select_clock
480 *
481 * Calculates the nearest discrete clock frequency that can be
482 * achieved using the 288MHz and 336MHz PLLs.
483 * the maximum divisor is 3 or 5
484 */
485
486static unsigned long sm501_select_clock(unsigned long freq,
487 struct sm501_clock *clock,
488 int max_div)
489{
490 unsigned long mclk;
491 long best_diff = 999999999;
492
493 /* Try 288MHz and 336MHz clocks. */
494 for (mclk = 288000000; mclk <= 336000000; mclk += 48000000) {
495 sm501_calc_clock(freq, clock, max_div, mclk, &best_diff);
496 }
497
498 /* Return best clock. */
499 return clock->mclk / (clock->divider << clock->shift);
500}
501
502/* sm501_set_clock
503 *
504 * set one of the four clock sources to the closest available frequency to
505 * the one specified
506*/
507
508unsigned long sm501_set_clock(struct device *dev,
509 int clksrc,
510 unsigned long req_freq)
511{
512 struct sm501_devdata *sm = dev_get_drvdata(dev);
513 unsigned long mode = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL);
514 unsigned long gate = smc501_readl(sm->regs + SM501_CURRENT_GATE);
515 unsigned long clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK);
516 unsigned int pll_reg = 0;
517 unsigned long sm501_freq; /* the actual frequency achieved */
518 u64 reg;
519
520 struct sm501_clock to;
521
522 /* find achivable discrete frequency and setup register value
523 * accordingly, V2XCLK, MCLK and M1XCLK are the same P2XCLK
524 * has an extra bit for the divider */
525
526 switch (clksrc) {
527 case SM501_CLOCK_P2XCLK:
528 /* This clock is divided in half so to achieve the
529 * requested frequency the value must be multiplied by
530 * 2. This clock also has an additional pre divisor */
531
532 if (sm->rev >= 0xC0) {
533 /* SM502 -> use the programmable PLL */
534 sm501_freq = (sm501_calc_pll(2 * req_freq,
535 &to, 5) / 2);
536 reg = to.shift & 0x07;/* bottom 3 bits are shift */
537 if (to.divider == 3)
538 reg |= 0x08; /* /3 divider required */
539 else if (to.divider == 5)
540 reg |= 0x10; /* /5 divider required */
541 reg |= 0x40; /* select the programmable PLL */
542 pll_reg = 0x20000 | (to.k << 15) | (to.n << 8) | to.m;
543 } else {
544 sm501_freq = (sm501_select_clock(2 * req_freq,
545 &to, 5) / 2);
546 reg = to.shift & 0x07;/* bottom 3 bits are shift */
547 if (to.divider == 3)
548 reg |= 0x08; /* /3 divider required */
549 else if (to.divider == 5)
550 reg |= 0x10; /* /5 divider required */
551 if (to.mclk != 288000000)
552 reg |= 0x20; /* which mclk pll is source */
553 }
554 break;
555
556 case SM501_CLOCK_V2XCLK:
557 /* This clock is divided in half so to achieve the
558 * requested frequency the value must be multiplied by 2. */
559
560 sm501_freq = (sm501_select_clock(2 * req_freq, &to, 3) / 2);
561 reg=to.shift & 0x07; /* bottom 3 bits are shift */
562 if (to.divider == 3)
563 reg |= 0x08; /* /3 divider required */
564 if (to.mclk != 288000000)
565 reg |= 0x10; /* which mclk pll is source */
566 break;
567
568 case SM501_CLOCK_MCLK:
569 case SM501_CLOCK_M1XCLK:
570 /* These clocks are the same and not further divided */
571
572 sm501_freq = sm501_select_clock( req_freq, &to, 3);
573 reg=to.shift & 0x07; /* bottom 3 bits are shift */
574 if (to.divider == 3)
575 reg |= 0x08; /* /3 divider required */
576 if (to.mclk != 288000000)
577 reg |= 0x10; /* which mclk pll is source */
578 break;
579
580 default:
581 return 0; /* this is bad */
582 }
583
584 mutex_lock(&sm->clock_lock);
585
586 mode = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL);
587 gate = smc501_readl(sm->regs + SM501_CURRENT_GATE);
588 clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK);
589
590 clock = clock & ~(0xFF << clksrc);
591 clock |= reg<<clksrc;
592
593 mode &= 3; /* find current mode */
594
595 switch (mode) {
596 case 1:
597 smc501_writel(gate, sm->regs + SM501_POWER_MODE_0_GATE);
598 smc501_writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK);
599 mode = 0;
600 break;
601 case 2:
602 case 0:
603 smc501_writel(gate, sm->regs + SM501_POWER_MODE_1_GATE);
604 smc501_writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK);
605 mode = 1;
606 break;
607
608 default:
609 mutex_unlock(&sm->clock_lock);
610 return -1;
611 }
612
613 smc501_writel(mode, sm->regs + SM501_POWER_MODE_CONTROL);
614
615 if (pll_reg)
616 smc501_writel(pll_reg,
617 sm->regs + SM501_PROGRAMMABLE_PLL_CONTROL);
618
619 sm501_sync_regs(sm);
620
621 dev_dbg(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n",
622 gate, clock, mode);
623
624 sm501_mdelay(sm, 16);
625 mutex_unlock(&sm->clock_lock);
626
627 sm501_dump_clk(sm);
628
629 return sm501_freq;
630}
631
632EXPORT_SYMBOL_GPL(sm501_set_clock);
633
634/* sm501_find_clock
635 *
636 * finds the closest available frequency for a given clock
637*/
638
639unsigned long sm501_find_clock(struct device *dev,
640 int clksrc,
641 unsigned long req_freq)
642{
643 struct sm501_devdata *sm = dev_get_drvdata(dev);
644 unsigned long sm501_freq; /* the frequency achieveable by the 501 */
645 struct sm501_clock to;
646
647 switch (clksrc) {
648 case SM501_CLOCK_P2XCLK:
649 if (sm->rev >= 0xC0) {
650 /* SM502 -> use the programmable PLL */
651 sm501_freq = (sm501_calc_pll(2 * req_freq,
652 &to, 5) / 2);
653 } else {
654 sm501_freq = (sm501_select_clock(2 * req_freq,
655 &to, 5) / 2);
656 }
657 break;
658
659 case SM501_CLOCK_V2XCLK:
660 sm501_freq = (sm501_select_clock(2 * req_freq, &to, 3) / 2);
661 break;
662
663 case SM501_CLOCK_MCLK:
664 case SM501_CLOCK_M1XCLK:
665 sm501_freq = sm501_select_clock(req_freq, &to, 3);
666 break;
667
668 default:
669 sm501_freq = 0; /* error */
670 }
671
672 return sm501_freq;
673}
674
675EXPORT_SYMBOL_GPL(sm501_find_clock);
676
677static struct sm501_device *to_sm_device(struct platform_device *pdev)
678{
679 return container_of(pdev, struct sm501_device, pdev);
680}
681
682/* sm501_device_release
683 *
684 * A release function for the platform devices we create to allow us to
685 * free any items we allocated
686*/
687
688static void sm501_device_release(struct device *dev)
689{
690 kfree(to_sm_device(to_platform_device(dev)));
691}
692
693/* sm501_create_subdev
694 *
695 * Create a skeleton platform device with resources for passing to a
696 * sub-driver
697*/
698
699static struct platform_device *
700sm501_create_subdev(struct sm501_devdata *sm, char *name,
701 unsigned int res_count, unsigned int platform_data_size)
702{
703 struct sm501_device *smdev;
704
705 smdev = kzalloc(sizeof(struct sm501_device) +
706 (sizeof(struct resource) * res_count) +
707 platform_data_size, GFP_KERNEL);
708 if (!smdev)
709 return NULL;
710
711 smdev->pdev.dev.release = sm501_device_release;
712
713 smdev->pdev.name = name;
714 smdev->pdev.id = sm->pdev_id;
715 smdev->pdev.dev.parent = sm->dev;
716 smdev->pdev.dev.coherent_dma_mask = 0xffffffff;
717
718 if (res_count) {
719 smdev->pdev.resource = (struct resource *)(smdev+1);
720 smdev->pdev.num_resources = res_count;
721 }
722 if (platform_data_size)
723 smdev->pdev.dev.platform_data = (void *)(smdev+1);
724
725 return &smdev->pdev;
726}
727
728/* sm501_register_device
729 *
730 * Register a platform device created with sm501_create_subdev()
731*/
732
733static int sm501_register_device(struct sm501_devdata *sm,
734 struct platform_device *pdev)
735{
736 struct sm501_device *smdev = to_sm_device(pdev);
737 int ptr;
738 int ret;
739
740 for (ptr = 0; ptr < pdev->num_resources; ptr++) {
741 printk(KERN_DEBUG "%s[%d] %pR\n",
742 pdev->name, ptr, &pdev->resource[ptr]);
743 }
744
745 ret = platform_device_register(pdev);
746
747 if (ret >= 0) {
748 dev_dbg(sm->dev, "registered %s\n", pdev->name);
749 list_add_tail(&smdev->list, &sm->devices);
750 } else
751 dev_err(sm->dev, "error registering %s (%d)\n",
752 pdev->name, ret);
753
754 return ret;
755}
756
757/* sm501_create_subio
758 *
759 * Fill in an IO resource for a sub device
760*/
761
762static void sm501_create_subio(struct sm501_devdata *sm,
763 struct resource *res,
764 resource_size_t offs,
765 resource_size_t size)
766{
767 res->flags = IORESOURCE_MEM;
768 res->parent = sm->io_res;
769 res->start = sm->io_res->start + offs;
770 res->end = res->start + size - 1;
771}
772
773/* sm501_create_mem
774 *
775 * Fill in an MEM resource for a sub device
776*/
777
778static void sm501_create_mem(struct sm501_devdata *sm,
779 struct resource *res,
780 resource_size_t *offs,
781 resource_size_t size)
782{
783 *offs -= size; /* adjust memory size */
784
785 res->flags = IORESOURCE_MEM;
786 res->parent = sm->mem_res;
787 res->start = sm->mem_res->start + *offs;
788 res->end = res->start + size - 1;
789}
790
791/* sm501_create_irq
792 *
793 * Fill in an IRQ resource for a sub device
794*/
795
796static void sm501_create_irq(struct sm501_devdata *sm,
797 struct resource *res)
798{
799 res->flags = IORESOURCE_IRQ;
800 res->parent = NULL;
801 res->start = res->end = sm->irq;
802}
803
804static int sm501_register_usbhost(struct sm501_devdata *sm,
805 resource_size_t *mem_avail)
806{
807 struct platform_device *pdev;
808
809 pdev = sm501_create_subdev(sm, "sm501-usb", 3, 0);
810 if (!pdev)
811 return -ENOMEM;
812
813 sm501_create_subio(sm, &pdev->resource[0], 0x40000, 0x20000);
814 sm501_create_mem(sm, &pdev->resource[1], mem_avail, 256*1024);
815 sm501_create_irq(sm, &pdev->resource[2]);
816
817 return sm501_register_device(sm, pdev);
818}
819
820static void sm501_setup_uart_data(struct sm501_devdata *sm,
821 struct plat_serial8250_port *uart_data,
822 unsigned int offset)
823{
824 uart_data->membase = sm->regs + offset;
825 uart_data->mapbase = sm->io_res->start + offset;
826 uart_data->iotype = UPIO_MEM;
827 uart_data->irq = sm->irq;
828 uart_data->flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ;
829 uart_data->regshift = 2;
830 uart_data->uartclk = (9600 * 16);
831}
832
833static int sm501_register_uart(struct sm501_devdata *sm, int devices)
834{
835 struct platform_device *pdev;
836 struct plat_serial8250_port *uart_data;
837
838 pdev = sm501_create_subdev(sm, "serial8250", 0,
839 sizeof(struct plat_serial8250_port) * 3);
840 if (!pdev)
841 return -ENOMEM;
842
843 uart_data = dev_get_platdata(&pdev->dev);
844
845 if (devices & SM501_USE_UART0) {
846 sm501_setup_uart_data(sm, uart_data++, 0x30000);
847 sm501_unit_power(sm->dev, SM501_GATE_UART0, 1);
848 sm501_modify_reg(sm->dev, SM501_IRQ_MASK, 1 << 12, 0);
849 sm501_modify_reg(sm->dev, SM501_GPIO63_32_CONTROL, 0x01e0, 0);
850 }
851 if (devices & SM501_USE_UART1) {
852 sm501_setup_uart_data(sm, uart_data++, 0x30020);
853 sm501_unit_power(sm->dev, SM501_GATE_UART1, 1);
854 sm501_modify_reg(sm->dev, SM501_IRQ_MASK, 1 << 13, 0);
855 sm501_modify_reg(sm->dev, SM501_GPIO63_32_CONTROL, 0x1e00, 0);
856 }
857
858 pdev->id = PLAT8250_DEV_SM501;
859
860 return sm501_register_device(sm, pdev);
861}
862
863static int sm501_register_display(struct sm501_devdata *sm,
864 resource_size_t *mem_avail)
865{
866 struct platform_device *pdev;
867
868 pdev = sm501_create_subdev(sm, "sm501-fb", 4, 0);
869 if (!pdev)
870 return -ENOMEM;
871
872 sm501_create_subio(sm, &pdev->resource[0], 0x80000, 0x10000);
873 sm501_create_subio(sm, &pdev->resource[1], 0x100000, 0x50000);
874 sm501_create_mem(sm, &pdev->resource[2], mem_avail, *mem_avail);
875 sm501_create_irq(sm, &pdev->resource[3]);
876
877 return sm501_register_device(sm, pdev);
878}
879
880#ifdef CONFIG_MFD_SM501_GPIO
881
882static inline struct sm501_devdata *sm501_gpio_to_dev(struct sm501_gpio *gpio)
883{
884 return container_of(gpio, struct sm501_devdata, gpio);
885}
886
887static int sm501_gpio_get(struct gpio_chip *chip, unsigned offset)
888
889{
890 struct sm501_gpio_chip *smgpio = gpiochip_get_data(chip);
891 unsigned long result;
892
893 result = smc501_readl(smgpio->regbase + SM501_GPIO_DATA_LOW);
894 result >>= offset;
895
896 return result & 1UL;
897}
898
899static void sm501_gpio_ensure_gpio(struct sm501_gpio_chip *smchip,
900 unsigned long bit)
901{
902 unsigned long ctrl;
903
904 /* check and modify if this pin is not set as gpio. */
905
906 if (smc501_readl(smchip->control) & bit) {
907 dev_info(sm501_gpio_to_dev(smchip->ourgpio)->dev,
908 "changing mode of gpio, bit %08lx\n", bit);
909
910 ctrl = smc501_readl(smchip->control);
911 ctrl &= ~bit;
912 smc501_writel(ctrl, smchip->control);
913
914 sm501_sync_regs(sm501_gpio_to_dev(smchip->ourgpio));
915 }
916}
917
918static void sm501_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
919
920{
921 struct sm501_gpio_chip *smchip = gpiochip_get_data(chip);
922 struct sm501_gpio *smgpio = smchip->ourgpio;
923 unsigned long bit = 1 << offset;
924 void __iomem *regs = smchip->regbase;
925 unsigned long save;
926 unsigned long val;
927
928 dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d)\n",
929 __func__, chip, offset);
930
931 spin_lock_irqsave(&smgpio->lock, save);
932
933 val = smc501_readl(regs + SM501_GPIO_DATA_LOW) & ~bit;
934 if (value)
935 val |= bit;
936 smc501_writel(val, regs);
937
938 sm501_sync_regs(sm501_gpio_to_dev(smgpio));
939 sm501_gpio_ensure_gpio(smchip, bit);
940
941 spin_unlock_irqrestore(&smgpio->lock, save);
942}
943
944static int sm501_gpio_input(struct gpio_chip *chip, unsigned offset)
945{
946 struct sm501_gpio_chip *smchip = gpiochip_get_data(chip);
947 struct sm501_gpio *smgpio = smchip->ourgpio;
948 void __iomem *regs = smchip->regbase;
949 unsigned long bit = 1 << offset;
950 unsigned long save;
951 unsigned long ddr;
952
953 dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d)\n",
954 __func__, chip, offset);
955
956 spin_lock_irqsave(&smgpio->lock, save);
957
958 ddr = smc501_readl(regs + SM501_GPIO_DDR_LOW);
959 smc501_writel(ddr & ~bit, regs + SM501_GPIO_DDR_LOW);
960
961 sm501_sync_regs(sm501_gpio_to_dev(smgpio));
962 sm501_gpio_ensure_gpio(smchip, bit);
963
964 spin_unlock_irqrestore(&smgpio->lock, save);
965
966 return 0;
967}
968
969static int sm501_gpio_output(struct gpio_chip *chip,
970 unsigned offset, int value)
971{
972 struct sm501_gpio_chip *smchip = gpiochip_get_data(chip);
973 struct sm501_gpio *smgpio = smchip->ourgpio;
974 unsigned long bit = 1 << offset;
975 void __iomem *regs = smchip->regbase;
976 unsigned long save;
977 unsigned long val;
978 unsigned long ddr;
979
980 dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d,%d)\n",
981 __func__, chip, offset, value);
982
983 spin_lock_irqsave(&smgpio->lock, save);
984
985 val = smc501_readl(regs + SM501_GPIO_DATA_LOW);
986 if (value)
987 val |= bit;
988 else
989 val &= ~bit;
990 smc501_writel(val, regs);
991
992 ddr = smc501_readl(regs + SM501_GPIO_DDR_LOW);
993 smc501_writel(ddr | bit, regs + SM501_GPIO_DDR_LOW);
994
995 sm501_sync_regs(sm501_gpio_to_dev(smgpio));
996 smc501_writel(val, regs + SM501_GPIO_DATA_LOW);
997
998 sm501_sync_regs(sm501_gpio_to_dev(smgpio));
999 spin_unlock_irqrestore(&smgpio->lock, save);
1000
1001 return 0;
1002}
1003
1004static const struct gpio_chip gpio_chip_template = {
1005 .ngpio = 32,
1006 .direction_input = sm501_gpio_input,
1007 .direction_output = sm501_gpio_output,
1008 .set = sm501_gpio_set,
1009 .get = sm501_gpio_get,
1010};
1011
1012static int sm501_gpio_register_chip(struct sm501_devdata *sm,
1013 struct sm501_gpio *gpio,
1014 struct sm501_gpio_chip *chip)
1015{
1016 struct sm501_platdata *pdata = sm->platdata;
1017 struct gpio_chip *gchip = &chip->gpio;
1018 int base = pdata->gpio_base;
1019
1020 chip->gpio = gpio_chip_template;
1021
1022 if (chip == &gpio->high) {
1023 if (base > 0)
1024 base += 32;
1025 chip->regbase = gpio->regs + SM501_GPIO_DATA_HIGH;
1026 chip->control = sm->regs + SM501_GPIO63_32_CONTROL;
1027 gchip->label = "SM501-HIGH";
1028 } else {
1029 chip->regbase = gpio->regs + SM501_GPIO_DATA_LOW;
1030 chip->control = sm->regs + SM501_GPIO31_0_CONTROL;
1031 gchip->label = "SM501-LOW";
1032 }
1033
1034 gchip->base = base;
1035 chip->ourgpio = gpio;
1036
1037 return gpiochip_add_data(gchip, chip);
1038}
1039
1040static int sm501_register_gpio(struct sm501_devdata *sm)
1041{
1042 struct sm501_gpio *gpio = &sm->gpio;
1043 resource_size_t iobase = sm->io_res->start + SM501_GPIO;
1044 int ret;
1045
1046 dev_dbg(sm->dev, "registering gpio block %08llx\n",
1047 (unsigned long long)iobase);
1048
1049 spin_lock_init(&gpio->lock);
1050
1051 gpio->regs_res = request_mem_region(iobase, 0x20, "sm501-gpio");
1052 if (!gpio->regs_res) {
1053 dev_err(sm->dev, "gpio: failed to request region\n");
1054 return -ENXIO;
1055 }
1056
1057 gpio->regs = ioremap(iobase, 0x20);
1058 if (!gpio->regs) {
1059 dev_err(sm->dev, "gpio: failed to remap registers\n");
1060 ret = -ENXIO;
1061 goto err_claimed;
1062 }
1063
1064 /* Register both our chips. */
1065
1066 ret = sm501_gpio_register_chip(sm, gpio, &gpio->low);
1067 if (ret) {
1068 dev_err(sm->dev, "failed to add low chip\n");
1069 goto err_mapped;
1070 }
1071
1072 ret = sm501_gpio_register_chip(sm, gpio, &gpio->high);
1073 if (ret) {
1074 dev_err(sm->dev, "failed to add high chip\n");
1075 goto err_low_chip;
1076 }
1077
1078 gpio->registered = 1;
1079
1080 return 0;
1081
1082 err_low_chip:
1083 gpiochip_remove(&gpio->low.gpio);
1084
1085 err_mapped:
1086 iounmap(gpio->regs);
1087
1088 err_claimed:
1089 release_mem_region(iobase, 0x20);
1090
1091 return ret;
1092}
1093
1094static void sm501_gpio_remove(struct sm501_devdata *sm)
1095{
1096 struct sm501_gpio *gpio = &sm->gpio;
1097 resource_size_t iobase = sm->io_res->start + SM501_GPIO;
1098
1099 if (!sm->gpio.registered)
1100 return;
1101
1102 gpiochip_remove(&gpio->low.gpio);
1103 gpiochip_remove(&gpio->high.gpio);
1104
1105 iounmap(gpio->regs);
1106 release_mem_region(iobase, 0x20);
1107}
1108
1109static inline int sm501_gpio_isregistered(struct sm501_devdata *sm)
1110{
1111 return sm->gpio.registered;
1112}
1113#else
1114static inline int sm501_register_gpio(struct sm501_devdata *sm)
1115{
1116 return 0;
1117}
1118
1119static inline void sm501_gpio_remove(struct sm501_devdata *sm)
1120{
1121}
1122
1123static inline int sm501_gpio_isregistered(struct sm501_devdata *sm)
1124{
1125 return 0;
1126}
1127#endif
1128
1129static int sm501_register_gpio_i2c_instance(struct sm501_devdata *sm,
1130 struct sm501_platdata_gpio_i2c *iic)
1131{
1132 struct i2c_gpio_platform_data *icd;
1133 struct platform_device *pdev;
1134 struct gpiod_lookup_table *lookup;
1135
1136 pdev = sm501_create_subdev(sm, "i2c-gpio", 0,
1137 sizeof(struct i2c_gpio_platform_data));
1138 if (!pdev)
1139 return -ENOMEM;
1140
1141 /* Create a gpiod lookup using gpiochip-local offsets */
1142 lookup = devm_kzalloc(&pdev->dev, struct_size(lookup, table, 3),
1143 GFP_KERNEL);
1144 if (!lookup)
1145 return -ENOMEM;
1146
1147 lookup->dev_id = "i2c-gpio";
1148 lookup->table[0] = (struct gpiod_lookup)
1149 GPIO_LOOKUP_IDX(iic->pin_sda < 32 ? "SM501-LOW" : "SM501-HIGH",
1150 iic->pin_sda % 32, NULL, 0,
1151 GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN);
1152 lookup->table[1] = (struct gpiod_lookup)
1153 GPIO_LOOKUP_IDX(iic->pin_scl < 32 ? "SM501-LOW" : "SM501-HIGH",
1154 iic->pin_scl % 32, NULL, 1,
1155 GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN);
1156 gpiod_add_lookup_table(lookup);
1157
1158 icd = dev_get_platdata(&pdev->dev);
1159 icd->timeout = iic->timeout;
1160 icd->udelay = iic->udelay;
1161
1162 /* note, we can't use either of the pin numbers, as the i2c-gpio
1163 * driver uses the platform.id field to generate the bus number
1164 * to register with the i2c core; The i2c core doesn't have enough
1165 * entries to deal with anything we currently use.
1166 */
1167
1168 pdev->id = iic->bus_num;
1169
1170 dev_info(sm->dev, "registering i2c-%d: sda=%d, scl=%d\n",
1171 iic->bus_num,
1172 iic->pin_sda, iic->pin_scl);
1173
1174 return sm501_register_device(sm, pdev);
1175}
1176
1177static int sm501_register_gpio_i2c(struct sm501_devdata *sm,
1178 struct sm501_platdata *pdata)
1179{
1180 struct sm501_platdata_gpio_i2c *iic = pdata->gpio_i2c;
1181 int index;
1182 int ret;
1183
1184 for (index = 0; index < pdata->gpio_i2c_nr; index++, iic++) {
1185 ret = sm501_register_gpio_i2c_instance(sm, iic);
1186 if (ret < 0)
1187 return ret;
1188 }
1189
1190 return 0;
1191}
1192
1193/* sm501_dbg_regs
1194 *
1195 * Debug attribute to attach to parent device to show core registers
1196*/
1197
1198static ssize_t sm501_dbg_regs(struct device *dev,
1199 struct device_attribute *attr, char *buff)
1200{
1201 struct sm501_devdata *sm = dev_get_drvdata(dev) ;
1202 unsigned int reg;
1203 char *ptr = buff;
1204 int ret;
1205
1206 for (reg = 0x00; reg < 0x70; reg += 4) {
1207 ret = sprintf(ptr, "%08x = %08x\n",
1208 reg, smc501_readl(sm->regs + reg));
1209 ptr += ret;
1210 }
1211
1212 return ptr - buff;
1213}
1214
1215
1216static DEVICE_ATTR(dbg_regs, 0444, sm501_dbg_regs, NULL);
1217
1218/* sm501_init_reg
1219 *
1220 * Helper function for the init code to setup a register
1221 *
1222 * clear the bits which are set in r->mask, and then set
1223 * the bits set in r->set.
1224*/
1225
1226static inline void sm501_init_reg(struct sm501_devdata *sm,
1227 unsigned long reg,
1228 struct sm501_reg_init *r)
1229{
1230 unsigned long tmp;
1231
1232 tmp = smc501_readl(sm->regs + reg);
1233 tmp &= ~r->mask;
1234 tmp |= r->set;
1235 smc501_writel(tmp, sm->regs + reg);
1236}
1237
1238/* sm501_init_regs
1239 *
1240 * Setup core register values
1241*/
1242
1243static void sm501_init_regs(struct sm501_devdata *sm,
1244 struct sm501_initdata *init)
1245{
1246 sm501_misc_control(sm->dev,
1247 init->misc_control.set,
1248 init->misc_control.mask);
1249
1250 sm501_init_reg(sm, SM501_MISC_TIMING, &init->misc_timing);
1251 sm501_init_reg(sm, SM501_GPIO31_0_CONTROL, &init->gpio_low);
1252 sm501_init_reg(sm, SM501_GPIO63_32_CONTROL, &init->gpio_high);
1253
1254 if (init->m1xclk) {
1255 dev_info(sm->dev, "setting M1XCLK to %ld\n", init->m1xclk);
1256 sm501_set_clock(sm->dev, SM501_CLOCK_M1XCLK, init->m1xclk);
1257 }
1258
1259 if (init->mclk) {
1260 dev_info(sm->dev, "setting MCLK to %ld\n", init->mclk);
1261 sm501_set_clock(sm->dev, SM501_CLOCK_MCLK, init->mclk);
1262 }
1263
1264}
1265
1266/* Check the PLL sources for the M1CLK and M1XCLK
1267 *
1268 * If the M1CLK and M1XCLKs are not sourced from the same PLL, then
1269 * there is a risk (see errata AB-5) that the SM501 will cease proper
1270 * function. If this happens, then it is likely the SM501 will
1271 * hang the system.
1272*/
1273
1274static int sm501_check_clocks(struct sm501_devdata *sm)
1275{
1276 unsigned long pwrmode = smc501_readl(sm->regs + SM501_CURRENT_CLOCK);
1277 unsigned long msrc = (pwrmode & SM501_POWERMODE_M_SRC);
1278 unsigned long m1src = (pwrmode & SM501_POWERMODE_M1_SRC);
1279
1280 return ((msrc == 0 && m1src != 0) || (msrc != 0 && m1src == 0));
1281}
1282
1283static unsigned int sm501_mem_local[] = {
1284 [0] = 4*1024*1024,
1285 [1] = 8*1024*1024,
1286 [2] = 16*1024*1024,
1287 [3] = 32*1024*1024,
1288 [4] = 64*1024*1024,
1289 [5] = 2*1024*1024,
1290};
1291
1292/* sm501_init_dev
1293 *
1294 * Common init code for an SM501
1295*/
1296
1297static int sm501_init_dev(struct sm501_devdata *sm)
1298{
1299 struct sm501_initdata *idata;
1300 struct sm501_platdata *pdata;
1301 resource_size_t mem_avail;
1302 unsigned long dramctrl;
1303 unsigned long devid;
1304 int ret;
1305
1306 mutex_init(&sm->clock_lock);
1307 spin_lock_init(&sm->reg_lock);
1308
1309 INIT_LIST_HEAD(&sm->devices);
1310
1311 devid = smc501_readl(sm->regs + SM501_DEVICEID);
1312
1313 if ((devid & SM501_DEVICEID_IDMASK) != SM501_DEVICEID_SM501) {
1314 dev_err(sm->dev, "incorrect device id %08lx\n", devid);
1315 return -EINVAL;
1316 }
1317
1318 /* disable irqs */
1319 smc501_writel(0, sm->regs + SM501_IRQ_MASK);
1320
1321 dramctrl = smc501_readl(sm->regs + SM501_DRAM_CONTROL);
1322 mem_avail = sm501_mem_local[(dramctrl >> 13) & 0x7];
1323
1324 dev_info(sm->dev, "SM501 At %p: Version %08lx, %ld Mb, IRQ %d\n",
1325 sm->regs, devid, (unsigned long)mem_avail >> 20, sm->irq);
1326
1327 sm->rev = devid & SM501_DEVICEID_REVMASK;
1328
1329 sm501_dump_gate(sm);
1330
1331 ret = device_create_file(sm->dev, &dev_attr_dbg_regs);
1332 if (ret)
1333 dev_err(sm->dev, "failed to create debug regs file\n");
1334
1335 sm501_dump_clk(sm);
1336
1337 /* check to see if we have some device initialisation */
1338
1339 pdata = sm->platdata;
1340 idata = pdata ? pdata->init : NULL;
1341
1342 if (idata) {
1343 sm501_init_regs(sm, idata);
1344
1345 if (idata->devices & SM501_USE_USB_HOST)
1346 sm501_register_usbhost(sm, &mem_avail);
1347 if (idata->devices & (SM501_USE_UART0 | SM501_USE_UART1))
1348 sm501_register_uart(sm, idata->devices);
1349 if (idata->devices & SM501_USE_GPIO)
1350 sm501_register_gpio(sm);
1351 }
1352
1353 if (pdata && pdata->gpio_i2c && pdata->gpio_i2c_nr > 0) {
1354 if (!sm501_gpio_isregistered(sm))
1355 dev_err(sm->dev, "no gpio available for i2c gpio.\n");
1356 else
1357 sm501_register_gpio_i2c(sm, pdata);
1358 }
1359
1360 ret = sm501_check_clocks(sm);
1361 if (ret) {
1362 dev_err(sm->dev, "M1X and M clocks sourced from different "
1363 "PLLs\n");
1364 return -EINVAL;
1365 }
1366
1367 /* always create a framebuffer */
1368 sm501_register_display(sm, &mem_avail);
1369
1370 return 0;
1371}
1372
1373static int sm501_plat_probe(struct platform_device *dev)
1374{
1375 struct sm501_devdata *sm;
1376 int ret;
1377
1378 sm = kzalloc(sizeof(*sm), GFP_KERNEL);
1379 if (!sm) {
1380 ret = -ENOMEM;
1381 goto err1;
1382 }
1383
1384 sm->dev = &dev->dev;
1385 sm->pdev_id = dev->id;
1386 sm->platdata = dev_get_platdata(&dev->dev);
1387
1388 ret = platform_get_irq(dev, 0);
1389 if (ret < 0)
1390 goto err_res;
1391 sm->irq = ret;
1392
1393 sm->io_res = platform_get_resource(dev, IORESOURCE_MEM, 1);
1394 sm->mem_res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1395 if (!sm->io_res || !sm->mem_res) {
1396 dev_err(&dev->dev, "failed to get IO resource\n");
1397 ret = -ENOENT;
1398 goto err_res;
1399 }
1400
1401 sm->regs_claim = request_mem_region(sm->io_res->start,
1402 0x100, "sm501");
1403 if (!sm->regs_claim) {
1404 dev_err(&dev->dev, "cannot claim registers\n");
1405 ret = -EBUSY;
1406 goto err_res;
1407 }
1408
1409 platform_set_drvdata(dev, sm);
1410
1411 sm->regs = ioremap(sm->io_res->start, resource_size(sm->io_res));
1412 if (!sm->regs) {
1413 dev_err(&dev->dev, "cannot remap registers\n");
1414 ret = -EIO;
1415 goto err_claim;
1416 }
1417
1418 return sm501_init_dev(sm);
1419
1420 err_claim:
1421 release_mem_region(sm->io_res->start, 0x100);
1422 err_res:
1423 kfree(sm);
1424 err1:
1425 return ret;
1426
1427}
1428
1429#ifdef CONFIG_PM
1430
1431/* power management support */
1432
1433static void sm501_set_power(struct sm501_devdata *sm, int on)
1434{
1435 struct sm501_platdata *pd = sm->platdata;
1436
1437 if (!pd)
1438 return;
1439
1440 if (pd->get_power) {
1441 if (pd->get_power(sm->dev) == on) {
1442 dev_dbg(sm->dev, "is already %d\n", on);
1443 return;
1444 }
1445 }
1446
1447 if (pd->set_power) {
1448 dev_dbg(sm->dev, "setting power to %d\n", on);
1449
1450 pd->set_power(sm->dev, on);
1451 sm501_mdelay(sm, 10);
1452 }
1453}
1454
1455static int sm501_plat_suspend(struct platform_device *pdev, pm_message_t state)
1456{
1457 struct sm501_devdata *sm = platform_get_drvdata(pdev);
1458
1459 sm->in_suspend = 1;
1460 sm->pm_misc = smc501_readl(sm->regs + SM501_MISC_CONTROL);
1461
1462 sm501_dump_regs(sm);
1463
1464 if (sm->platdata) {
1465 if (sm->platdata->flags & SM501_FLAG_SUSPEND_OFF)
1466 sm501_set_power(sm, 0);
1467 }
1468
1469 return 0;
1470}
1471
1472static int sm501_plat_resume(struct platform_device *pdev)
1473{
1474 struct sm501_devdata *sm = platform_get_drvdata(pdev);
1475
1476 sm501_set_power(sm, 1);
1477
1478 sm501_dump_regs(sm);
1479 sm501_dump_gate(sm);
1480 sm501_dump_clk(sm);
1481
1482 /* check to see if we are in the same state as when suspended */
1483
1484 if (smc501_readl(sm->regs + SM501_MISC_CONTROL) != sm->pm_misc) {
1485 dev_info(sm->dev, "SM501_MISC_CONTROL changed over sleep\n");
1486 smc501_writel(sm->pm_misc, sm->regs + SM501_MISC_CONTROL);
1487
1488 /* our suspend causes the controller state to change,
1489 * either by something attempting setup, power loss,
1490 * or an external reset event on power change */
1491
1492 if (sm->platdata && sm->platdata->init) {
1493 sm501_init_regs(sm, sm->platdata->init);
1494 }
1495 }
1496
1497 /* dump our state from resume */
1498
1499 sm501_dump_regs(sm);
1500 sm501_dump_clk(sm);
1501
1502 sm->in_suspend = 0;
1503
1504 return 0;
1505}
1506#else
1507#define sm501_plat_suspend NULL
1508#define sm501_plat_resume NULL
1509#endif
1510
1511/* Initialisation data for PCI devices */
1512
1513static struct sm501_initdata sm501_pci_initdata = {
1514 .gpio_high = {
1515 .set = 0x3F000000, /* 24bit panel */
1516 .mask = 0x0,
1517 },
1518 .misc_timing = {
1519 .set = 0x010100, /* SDRAM timing */
1520 .mask = 0x1F1F00,
1521 },
1522 .misc_control = {
1523 .set = SM501_MISC_PNL_24BIT,
1524 .mask = 0,
1525 },
1526
1527 .devices = SM501_USE_ALL,
1528
1529 /* Errata AB-3 says that 72MHz is the fastest available
1530 * for 33MHZ PCI with proper bus-mastering operation */
1531
1532 .mclk = 72 * MHZ,
1533 .m1xclk = 144 * MHZ,
1534};
1535
1536static struct sm501_platdata_fbsub sm501_pdata_fbsub = {
1537 .flags = (SM501FB_FLAG_USE_INIT_MODE |
1538 SM501FB_FLAG_USE_HWCURSOR |
1539 SM501FB_FLAG_USE_HWACCEL |
1540 SM501FB_FLAG_DISABLE_AT_EXIT),
1541};
1542
1543static struct sm501_platdata_fb sm501_fb_pdata = {
1544 .fb_route = SM501_FB_OWN,
1545 .fb_crt = &sm501_pdata_fbsub,
1546 .fb_pnl = &sm501_pdata_fbsub,
1547};
1548
1549static struct sm501_platdata sm501_pci_platdata = {
1550 .init = &sm501_pci_initdata,
1551 .fb = &sm501_fb_pdata,
1552 .gpio_base = -1,
1553};
1554
1555static int sm501_pci_probe(struct pci_dev *dev,
1556 const struct pci_device_id *id)
1557{
1558 struct sm501_devdata *sm;
1559 int err;
1560
1561 sm = kzalloc(sizeof(*sm), GFP_KERNEL);
1562 if (!sm) {
1563 err = -ENOMEM;
1564 goto err1;
1565 }
1566
1567 /* set a default set of platform data */
1568 dev->dev.platform_data = sm->platdata = &sm501_pci_platdata;
1569
1570 /* set a hopefully unique id for our child platform devices */
1571 sm->pdev_id = 32 + dev->devfn;
1572
1573 pci_set_drvdata(dev, sm);
1574
1575 err = pci_enable_device(dev);
1576 if (err) {
1577 dev_err(&dev->dev, "cannot enable device\n");
1578 goto err2;
1579 }
1580
1581 sm->dev = &dev->dev;
1582 sm->irq = dev->irq;
1583
1584#ifdef __BIG_ENDIAN
1585 /* if the system is big-endian, we most probably have a
1586 * translation in the IO layer making the PCI bus little endian
1587 * so make the framebuffer swapped pixels */
1588
1589 sm501_fb_pdata.flags |= SM501_FBPD_SWAP_FB_ENDIAN;
1590#endif
1591
1592 /* check our resources */
1593
1594 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM)) {
1595 dev_err(&dev->dev, "region #0 is not memory?\n");
1596 err = -EINVAL;
1597 goto err3;
1598 }
1599
1600 if (!(pci_resource_flags(dev, 1) & IORESOURCE_MEM)) {
1601 dev_err(&dev->dev, "region #1 is not memory?\n");
1602 err = -EINVAL;
1603 goto err3;
1604 }
1605
1606 /* make our resources ready for sharing */
1607
1608 sm->io_res = &dev->resource[1];
1609 sm->mem_res = &dev->resource[0];
1610
1611 sm->regs_claim = request_mem_region(sm->io_res->start,
1612 0x100, "sm501");
1613 if (!sm->regs_claim) {
1614 dev_err(&dev->dev, "cannot claim registers\n");
1615 err= -EBUSY;
1616 goto err3;
1617 }
1618
1619 sm->regs = pci_ioremap_bar(dev, 1);
1620 if (!sm->regs) {
1621 dev_err(&dev->dev, "cannot remap registers\n");
1622 err = -EIO;
1623 goto err4;
1624 }
1625
1626 sm501_init_dev(sm);
1627 return 0;
1628
1629 err4:
1630 release_mem_region(sm->io_res->start, 0x100);
1631 err3:
1632 pci_disable_device(dev);
1633 err2:
1634 kfree(sm);
1635 err1:
1636 return err;
1637}
1638
1639static void sm501_remove_sub(struct sm501_devdata *sm,
1640 struct sm501_device *smdev)
1641{
1642 list_del(&smdev->list);
1643 platform_device_unregister(&smdev->pdev);
1644}
1645
1646static void sm501_dev_remove(struct sm501_devdata *sm)
1647{
1648 struct sm501_device *smdev, *tmp;
1649
1650 list_for_each_entry_safe(smdev, tmp, &sm->devices, list)
1651 sm501_remove_sub(sm, smdev);
1652
1653 device_remove_file(sm->dev, &dev_attr_dbg_regs);
1654
1655 sm501_gpio_remove(sm);
1656}
1657
1658static void sm501_pci_remove(struct pci_dev *dev)
1659{
1660 struct sm501_devdata *sm = pci_get_drvdata(dev);
1661
1662 sm501_dev_remove(sm);
1663 iounmap(sm->regs);
1664
1665 release_mem_region(sm->io_res->start, 0x100);
1666
1667 pci_disable_device(dev);
1668}
1669
1670static int sm501_plat_remove(struct platform_device *dev)
1671{
1672 struct sm501_devdata *sm = platform_get_drvdata(dev);
1673
1674 sm501_dev_remove(sm);
1675 iounmap(sm->regs);
1676
1677 release_mem_region(sm->io_res->start, 0x100);
1678
1679 return 0;
1680}
1681
1682static const struct pci_device_id sm501_pci_tbl[] = {
1683 { 0x126f, 0x0501, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
1684 { 0, },
1685};
1686
1687MODULE_DEVICE_TABLE(pci, sm501_pci_tbl);
1688
1689static struct pci_driver sm501_pci_driver = {
1690 .name = "sm501",
1691 .id_table = sm501_pci_tbl,
1692 .probe = sm501_pci_probe,
1693 .remove = sm501_pci_remove,
1694};
1695
1696MODULE_ALIAS("platform:sm501");
1697
1698static const struct of_device_id of_sm501_match_tbl[] = {
1699 { .compatible = "smi,sm501", },
1700 { /* end */ }
1701};
1702MODULE_DEVICE_TABLE(of, of_sm501_match_tbl);
1703
1704static struct platform_driver sm501_plat_driver = {
1705 .driver = {
1706 .name = "sm501",
1707 .of_match_table = of_sm501_match_tbl,
1708 },
1709 .probe = sm501_plat_probe,
1710 .remove = sm501_plat_remove,
1711 .suspend = sm501_plat_suspend,
1712 .resume = sm501_plat_resume,
1713};
1714
1715static int __init sm501_base_init(void)
1716{
1717 platform_driver_register(&sm501_plat_driver);
1718 return pci_register_driver(&sm501_pci_driver);
1719}
1720
1721static void __exit sm501_base_exit(void)
1722{
1723 platform_driver_unregister(&sm501_plat_driver);
1724 pci_unregister_driver(&sm501_pci_driver);
1725}
1726
1727module_init(sm501_base_init);
1728module_exit(sm501_base_exit);
1729
1730MODULE_DESCRIPTION("SM501 Core Driver");
1731MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, Vincent Sanders");
1732MODULE_LICENSE("GPL v2");