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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
4 *
5 * Description: CoreSight System Trace Macrocell driver
6 *
7 * Initial implementation by Pratik Patel
8 * (C) 2014-2015 Pratik Patel <pratikp@codeaurora.org>
9 *
10 * Serious refactoring, code cleanup and upgrading to the Coresight upstream
11 * framework by Mathieu Poirier
12 * (C) 2015-2016 Mathieu Poirier <mathieu.poirier@linaro.org>
13 *
14 * Guaranteed timing and support for various packet type coming from the
15 * generic STM API by Chunyan Zhang
16 * (C) 2015-2016 Chunyan Zhang <zhang.chunyan@linaro.org>
17 */
18#include <asm/local.h>
19#include <linux/acpi.h>
20#include <linux/amba/bus.h>
21#include <linux/bitmap.h>
22#include <linux/clk.h>
23#include <linux/coresight.h>
24#include <linux/coresight-stm.h>
25#include <linux/err.h>
26#include <linux/kernel.h>
27#include <linux/moduleparam.h>
28#include <linux/of_address.h>
29#include <linux/perf_event.h>
30#include <linux/pm_runtime.h>
31#include <linux/stm.h>
32
33#include "coresight-priv.h"
34
35#define STMDMASTARTR 0xc04
36#define STMDMASTOPR 0xc08
37#define STMDMASTATR 0xc0c
38#define STMDMACTLR 0xc10
39#define STMDMAIDR 0xcfc
40#define STMHEER 0xd00
41#define STMHETER 0xd20
42#define STMHEBSR 0xd60
43#define STMHEMCR 0xd64
44#define STMHEMASTR 0xdf4
45#define STMHEFEAT1R 0xdf8
46#define STMHEIDR 0xdfc
47#define STMSPER 0xe00
48#define STMSPTER 0xe20
49#define STMPRIVMASKR 0xe40
50#define STMSPSCR 0xe60
51#define STMSPMSCR 0xe64
52#define STMSPOVERRIDER 0xe68
53#define STMSPMOVERRIDER 0xe6c
54#define STMSPTRIGCSR 0xe70
55#define STMTCSR 0xe80
56#define STMTSSTIMR 0xe84
57#define STMTSFREQR 0xe8c
58#define STMSYNCR 0xe90
59#define STMAUXCR 0xe94
60#define STMSPFEAT1R 0xea0
61#define STMSPFEAT2R 0xea4
62#define STMSPFEAT3R 0xea8
63#define STMITTRIGGER 0xee8
64#define STMITATBDATA0 0xeec
65#define STMITATBCTR2 0xef0
66#define STMITATBID 0xef4
67#define STMITATBCTR0 0xef8
68
69#define STM_32_CHANNEL 32
70#define BYTES_PER_CHANNEL 256
71#define STM_TRACE_BUF_SIZE 4096
72#define STM_SW_MASTER_END 127
73
74/* Register bit definition */
75#define STMTCSR_BUSY_BIT 23
76/* Reserve the first 10 channels for kernel usage */
77#define STM_CHANNEL_OFFSET 0
78
79enum stm_pkt_type {
80 STM_PKT_TYPE_DATA = 0x98,
81 STM_PKT_TYPE_FLAG = 0xE8,
82 STM_PKT_TYPE_TRIG = 0xF8,
83};
84
85#define stm_channel_addr(drvdata, ch) (drvdata->chs.base + \
86 (ch * BYTES_PER_CHANNEL))
87#define stm_channel_off(type, opts) (type & ~opts)
88
89static int boot_nr_channel;
90
91/*
92 * Not really modular but using module_param is the easiest way to
93 * remain consistent with existing use cases for now.
94 */
95module_param_named(
96 boot_nr_channel, boot_nr_channel, int, S_IRUGO
97);
98
99/**
100 * struct channel_space - central management entity for extended ports
101 * @base: memory mapped base address where channels start.
102 * @phys: physical base address of channel region.
103 * @guaraneed: is the channel delivery guaranteed.
104 */
105struct channel_space {
106 void __iomem *base;
107 phys_addr_t phys;
108 unsigned long *guaranteed;
109};
110
111DEFINE_CORESIGHT_DEVLIST(stm_devs, "stm");
112
113/**
114 * struct stm_drvdata - specifics associated to an STM component
115 * @base: memory mapped base address for this component.
116 * @atclk: optional clock for the core parts of the STM.
117 * @csdev: component vitals needed by the framework.
118 * @spinlock: only one at a time pls.
119 * @chs: the channels accociated to this STM.
120 * @stm: structure associated to the generic STM interface.
121 * @mode: this tracer's mode, i.e sysFS, or disabled.
122 * @traceid: value of the current ID for this component.
123 * @write_bytes: Maximus bytes this STM can write at a time.
124 * @stmsper: settings for register STMSPER.
125 * @stmspscr: settings for register STMSPSCR.
126 * @numsp: the total number of stimulus port support by this STM.
127 * @stmheer: settings for register STMHEER.
128 * @stmheter: settings for register STMHETER.
129 * @stmhebsr: settings for register STMHEBSR.
130 */
131struct stm_drvdata {
132 void __iomem *base;
133 struct clk *atclk;
134 struct coresight_device *csdev;
135 spinlock_t spinlock;
136 struct channel_space chs;
137 struct stm_data stm;
138 local_t mode;
139 u8 traceid;
140 u32 write_bytes;
141 u32 stmsper;
142 u32 stmspscr;
143 u32 numsp;
144 u32 stmheer;
145 u32 stmheter;
146 u32 stmhebsr;
147};
148
149static void stm_hwevent_enable_hw(struct stm_drvdata *drvdata)
150{
151 CS_UNLOCK(drvdata->base);
152
153 writel_relaxed(drvdata->stmhebsr, drvdata->base + STMHEBSR);
154 writel_relaxed(drvdata->stmheter, drvdata->base + STMHETER);
155 writel_relaxed(drvdata->stmheer, drvdata->base + STMHEER);
156 writel_relaxed(0x01 | /* Enable HW event tracing */
157 0x04, /* Error detection on event tracing */
158 drvdata->base + STMHEMCR);
159
160 CS_LOCK(drvdata->base);
161}
162
163static void stm_port_enable_hw(struct stm_drvdata *drvdata)
164{
165 CS_UNLOCK(drvdata->base);
166 /* ATB trigger enable on direct writes to TRIG locations */
167 writel_relaxed(0x10,
168 drvdata->base + STMSPTRIGCSR);
169 writel_relaxed(drvdata->stmspscr, drvdata->base + STMSPSCR);
170 writel_relaxed(drvdata->stmsper, drvdata->base + STMSPER);
171
172 CS_LOCK(drvdata->base);
173}
174
175static void stm_enable_hw(struct stm_drvdata *drvdata)
176{
177 if (drvdata->stmheer)
178 stm_hwevent_enable_hw(drvdata);
179
180 stm_port_enable_hw(drvdata);
181
182 CS_UNLOCK(drvdata->base);
183
184 /* 4096 byte between synchronisation packets */
185 writel_relaxed(0xFFF, drvdata->base + STMSYNCR);
186 writel_relaxed((drvdata->traceid << 16 | /* trace id */
187 0x02 | /* timestamp enable */
188 0x01), /* global STM enable */
189 drvdata->base + STMTCSR);
190
191 CS_LOCK(drvdata->base);
192}
193
194static int stm_enable(struct coresight_device *csdev,
195 struct perf_event *event, u32 mode)
196{
197 u32 val;
198 struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
199
200 if (mode != CS_MODE_SYSFS)
201 return -EINVAL;
202
203 val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode);
204
205 /* Someone is already using the tracer */
206 if (val)
207 return -EBUSY;
208
209 pm_runtime_get_sync(csdev->dev.parent);
210
211 spin_lock(&drvdata->spinlock);
212 stm_enable_hw(drvdata);
213 spin_unlock(&drvdata->spinlock);
214
215 dev_dbg(&csdev->dev, "STM tracing enabled\n");
216 return 0;
217}
218
219static void stm_hwevent_disable_hw(struct stm_drvdata *drvdata)
220{
221 CS_UNLOCK(drvdata->base);
222
223 writel_relaxed(0x0, drvdata->base + STMHEMCR);
224 writel_relaxed(0x0, drvdata->base + STMHEER);
225 writel_relaxed(0x0, drvdata->base + STMHETER);
226
227 CS_LOCK(drvdata->base);
228}
229
230static void stm_port_disable_hw(struct stm_drvdata *drvdata)
231{
232 CS_UNLOCK(drvdata->base);
233
234 writel_relaxed(0x0, drvdata->base + STMSPER);
235 writel_relaxed(0x0, drvdata->base + STMSPTRIGCSR);
236
237 CS_LOCK(drvdata->base);
238}
239
240static void stm_disable_hw(struct stm_drvdata *drvdata)
241{
242 u32 val;
243
244 CS_UNLOCK(drvdata->base);
245
246 val = readl_relaxed(drvdata->base + STMTCSR);
247 val &= ~0x1; /* clear global STM enable [0] */
248 writel_relaxed(val, drvdata->base + STMTCSR);
249
250 CS_LOCK(drvdata->base);
251
252 stm_port_disable_hw(drvdata);
253 if (drvdata->stmheer)
254 stm_hwevent_disable_hw(drvdata);
255}
256
257static void stm_disable(struct coresight_device *csdev,
258 struct perf_event *event)
259{
260 struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
261
262 /*
263 * For as long as the tracer isn't disabled another entity can't
264 * change its status. As such we can read the status here without
265 * fearing it will change under us.
266 */
267 if (local_read(&drvdata->mode) == CS_MODE_SYSFS) {
268 spin_lock(&drvdata->spinlock);
269 stm_disable_hw(drvdata);
270 spin_unlock(&drvdata->spinlock);
271
272 /* Wait until the engine has completely stopped */
273 coresight_timeout(drvdata->base, STMTCSR, STMTCSR_BUSY_BIT, 0);
274
275 pm_runtime_put(csdev->dev.parent);
276
277 local_set(&drvdata->mode, CS_MODE_DISABLED);
278 dev_dbg(&csdev->dev, "STM tracing disabled\n");
279 }
280}
281
282static int stm_trace_id(struct coresight_device *csdev)
283{
284 struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
285
286 return drvdata->traceid;
287}
288
289static const struct coresight_ops_source stm_source_ops = {
290 .trace_id = stm_trace_id,
291 .enable = stm_enable,
292 .disable = stm_disable,
293};
294
295static const struct coresight_ops stm_cs_ops = {
296 .source_ops = &stm_source_ops,
297};
298
299static inline bool stm_addr_unaligned(const void *addr, u8 write_bytes)
300{
301 return ((unsigned long)addr & (write_bytes - 1));
302}
303
304static void stm_send(void __iomem *addr, const void *data,
305 u32 size, u8 write_bytes)
306{
307 u8 paload[8];
308
309 if (stm_addr_unaligned(data, write_bytes)) {
310 memcpy(paload, data, size);
311 data = paload;
312 }
313
314 /* now we are 64bit/32bit aligned */
315 switch (size) {
316#ifdef CONFIG_64BIT
317 case 8:
318 writeq_relaxed(*(u64 *)data, addr);
319 break;
320#endif
321 case 4:
322 writel_relaxed(*(u32 *)data, addr);
323 break;
324 case 2:
325 writew_relaxed(*(u16 *)data, addr);
326 break;
327 case 1:
328 writeb_relaxed(*(u8 *)data, addr);
329 break;
330 default:
331 break;
332 }
333}
334
335static int stm_generic_link(struct stm_data *stm_data,
336 unsigned int master, unsigned int channel)
337{
338 struct stm_drvdata *drvdata = container_of(stm_data,
339 struct stm_drvdata, stm);
340 if (!drvdata || !drvdata->csdev)
341 return -EINVAL;
342
343 return coresight_enable(drvdata->csdev);
344}
345
346static void stm_generic_unlink(struct stm_data *stm_data,
347 unsigned int master, unsigned int channel)
348{
349 struct stm_drvdata *drvdata = container_of(stm_data,
350 struct stm_drvdata, stm);
351 if (!drvdata || !drvdata->csdev)
352 return;
353
354 coresight_disable(drvdata->csdev);
355}
356
357static phys_addr_t
358stm_mmio_addr(struct stm_data *stm_data, unsigned int master,
359 unsigned int channel, unsigned int nr_chans)
360{
361 struct stm_drvdata *drvdata = container_of(stm_data,
362 struct stm_drvdata, stm);
363 phys_addr_t addr;
364
365 addr = drvdata->chs.phys + channel * BYTES_PER_CHANNEL;
366
367 if (offset_in_page(addr) ||
368 offset_in_page(nr_chans * BYTES_PER_CHANNEL))
369 return 0;
370
371 return addr;
372}
373
374static long stm_generic_set_options(struct stm_data *stm_data,
375 unsigned int master,
376 unsigned int channel,
377 unsigned int nr_chans,
378 unsigned long options)
379{
380 struct stm_drvdata *drvdata = container_of(stm_data,
381 struct stm_drvdata, stm);
382 if (!(drvdata && local_read(&drvdata->mode)))
383 return -EINVAL;
384
385 if (channel >= drvdata->numsp)
386 return -EINVAL;
387
388 switch (options) {
389 case STM_OPTION_GUARANTEED:
390 set_bit(channel, drvdata->chs.guaranteed);
391 break;
392
393 case STM_OPTION_INVARIANT:
394 clear_bit(channel, drvdata->chs.guaranteed);
395 break;
396
397 default:
398 return -EINVAL;
399 }
400
401 return 0;
402}
403
404static ssize_t notrace stm_generic_packet(struct stm_data *stm_data,
405 unsigned int master,
406 unsigned int channel,
407 unsigned int packet,
408 unsigned int flags,
409 unsigned int size,
410 const unsigned char *payload)
411{
412 void __iomem *ch_addr;
413 struct stm_drvdata *drvdata = container_of(stm_data,
414 struct stm_drvdata, stm);
415
416 if (!(drvdata && local_read(&drvdata->mode)))
417 return -EACCES;
418
419 if (channel >= drvdata->numsp)
420 return -EINVAL;
421
422 ch_addr = stm_channel_addr(drvdata, channel);
423
424 flags = (flags == STP_PACKET_TIMESTAMPED) ? STM_FLAG_TIMESTAMPED : 0;
425 flags |= test_bit(channel, drvdata->chs.guaranteed) ?
426 STM_FLAG_GUARANTEED : 0;
427
428 if (size > drvdata->write_bytes)
429 size = drvdata->write_bytes;
430 else
431 size = rounddown_pow_of_two(size);
432
433 switch (packet) {
434 case STP_PACKET_FLAG:
435 ch_addr += stm_channel_off(STM_PKT_TYPE_FLAG, flags);
436
437 /*
438 * The generic STM core sets a size of '0' on flag packets.
439 * As such send a flag packet of size '1' and tell the
440 * core we did so.
441 */
442 stm_send(ch_addr, payload, 1, drvdata->write_bytes);
443 size = 1;
444 break;
445
446 case STP_PACKET_DATA:
447 ch_addr += stm_channel_off(STM_PKT_TYPE_DATA, flags);
448 stm_send(ch_addr, payload, size,
449 drvdata->write_bytes);
450 break;
451
452 default:
453 return -ENOTSUPP;
454 }
455
456 return size;
457}
458
459static ssize_t hwevent_enable_show(struct device *dev,
460 struct device_attribute *attr, char *buf)
461{
462 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
463 unsigned long val = drvdata->stmheer;
464
465 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
466}
467
468static ssize_t hwevent_enable_store(struct device *dev,
469 struct device_attribute *attr,
470 const char *buf, size_t size)
471{
472 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
473 unsigned long val;
474 int ret = 0;
475
476 ret = kstrtoul(buf, 16, &val);
477 if (ret)
478 return -EINVAL;
479
480 drvdata->stmheer = val;
481 /* HW event enable and trigger go hand in hand */
482 drvdata->stmheter = val;
483
484 return size;
485}
486static DEVICE_ATTR_RW(hwevent_enable);
487
488static ssize_t hwevent_select_show(struct device *dev,
489 struct device_attribute *attr, char *buf)
490{
491 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
492 unsigned long val = drvdata->stmhebsr;
493
494 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
495}
496
497static ssize_t hwevent_select_store(struct device *dev,
498 struct device_attribute *attr,
499 const char *buf, size_t size)
500{
501 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
502 unsigned long val;
503 int ret = 0;
504
505 ret = kstrtoul(buf, 16, &val);
506 if (ret)
507 return -EINVAL;
508
509 drvdata->stmhebsr = val;
510
511 return size;
512}
513static DEVICE_ATTR_RW(hwevent_select);
514
515static ssize_t port_select_show(struct device *dev,
516 struct device_attribute *attr, char *buf)
517{
518 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
519 unsigned long val;
520
521 if (!local_read(&drvdata->mode)) {
522 val = drvdata->stmspscr;
523 } else {
524 spin_lock(&drvdata->spinlock);
525 val = readl_relaxed(drvdata->base + STMSPSCR);
526 spin_unlock(&drvdata->spinlock);
527 }
528
529 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
530}
531
532static ssize_t port_select_store(struct device *dev,
533 struct device_attribute *attr,
534 const char *buf, size_t size)
535{
536 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
537 unsigned long val, stmsper;
538 int ret = 0;
539
540 ret = kstrtoul(buf, 16, &val);
541 if (ret)
542 return ret;
543
544 spin_lock(&drvdata->spinlock);
545 drvdata->stmspscr = val;
546
547 if (local_read(&drvdata->mode)) {
548 CS_UNLOCK(drvdata->base);
549 /* Process as per ARM's TRM recommendation */
550 stmsper = readl_relaxed(drvdata->base + STMSPER);
551 writel_relaxed(0x0, drvdata->base + STMSPER);
552 writel_relaxed(drvdata->stmspscr, drvdata->base + STMSPSCR);
553 writel_relaxed(stmsper, drvdata->base + STMSPER);
554 CS_LOCK(drvdata->base);
555 }
556 spin_unlock(&drvdata->spinlock);
557
558 return size;
559}
560static DEVICE_ATTR_RW(port_select);
561
562static ssize_t port_enable_show(struct device *dev,
563 struct device_attribute *attr, char *buf)
564{
565 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
566 unsigned long val;
567
568 if (!local_read(&drvdata->mode)) {
569 val = drvdata->stmsper;
570 } else {
571 spin_lock(&drvdata->spinlock);
572 val = readl_relaxed(drvdata->base + STMSPER);
573 spin_unlock(&drvdata->spinlock);
574 }
575
576 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
577}
578
579static ssize_t port_enable_store(struct device *dev,
580 struct device_attribute *attr,
581 const char *buf, size_t size)
582{
583 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
584 unsigned long val;
585 int ret = 0;
586
587 ret = kstrtoul(buf, 16, &val);
588 if (ret)
589 return ret;
590
591 spin_lock(&drvdata->spinlock);
592 drvdata->stmsper = val;
593
594 if (local_read(&drvdata->mode)) {
595 CS_UNLOCK(drvdata->base);
596 writel_relaxed(drvdata->stmsper, drvdata->base + STMSPER);
597 CS_LOCK(drvdata->base);
598 }
599 spin_unlock(&drvdata->spinlock);
600
601 return size;
602}
603static DEVICE_ATTR_RW(port_enable);
604
605static ssize_t traceid_show(struct device *dev,
606 struct device_attribute *attr, char *buf)
607{
608 unsigned long val;
609 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
610
611 val = drvdata->traceid;
612 return sprintf(buf, "%#lx\n", val);
613}
614
615static ssize_t traceid_store(struct device *dev,
616 struct device_attribute *attr,
617 const char *buf, size_t size)
618{
619 int ret;
620 unsigned long val;
621 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
622
623 ret = kstrtoul(buf, 16, &val);
624 if (ret)
625 return ret;
626
627 /* traceid field is 7bit wide on STM32 */
628 drvdata->traceid = val & 0x7f;
629 return size;
630}
631static DEVICE_ATTR_RW(traceid);
632
633#define coresight_stm_reg(name, offset) \
634 coresight_simple_reg32(struct stm_drvdata, name, offset)
635
636coresight_stm_reg(tcsr, STMTCSR);
637coresight_stm_reg(tsfreqr, STMTSFREQR);
638coresight_stm_reg(syncr, STMSYNCR);
639coresight_stm_reg(sper, STMSPER);
640coresight_stm_reg(spter, STMSPTER);
641coresight_stm_reg(privmaskr, STMPRIVMASKR);
642coresight_stm_reg(spscr, STMSPSCR);
643coresight_stm_reg(spmscr, STMSPMSCR);
644coresight_stm_reg(spfeat1r, STMSPFEAT1R);
645coresight_stm_reg(spfeat2r, STMSPFEAT2R);
646coresight_stm_reg(spfeat3r, STMSPFEAT3R);
647coresight_stm_reg(devid, CORESIGHT_DEVID);
648
649static struct attribute *coresight_stm_attrs[] = {
650 &dev_attr_hwevent_enable.attr,
651 &dev_attr_hwevent_select.attr,
652 &dev_attr_port_enable.attr,
653 &dev_attr_port_select.attr,
654 &dev_attr_traceid.attr,
655 NULL,
656};
657
658static struct attribute *coresight_stm_mgmt_attrs[] = {
659 &dev_attr_tcsr.attr,
660 &dev_attr_tsfreqr.attr,
661 &dev_attr_syncr.attr,
662 &dev_attr_sper.attr,
663 &dev_attr_spter.attr,
664 &dev_attr_privmaskr.attr,
665 &dev_attr_spscr.attr,
666 &dev_attr_spmscr.attr,
667 &dev_attr_spfeat1r.attr,
668 &dev_attr_spfeat2r.attr,
669 &dev_attr_spfeat3r.attr,
670 &dev_attr_devid.attr,
671 NULL,
672};
673
674static const struct attribute_group coresight_stm_group = {
675 .attrs = coresight_stm_attrs,
676};
677
678static const struct attribute_group coresight_stm_mgmt_group = {
679 .attrs = coresight_stm_mgmt_attrs,
680 .name = "mgmt",
681};
682
683static const struct attribute_group *coresight_stm_groups[] = {
684 &coresight_stm_group,
685 &coresight_stm_mgmt_group,
686 NULL,
687};
688
689#ifdef CONFIG_OF
690static int of_stm_get_stimulus_area(struct device *dev, struct resource *res)
691{
692 const char *name = NULL;
693 int index = 0, found = 0;
694 struct device_node *np = dev->of_node;
695
696 while (!of_property_read_string_index(np, "reg-names", index, &name)) {
697 if (strcmp("stm-stimulus-base", name)) {
698 index++;
699 continue;
700 }
701
702 /* We have a match and @index is where it's at */
703 found = 1;
704 break;
705 }
706
707 if (!found)
708 return -EINVAL;
709
710 return of_address_to_resource(np, index, res);
711}
712#else
713static inline int of_stm_get_stimulus_area(struct device *dev,
714 struct resource *res)
715{
716 return -ENOENT;
717}
718#endif
719
720#ifdef CONFIG_ACPI
721static int acpi_stm_get_stimulus_area(struct device *dev, struct resource *res)
722{
723 int rc;
724 bool found_base = false;
725 struct resource_entry *rent;
726 LIST_HEAD(res_list);
727
728 struct acpi_device *adev = ACPI_COMPANION(dev);
729
730 rc = acpi_dev_get_resources(adev, &res_list, NULL, NULL);
731 if (rc < 0)
732 return rc;
733
734 /*
735 * The stimulus base for STM device must be listed as the second memory
736 * resource, followed by the programming base address as described in
737 * "Section 2.3 Resources" in ACPI for CoreSightTM 1.0 Platform Design
738 * document (DEN0067).
739 */
740 rc = -ENOENT;
741 list_for_each_entry(rent, &res_list, node) {
742 if (resource_type(rent->res) != IORESOURCE_MEM)
743 continue;
744 if (found_base) {
745 *res = *rent->res;
746 rc = 0;
747 break;
748 }
749
750 found_base = true;
751 }
752
753 acpi_dev_free_resource_list(&res_list);
754 return rc;
755}
756#else
757static inline int acpi_stm_get_stimulus_area(struct device *dev,
758 struct resource *res)
759{
760 return -ENOENT;
761}
762#endif
763
764static int stm_get_stimulus_area(struct device *dev, struct resource *res)
765{
766 struct fwnode_handle *fwnode = dev_fwnode(dev);
767
768 if (is_of_node(fwnode))
769 return of_stm_get_stimulus_area(dev, res);
770 else if (is_acpi_node(fwnode))
771 return acpi_stm_get_stimulus_area(dev, res);
772 return -ENOENT;
773}
774
775static u32 stm_fundamental_data_size(struct stm_drvdata *drvdata)
776{
777 u32 stmspfeat2r;
778
779 if (!IS_ENABLED(CONFIG_64BIT))
780 return 4;
781
782 stmspfeat2r = readl_relaxed(drvdata->base + STMSPFEAT2R);
783
784 /*
785 * bit[15:12] represents the fundamental data size
786 * 0 - 32-bit data
787 * 1 - 64-bit data
788 */
789 return BMVAL(stmspfeat2r, 12, 15) ? 8 : 4;
790}
791
792static u32 stm_num_stimulus_port(struct stm_drvdata *drvdata)
793{
794 u32 numsp;
795
796 numsp = readl_relaxed(drvdata->base + CORESIGHT_DEVID);
797 /*
798 * NUMPS in STMDEVID is 17 bit long and if equal to 0x0,
799 * 32 stimulus ports are supported.
800 */
801 numsp &= 0x1ffff;
802 if (!numsp)
803 numsp = STM_32_CHANNEL;
804 return numsp;
805}
806
807static void stm_init_default_data(struct stm_drvdata *drvdata)
808{
809 /* Don't use port selection */
810 drvdata->stmspscr = 0x0;
811 /*
812 * Enable all channel regardless of their number. When port
813 * selection isn't used (see above) STMSPER applies to all
814 * 32 channel group available, hence setting all 32 bits to 1
815 */
816 drvdata->stmsper = ~0x0;
817
818 /*
819 * The trace ID value for *ETM* tracers start at CPU_ID * 2 + 0x10 and
820 * anything equal to or higher than 0x70 is reserved. Since 0x00 is
821 * also reserved the STM trace ID needs to be higher than 0x00 and
822 * lowner than 0x10.
823 */
824 drvdata->traceid = 0x1;
825
826 /* Set invariant transaction timing on all channels */
827 bitmap_clear(drvdata->chs.guaranteed, 0, drvdata->numsp);
828}
829
830static void stm_init_generic_data(struct stm_drvdata *drvdata,
831 const char *name)
832{
833 drvdata->stm.name = name;
834
835 /*
836 * MasterIDs are assigned at HW design phase. As such the core is
837 * using a single master for interaction with this device.
838 */
839 drvdata->stm.sw_start = 1;
840 drvdata->stm.sw_end = 1;
841 drvdata->stm.hw_override = true;
842 drvdata->stm.sw_nchannels = drvdata->numsp;
843 drvdata->stm.sw_mmiosz = BYTES_PER_CHANNEL;
844 drvdata->stm.packet = stm_generic_packet;
845 drvdata->stm.mmio_addr = stm_mmio_addr;
846 drvdata->stm.link = stm_generic_link;
847 drvdata->stm.unlink = stm_generic_unlink;
848 drvdata->stm.set_options = stm_generic_set_options;
849}
850
851static int stm_probe(struct amba_device *adev, const struct amba_id *id)
852{
853 int ret;
854 void __iomem *base;
855 unsigned long *guaranteed;
856 struct device *dev = &adev->dev;
857 struct coresight_platform_data *pdata = NULL;
858 struct stm_drvdata *drvdata;
859 struct resource *res = &adev->res;
860 struct resource ch_res;
861 size_t bitmap_size;
862 struct coresight_desc desc = { 0 };
863
864 desc.name = coresight_alloc_device_name(&stm_devs, dev);
865 if (!desc.name)
866 return -ENOMEM;
867
868 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
869 if (!drvdata)
870 return -ENOMEM;
871
872 drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */
873 if (!IS_ERR(drvdata->atclk)) {
874 ret = clk_prepare_enable(drvdata->atclk);
875 if (ret)
876 return ret;
877 }
878 dev_set_drvdata(dev, drvdata);
879
880 base = devm_ioremap_resource(dev, res);
881 if (IS_ERR(base))
882 return PTR_ERR(base);
883 drvdata->base = base;
884
885 ret = stm_get_stimulus_area(dev, &ch_res);
886 if (ret)
887 return ret;
888 drvdata->chs.phys = ch_res.start;
889
890 base = devm_ioremap_resource(dev, &ch_res);
891 if (IS_ERR(base))
892 return PTR_ERR(base);
893 drvdata->chs.base = base;
894
895 drvdata->write_bytes = stm_fundamental_data_size(drvdata);
896
897 if (boot_nr_channel)
898 drvdata->numsp = boot_nr_channel;
899 else
900 drvdata->numsp = stm_num_stimulus_port(drvdata);
901
902 bitmap_size = BITS_TO_LONGS(drvdata->numsp) * sizeof(long);
903
904 guaranteed = devm_kzalloc(dev, bitmap_size, GFP_KERNEL);
905 if (!guaranteed)
906 return -ENOMEM;
907 drvdata->chs.guaranteed = guaranteed;
908
909 spin_lock_init(&drvdata->spinlock);
910
911 stm_init_default_data(drvdata);
912 stm_init_generic_data(drvdata, desc.name);
913
914 if (stm_register_device(dev, &drvdata->stm, THIS_MODULE)) {
915 dev_info(dev,
916 "%s : stm_register_device failed, probing deferred\n",
917 desc.name);
918 return -EPROBE_DEFER;
919 }
920
921 pdata = coresight_get_platform_data(dev);
922 if (IS_ERR(pdata)) {
923 ret = PTR_ERR(pdata);
924 goto stm_unregister;
925 }
926 adev->dev.platform_data = pdata;
927
928 desc.type = CORESIGHT_DEV_TYPE_SOURCE;
929 desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE;
930 desc.ops = &stm_cs_ops;
931 desc.pdata = pdata;
932 desc.dev = dev;
933 desc.groups = coresight_stm_groups;
934 drvdata->csdev = coresight_register(&desc);
935 if (IS_ERR(drvdata->csdev)) {
936 ret = PTR_ERR(drvdata->csdev);
937 goto stm_unregister;
938 }
939
940 pm_runtime_put(&adev->dev);
941
942 dev_info(&drvdata->csdev->dev, "%s initialized\n",
943 (char *)coresight_get_uci_data(id));
944 return 0;
945
946stm_unregister:
947 stm_unregister_device(&drvdata->stm);
948 return ret;
949}
950
951#ifdef CONFIG_PM
952static int stm_runtime_suspend(struct device *dev)
953{
954 struct stm_drvdata *drvdata = dev_get_drvdata(dev);
955
956 if (drvdata && !IS_ERR(drvdata->atclk))
957 clk_disable_unprepare(drvdata->atclk);
958
959 return 0;
960}
961
962static int stm_runtime_resume(struct device *dev)
963{
964 struct stm_drvdata *drvdata = dev_get_drvdata(dev);
965
966 if (drvdata && !IS_ERR(drvdata->atclk))
967 clk_prepare_enable(drvdata->atclk);
968
969 return 0;
970}
971#endif
972
973static const struct dev_pm_ops stm_dev_pm_ops = {
974 SET_RUNTIME_PM_OPS(stm_runtime_suspend, stm_runtime_resume, NULL)
975};
976
977static const struct amba_id stm_ids[] = {
978 CS_AMBA_ID_DATA(0x000bb962, "STM32"),
979 CS_AMBA_ID_DATA(0x000bb963, "STM500"),
980 { 0, 0},
981};
982
983static struct amba_driver stm_driver = {
984 .drv = {
985 .name = "coresight-stm",
986 .owner = THIS_MODULE,
987 .pm = &stm_dev_pm_ops,
988 .suppress_bind_attrs = true,
989 },
990 .probe = stm_probe,
991 .id_table = stm_ids,
992};
993
994builtin_amba_driver(stm_driver);