1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Tegra host1x Register Offsets for Tegra194
  4 *
  5 * Copyright (c) 2018 NVIDIA Corporation.
  6 */
  7
  8#ifndef __HOST1X_HOST1X07_HARDWARE_H
  9#define __HOST1X_HOST1X07_HARDWARE_H
 10
 11#include <linux/types.h>
 12#include <linux/bitops.h>
 13
 14#include "hw_host1x07_channel.h"
 15#include "hw_host1x07_uclass.h"
 16#include "hw_host1x07_vm.h"
 17#include "hw_host1x07_hypervisor.h"
 18
 19static inline u32 host1x_class_host_wait_syncpt(
 20	unsigned indx, unsigned threshold)
 21{
 22	return host1x_uclass_wait_syncpt_indx_f(indx)
 23		| host1x_uclass_wait_syncpt_thresh_f(threshold);
 24}
 25
 26static inline u32 host1x_class_host_load_syncpt_base(
 27	unsigned indx, unsigned threshold)
 28{
 29	return host1x_uclass_load_syncpt_base_base_indx_f(indx)
 30		| host1x_uclass_load_syncpt_base_value_f(threshold);
 31}
 32
 33static inline u32 host1x_class_host_wait_syncpt_base(
 34	unsigned indx, unsigned base_indx, unsigned offset)
 35{
 36	return host1x_uclass_wait_syncpt_base_indx_f(indx)
 37		| host1x_uclass_wait_syncpt_base_base_indx_f(base_indx)
 38		| host1x_uclass_wait_syncpt_base_offset_f(offset);
 39}
 40
 41static inline u32 host1x_class_host_incr_syncpt_base(
 42	unsigned base_indx, unsigned offset)
 43{
 44	return host1x_uclass_incr_syncpt_base_base_indx_f(base_indx)
 45		| host1x_uclass_incr_syncpt_base_offset_f(offset);
 46}
 47
 48static inline u32 host1x_class_host_incr_syncpt(
 49	unsigned cond, unsigned indx)
 50{
 51	return host1x_uclass_incr_syncpt_cond_f(cond)
 52		| host1x_uclass_incr_syncpt_indx_f(indx);
 53}
 54
 55static inline u32 host1x_class_host_indoff_reg_write(
 56	unsigned mod_id, unsigned offset, bool auto_inc)
 57{
 58	u32 v = host1x_uclass_indoff_indbe_f(0xf)
 59		| host1x_uclass_indoff_indmodid_f(mod_id)
 60		| host1x_uclass_indoff_indroffset_f(offset);
 61	if (auto_inc)
 62		v |= host1x_uclass_indoff_autoinc_f(1);
 63	return v;
 64}
 65
 66static inline u32 host1x_class_host_indoff_reg_read(
 67	unsigned mod_id, unsigned offset, bool auto_inc)
 68{
 69	u32 v = host1x_uclass_indoff_indmodid_f(mod_id)
 70		| host1x_uclass_indoff_indroffset_f(offset)
 71		| host1x_uclass_indoff_rwn_read_v();
 72	if (auto_inc)
 73		v |= host1x_uclass_indoff_autoinc_f(1);
 74	return v;
 75}
 76
 77/* cdma opcodes */
 78static inline u32 host1x_opcode_setclass(
 79	unsigned class_id, unsigned offset, unsigned mask)
 80{
 81	return (0 << 28) | (offset << 16) | (class_id << 6) | mask;
 82}
 83
 84static inline u32 host1x_opcode_incr(unsigned offset, unsigned count)
 85{
 86	return (1 << 28) | (offset << 16) | count;
 87}
 88
 89static inline u32 host1x_opcode_nonincr(unsigned offset, unsigned count)
 90{
 91	return (2 << 28) | (offset << 16) | count;
 92}
 93
 94static inline u32 host1x_opcode_mask(unsigned offset, unsigned mask)
 95{
 96	return (3 << 28) | (offset << 16) | mask;
 97}
 98
 99static inline u32 host1x_opcode_imm(unsigned offset, unsigned value)
100{
101	return (4 << 28) | (offset << 16) | value;
102}
103
104static inline u32 host1x_opcode_imm_incr_syncpt(unsigned cond, unsigned indx)
105{
106	return host1x_opcode_imm(host1x_uclass_incr_syncpt_r(),
107		host1x_class_host_incr_syncpt(cond, indx));
108}
109
110static inline u32 host1x_opcode_restart(unsigned address)
111{
112	return (5 << 28) | (address >> 4);
113}
114
115static inline u32 host1x_opcode_gather(unsigned count)
116{
117	return (6 << 28) | count;
118}
119
120static inline u32 host1x_opcode_gather_nonincr(unsigned offset,	unsigned count)
121{
122	return (6 << 28) | (offset << 16) | BIT(15) | count;
123}
124
125static inline u32 host1x_opcode_gather_incr(unsigned offset, unsigned count)
126{
127	return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count;
128}
129
130static inline u32 host1x_opcode_gather_wide(unsigned count)
131{
132	return (12 << 28) | count;
133}
134
135#define HOST1X_OPCODE_NOP host1x_opcode_nonincr(0, 0)
136
137#endif