1/* SPDX-License-Identifier: GPL-2.0 */
  2/*
  3 * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
  4 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
  5 */
  6
  7#ifndef __TIDSS_DISPC_H__
  8#define __TIDSS_DISPC_H__
  9
 10#include "tidss_drv.h"
 11
 12struct dispc_device;
 13
 14struct drm_crtc_state;
 15
 16enum tidss_gamma_type { TIDSS_GAMMA_8BIT, TIDSS_GAMMA_10BIT };
 17
 18struct tidss_vp_feat {
 19	struct tidss_vp_color_feat {
 20		u32 gamma_size;
 21		enum tidss_gamma_type gamma_type;
 22		bool has_ctm;
 23	} color;
 24};
 25
 26struct tidss_plane_feat {
 27	struct tidss_plane_color_feat {
 28		u32 encodings;
 29		u32 ranges;
 30		enum drm_color_encoding default_encoding;
 31		enum drm_color_range default_range;
 32	} color;
 33	struct tidss_plane_blend_feat {
 34		bool global_alpha;
 35	} blend;
 36};
 37
 38struct dispc_features_scaling {
 39	u32 in_width_max_5tap_rgb;
 40	u32 in_width_max_3tap_rgb;
 41	u32 in_width_max_5tap_yuv;
 42	u32 in_width_max_3tap_yuv;
 43	u32 upscale_limit;
 44	u32 downscale_limit_5tap;
 45	u32 downscale_limit_3tap;
 46	u32 xinc_max;
 47};
 48
 49enum dispc_vp_bus_type {
 50	DISPC_VP_DPI,		/* DPI output */
 51	DISPC_VP_OLDI,		/* OLDI (LVDS) output */
 52	DISPC_VP_INTERNAL,	/* SoC internal routing */
 53	DISPC_VP_MAX_BUS_TYPE,
 54};
 55
 56enum dispc_dss_subrevision {
 57	DISPC_K2G,
 58	DISPC_AM65X,
 59	DISPC_J721E,
 60};
 61
 62struct dispc_features {
 63	int min_pclk_khz;
 64	int max_pclk_khz[DISPC_VP_MAX_BUS_TYPE];
 65
 66	struct dispc_features_scaling scaling;
 67
 68	enum dispc_dss_subrevision subrev;
 69
 70	const char *common;
 71	const u16 *common_regs;
 72	u32 num_vps;
 73	const char *vp_name[TIDSS_MAX_PORTS]; /* Should match dt reg names */
 74	const char *ovr_name[TIDSS_MAX_PORTS]; /* Should match dt reg names */
 75	const char *vpclk_name[TIDSS_MAX_PORTS]; /* Should match dt clk names */
 76	const enum dispc_vp_bus_type vp_bus_type[TIDSS_MAX_PORTS];
 77	struct tidss_vp_feat vp_feat;
 78	u32 num_planes;
 79	const char *vid_name[TIDSS_MAX_PLANES]; /* Should match dt reg names */
 80	bool vid_lite[TIDSS_MAX_PLANES];
 81	u32 vid_order[TIDSS_MAX_PLANES];
 82};
 83
 84extern const struct dispc_features dispc_k2g_feats;
 85extern const struct dispc_features dispc_am65x_feats;
 86extern const struct dispc_features dispc_j721e_feats;
 87
 88void dispc_set_irqenable(struct dispc_device *dispc, dispc_irq_t mask);
 89dispc_irq_t dispc_read_and_clear_irqstatus(struct dispc_device *dispc);
 90
 91void dispc_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane,
 92			 u32 hw_videoport, u32 x, u32 y, u32 layer);
 93void dispc_ovr_enable_layer(struct dispc_device *dispc,
 94			    u32 hw_videoport, u32 layer, bool enable);
 95
 96void dispc_vp_prepare(struct dispc_device *dispc, u32 hw_videoport,
 97		      const struct drm_crtc_state *state);
 98void dispc_vp_enable(struct dispc_device *dispc, u32 hw_videoport,
 99		     const struct drm_crtc_state *state);
100void dispc_vp_disable(struct dispc_device *dispc, u32 hw_videoport);
101void dispc_vp_unprepare(struct dispc_device *dispc, u32 hw_videoport);
102bool dispc_vp_go_busy(struct dispc_device *dispc, u32 hw_videoport);
103void dispc_vp_go(struct dispc_device *dispc, u32 hw_videoport);
104int dispc_vp_bus_check(struct dispc_device *dispc, u32 hw_videoport,
105		       const struct drm_crtc_state *state);
106enum drm_mode_status dispc_vp_mode_valid(struct dispc_device *dispc,
107					 u32 hw_videoport,
108					 const struct drm_display_mode *mode);
109int dispc_vp_enable_clk(struct dispc_device *dispc, u32 hw_videoport);
110void dispc_vp_disable_clk(struct dispc_device *dispc, u32 hw_videoport);
111int dispc_vp_set_clk_rate(struct dispc_device *dispc, u32 hw_videoport,
112			  unsigned long rate);
113void dispc_vp_setup(struct dispc_device *dispc, u32 hw_videoport,
114		    const struct drm_crtc_state *state, bool newmodeset);
115
116int dispc_runtime_suspend(struct dispc_device *dispc);
117int dispc_runtime_resume(struct dispc_device *dispc);
118
119int dispc_plane_check(struct dispc_device *dispc, u32 hw_plane,
120		      const struct drm_plane_state *state,
121		      u32 hw_videoport);
122int dispc_plane_setup(struct dispc_device *dispc, u32 hw_plane,
123		      const struct drm_plane_state *state,
124		      u32 hw_videoport);
125int dispc_plane_enable(struct dispc_device *dispc, u32 hw_plane, bool enable);
126const u32 *dispc_plane_formats(struct dispc_device *dispc, unsigned int *len);
127
128int dispc_init(struct tidss_device *tidss);
129void dispc_remove(struct tidss_device *tidss);
130
131#endif