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1/*
2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#ifndef TEGRA_DC_H
11#define TEGRA_DC_H 1
12
13#define DC_CMD_GENERAL_INCR_SYNCPT 0x000
14#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL 0x001
15#define SYNCPT_CNTRL_NO_STALL (1 << 8)
16#define SYNCPT_CNTRL_SOFT_RESET (1 << 0)
17#define DC_CMD_GENERAL_INCR_SYNCPT_ERROR 0x002
18#define DC_CMD_WIN_A_INCR_SYNCPT 0x008
19#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL 0x009
20#define DC_CMD_WIN_A_INCR_SYNCPT_ERROR 0x00a
21#define DC_CMD_WIN_B_INCR_SYNCPT 0x010
22#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL 0x011
23#define DC_CMD_WIN_B_INCR_SYNCPT_ERROR 0x012
24#define DC_CMD_WIN_C_INCR_SYNCPT 0x018
25#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL 0x019
26#define DC_CMD_WIN_C_INCR_SYNCPT_ERROR 0x01a
27#define DC_CMD_CONT_SYNCPT_VSYNC 0x028
28#define SYNCPT_VSYNC_ENABLE (1 << 8)
29#define DC_CMD_DISPLAY_COMMAND_OPTION0 0x031
30#define DC_CMD_DISPLAY_COMMAND 0x032
31#define DISP_CTRL_MODE_STOP (0 << 5)
32#define DISP_CTRL_MODE_C_DISPLAY (1 << 5)
33#define DISP_CTRL_MODE_NC_DISPLAY (2 << 5)
34#define DISP_CTRL_MODE_MASK (3 << 5)
35#define DC_CMD_SIGNAL_RAISE 0x033
36#define DC_CMD_DISPLAY_POWER_CONTROL 0x036
37#define PW0_ENABLE (1 << 0)
38#define PW1_ENABLE (1 << 2)
39#define PW2_ENABLE (1 << 4)
40#define PW3_ENABLE (1 << 6)
41#define PW4_ENABLE (1 << 8)
42#define PM0_ENABLE (1 << 16)
43#define PM1_ENABLE (1 << 18)
44
45#define DC_CMD_INT_STATUS 0x037
46#define DC_CMD_INT_MASK 0x038
47#define DC_CMD_INT_ENABLE 0x039
48#define DC_CMD_INT_TYPE 0x03a
49#define DC_CMD_INT_POLARITY 0x03b
50#define CTXSW_INT (1 << 0)
51#define FRAME_END_INT (1 << 1)
52#define VBLANK_INT (1 << 2)
53#define WIN_A_UF_INT (1 << 8)
54#define WIN_B_UF_INT (1 << 9)
55#define WIN_C_UF_INT (1 << 10)
56#define WIN_A_OF_INT (1 << 14)
57#define WIN_B_OF_INT (1 << 15)
58#define WIN_C_OF_INT (1 << 16)
59
60#define DC_CMD_SIGNAL_RAISE1 0x03c
61#define DC_CMD_SIGNAL_RAISE2 0x03d
62#define DC_CMD_SIGNAL_RAISE3 0x03e
63
64#define DC_CMD_STATE_ACCESS 0x040
65#define READ_MUX (1 << 0)
66#define WRITE_MUX (1 << 2)
67
68#define DC_CMD_STATE_CONTROL 0x041
69#define GENERAL_ACT_REQ (1 << 0)
70#define WIN_A_ACT_REQ (1 << 1)
71#define WIN_B_ACT_REQ (1 << 2)
72#define WIN_C_ACT_REQ (1 << 3)
73#define CURSOR_ACT_REQ (1 << 7)
74#define GENERAL_UPDATE (1 << 8)
75#define WIN_A_UPDATE (1 << 9)
76#define WIN_B_UPDATE (1 << 10)
77#define WIN_C_UPDATE (1 << 11)
78#define CURSOR_UPDATE (1 << 15)
79#define NC_HOST_TRIG (1 << 24)
80
81#define DC_CMD_DISPLAY_WINDOW_HEADER 0x042
82#define WINDOW_A_SELECT (1 << 4)
83#define WINDOW_B_SELECT (1 << 5)
84#define WINDOW_C_SELECT (1 << 6)
85
86#define DC_CMD_REG_ACT_CONTROL 0x043
87
88#define DC_COM_CRC_CONTROL 0x300
89#define DC_COM_CRC_CONTROL_ALWAYS (1 << 3)
90#define DC_COM_CRC_CONTROL_FULL_FRAME (0 << 2)
91#define DC_COM_CRC_CONTROL_ACTIVE_DATA (1 << 2)
92#define DC_COM_CRC_CONTROL_WAIT (1 << 1)
93#define DC_COM_CRC_CONTROL_ENABLE (1 << 0)
94#define DC_COM_CRC_CHECKSUM 0x301
95#define DC_COM_PIN_OUTPUT_ENABLE(x) (0x302 + (x))
96#define DC_COM_PIN_OUTPUT_POLARITY(x) (0x306 + (x))
97#define LVS_OUTPUT_POLARITY_LOW (1 << 28)
98#define LHS_OUTPUT_POLARITY_LOW (1 << 30)
99#define DC_COM_PIN_OUTPUT_DATA(x) (0x30a + (x))
100#define DC_COM_PIN_INPUT_ENABLE(x) (0x30e + (x))
101#define DC_COM_PIN_INPUT_DATA(x) (0x312 + (x))
102#define DC_COM_PIN_OUTPUT_SELECT(x) (0x314 + (x))
103
104#define DC_COM_PIN_MISC_CONTROL 0x31b
105#define DC_COM_PIN_PM0_CONTROL 0x31c
106#define DC_COM_PIN_PM0_DUTY_CYCLE 0x31d
107#define DC_COM_PIN_PM1_CONTROL 0x31e
108#define DC_COM_PIN_PM1_DUTY_CYCLE 0x31f
109
110#define DC_COM_SPI_CONTROL 0x320
111#define DC_COM_SPI_START_BYTE 0x321
112#define DC_COM_HSPI_WRITE_DATA_AB 0x322
113#define DC_COM_HSPI_WRITE_DATA_CD 0x323
114#define DC_COM_HSPI_CS_DC 0x324
115#define DC_COM_SCRATCH_REGISTER_A 0x325
116#define DC_COM_SCRATCH_REGISTER_B 0x326
117#define DC_COM_GPIO_CTRL 0x327
118#define DC_COM_GPIO_DEBOUNCE_COUNTER 0x328
119#define DC_COM_CRC_CHECKSUM_LATCHED 0x329
120
121#define DC_DISP_DISP_SIGNAL_OPTIONS0 0x400
122#define H_PULSE0_ENABLE (1 << 8)
123#define H_PULSE1_ENABLE (1 << 10)
124#define H_PULSE2_ENABLE (1 << 12)
125
126#define DC_DISP_DISP_SIGNAL_OPTIONS1 0x401
127
128#define DC_DISP_DISP_WIN_OPTIONS 0x402
129#define HDMI_ENABLE (1 << 30)
130#define DSI_ENABLE (1 << 29)
131#define SOR1_TIMING_CYA (1 << 27)
132#define SOR1_ENABLE (1 << 26)
133#define SOR_ENABLE (1 << 25)
134#define CURSOR_ENABLE (1 << 16)
135
136#define DC_DISP_DISP_MEM_HIGH_PRIORITY 0x403
137#define CURSOR_THRESHOLD(x) (((x) & 0x03) << 24)
138#define WINDOW_A_THRESHOLD(x) (((x) & 0x7f) << 16)
139#define WINDOW_B_THRESHOLD(x) (((x) & 0x7f) << 8)
140#define WINDOW_C_THRESHOLD(x) (((x) & 0xff) << 0)
141
142#define DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER 0x404
143#define CURSOR_DELAY(x) (((x) & 0x3f) << 24)
144#define WINDOW_A_DELAY(x) (((x) & 0x3f) << 16)
145#define WINDOW_B_DELAY(x) (((x) & 0x3f) << 8)
146#define WINDOW_C_DELAY(x) (((x) & 0x3f) << 0)
147
148#define DC_DISP_DISP_TIMING_OPTIONS 0x405
149#define VSYNC_H_POSITION(x) ((x) & 0xfff)
150
151#define DC_DISP_REF_TO_SYNC 0x406
152#define DC_DISP_SYNC_WIDTH 0x407
153#define DC_DISP_BACK_PORCH 0x408
154#define DC_DISP_ACTIVE 0x409
155#define DC_DISP_FRONT_PORCH 0x40a
156#define DC_DISP_H_PULSE0_CONTROL 0x40b
157#define DC_DISP_H_PULSE0_POSITION_A 0x40c
158#define DC_DISP_H_PULSE0_POSITION_B 0x40d
159#define DC_DISP_H_PULSE0_POSITION_C 0x40e
160#define DC_DISP_H_PULSE0_POSITION_D 0x40f
161#define DC_DISP_H_PULSE1_CONTROL 0x410
162#define DC_DISP_H_PULSE1_POSITION_A 0x411
163#define DC_DISP_H_PULSE1_POSITION_B 0x412
164#define DC_DISP_H_PULSE1_POSITION_C 0x413
165#define DC_DISP_H_PULSE1_POSITION_D 0x414
166#define DC_DISP_H_PULSE2_CONTROL 0x415
167#define DC_DISP_H_PULSE2_POSITION_A 0x416
168#define DC_DISP_H_PULSE2_POSITION_B 0x417
169#define DC_DISP_H_PULSE2_POSITION_C 0x418
170#define DC_DISP_H_PULSE2_POSITION_D 0x419
171#define DC_DISP_V_PULSE0_CONTROL 0x41a
172#define DC_DISP_V_PULSE0_POSITION_A 0x41b
173#define DC_DISP_V_PULSE0_POSITION_B 0x41c
174#define DC_DISP_V_PULSE0_POSITION_C 0x41d
175#define DC_DISP_V_PULSE1_CONTROL 0x41e
176#define DC_DISP_V_PULSE1_POSITION_A 0x41f
177#define DC_DISP_V_PULSE1_POSITION_B 0x420
178#define DC_DISP_V_PULSE1_POSITION_C 0x421
179#define DC_DISP_V_PULSE2_CONTROL 0x422
180#define DC_DISP_V_PULSE2_POSITION_A 0x423
181#define DC_DISP_V_PULSE3_CONTROL 0x424
182#define DC_DISP_V_PULSE3_POSITION_A 0x425
183#define DC_DISP_M0_CONTROL 0x426
184#define DC_DISP_M1_CONTROL 0x427
185#define DC_DISP_DI_CONTROL 0x428
186#define DC_DISP_PP_CONTROL 0x429
187#define DC_DISP_PP_SELECT_A 0x42a
188#define DC_DISP_PP_SELECT_B 0x42b
189#define DC_DISP_PP_SELECT_C 0x42c
190#define DC_DISP_PP_SELECT_D 0x42d
191
192#define PULSE_MODE_NORMAL (0 << 3)
193#define PULSE_MODE_ONE_CLOCK (1 << 3)
194#define PULSE_POLARITY_HIGH (0 << 4)
195#define PULSE_POLARITY_LOW (1 << 4)
196#define PULSE_QUAL_ALWAYS (0 << 6)
197#define PULSE_QUAL_VACTIVE (2 << 6)
198#define PULSE_QUAL_VACTIVE1 (3 << 6)
199#define PULSE_LAST_START_A (0 << 8)
200#define PULSE_LAST_END_A (1 << 8)
201#define PULSE_LAST_START_B (2 << 8)
202#define PULSE_LAST_END_B (3 << 8)
203#define PULSE_LAST_START_C (4 << 8)
204#define PULSE_LAST_END_C (5 << 8)
205#define PULSE_LAST_START_D (6 << 8)
206#define PULSE_LAST_END_D (7 << 8)
207
208#define PULSE_START(x) (((x) & 0xfff) << 0)
209#define PULSE_END(x) (((x) & 0xfff) << 16)
210
211#define DC_DISP_DISP_CLOCK_CONTROL 0x42e
212#define PIXEL_CLK_DIVIDER_PCD1 (0 << 8)
213#define PIXEL_CLK_DIVIDER_PCD1H (1 << 8)
214#define PIXEL_CLK_DIVIDER_PCD2 (2 << 8)
215#define PIXEL_CLK_DIVIDER_PCD3 (3 << 8)
216#define PIXEL_CLK_DIVIDER_PCD4 (4 << 8)
217#define PIXEL_CLK_DIVIDER_PCD6 (5 << 8)
218#define PIXEL_CLK_DIVIDER_PCD8 (6 << 8)
219#define PIXEL_CLK_DIVIDER_PCD9 (7 << 8)
220#define PIXEL_CLK_DIVIDER_PCD12 (8 << 8)
221#define PIXEL_CLK_DIVIDER_PCD16 (9 << 8)
222#define PIXEL_CLK_DIVIDER_PCD18 (10 << 8)
223#define PIXEL_CLK_DIVIDER_PCD24 (11 << 8)
224#define PIXEL_CLK_DIVIDER_PCD13 (12 << 8)
225#define SHIFT_CLK_DIVIDER(x) ((x) & 0xff)
226
227#define DC_DISP_DISP_INTERFACE_CONTROL 0x42f
228#define DISP_DATA_FORMAT_DF1P1C (0 << 0)
229#define DISP_DATA_FORMAT_DF1P2C24B (1 << 0)
230#define DISP_DATA_FORMAT_DF1P2C18B (2 << 0)
231#define DISP_DATA_FORMAT_DF1P2C16B (3 << 0)
232#define DISP_DATA_FORMAT_DF2S (4 << 0)
233#define DISP_DATA_FORMAT_DF3S (5 << 0)
234#define DISP_DATA_FORMAT_DFSPI (6 << 0)
235#define DISP_DATA_FORMAT_DF1P3C24B (7 << 0)
236#define DISP_DATA_FORMAT_DF1P3C18B (8 << 0)
237#define DISP_ALIGNMENT_MSB (0 << 8)
238#define DISP_ALIGNMENT_LSB (1 << 8)
239#define DISP_ORDER_RED_BLUE (0 << 9)
240#define DISP_ORDER_BLUE_RED (1 << 9)
241
242#define DC_DISP_DISP_COLOR_CONTROL 0x430
243#define BASE_COLOR_SIZE666 (0 << 0)
244#define BASE_COLOR_SIZE111 (1 << 0)
245#define BASE_COLOR_SIZE222 (2 << 0)
246#define BASE_COLOR_SIZE333 (3 << 0)
247#define BASE_COLOR_SIZE444 (4 << 0)
248#define BASE_COLOR_SIZE555 (5 << 0)
249#define BASE_COLOR_SIZE565 (6 << 0)
250#define BASE_COLOR_SIZE332 (7 << 0)
251#define BASE_COLOR_SIZE888 (8 << 0)
252#define DITHER_CONTROL_MASK (3 << 8)
253#define DITHER_CONTROL_DISABLE (0 << 8)
254#define DITHER_CONTROL_ORDERED (2 << 8)
255#define DITHER_CONTROL_ERRDIFF (3 << 8)
256#define BASE_COLOR_SIZE_MASK (0xf << 0)
257#define BASE_COLOR_SIZE_666 (0 << 0)
258#define BASE_COLOR_SIZE_111 (1 << 0)
259#define BASE_COLOR_SIZE_222 (2 << 0)
260#define BASE_COLOR_SIZE_333 (3 << 0)
261#define BASE_COLOR_SIZE_444 (4 << 0)
262#define BASE_COLOR_SIZE_555 (5 << 0)
263#define BASE_COLOR_SIZE_565 (6 << 0)
264#define BASE_COLOR_SIZE_332 (7 << 0)
265#define BASE_COLOR_SIZE_888 (8 << 0)
266
267#define DC_DISP_SHIFT_CLOCK_OPTIONS 0x431
268#define SC1_H_QUALIFIER_NONE (1 << 16)
269#define SC0_H_QUALIFIER_NONE (1 << 0)
270
271#define DC_DISP_DATA_ENABLE_OPTIONS 0x432
272#define DE_SELECT_ACTIVE_BLANK (0 << 0)
273#define DE_SELECT_ACTIVE (1 << 0)
274#define DE_SELECT_ACTIVE_IS (2 << 0)
275#define DE_CONTROL_ONECLK (0 << 2)
276#define DE_CONTROL_NORMAL (1 << 2)
277#define DE_CONTROL_EARLY_EXT (2 << 2)
278#define DE_CONTROL_EARLY (3 << 2)
279#define DE_CONTROL_ACTIVE_BLANK (4 << 2)
280
281#define DC_DISP_SERIAL_INTERFACE_OPTIONS 0x433
282#define DC_DISP_LCD_SPI_OPTIONS 0x434
283#define DC_DISP_BORDER_COLOR 0x435
284#define DC_DISP_COLOR_KEY0_LOWER 0x436
285#define DC_DISP_COLOR_KEY0_UPPER 0x437
286#define DC_DISP_COLOR_KEY1_LOWER 0x438
287#define DC_DISP_COLOR_KEY1_UPPER 0x439
288
289#define DC_DISP_CURSOR_FOREGROUND 0x43c
290#define DC_DISP_CURSOR_BACKGROUND 0x43d
291
292#define DC_DISP_CURSOR_START_ADDR 0x43e
293#define CURSOR_CLIP_DISPLAY (0 << 28)
294#define CURSOR_CLIP_WIN_A (1 << 28)
295#define CURSOR_CLIP_WIN_B (2 << 28)
296#define CURSOR_CLIP_WIN_C (3 << 28)
297#define CURSOR_SIZE_32x32 (0 << 24)
298#define CURSOR_SIZE_64x64 (1 << 24)
299#define CURSOR_SIZE_128x128 (2 << 24)
300#define CURSOR_SIZE_256x256 (3 << 24)
301#define DC_DISP_CURSOR_START_ADDR_NS 0x43f
302
303#define DC_DISP_CURSOR_POSITION 0x440
304#define DC_DISP_CURSOR_POSITION_NS 0x441
305
306#define DC_DISP_INIT_SEQ_CONTROL 0x442
307#define DC_DISP_SPI_INIT_SEQ_DATA_A 0x443
308#define DC_DISP_SPI_INIT_SEQ_DATA_B 0x444
309#define DC_DISP_SPI_INIT_SEQ_DATA_C 0x445
310#define DC_DISP_SPI_INIT_SEQ_DATA_D 0x446
311
312#define DC_DISP_DC_MCCIF_FIFOCTRL 0x480
313#define DC_DISP_MCCIF_DISPLAY0A_HYST 0x481
314#define DC_DISP_MCCIF_DISPLAY0B_HYST 0x482
315#define DC_DISP_MCCIF_DISPLAY1A_HYST 0x483
316#define DC_DISP_MCCIF_DISPLAY1B_HYST 0x484
317
318#define DC_DISP_DAC_CRT_CTRL 0x4c0
319#define DC_DISP_DISP_MISC_CONTROL 0x4c1
320#define DC_DISP_SD_CONTROL 0x4c2
321#define DC_DISP_SD_CSC_COEFF 0x4c3
322#define DC_DISP_SD_LUT(x) (0x4c4 + (x))
323#define DC_DISP_SD_FLICKER_CONTROL 0x4cd
324#define DC_DISP_DC_PIXEL_COUNT 0x4ce
325#define DC_DISP_SD_HISTOGRAM(x) (0x4cf + (x))
326#define DC_DISP_SD_BL_PARAMETERS 0x4d7
327#define DC_DISP_SD_BL_TF(x) (0x4d8 + (x))
328#define DC_DISP_SD_BL_CONTROL 0x4dc
329#define DC_DISP_SD_HW_K_VALUES 0x4dd
330#define DC_DISP_SD_MAN_K_VALUES 0x4de
331
332#define DC_DISP_INTERLACE_CONTROL 0x4e5
333#define INTERLACE_STATUS (1 << 2)
334#define INTERLACE_START (1 << 1)
335#define INTERLACE_ENABLE (1 << 0)
336
337#define DC_DISP_CURSOR_START_ADDR_HI 0x4ec
338#define DC_DISP_BLEND_CURSOR_CONTROL 0x4f1
339#define CURSOR_MODE_LEGACY (0 << 24)
340#define CURSOR_MODE_NORMAL (1 << 24)
341#define CURSOR_DST_BLEND_ZERO (0 << 16)
342#define CURSOR_DST_BLEND_K1 (1 << 16)
343#define CURSOR_DST_BLEND_NEG_K1_TIMES_SRC (2 << 16)
344#define CURSOR_DST_BLEND_MASK (3 << 16)
345#define CURSOR_SRC_BLEND_K1 (0 << 8)
346#define CURSOR_SRC_BLEND_K1_TIMES_SRC (1 << 8)
347#define CURSOR_SRC_BLEND_MASK (3 << 8)
348#define CURSOR_ALPHA 0xff
349
350#define DC_WIN_CSC_YOF 0x611
351#define DC_WIN_CSC_KYRGB 0x612
352#define DC_WIN_CSC_KUR 0x613
353#define DC_WIN_CSC_KVR 0x614
354#define DC_WIN_CSC_KUG 0x615
355#define DC_WIN_CSC_KVG 0x616
356#define DC_WIN_CSC_KUB 0x617
357#define DC_WIN_CSC_KVB 0x618
358
359#define DC_WIN_WIN_OPTIONS 0x700
360#define H_DIRECTION (1 << 0)
361#define V_DIRECTION (1 << 2)
362#define COLOR_EXPAND (1 << 6)
363#define CSC_ENABLE (1 << 18)
364#define WIN_ENABLE (1 << 30)
365
366#define DC_WIN_BYTE_SWAP 0x701
367#define BYTE_SWAP_NOSWAP (0 << 0)
368#define BYTE_SWAP_SWAP2 (1 << 0)
369#define BYTE_SWAP_SWAP4 (2 << 0)
370#define BYTE_SWAP_SWAP4HW (3 << 0)
371
372#define DC_WIN_BUFFER_CONTROL 0x702
373#define BUFFER_CONTROL_HOST (0 << 0)
374#define BUFFER_CONTROL_VI (1 << 0)
375#define BUFFER_CONTROL_EPP (2 << 0)
376#define BUFFER_CONTROL_MPEGE (3 << 0)
377#define BUFFER_CONTROL_SB2D (4 << 0)
378
379#define DC_WIN_COLOR_DEPTH 0x703
380#define WIN_COLOR_DEPTH_P1 0
381#define WIN_COLOR_DEPTH_P2 1
382#define WIN_COLOR_DEPTH_P4 2
383#define WIN_COLOR_DEPTH_P8 3
384#define WIN_COLOR_DEPTH_B4G4R4A4 4
385#define WIN_COLOR_DEPTH_B5G5R5A 5
386#define WIN_COLOR_DEPTH_B5G6R5 6
387#define WIN_COLOR_DEPTH_AB5G5R5 7
388#define WIN_COLOR_DEPTH_B8G8R8A8 12
389#define WIN_COLOR_DEPTH_R8G8B8A8 13
390#define WIN_COLOR_DEPTH_B6x2G6x2R6x2A8 14
391#define WIN_COLOR_DEPTH_R6x2G6x2B6x2A8 15
392#define WIN_COLOR_DEPTH_YCbCr422 16
393#define WIN_COLOR_DEPTH_YUV422 17
394#define WIN_COLOR_DEPTH_YCbCr420P 18
395#define WIN_COLOR_DEPTH_YUV420P 19
396#define WIN_COLOR_DEPTH_YCbCr422P 20
397#define WIN_COLOR_DEPTH_YUV422P 21
398#define WIN_COLOR_DEPTH_YCbCr422R 22
399#define WIN_COLOR_DEPTH_YUV422R 23
400#define WIN_COLOR_DEPTH_YCbCr422RA 24
401#define WIN_COLOR_DEPTH_YUV422RA 25
402
403#define DC_WIN_POSITION 0x704
404#define H_POSITION(x) (((x) & 0x1fff) << 0)
405#define V_POSITION(x) (((x) & 0x1fff) << 16)
406
407#define DC_WIN_SIZE 0x705
408#define H_SIZE(x) (((x) & 0x1fff) << 0)
409#define V_SIZE(x) (((x) & 0x1fff) << 16)
410
411#define DC_WIN_PRESCALED_SIZE 0x706
412#define H_PRESCALED_SIZE(x) (((x) & 0x7fff) << 0)
413#define V_PRESCALED_SIZE(x) (((x) & 0x1fff) << 16)
414
415#define DC_WIN_H_INITIAL_DDA 0x707
416#define DC_WIN_V_INITIAL_DDA 0x708
417#define DC_WIN_DDA_INC 0x709
418#define H_DDA_INC(x) (((x) & 0xffff) << 0)
419#define V_DDA_INC(x) (((x) & 0xffff) << 16)
420
421#define DC_WIN_LINE_STRIDE 0x70a
422#define DC_WIN_BUF_STRIDE 0x70b
423#define DC_WIN_UV_BUF_STRIDE 0x70c
424#define DC_WIN_BUFFER_ADDR_MODE 0x70d
425#define DC_WIN_BUFFER_ADDR_MODE_LINEAR (0 << 0)
426#define DC_WIN_BUFFER_ADDR_MODE_TILE (1 << 0)
427#define DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV (0 << 16)
428#define DC_WIN_BUFFER_ADDR_MODE_TILE_UV (1 << 16)
429#define DC_WIN_DV_CONTROL 0x70e
430
431#define DC_WIN_BLEND_NOKEY 0x70f
432#define DC_WIN_BLEND_1WIN 0x710
433#define DC_WIN_BLEND_2WIN_X 0x711
434#define DC_WIN_BLEND_2WIN_Y 0x712
435#define DC_WIN_BLEND_3WIN_XY 0x713
436
437#define DC_WIN_HP_FETCH_CONTROL 0x714
438
439#define DC_WINBUF_START_ADDR 0x800
440#define DC_WINBUF_START_ADDR_NS 0x801
441#define DC_WINBUF_START_ADDR_U 0x802
442#define DC_WINBUF_START_ADDR_U_NS 0x803
443#define DC_WINBUF_START_ADDR_V 0x804
444#define DC_WINBUF_START_ADDR_V_NS 0x805
445
446#define DC_WINBUF_ADDR_H_OFFSET 0x806
447#define DC_WINBUF_ADDR_H_OFFSET_NS 0x807
448#define DC_WINBUF_ADDR_V_OFFSET 0x808
449#define DC_WINBUF_ADDR_V_OFFSET_NS 0x809
450
451#define DC_WINBUF_UFLOW_STATUS 0x80a
452#define DC_WINBUF_SURFACE_KIND 0x80b
453#define DC_WINBUF_SURFACE_KIND_PITCH (0 << 0)
454#define DC_WINBUF_SURFACE_KIND_TILED (1 << 0)
455#define DC_WINBUF_SURFACE_KIND_BLOCK (2 << 0)
456#define DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(x) (((x) & 0x7) << 4)
457
458#define DC_WINBUF_AD_UFLOW_STATUS 0xbca
459#define DC_WINBUF_BD_UFLOW_STATUS 0xdca
460#define DC_WINBUF_CD_UFLOW_STATUS 0xfca
461
462#endif /* TEGRA_DC_H */
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2012 Avionic Design GmbH
4 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
5 */
6
7#ifndef TEGRA_DC_H
8#define TEGRA_DC_H 1
9
10#include <linux/host1x.h>
11
12#include <drm/drm_crtc.h>
13
14#include "drm.h"
15
16struct tegra_output;
17
18struct tegra_dc_state {
19 struct drm_crtc_state base;
20
21 struct clk *clk;
22 unsigned long pclk;
23 unsigned int div;
24
25 u32 planes;
26};
27
28static inline struct tegra_dc_state *to_dc_state(struct drm_crtc_state *state)
29{
30 if (state)
31 return container_of(state, struct tegra_dc_state, base);
32
33 return NULL;
34}
35
36struct tegra_dc_stats {
37 unsigned long frames;
38 unsigned long vblank;
39 unsigned long underflow;
40 unsigned long overflow;
41};
42
43struct tegra_windowgroup_soc {
44 unsigned int index;
45 unsigned int dc;
46 const unsigned int *windows;
47 unsigned int num_windows;
48};
49
50struct tegra_dc_soc_info {
51 bool supports_background_color;
52 bool supports_interlacing;
53 bool supports_cursor;
54 bool supports_block_linear;
55 bool has_legacy_blending;
56 unsigned int pitch_align;
57 bool has_powergate;
58 bool coupled_pm;
59 bool has_nvdisplay;
60 const struct tegra_windowgroup_soc *wgrps;
61 unsigned int num_wgrps;
62 const u32 *primary_formats;
63 unsigned int num_primary_formats;
64 const u32 *overlay_formats;
65 unsigned int num_overlay_formats;
66 const u64 *modifiers;
67 bool has_win_a_without_filters;
68 bool has_win_c_without_vert_filter;
69};
70
71struct tegra_dc {
72 struct host1x_client client;
73 struct host1x_syncpt *syncpt;
74 struct device *dev;
75
76 struct drm_crtc base;
77 unsigned int powergate;
78 int pipe;
79
80 struct clk *clk;
81 struct reset_control *rst;
82 void __iomem *regs;
83 int irq;
84
85 struct tegra_output *rgb;
86
87 struct tegra_dc_stats stats;
88 struct list_head list;
89
90 struct drm_info_list *debugfs_files;
91
92 const struct tegra_dc_soc_info *soc;
93};
94
95static inline struct tegra_dc *
96host1x_client_to_dc(struct host1x_client *client)
97{
98 return container_of(client, struct tegra_dc, client);
99}
100
101static inline struct tegra_dc *to_tegra_dc(struct drm_crtc *crtc)
102{
103 return crtc ? container_of(crtc, struct tegra_dc, base) : NULL;
104}
105
106static inline void tegra_dc_writel(struct tegra_dc *dc, u32 value,
107 unsigned int offset)
108{
109 trace_dc_writel(dc->dev, offset, value);
110 writel(value, dc->regs + (offset << 2));
111}
112
113static inline u32 tegra_dc_readl(struct tegra_dc *dc, unsigned int offset)
114{
115 u32 value = readl(dc->regs + (offset << 2));
116
117 trace_dc_readl(dc->dev, offset, value);
118
119 return value;
120}
121
122struct tegra_dc_window {
123 struct {
124 unsigned int x;
125 unsigned int y;
126 unsigned int w;
127 unsigned int h;
128 } src;
129 struct {
130 unsigned int x;
131 unsigned int y;
132 unsigned int w;
133 unsigned int h;
134 } dst;
135 unsigned int bits_per_pixel;
136 unsigned int stride[2];
137 unsigned long base[3];
138 unsigned int zpos;
139 bool reflect_x;
140 bool reflect_y;
141
142 struct tegra_bo_tiling tiling;
143 u32 format;
144 u32 swap;
145};
146
147/* from dc.c */
148bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev);
149void tegra_dc_commit(struct tegra_dc *dc);
150int tegra_dc_state_setup_clock(struct tegra_dc *dc,
151 struct drm_crtc_state *crtc_state,
152 struct clk *clk, unsigned long pclk,
153 unsigned int div);
154
155/* from rgb.c */
156int tegra_dc_rgb_probe(struct tegra_dc *dc);
157int tegra_dc_rgb_remove(struct tegra_dc *dc);
158int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc);
159int tegra_dc_rgb_exit(struct tegra_dc *dc);
160
161#define DC_CMD_GENERAL_INCR_SYNCPT 0x000
162#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL 0x001
163#define SYNCPT_CNTRL_NO_STALL (1 << 8)
164#define SYNCPT_CNTRL_SOFT_RESET (1 << 0)
165#define DC_CMD_GENERAL_INCR_SYNCPT_ERROR 0x002
166#define DC_CMD_WIN_A_INCR_SYNCPT 0x008
167#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL 0x009
168#define DC_CMD_WIN_A_INCR_SYNCPT_ERROR 0x00a
169#define DC_CMD_WIN_B_INCR_SYNCPT 0x010
170#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL 0x011
171#define DC_CMD_WIN_B_INCR_SYNCPT_ERROR 0x012
172#define DC_CMD_WIN_C_INCR_SYNCPT 0x018
173#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL 0x019
174#define DC_CMD_WIN_C_INCR_SYNCPT_ERROR 0x01a
175#define DC_CMD_CONT_SYNCPT_VSYNC 0x028
176#define SYNCPT_VSYNC_ENABLE (1 << 8)
177#define DC_CMD_DISPLAY_COMMAND_OPTION0 0x031
178#define DC_CMD_DISPLAY_COMMAND 0x032
179#define DISP_CTRL_MODE_STOP (0 << 5)
180#define DISP_CTRL_MODE_C_DISPLAY (1 << 5)
181#define DISP_CTRL_MODE_NC_DISPLAY (2 << 5)
182#define DISP_CTRL_MODE_MASK (3 << 5)
183#define DC_CMD_SIGNAL_RAISE 0x033
184#define DC_CMD_DISPLAY_POWER_CONTROL 0x036
185#define PW0_ENABLE (1 << 0)
186#define PW1_ENABLE (1 << 2)
187#define PW2_ENABLE (1 << 4)
188#define PW3_ENABLE (1 << 6)
189#define PW4_ENABLE (1 << 8)
190#define PM0_ENABLE (1 << 16)
191#define PM1_ENABLE (1 << 18)
192
193#define DC_CMD_INT_STATUS 0x037
194#define DC_CMD_INT_MASK 0x038
195#define DC_CMD_INT_ENABLE 0x039
196#define DC_CMD_INT_TYPE 0x03a
197#define DC_CMD_INT_POLARITY 0x03b
198#define CTXSW_INT (1 << 0)
199#define FRAME_END_INT (1 << 1)
200#define VBLANK_INT (1 << 2)
201#define V_PULSE3_INT (1 << 4)
202#define V_PULSE2_INT (1 << 5)
203#define REGION_CRC_INT (1 << 6)
204#define REG_TMOUT_INT (1 << 7)
205#define WIN_A_UF_INT (1 << 8)
206#define WIN_B_UF_INT (1 << 9)
207#define WIN_C_UF_INT (1 << 10)
208#define MSF_INT (1 << 12)
209#define WIN_A_OF_INT (1 << 14)
210#define WIN_B_OF_INT (1 << 15)
211#define WIN_C_OF_INT (1 << 16)
212#define HEAD_UF_INT (1 << 23)
213#define SD3_BUCKET_WALK_DONE_INT (1 << 24)
214#define DSC_OBUF_UF_INT (1 << 26)
215#define DSC_RBUF_UF_INT (1 << 27)
216#define DSC_BBUF_UF_INT (1 << 28)
217#define DSC_TO_UF_INT (1 << 29)
218
219#define DC_CMD_SIGNAL_RAISE1 0x03c
220#define DC_CMD_SIGNAL_RAISE2 0x03d
221#define DC_CMD_SIGNAL_RAISE3 0x03e
222
223#define DC_CMD_STATE_ACCESS 0x040
224#define READ_MUX (1 << 0)
225#define WRITE_MUX (1 << 2)
226
227#define DC_CMD_STATE_CONTROL 0x041
228#define GENERAL_ACT_REQ (1 << 0)
229#define WIN_A_ACT_REQ (1 << 1)
230#define WIN_B_ACT_REQ (1 << 2)
231#define WIN_C_ACT_REQ (1 << 3)
232#define CURSOR_ACT_REQ (1 << 7)
233#define GENERAL_UPDATE (1 << 8)
234#define WIN_A_UPDATE (1 << 9)
235#define WIN_B_UPDATE (1 << 10)
236#define WIN_C_UPDATE (1 << 11)
237#define CURSOR_UPDATE (1 << 15)
238#define COMMON_ACTREQ (1 << 16)
239#define COMMON_UPDATE (1 << 17)
240#define NC_HOST_TRIG (1 << 24)
241
242#define DC_CMD_DISPLAY_WINDOW_HEADER 0x042
243#define WINDOW_A_SELECT (1 << 4)
244#define WINDOW_B_SELECT (1 << 5)
245#define WINDOW_C_SELECT (1 << 6)
246
247#define DC_CMD_REG_ACT_CONTROL 0x043
248
249#define DC_COM_CRC_CONTROL 0x300
250#define DC_COM_CRC_CONTROL_ALWAYS (1 << 3)
251#define DC_COM_CRC_CONTROL_FULL_FRAME (0 << 2)
252#define DC_COM_CRC_CONTROL_ACTIVE_DATA (1 << 2)
253#define DC_COM_CRC_CONTROL_WAIT (1 << 1)
254#define DC_COM_CRC_CONTROL_ENABLE (1 << 0)
255#define DC_COM_CRC_CHECKSUM 0x301
256#define DC_COM_PIN_OUTPUT_ENABLE(x) (0x302 + (x))
257#define DC_COM_PIN_OUTPUT_POLARITY(x) (0x306 + (x))
258#define LVS_OUTPUT_POLARITY_LOW (1 << 28)
259#define LHS_OUTPUT_POLARITY_LOW (1 << 30)
260#define DC_COM_PIN_OUTPUT_DATA(x) (0x30a + (x))
261#define DC_COM_PIN_INPUT_ENABLE(x) (0x30e + (x))
262#define DC_COM_PIN_INPUT_DATA(x) (0x312 + (x))
263#define DC_COM_PIN_OUTPUT_SELECT(x) (0x314 + (x))
264
265#define DC_COM_PIN_MISC_CONTROL 0x31b
266#define DC_COM_PIN_PM0_CONTROL 0x31c
267#define DC_COM_PIN_PM0_DUTY_CYCLE 0x31d
268#define DC_COM_PIN_PM1_CONTROL 0x31e
269#define DC_COM_PIN_PM1_DUTY_CYCLE 0x31f
270
271#define DC_COM_SPI_CONTROL 0x320
272#define DC_COM_SPI_START_BYTE 0x321
273#define DC_COM_HSPI_WRITE_DATA_AB 0x322
274#define DC_COM_HSPI_WRITE_DATA_CD 0x323
275#define DC_COM_HSPI_CS_DC 0x324
276#define DC_COM_SCRATCH_REGISTER_A 0x325
277#define DC_COM_SCRATCH_REGISTER_B 0x326
278#define DC_COM_GPIO_CTRL 0x327
279#define DC_COM_GPIO_DEBOUNCE_COUNTER 0x328
280#define DC_COM_CRC_CHECKSUM_LATCHED 0x329
281
282#define DC_COM_RG_UNDERFLOW 0x365
283#define UNDERFLOW_MODE_RED (1 << 8)
284#define UNDERFLOW_REPORT_ENABLE (1 << 0)
285
286#define DC_DISP_DISP_SIGNAL_OPTIONS0 0x400
287#define H_PULSE0_ENABLE (1 << 8)
288#define H_PULSE1_ENABLE (1 << 10)
289#define H_PULSE2_ENABLE (1 << 12)
290
291#define DC_DISP_DISP_SIGNAL_OPTIONS1 0x401
292
293#define DC_DISP_DISP_WIN_OPTIONS 0x402
294#define HDMI_ENABLE (1 << 30)
295#define DSI_ENABLE (1 << 29)
296#define SOR1_TIMING_CYA (1 << 27)
297#define CURSOR_ENABLE (1 << 16)
298
299#define SOR_ENABLE(x) (1 << (25 + (((x) > 1) ? ((x) + 1) : (x))))
300
301#define DC_DISP_DISP_MEM_HIGH_PRIORITY 0x403
302#define CURSOR_THRESHOLD(x) (((x) & 0x03) << 24)
303#define WINDOW_A_THRESHOLD(x) (((x) & 0x7f) << 16)
304#define WINDOW_B_THRESHOLD(x) (((x) & 0x7f) << 8)
305#define WINDOW_C_THRESHOLD(x) (((x) & 0xff) << 0)
306
307#define DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER 0x404
308#define CURSOR_DELAY(x) (((x) & 0x3f) << 24)
309#define WINDOW_A_DELAY(x) (((x) & 0x3f) << 16)
310#define WINDOW_B_DELAY(x) (((x) & 0x3f) << 8)
311#define WINDOW_C_DELAY(x) (((x) & 0x3f) << 0)
312
313#define DC_DISP_DISP_TIMING_OPTIONS 0x405
314#define VSYNC_H_POSITION(x) ((x) & 0xfff)
315
316#define DC_DISP_REF_TO_SYNC 0x406
317#define DC_DISP_SYNC_WIDTH 0x407
318#define DC_DISP_BACK_PORCH 0x408
319#define DC_DISP_ACTIVE 0x409
320#define DC_DISP_FRONT_PORCH 0x40a
321#define DC_DISP_H_PULSE0_CONTROL 0x40b
322#define DC_DISP_H_PULSE0_POSITION_A 0x40c
323#define DC_DISP_H_PULSE0_POSITION_B 0x40d
324#define DC_DISP_H_PULSE0_POSITION_C 0x40e
325#define DC_DISP_H_PULSE0_POSITION_D 0x40f
326#define DC_DISP_H_PULSE1_CONTROL 0x410
327#define DC_DISP_H_PULSE1_POSITION_A 0x411
328#define DC_DISP_H_PULSE1_POSITION_B 0x412
329#define DC_DISP_H_PULSE1_POSITION_C 0x413
330#define DC_DISP_H_PULSE1_POSITION_D 0x414
331#define DC_DISP_H_PULSE2_CONTROL 0x415
332#define DC_DISP_H_PULSE2_POSITION_A 0x416
333#define DC_DISP_H_PULSE2_POSITION_B 0x417
334#define DC_DISP_H_PULSE2_POSITION_C 0x418
335#define DC_DISP_H_PULSE2_POSITION_D 0x419
336#define DC_DISP_V_PULSE0_CONTROL 0x41a
337#define DC_DISP_V_PULSE0_POSITION_A 0x41b
338#define DC_DISP_V_PULSE0_POSITION_B 0x41c
339#define DC_DISP_V_PULSE0_POSITION_C 0x41d
340#define DC_DISP_V_PULSE1_CONTROL 0x41e
341#define DC_DISP_V_PULSE1_POSITION_A 0x41f
342#define DC_DISP_V_PULSE1_POSITION_B 0x420
343#define DC_DISP_V_PULSE1_POSITION_C 0x421
344#define DC_DISP_V_PULSE2_CONTROL 0x422
345#define DC_DISP_V_PULSE2_POSITION_A 0x423
346#define DC_DISP_V_PULSE3_CONTROL 0x424
347#define DC_DISP_V_PULSE3_POSITION_A 0x425
348#define DC_DISP_M0_CONTROL 0x426
349#define DC_DISP_M1_CONTROL 0x427
350#define DC_DISP_DI_CONTROL 0x428
351#define DC_DISP_PP_CONTROL 0x429
352#define DC_DISP_PP_SELECT_A 0x42a
353#define DC_DISP_PP_SELECT_B 0x42b
354#define DC_DISP_PP_SELECT_C 0x42c
355#define DC_DISP_PP_SELECT_D 0x42d
356
357#define PULSE_MODE_NORMAL (0 << 3)
358#define PULSE_MODE_ONE_CLOCK (1 << 3)
359#define PULSE_POLARITY_HIGH (0 << 4)
360#define PULSE_POLARITY_LOW (1 << 4)
361#define PULSE_QUAL_ALWAYS (0 << 6)
362#define PULSE_QUAL_VACTIVE (2 << 6)
363#define PULSE_QUAL_VACTIVE1 (3 << 6)
364#define PULSE_LAST_START_A (0 << 8)
365#define PULSE_LAST_END_A (1 << 8)
366#define PULSE_LAST_START_B (2 << 8)
367#define PULSE_LAST_END_B (3 << 8)
368#define PULSE_LAST_START_C (4 << 8)
369#define PULSE_LAST_END_C (5 << 8)
370#define PULSE_LAST_START_D (6 << 8)
371#define PULSE_LAST_END_D (7 << 8)
372
373#define PULSE_START(x) (((x) & 0xfff) << 0)
374#define PULSE_END(x) (((x) & 0xfff) << 16)
375
376#define DC_DISP_DISP_CLOCK_CONTROL 0x42e
377#define PIXEL_CLK_DIVIDER_PCD1 (0 << 8)
378#define PIXEL_CLK_DIVIDER_PCD1H (1 << 8)
379#define PIXEL_CLK_DIVIDER_PCD2 (2 << 8)
380#define PIXEL_CLK_DIVIDER_PCD3 (3 << 8)
381#define PIXEL_CLK_DIVIDER_PCD4 (4 << 8)
382#define PIXEL_CLK_DIVIDER_PCD6 (5 << 8)
383#define PIXEL_CLK_DIVIDER_PCD8 (6 << 8)
384#define PIXEL_CLK_DIVIDER_PCD9 (7 << 8)
385#define PIXEL_CLK_DIVIDER_PCD12 (8 << 8)
386#define PIXEL_CLK_DIVIDER_PCD16 (9 << 8)
387#define PIXEL_CLK_DIVIDER_PCD18 (10 << 8)
388#define PIXEL_CLK_DIVIDER_PCD24 (11 << 8)
389#define PIXEL_CLK_DIVIDER_PCD13 (12 << 8)
390#define SHIFT_CLK_DIVIDER(x) ((x) & 0xff)
391
392#define DC_DISP_DISP_INTERFACE_CONTROL 0x42f
393#define DISP_DATA_FORMAT_DF1P1C (0 << 0)
394#define DISP_DATA_FORMAT_DF1P2C24B (1 << 0)
395#define DISP_DATA_FORMAT_DF1P2C18B (2 << 0)
396#define DISP_DATA_FORMAT_DF1P2C16B (3 << 0)
397#define DISP_DATA_FORMAT_DF2S (4 << 0)
398#define DISP_DATA_FORMAT_DF3S (5 << 0)
399#define DISP_DATA_FORMAT_DFSPI (6 << 0)
400#define DISP_DATA_FORMAT_DF1P3C24B (7 << 0)
401#define DISP_DATA_FORMAT_DF1P3C18B (8 << 0)
402#define DISP_ALIGNMENT_MSB (0 << 8)
403#define DISP_ALIGNMENT_LSB (1 << 8)
404#define DISP_ORDER_RED_BLUE (0 << 9)
405#define DISP_ORDER_BLUE_RED (1 << 9)
406
407#define DC_DISP_DISP_COLOR_CONTROL 0x430
408#define BASE_COLOR_SIZE666 ( 0 << 0)
409#define BASE_COLOR_SIZE111 ( 1 << 0)
410#define BASE_COLOR_SIZE222 ( 2 << 0)
411#define BASE_COLOR_SIZE333 ( 3 << 0)
412#define BASE_COLOR_SIZE444 ( 4 << 0)
413#define BASE_COLOR_SIZE555 ( 5 << 0)
414#define BASE_COLOR_SIZE565 ( 6 << 0)
415#define BASE_COLOR_SIZE332 ( 7 << 0)
416#define BASE_COLOR_SIZE888 ( 8 << 0)
417#define BASE_COLOR_SIZE101010 (10 << 0)
418#define BASE_COLOR_SIZE121212 (12 << 0)
419#define DITHER_CONTROL_MASK (3 << 8)
420#define DITHER_CONTROL_DISABLE (0 << 8)
421#define DITHER_CONTROL_ORDERED (2 << 8)
422#define DITHER_CONTROL_ERRDIFF (3 << 8)
423#define BASE_COLOR_SIZE_MASK (0xf << 0)
424#define BASE_COLOR_SIZE_666 ( 0 << 0)
425#define BASE_COLOR_SIZE_111 ( 1 << 0)
426#define BASE_COLOR_SIZE_222 ( 2 << 0)
427#define BASE_COLOR_SIZE_333 ( 3 << 0)
428#define BASE_COLOR_SIZE_444 ( 4 << 0)
429#define BASE_COLOR_SIZE_555 ( 5 << 0)
430#define BASE_COLOR_SIZE_565 ( 6 << 0)
431#define BASE_COLOR_SIZE_332 ( 7 << 0)
432#define BASE_COLOR_SIZE_888 ( 8 << 0)
433#define BASE_COLOR_SIZE_101010 ( 10 << 0)
434#define BASE_COLOR_SIZE_121212 ( 12 << 0)
435
436#define DC_DISP_SHIFT_CLOCK_OPTIONS 0x431
437#define SC1_H_QUALIFIER_NONE (1 << 16)
438#define SC0_H_QUALIFIER_NONE (1 << 0)
439
440#define DC_DISP_DATA_ENABLE_OPTIONS 0x432
441#define DE_SELECT_ACTIVE_BLANK (0 << 0)
442#define DE_SELECT_ACTIVE (1 << 0)
443#define DE_SELECT_ACTIVE_IS (2 << 0)
444#define DE_CONTROL_ONECLK (0 << 2)
445#define DE_CONTROL_NORMAL (1 << 2)
446#define DE_CONTROL_EARLY_EXT (2 << 2)
447#define DE_CONTROL_EARLY (3 << 2)
448#define DE_CONTROL_ACTIVE_BLANK (4 << 2)
449
450#define DC_DISP_SERIAL_INTERFACE_OPTIONS 0x433
451#define DC_DISP_LCD_SPI_OPTIONS 0x434
452#define DC_DISP_BORDER_COLOR 0x435
453#define DC_DISP_COLOR_KEY0_LOWER 0x436
454#define DC_DISP_COLOR_KEY0_UPPER 0x437
455#define DC_DISP_COLOR_KEY1_LOWER 0x438
456#define DC_DISP_COLOR_KEY1_UPPER 0x439
457
458#define DC_DISP_CURSOR_FOREGROUND 0x43c
459#define DC_DISP_CURSOR_BACKGROUND 0x43d
460
461#define DC_DISP_CURSOR_START_ADDR 0x43e
462#define CURSOR_CLIP_DISPLAY (0 << 28)
463#define CURSOR_CLIP_WIN_A (1 << 28)
464#define CURSOR_CLIP_WIN_B (2 << 28)
465#define CURSOR_CLIP_WIN_C (3 << 28)
466#define CURSOR_SIZE_32x32 (0 << 24)
467#define CURSOR_SIZE_64x64 (1 << 24)
468#define CURSOR_SIZE_128x128 (2 << 24)
469#define CURSOR_SIZE_256x256 (3 << 24)
470#define DC_DISP_CURSOR_START_ADDR_NS 0x43f
471
472#define DC_DISP_CURSOR_POSITION 0x440
473#define DC_DISP_CURSOR_POSITION_NS 0x441
474
475#define DC_DISP_INIT_SEQ_CONTROL 0x442
476#define DC_DISP_SPI_INIT_SEQ_DATA_A 0x443
477#define DC_DISP_SPI_INIT_SEQ_DATA_B 0x444
478#define DC_DISP_SPI_INIT_SEQ_DATA_C 0x445
479#define DC_DISP_SPI_INIT_SEQ_DATA_D 0x446
480
481#define DC_DISP_DC_MCCIF_FIFOCTRL 0x480
482#define DC_DISP_MCCIF_DISPLAY0A_HYST 0x481
483#define DC_DISP_MCCIF_DISPLAY0B_HYST 0x482
484#define DC_DISP_MCCIF_DISPLAY1A_HYST 0x483
485#define DC_DISP_MCCIF_DISPLAY1B_HYST 0x484
486
487#define DC_DISP_DAC_CRT_CTRL 0x4c0
488#define DC_DISP_DISP_MISC_CONTROL 0x4c1
489#define DC_DISP_SD_CONTROL 0x4c2
490#define DC_DISP_SD_CSC_COEFF 0x4c3
491#define DC_DISP_SD_LUT(x) (0x4c4 + (x))
492#define DC_DISP_SD_FLICKER_CONTROL 0x4cd
493#define DC_DISP_DC_PIXEL_COUNT 0x4ce
494#define DC_DISP_SD_HISTOGRAM(x) (0x4cf + (x))
495#define DC_DISP_SD_BL_PARAMETERS 0x4d7
496#define DC_DISP_SD_BL_TF(x) (0x4d8 + (x))
497#define DC_DISP_SD_BL_CONTROL 0x4dc
498#define DC_DISP_SD_HW_K_VALUES 0x4dd
499#define DC_DISP_SD_MAN_K_VALUES 0x4de
500
501#define DC_DISP_BLEND_BACKGROUND_COLOR 0x4e4
502#define BACKGROUND_COLOR_ALPHA(x) (((x) & 0xff) << 24)
503#define BACKGROUND_COLOR_BLUE(x) (((x) & 0xff) << 16)
504#define BACKGROUND_COLOR_GREEN(x) (((x) & 0xff) << 8)
505#define BACKGROUND_COLOR_RED(x) (((x) & 0xff) << 0)
506
507#define DC_DISP_INTERLACE_CONTROL 0x4e5
508#define INTERLACE_STATUS (1 << 2)
509#define INTERLACE_START (1 << 1)
510#define INTERLACE_ENABLE (1 << 0)
511
512#define DC_DISP_CURSOR_START_ADDR_HI 0x4ec
513#define DC_DISP_BLEND_CURSOR_CONTROL 0x4f1
514#define CURSOR_MODE_LEGACY (0 << 24)
515#define CURSOR_MODE_NORMAL (1 << 24)
516#define CURSOR_DST_BLEND_ZERO (0 << 16)
517#define CURSOR_DST_BLEND_K1 (1 << 16)
518#define CURSOR_DST_BLEND_NEG_K1_TIMES_SRC (2 << 16)
519#define CURSOR_DST_BLEND_MASK (3 << 16)
520#define CURSOR_SRC_BLEND_K1 (0 << 8)
521#define CURSOR_SRC_BLEND_K1_TIMES_SRC (1 << 8)
522#define CURSOR_SRC_BLEND_MASK (3 << 8)
523#define CURSOR_ALPHA 0xff
524
525#define DC_WIN_CORE_ACT_CONTROL 0x50e
526#define VCOUNTER (0 << 0)
527#define HCOUNTER (1 << 0)
528
529#define DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLA 0x543
530#define LATENCY_CTL_MODE_ENABLE (1 << 2)
531
532#define DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLB 0x544
533#define WATERMARK_MASK 0x1fffffff
534
535#define DC_WIN_CORE_PRECOMP_WGRP_PIPE_METER 0x560
536#define PIPE_METER_INT(x) (((x) & 0xff) << 8)
537#define PIPE_METER_FRAC(x) (((x) & 0xff) << 0)
538
539#define DC_WIN_CORE_IHUB_WGRP_POOL_CONFIG 0x561
540#define MEMPOOL_ENTRIES(x) (((x) & 0xffff) << 0)
541
542#define DC_WIN_CORE_IHUB_WGRP_FETCH_METER 0x562
543#define SLOTS(x) (((x) & 0xff) << 0)
544
545#define DC_WIN_CORE_IHUB_LINEBUF_CONFIG 0x563
546#define MODE_TWO_LINES (0 << 14)
547#define MODE_FOUR_LINES (1 << 14)
548
549#define DC_WIN_CORE_IHUB_THREAD_GROUP 0x568
550#define THREAD_NUM_MASK (0x1f << 1)
551#define THREAD_NUM(x) (((x) & 0x1f) << 1)
552#define THREAD_GROUP_ENABLE (1 << 0)
553
554#define DC_WIN_H_FILTER_P(p) (0x601 + (p))
555#define DC_WIN_V_FILTER_P(p) (0x619 + (p))
556
557#define DC_WIN_CSC_YOF 0x611
558#define DC_WIN_CSC_KYRGB 0x612
559#define DC_WIN_CSC_KUR 0x613
560#define DC_WIN_CSC_KVR 0x614
561#define DC_WIN_CSC_KUG 0x615
562#define DC_WIN_CSC_KVG 0x616
563#define DC_WIN_CSC_KUB 0x617
564#define DC_WIN_CSC_KVB 0x618
565
566#define DC_WIN_WIN_OPTIONS 0x700
567#define H_DIRECTION (1 << 0)
568#define V_DIRECTION (1 << 2)
569#define COLOR_EXPAND (1 << 6)
570#define H_FILTER (1 << 8)
571#define V_FILTER (1 << 10)
572#define CSC_ENABLE (1 << 18)
573#define WIN_ENABLE (1 << 30)
574
575#define DC_WIN_BYTE_SWAP 0x701
576#define BYTE_SWAP_NOSWAP (0 << 0)
577#define BYTE_SWAP_SWAP2 (1 << 0)
578#define BYTE_SWAP_SWAP4 (2 << 0)
579#define BYTE_SWAP_SWAP4HW (3 << 0)
580
581#define DC_WIN_BUFFER_CONTROL 0x702
582#define BUFFER_CONTROL_HOST (0 << 0)
583#define BUFFER_CONTROL_VI (1 << 0)
584#define BUFFER_CONTROL_EPP (2 << 0)
585#define BUFFER_CONTROL_MPEGE (3 << 0)
586#define BUFFER_CONTROL_SB2D (4 << 0)
587
588#define DC_WIN_COLOR_DEPTH 0x703
589#define WIN_COLOR_DEPTH_P1 0
590#define WIN_COLOR_DEPTH_P2 1
591#define WIN_COLOR_DEPTH_P4 2
592#define WIN_COLOR_DEPTH_P8 3
593#define WIN_COLOR_DEPTH_B4G4R4A4 4
594#define WIN_COLOR_DEPTH_B5G5R5A1 5
595#define WIN_COLOR_DEPTH_B5G6R5 6
596#define WIN_COLOR_DEPTH_A1B5G5R5 7
597#define WIN_COLOR_DEPTH_B8G8R8A8 12
598#define WIN_COLOR_DEPTH_R8G8B8A8 13
599#define WIN_COLOR_DEPTH_B6x2G6x2R6x2A8 14
600#define WIN_COLOR_DEPTH_R6x2G6x2B6x2A8 15
601#define WIN_COLOR_DEPTH_YCbCr422 16
602#define WIN_COLOR_DEPTH_YUV422 17
603#define WIN_COLOR_DEPTH_YCbCr420P 18
604#define WIN_COLOR_DEPTH_YUV420P 19
605#define WIN_COLOR_DEPTH_YCbCr422P 20
606#define WIN_COLOR_DEPTH_YUV422P 21
607#define WIN_COLOR_DEPTH_YCbCr422R 22
608#define WIN_COLOR_DEPTH_YUV422R 23
609#define WIN_COLOR_DEPTH_YCbCr422RA 24
610#define WIN_COLOR_DEPTH_YUV422RA 25
611#define WIN_COLOR_DEPTH_R4G4B4A4 27
612#define WIN_COLOR_DEPTH_R5G5B5A 28
613#define WIN_COLOR_DEPTH_AR5G5B5 29
614#define WIN_COLOR_DEPTH_B5G5R5X1 30
615#define WIN_COLOR_DEPTH_X1B5G5R5 31
616#define WIN_COLOR_DEPTH_R5G5B5X1 32
617#define WIN_COLOR_DEPTH_X1R5G5B5 33
618#define WIN_COLOR_DEPTH_R5G6B5 34
619#define WIN_COLOR_DEPTH_A8R8G8B8 35
620#define WIN_COLOR_DEPTH_A8B8G8R8 36
621#define WIN_COLOR_DEPTH_B8G8R8X8 37
622#define WIN_COLOR_DEPTH_R8G8B8X8 38
623#define WIN_COLOR_DEPTH_X8B8G8R8 65
624#define WIN_COLOR_DEPTH_X8R8G8B8 66
625
626#define DC_WIN_POSITION 0x704
627#define H_POSITION(x) (((x) & 0x1fff) << 0) /* XXX 0x7fff on Tegra186 */
628#define V_POSITION(x) (((x) & 0x1fff) << 16) /* XXX 0x7fff on Tegra186 */
629
630#define DC_WIN_SIZE 0x705
631#define H_SIZE(x) (((x) & 0x1fff) << 0) /* XXX 0x7fff on Tegra186 */
632#define V_SIZE(x) (((x) & 0x1fff) << 16) /* XXX 0x7fff on Tegra186 */
633
634#define DC_WIN_PRESCALED_SIZE 0x706
635#define H_PRESCALED_SIZE(x) (((x) & 0x7fff) << 0)
636#define V_PRESCALED_SIZE(x) (((x) & 0x1fff) << 16) /* XXX 0x7fff on Tegra186 */
637
638#define DC_WIN_H_INITIAL_DDA 0x707
639#define DC_WIN_V_INITIAL_DDA 0x708
640#define DC_WIN_DDA_INC 0x709
641#define H_DDA_INC(x) (((x) & 0xffff) << 0)
642#define V_DDA_INC(x) (((x) & 0xffff) << 16)
643
644#define DC_WIN_LINE_STRIDE 0x70a
645#define DC_WIN_BUF_STRIDE 0x70b
646#define DC_WIN_UV_BUF_STRIDE 0x70c
647#define DC_WIN_BUFFER_ADDR_MODE 0x70d
648#define DC_WIN_BUFFER_ADDR_MODE_LINEAR (0 << 0)
649#define DC_WIN_BUFFER_ADDR_MODE_TILE (1 << 0)
650#define DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV (0 << 16)
651#define DC_WIN_BUFFER_ADDR_MODE_TILE_UV (1 << 16)
652
653#define DC_WIN_DV_CONTROL 0x70e
654
655#define DC_WIN_BLEND_NOKEY 0x70f
656#define BLEND_WEIGHT1(x) (((x) & 0xff) << 16)
657#define BLEND_WEIGHT0(x) (((x) & 0xff) << 8)
658
659#define DC_WIN_BLEND_1WIN 0x710
660#define BLEND_CONTROL_FIX (0 << 2)
661#define BLEND_CONTROL_ALPHA (1 << 2)
662#define BLEND_COLOR_KEY_NONE (0 << 0)
663#define BLEND_COLOR_KEY_0 (1 << 0)
664#define BLEND_COLOR_KEY_1 (2 << 0)
665#define BLEND_COLOR_KEY_BOTH (3 << 0)
666
667#define DC_WIN_BLEND_2WIN_X 0x711
668#define BLEND_CONTROL_DEPENDENT (2 << 2)
669
670#define DC_WIN_BLEND_2WIN_Y 0x712
671#define DC_WIN_BLEND_3WIN_XY 0x713
672
673#define DC_WIN_HP_FETCH_CONTROL 0x714
674
675#define DC_WINBUF_START_ADDR 0x800
676#define DC_WINBUF_START_ADDR_NS 0x801
677#define DC_WINBUF_START_ADDR_U 0x802
678#define DC_WINBUF_START_ADDR_U_NS 0x803
679#define DC_WINBUF_START_ADDR_V 0x804
680#define DC_WINBUF_START_ADDR_V_NS 0x805
681
682#define DC_WINBUF_ADDR_H_OFFSET 0x806
683#define DC_WINBUF_ADDR_H_OFFSET_NS 0x807
684#define DC_WINBUF_ADDR_V_OFFSET 0x808
685#define DC_WINBUF_ADDR_V_OFFSET_NS 0x809
686
687#define DC_WINBUF_UFLOW_STATUS 0x80a
688#define DC_WINBUF_SURFACE_KIND 0x80b
689#define DC_WINBUF_SURFACE_KIND_PITCH (0 << 0)
690#define DC_WINBUF_SURFACE_KIND_TILED (1 << 0)
691#define DC_WINBUF_SURFACE_KIND_BLOCK (2 << 0)
692#define DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(x) (((x) & 0x7) << 4)
693
694#define DC_WINBUF_START_ADDR_HI 0x80d
695
696#define DC_WINBUF_CDE_CONTROL 0x82f
697#define ENABLE_SURFACE (1 << 0)
698
699#define DC_WINBUF_AD_UFLOW_STATUS 0xbca
700#define DC_WINBUF_BD_UFLOW_STATUS 0xdca
701#define DC_WINBUF_CD_UFLOW_STATUS 0xfca
702
703/* Tegra186 and later */
704#define DC_DISP_CORE_SOR_SET_CONTROL(x) (0x403 + (x))
705#define PROTOCOL_MASK (0xf << 8)
706#define PROTOCOL_SINGLE_TMDS_A (0x1 << 8)
707
708#define DC_WIN_CORE_WINDOWGROUP_SET_CONTROL 0x702
709#define OWNER_MASK (0xf << 0)
710#define OWNER(x) (((x) & 0xf) << 0)
711
712#define DC_WIN_CROPPED_SIZE 0x706
713
714#define DC_WIN_PLANAR_STORAGE 0x709
715#define PITCH(x) (((x) >> 6) & 0x1fff)
716
717#define DC_WIN_SET_PARAMS 0x70d
718#define CLAMP_BEFORE_BLEND (1 << 15)
719#define DEGAMMA_NONE (0 << 13)
720#define DEGAMMA_SRGB (1 << 13)
721#define DEGAMMA_YUV8_10 (2 << 13)
722#define DEGAMMA_YUV12 (3 << 13)
723#define INPUT_RANGE_BYPASS (0 << 10)
724#define INPUT_RANGE_LIMITED (1 << 10)
725#define INPUT_RANGE_FULL (2 << 10)
726#define COLOR_SPACE_RGB (0 << 8)
727#define COLOR_SPACE_YUV_601 (1 << 8)
728#define COLOR_SPACE_YUV_709 (2 << 8)
729#define COLOR_SPACE_YUV_2020 (3 << 8)
730
731#define DC_WIN_WINDOWGROUP_SET_CONTROL_INPUT_SCALER 0x70e
732#define HORIZONTAL_TAPS_2 (1 << 3)
733#define HORIZONTAL_TAPS_5 (4 << 3)
734#define VERTICAL_TAPS_2 (1 << 0)
735#define VERTICAL_TAPS_5 (4 << 0)
736
737#define DC_WIN_WINDOWGROUP_SET_INPUT_SCALER_USAGE 0x711
738#define INPUT_SCALER_USE422 (1 << 2)
739#define INPUT_SCALER_VBYPASS (1 << 1)
740#define INPUT_SCALER_HBYPASS (1 << 0)
741
742#define DC_WIN_BLEND_LAYER_CONTROL 0x716
743#define COLOR_KEY_NONE (0 << 25)
744#define COLOR_KEY_SRC (1 << 25)
745#define COLOR_KEY_DST (2 << 25)
746#define BLEND_BYPASS (1 << 24)
747#define K2(x) (((x) & 0xff) << 16)
748#define K1(x) (((x) & 0xff) << 8)
749#define WINDOW_LAYER_DEPTH(x) (((x) & 0xff) << 0)
750
751#define DC_WIN_BLEND_MATCH_SELECT 0x717
752#define BLEND_FACTOR_DST_ALPHA_ZERO (0 << 12)
753#define BLEND_FACTOR_DST_ALPHA_ONE (1 << 12)
754#define BLEND_FACTOR_DST_ALPHA_NEG_K1_TIMES_SRC (2 << 12)
755#define BLEND_FACTOR_DST_ALPHA_K2 (3 << 12)
756#define BLEND_FACTOR_SRC_ALPHA_ZERO (0 << 8)
757#define BLEND_FACTOR_SRC_ALPHA_K1 (1 << 8)
758#define BLEND_FACTOR_SRC_ALPHA_K2 (2 << 8)
759#define BLEND_FACTOR_SRC_ALPHA_NEG_K1_TIMES_DST (3 << 8)
760#define BLEND_FACTOR_DST_COLOR_ZERO (0 << 4)
761#define BLEND_FACTOR_DST_COLOR_ONE (1 << 4)
762#define BLEND_FACTOR_DST_COLOR_K1 (2 << 4)
763#define BLEND_FACTOR_DST_COLOR_K2 (3 << 4)
764#define BLEND_FACTOR_DST_COLOR_K1_TIMES_DST (4 << 4)
765#define BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_DST (5 << 4)
766#define BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC (6 << 4)
767#define BLEND_FACTOR_DST_COLOR_NEG_K1 (7 << 4)
768#define BLEND_FACTOR_SRC_COLOR_ZERO (0 << 0)
769#define BLEND_FACTOR_SRC_COLOR_ONE (1 << 0)
770#define BLEND_FACTOR_SRC_COLOR_K1 (2 << 0)
771#define BLEND_FACTOR_SRC_COLOR_K1_TIMES_DST (3 << 0)
772#define BLEND_FACTOR_SRC_COLOR_NEG_K1_TIMES_DST (4 << 0)
773#define BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC (5 << 0)
774
775#define DC_WIN_BLEND_NOMATCH_SELECT 0x718
776
777#define DC_WIN_PRECOMP_WGRP_PARAMS 0x724
778#define SWAP_UV (1 << 0)
779
780#define DC_WIN_WINDOW_SET_CONTROL 0x730
781#define CONTROL_CSC_ENABLE (1 << 5)
782
783#define DC_WINBUF_CROPPED_POINT 0x806
784#define OFFSET_Y(x) (((x) & 0xffff) << 16)
785#define OFFSET_X(x) (((x) & 0xffff) << 0)
786
787#endif /* TEGRA_DC_H */