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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (C) 2016 Marek Vasut <marex@denx.de>
4 *
5 * This code is based on drivers/video/fbdev/mxsfb.c :
6 * Copyright (C) 2010 Juergen Beisert, Pengutronix
7 * Copyright (C) 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
8 * Copyright (C) 2008 Embedded Alley Solutions, Inc All Rights Reserved.
9 */
10
11#include <linux/clk.h>
12#include <linux/iopoll.h>
13#include <linux/of_graph.h>
14#include <linux/platform_data/simplefb.h>
15
16#include <video/videomode.h>
17
18#include <drm/drm_atomic_helper.h>
19#include <drm/drm_crtc.h>
20#include <drm/drm_fb_cma_helper.h>
21#include <drm/drm_fb_helper.h>
22#include <drm/drm_gem_cma_helper.h>
23#include <drm/drm_of.h>
24#include <drm/drm_plane_helper.h>
25#include <drm/drm_probe_helper.h>
26#include <drm/drm_simple_kms_helper.h>
27#include <drm/drm_vblank.h>
28
29#include "mxsfb_drv.h"
30#include "mxsfb_regs.h"
31
32#define MXS_SET_ADDR 0x4
33#define MXS_CLR_ADDR 0x8
34#define MODULE_CLKGATE BIT(30)
35#define MODULE_SFTRST BIT(31)
36/* 1 second delay should be plenty of time for block reset */
37#define RESET_TIMEOUT 1000000
38
39static u32 set_hsync_pulse_width(struct mxsfb_drm_private *mxsfb, u32 val)
40{
41 return (val & mxsfb->devdata->hs_wdth_mask) <<
42 mxsfb->devdata->hs_wdth_shift;
43}
44
45/* Setup the MXSFB registers for decoding the pixels out of the framebuffer */
46static int mxsfb_set_pixel_fmt(struct mxsfb_drm_private *mxsfb)
47{
48 struct drm_crtc *crtc = &mxsfb->pipe.crtc;
49 struct drm_device *drm = crtc->dev;
50 const u32 format = crtc->primary->state->fb->format->format;
51 u32 ctrl, ctrl1;
52
53 ctrl = CTRL_BYPASS_COUNT | CTRL_MASTER;
54
55 /*
56 * WARNING: The bus width, CTRL_SET_BUS_WIDTH(), is configured to
57 * match the selected mode here. This differs from the original
58 * MXSFB driver, which had the option to configure the bus width
59 * to arbitrary value. This limitation should not pose an issue.
60 */
61
62 /* CTRL1 contains IRQ config and status bits, preserve those. */
63 ctrl1 = readl(mxsfb->base + LCDC_CTRL1);
64 ctrl1 &= CTRL1_CUR_FRAME_DONE_IRQ_EN | CTRL1_CUR_FRAME_DONE_IRQ;
65
66 switch (format) {
67 case DRM_FORMAT_RGB565:
68 dev_dbg(drm->dev, "Setting up RGB565 mode\n");
69 ctrl |= CTRL_SET_WORD_LENGTH(0);
70 ctrl1 |= CTRL1_SET_BYTE_PACKAGING(0xf);
71 break;
72 case DRM_FORMAT_XRGB8888:
73 dev_dbg(drm->dev, "Setting up XRGB8888 mode\n");
74 ctrl |= CTRL_SET_WORD_LENGTH(3);
75 /* Do not use packed pixels = one pixel per word instead. */
76 ctrl1 |= CTRL1_SET_BYTE_PACKAGING(0x7);
77 break;
78 default:
79 dev_err(drm->dev, "Unhandled pixel format %08x\n", format);
80 return -EINVAL;
81 }
82
83 writel(ctrl1, mxsfb->base + LCDC_CTRL1);
84 writel(ctrl, mxsfb->base + LCDC_CTRL);
85
86 return 0;
87}
88
89static void mxsfb_set_bus_fmt(struct mxsfb_drm_private *mxsfb)
90{
91 struct drm_crtc *crtc = &mxsfb->pipe.crtc;
92 struct drm_device *drm = crtc->dev;
93 u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24;
94 u32 reg;
95
96 reg = readl(mxsfb->base + LCDC_CTRL);
97
98 if (mxsfb->connector->display_info.num_bus_formats)
99 bus_format = mxsfb->connector->display_info.bus_formats[0];
100
101 DRM_DEV_DEBUG_DRIVER(drm->dev, "Using bus_format: 0x%08X\n",
102 bus_format);
103
104 reg &= ~CTRL_BUS_WIDTH_MASK;
105 switch (bus_format) {
106 case MEDIA_BUS_FMT_RGB565_1X16:
107 reg |= CTRL_SET_BUS_WIDTH(STMLCDIF_16BIT);
108 break;
109 case MEDIA_BUS_FMT_RGB666_1X18:
110 reg |= CTRL_SET_BUS_WIDTH(STMLCDIF_18BIT);
111 break;
112 case MEDIA_BUS_FMT_RGB888_1X24:
113 reg |= CTRL_SET_BUS_WIDTH(STMLCDIF_24BIT);
114 break;
115 default:
116 dev_err(drm->dev, "Unknown media bus format %d\n", bus_format);
117 break;
118 }
119 writel(reg, mxsfb->base + LCDC_CTRL);
120}
121
122static void mxsfb_enable_controller(struct mxsfb_drm_private *mxsfb)
123{
124 u32 reg;
125
126 if (mxsfb->clk_disp_axi)
127 clk_prepare_enable(mxsfb->clk_disp_axi);
128 clk_prepare_enable(mxsfb->clk);
129
130 /* If it was disabled, re-enable the mode again */
131 writel(CTRL_DOTCLK_MODE, mxsfb->base + LCDC_CTRL + REG_SET);
132
133 /* Enable the SYNC signals first, then the DMA engine */
134 reg = readl(mxsfb->base + LCDC_VDCTRL4);
135 reg |= VDCTRL4_SYNC_SIGNALS_ON;
136 writel(reg, mxsfb->base + LCDC_VDCTRL4);
137
138 writel(CTRL_RUN, mxsfb->base + LCDC_CTRL + REG_SET);
139}
140
141static void mxsfb_disable_controller(struct mxsfb_drm_private *mxsfb)
142{
143 u32 reg;
144
145 /*
146 * Even if we disable the controller here, it will still continue
147 * until its FIFOs are running out of data
148 */
149 writel(CTRL_DOTCLK_MODE, mxsfb->base + LCDC_CTRL + REG_CLR);
150
151 readl_poll_timeout(mxsfb->base + LCDC_CTRL, reg, !(reg & CTRL_RUN),
152 0, 1000);
153
154 reg = readl(mxsfb->base + LCDC_VDCTRL4);
155 reg &= ~VDCTRL4_SYNC_SIGNALS_ON;
156 writel(reg, mxsfb->base + LCDC_VDCTRL4);
157
158 clk_disable_unprepare(mxsfb->clk);
159 if (mxsfb->clk_disp_axi)
160 clk_disable_unprepare(mxsfb->clk_disp_axi);
161}
162
163/*
164 * Clear the bit and poll it cleared. This is usually called with
165 * a reset address and mask being either SFTRST(bit 31) or CLKGATE
166 * (bit 30).
167 */
168static int clear_poll_bit(void __iomem *addr, u32 mask)
169{
170 u32 reg;
171
172 writel(mask, addr + MXS_CLR_ADDR);
173 return readl_poll_timeout(addr, reg, !(reg & mask), 0, RESET_TIMEOUT);
174}
175
176static int mxsfb_reset_block(void __iomem *reset_addr)
177{
178 int ret;
179
180 ret = clear_poll_bit(reset_addr, MODULE_SFTRST);
181 if (ret)
182 return ret;
183
184 writel(MODULE_CLKGATE, reset_addr + MXS_CLR_ADDR);
185
186 ret = clear_poll_bit(reset_addr, MODULE_SFTRST);
187 if (ret)
188 return ret;
189
190 return clear_poll_bit(reset_addr, MODULE_CLKGATE);
191}
192
193static dma_addr_t mxsfb_get_fb_paddr(struct mxsfb_drm_private *mxsfb)
194{
195 struct drm_framebuffer *fb = mxsfb->pipe.plane.state->fb;
196 struct drm_gem_cma_object *gem;
197
198 if (!fb)
199 return 0;
200
201 gem = drm_fb_cma_get_gem_obj(fb, 0);
202 if (!gem)
203 return 0;
204
205 return gem->paddr;
206}
207
208static void mxsfb_crtc_mode_set_nofb(struct mxsfb_drm_private *mxsfb)
209{
210 struct drm_device *drm = mxsfb->pipe.crtc.dev;
211 struct drm_display_mode *m = &mxsfb->pipe.crtc.state->adjusted_mode;
212 u32 bus_flags = mxsfb->connector->display_info.bus_flags;
213 u32 vdctrl0, vsync_pulse_len, hsync_pulse_len;
214 int err;
215
216 /*
217 * It seems, you can't re-program the controller if it is still
218 * running. This may lead to shifted pictures (FIFO issue?), so
219 * first stop the controller and drain its FIFOs.
220 */
221
222 /* Mandatory eLCDIF reset as per the Reference Manual */
223 err = mxsfb_reset_block(mxsfb->base);
224 if (err)
225 return;
226
227 /* Clear the FIFOs */
228 writel(CTRL1_FIFO_CLEAR, mxsfb->base + LCDC_CTRL1 + REG_SET);
229
230 err = mxsfb_set_pixel_fmt(mxsfb);
231 if (err)
232 return;
233
234 clk_set_rate(mxsfb->clk, m->crtc_clock * 1000);
235
236 if (mxsfb->bridge && mxsfb->bridge->timings)
237 bus_flags = mxsfb->bridge->timings->input_bus_flags;
238
239 DRM_DEV_DEBUG_DRIVER(drm->dev, "Pixel clock: %dkHz (actual: %dkHz)\n",
240 m->crtc_clock,
241 (int)(clk_get_rate(mxsfb->clk) / 1000));
242 DRM_DEV_DEBUG_DRIVER(drm->dev, "Connector bus_flags: 0x%08X\n",
243 bus_flags);
244 DRM_DEV_DEBUG_DRIVER(drm->dev, "Mode flags: 0x%08X\n", m->flags);
245
246 writel(TRANSFER_COUNT_SET_VCOUNT(m->crtc_vdisplay) |
247 TRANSFER_COUNT_SET_HCOUNT(m->crtc_hdisplay),
248 mxsfb->base + mxsfb->devdata->transfer_count);
249
250 vsync_pulse_len = m->crtc_vsync_end - m->crtc_vsync_start;
251
252 vdctrl0 = VDCTRL0_ENABLE_PRESENT | /* Always in DOTCLOCK mode */
253 VDCTRL0_VSYNC_PERIOD_UNIT |
254 VDCTRL0_VSYNC_PULSE_WIDTH_UNIT |
255 VDCTRL0_SET_VSYNC_PULSE_WIDTH(vsync_pulse_len);
256 if (m->flags & DRM_MODE_FLAG_PHSYNC)
257 vdctrl0 |= VDCTRL0_HSYNC_ACT_HIGH;
258 if (m->flags & DRM_MODE_FLAG_PVSYNC)
259 vdctrl0 |= VDCTRL0_VSYNC_ACT_HIGH;
260 /* Make sure Data Enable is high active by default */
261 if (!(bus_flags & DRM_BUS_FLAG_DE_LOW))
262 vdctrl0 |= VDCTRL0_ENABLE_ACT_HIGH;
263 /*
264 * DRM_BUS_FLAG_PIXDATA_DRIVE_ defines are controller centric,
265 * controllers VDCTRL0_DOTCLK is display centric.
266 * Drive on positive edge -> display samples on falling edge
267 * DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE -> VDCTRL0_DOTCLK_ACT_FALLING
268 */
269 if (bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE)
270 vdctrl0 |= VDCTRL0_DOTCLK_ACT_FALLING;
271
272 writel(vdctrl0, mxsfb->base + LCDC_VDCTRL0);
273
274 mxsfb_set_bus_fmt(mxsfb);
275
276 /* Frame length in lines. */
277 writel(m->crtc_vtotal, mxsfb->base + LCDC_VDCTRL1);
278
279 /* Line length in units of clocks or pixels. */
280 hsync_pulse_len = m->crtc_hsync_end - m->crtc_hsync_start;
281 writel(set_hsync_pulse_width(mxsfb, hsync_pulse_len) |
282 VDCTRL2_SET_HSYNC_PERIOD(m->crtc_htotal),
283 mxsfb->base + LCDC_VDCTRL2);
284
285 writel(SET_HOR_WAIT_CNT(m->crtc_htotal - m->crtc_hsync_start) |
286 SET_VERT_WAIT_CNT(m->crtc_vtotal - m->crtc_vsync_start),
287 mxsfb->base + LCDC_VDCTRL3);
288
289 writel(SET_DOTCLK_H_VALID_DATA_CNT(m->hdisplay),
290 mxsfb->base + LCDC_VDCTRL4);
291}
292
293void mxsfb_crtc_enable(struct mxsfb_drm_private *mxsfb)
294{
295 dma_addr_t paddr;
296
297 mxsfb_enable_axi_clk(mxsfb);
298 mxsfb_crtc_mode_set_nofb(mxsfb);
299
300 /* Write cur_buf as well to avoid an initial corrupt frame */
301 paddr = mxsfb_get_fb_paddr(mxsfb);
302 if (paddr) {
303 writel(paddr, mxsfb->base + mxsfb->devdata->cur_buf);
304 writel(paddr, mxsfb->base + mxsfb->devdata->next_buf);
305 }
306
307 mxsfb_enable_controller(mxsfb);
308}
309
310void mxsfb_crtc_disable(struct mxsfb_drm_private *mxsfb)
311{
312 mxsfb_disable_controller(mxsfb);
313 mxsfb_disable_axi_clk(mxsfb);
314}
315
316void mxsfb_plane_atomic_update(struct mxsfb_drm_private *mxsfb,
317 struct drm_plane_state *state)
318{
319 struct drm_simple_display_pipe *pipe = &mxsfb->pipe;
320 struct drm_crtc *crtc = &pipe->crtc;
321 struct drm_pending_vblank_event *event;
322 dma_addr_t paddr;
323
324 spin_lock_irq(&crtc->dev->event_lock);
325 event = crtc->state->event;
326 if (event) {
327 crtc->state->event = NULL;
328
329 if (drm_crtc_vblank_get(crtc) == 0) {
330 drm_crtc_arm_vblank_event(crtc, event);
331 } else {
332 drm_crtc_send_vblank_event(crtc, event);
333 }
334 }
335 spin_unlock_irq(&crtc->dev->event_lock);
336
337 paddr = mxsfb_get_fb_paddr(mxsfb);
338 if (paddr) {
339 mxsfb_enable_axi_clk(mxsfb);
340 writel(paddr, mxsfb->base + mxsfb->devdata->next_buf);
341 mxsfb_disable_axi_clk(mxsfb);
342 }
343}