1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Copyright (c) 2016, The Linux Foundation. All rights reserved.
  4 */
  5
  6#include <linux/delay.h>
  7
  8#include "dsi_phy.h"
  9#include "dsi.xml.h"
 10
 11#define PHY_14NM_CKLN_IDX	4
 12
 13static void dsi_14nm_dphy_set_timing(struct msm_dsi_phy *phy,
 14				     struct msm_dsi_dphy_timing *timing,
 15				     int lane_idx)
 16{
 17	void __iomem *base = phy->lane_base;
 18	bool clk_ln = (lane_idx == PHY_14NM_CKLN_IDX);
 19	u32 zero = clk_ln ? timing->clk_zero : timing->hs_zero;
 20	u32 prepare = clk_ln ? timing->clk_prepare : timing->hs_prepare;
 21	u32 trail = clk_ln ? timing->clk_trail : timing->hs_trail;
 22	u32 rqst = clk_ln ? timing->hs_rqst_ckln : timing->hs_rqst;
 23	u32 prep_dly = clk_ln ? timing->hs_prep_dly_ckln : timing->hs_prep_dly;
 24	u32 halfbyte_en = clk_ln ? timing->hs_halfbyte_en_ckln :
 25				   timing->hs_halfbyte_en;
 26
 27	dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_4(lane_idx),
 28		      DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT(timing->hs_exit));
 29	dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_5(lane_idx),
 30		      DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO(zero));
 31	dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_6(lane_idx),
 32		      DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE(prepare));
 33	dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_7(lane_idx),
 34		      DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL(trail));
 35	dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_8(lane_idx),
 36		      DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST(rqst));
 37	dsi_phy_write(base + REG_DSI_14nm_PHY_LN_CFG0(lane_idx),
 38		      DSI_14nm_PHY_LN_CFG0_PREPARE_DLY(prep_dly));
 39	dsi_phy_write(base + REG_DSI_14nm_PHY_LN_CFG1(lane_idx),
 40		      halfbyte_en ? DSI_14nm_PHY_LN_CFG1_HALFBYTECLK_EN : 0);
 41	dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_9(lane_idx),
 42		      DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO(timing->ta_go) |
 43		      DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE(timing->ta_sure));
 44	dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_10(lane_idx),
 45		      DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET(timing->ta_get));
 46	dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_11(lane_idx),
 47		      DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD(0xa0));
 48}
 49
 50static int dsi_14nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
 51			       struct msm_dsi_phy_clk_request *clk_req)
 52{
 53	struct msm_dsi_dphy_timing *timing = &phy->timing;
 54	u32 data;
 55	int i;
 56	int ret;
 57	void __iomem *base = phy->base;
 58	void __iomem *lane_base = phy->lane_base;
 59
 60	if (msm_dsi_dphy_timing_calc_v2(timing, clk_req)) {
 61		DRM_DEV_ERROR(&phy->pdev->dev,
 62			"%s: D-PHY timing calculation failed\n", __func__);
 63		return -EINVAL;
 64	}
 65
 66	data = 0x1c;
 67	if (phy->usecase != MSM_DSI_PHY_STANDALONE)
 68		data |= DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL(32);
 69	dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_LDO_CNTRL, data);
 70
 71	dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL, 0x1);
 72
 73	/* 4 data lanes + 1 clk lane configuration */
 74	for (i = 0; i < 5; i++) {
 75		dsi_phy_write(lane_base + REG_DSI_14nm_PHY_LN_VREG_CNTRL(i),
 76			      0x1d);
 77
 78		dsi_phy_write(lane_base +
 79			      REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0(i), 0xff);
 80		dsi_phy_write(lane_base +
 81			      REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1(i),
 82			      (i == PHY_14NM_CKLN_IDX) ? 0x00 : 0x06);
 83
 84		dsi_phy_write(lane_base + REG_DSI_14nm_PHY_LN_CFG3(i),
 85			      (i == PHY_14NM_CKLN_IDX) ? 0x8f : 0x0f);
 86		dsi_phy_write(lane_base + REG_DSI_14nm_PHY_LN_CFG2(i), 0x10);
 87		dsi_phy_write(lane_base + REG_DSI_14nm_PHY_LN_TEST_DATAPATH(i),
 88			      0);
 89		dsi_phy_write(lane_base + REG_DSI_14nm_PHY_LN_TEST_STR(i),
 90			      0x88);
 91
 92		dsi_14nm_dphy_set_timing(phy, timing, i);
 93	}
 94
 95	/* Make sure PLL is not start */
 96	dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL, 0x00);
 97
 98	wmb(); /* make sure everything is written before reset and enable */
 99
100	/* reset digital block */
101	dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0x80);
102	wmb(); /* ensure reset is asserted */
103	udelay(100);
104	dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0x00);
105
106	msm_dsi_phy_set_src_pll(phy, src_pll_id,
107				REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL,
108				DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL);
109
110	ret = msm_dsi_pll_set_usecase(phy->pll, phy->usecase);
111	if (ret) {
112		DRM_DEV_ERROR(&phy->pdev->dev, "%s: set pll usecase failed, %d\n",
113			__func__, ret);
114		return ret;
115	}
116
117	/* Remove power down from PLL and all lanes */
118	dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_CTRL_0, 0xff);
119
120	return 0;
121}
122
123static void dsi_14nm_phy_disable(struct msm_dsi_phy *phy)
124{
125	dsi_phy_write(phy->base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL, 0);
126	dsi_phy_write(phy->base + REG_DSI_14nm_PHY_CMN_CTRL_0, 0);
127
128	/* ensure that the phy is completely disabled */
129	wmb();
130}
131
132static int dsi_14nm_phy_init(struct msm_dsi_phy *phy)
133{
134	struct platform_device *pdev = phy->pdev;
135
136	phy->lane_base = msm_ioremap(pdev, "dsi_phy_lane",
137				"DSI_PHY_LANE");
138	if (IS_ERR(phy->lane_base)) {
139		DRM_DEV_ERROR(&pdev->dev, "%s: failed to map phy lane base\n",
140			__func__);
141		return -ENOMEM;
142	}
143
144	return 0;
145}
146
147const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = {
148	.type = MSM_DSI_PHY_14NM,
149	.src_pll_truthtable = { {false, false}, {true, false} },
150	.reg_cfg = {
151		.num = 1,
152		.regs = {
153			{"vcca", 17000, 32},
154		},
155	},
156	.ops = {
157		.enable = dsi_14nm_phy_enable,
158		.disable = dsi_14nm_phy_disable,
159		.init = dsi_14nm_phy_init,
160	},
161	.io_start = { 0x994400, 0x996400 },
162	.num_dsi_phy = 2,
163};
164
165const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = {
166	.type = MSM_DSI_PHY_14NM,
167	.src_pll_truthtable = { {false, false}, {true, false} },
168	.reg_cfg = {
169		.num = 1,
170		.regs = {
171			{"vcca", 17000, 32},
172		},
173	},
174	.ops = {
175		.enable = dsi_14nm_phy_enable,
176		.disable = dsi_14nm_phy_disable,
177		.init = dsi_14nm_phy_init,
178	},
179	.io_start = { 0xc994400, 0xc996000 },
180	.num_dsi_phy = 2,
181};