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1/*
2 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/platform_device.h>
15
16#include "dsi_phy.h"
17
18#define S_DIV_ROUND_UP(n, d) \
19 (((n) >= 0) ? (((n) + (d) - 1) / (d)) : (((n) - (d) + 1) / (d)))
20
21static inline s32 linear_inter(s32 tmax, s32 tmin, s32 percent,
22 s32 min_result, bool even)
23{
24 s32 v;
25
26 v = (tmax - tmin) * percent;
27 v = S_DIV_ROUND_UP(v, 100) + tmin;
28 if (even && (v & 0x1))
29 return max_t(s32, min_result, v - 1);
30 else
31 return max_t(s32, min_result, v);
32}
33
34static void dsi_dphy_timing_calc_clk_zero(struct msm_dsi_dphy_timing *timing,
35 s32 ui, s32 coeff, s32 pcnt)
36{
37 s32 tmax, tmin, clk_z;
38 s32 temp;
39
40 /* reset */
41 temp = 300 * coeff - ((timing->clk_prepare >> 1) + 1) * 2 * ui;
42 tmin = S_DIV_ROUND_UP(temp, ui) - 2;
43 if (tmin > 255) {
44 tmax = 511;
45 clk_z = linear_inter(2 * tmin, tmin, pcnt, 0, true);
46 } else {
47 tmax = 255;
48 clk_z = linear_inter(tmax, tmin, pcnt, 0, true);
49 }
50
51 /* adjust */
52 temp = (timing->hs_rqst + timing->clk_prepare + clk_z) & 0x7;
53 timing->clk_zero = clk_z + 8 - temp;
54}
55
56int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing *timing,
57 const unsigned long bit_rate, const unsigned long esc_rate)
58{
59 s32 ui, lpx;
60 s32 tmax, tmin;
61 s32 pcnt0 = 10;
62 s32 pcnt1 = (bit_rate > 1200000000) ? 15 : 10;
63 s32 pcnt2 = 10;
64 s32 pcnt3 = (bit_rate > 180000000) ? 10 : 40;
65 s32 coeff = 1000; /* Precision, should avoid overflow */
66 s32 temp;
67
68 if (!bit_rate || !esc_rate)
69 return -EINVAL;
70
71 ui = mult_frac(NSEC_PER_MSEC, coeff, bit_rate / 1000);
72 lpx = mult_frac(NSEC_PER_MSEC, coeff, esc_rate / 1000);
73
74 tmax = S_DIV_ROUND_UP(95 * coeff, ui) - 2;
75 tmin = S_DIV_ROUND_UP(38 * coeff, ui) - 2;
76 timing->clk_prepare = linear_inter(tmax, tmin, pcnt0, 0, true);
77
78 temp = lpx / ui;
79 if (temp & 0x1)
80 timing->hs_rqst = temp;
81 else
82 timing->hs_rqst = max_t(s32, 0, temp - 2);
83
84 /* Calculate clk_zero after clk_prepare and hs_rqst */
85 dsi_dphy_timing_calc_clk_zero(timing, ui, coeff, pcnt2);
86
87 temp = 105 * coeff + 12 * ui - 20 * coeff;
88 tmax = S_DIV_ROUND_UP(temp, ui) - 2;
89 tmin = S_DIV_ROUND_UP(60 * coeff, ui) - 2;
90 timing->clk_trail = linear_inter(tmax, tmin, pcnt3, 0, true);
91
92 temp = 85 * coeff + 6 * ui;
93 tmax = S_DIV_ROUND_UP(temp, ui) - 2;
94 temp = 40 * coeff + 4 * ui;
95 tmin = S_DIV_ROUND_UP(temp, ui) - 2;
96 timing->hs_prepare = linear_inter(tmax, tmin, pcnt1, 0, true);
97
98 tmax = 255;
99 temp = ((timing->hs_prepare >> 1) + 1) * 2 * ui + 2 * ui;
100 temp = 145 * coeff + 10 * ui - temp;
101 tmin = S_DIV_ROUND_UP(temp, ui) - 2;
102 timing->hs_zero = linear_inter(tmax, tmin, pcnt2, 24, true);
103
104 temp = 105 * coeff + 12 * ui - 20 * coeff;
105 tmax = S_DIV_ROUND_UP(temp, ui) - 2;
106 temp = 60 * coeff + 4 * ui;
107 tmin = DIV_ROUND_UP(temp, ui) - 2;
108 timing->hs_trail = linear_inter(tmax, tmin, pcnt3, 0, true);
109
110 tmax = 255;
111 tmin = S_DIV_ROUND_UP(100 * coeff, ui) - 2;
112 timing->hs_exit = linear_inter(tmax, tmin, pcnt2, 0, true);
113
114 tmax = 63;
115 temp = ((timing->hs_exit >> 1) + 1) * 2 * ui;
116 temp = 60 * coeff + 52 * ui - 24 * ui - temp;
117 tmin = S_DIV_ROUND_UP(temp, 8 * ui) - 1;
118 timing->clk_post = linear_inter(tmax, tmin, pcnt2, 0, false);
119
120 tmax = 63;
121 temp = ((timing->clk_prepare >> 1) + 1) * 2 * ui;
122 temp += ((timing->clk_zero >> 1) + 1) * 2 * ui;
123 temp += 8 * ui + lpx;
124 tmin = S_DIV_ROUND_UP(temp, 8 * ui) - 1;
125 if (tmin > tmax) {
126 temp = linear_inter(2 * tmax, tmin, pcnt2, 0, false);
127 timing->clk_pre = temp >> 1;
128 } else {
129 timing->clk_pre = linear_inter(tmax, tmin, pcnt2, 0, false);
130 }
131
132 timing->ta_go = 3;
133 timing->ta_sure = 0;
134 timing->ta_get = 4;
135
136 DBG("PHY timings: %d, %d, %d, %d, %d, %d, %d, %d, %d, %d",
137 timing->clk_pre, timing->clk_post, timing->clk_zero,
138 timing->clk_trail, timing->clk_prepare, timing->hs_exit,
139 timing->hs_zero, timing->hs_prepare, timing->hs_trail,
140 timing->hs_rqst);
141
142 return 0;
143}
144
145void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg,
146 u32 bit_mask)
147{
148 int phy_id = phy->id;
149 u32 val;
150
151 if ((phy_id >= DSI_MAX) || (pll_id >= DSI_MAX))
152 return;
153
154 val = dsi_phy_read(phy->base + reg);
155
156 if (phy->cfg->src_pll_truthtable[phy_id][pll_id])
157 dsi_phy_write(phy->base + reg, val | bit_mask);
158 else
159 dsi_phy_write(phy->base + reg, val & (~bit_mask));
160}
161
162static int dsi_phy_regulator_init(struct msm_dsi_phy *phy)
163{
164 struct regulator_bulk_data *s = phy->supplies;
165 const struct dsi_reg_entry *regs = phy->cfg->reg_cfg.regs;
166 struct device *dev = &phy->pdev->dev;
167 int num = phy->cfg->reg_cfg.num;
168 int i, ret;
169
170 for (i = 0; i < num; i++)
171 s[i].supply = regs[i].name;
172
173 ret = devm_regulator_bulk_get(dev, num, s);
174 if (ret < 0) {
175 dev_err(dev, "%s: failed to init regulator, ret=%d\n",
176 __func__, ret);
177 return ret;
178 }
179
180 for (i = 0; i < num; i++) {
181 if (regulator_can_change_voltage(s[i].consumer)) {
182 ret = regulator_set_voltage(s[i].consumer,
183 regs[i].min_voltage, regs[i].max_voltage);
184 if (ret < 0) {
185 dev_err(dev,
186 "regulator %d set voltage failed, %d\n",
187 i, ret);
188 return ret;
189 }
190 }
191 }
192
193 return 0;
194}
195
196static void dsi_phy_regulator_disable(struct msm_dsi_phy *phy)
197{
198 struct regulator_bulk_data *s = phy->supplies;
199 const struct dsi_reg_entry *regs = phy->cfg->reg_cfg.regs;
200 int num = phy->cfg->reg_cfg.num;
201 int i;
202
203 DBG("");
204 for (i = num - 1; i >= 0; i--)
205 if (regs[i].disable_load >= 0)
206 regulator_set_load(s[i].consumer, regs[i].disable_load);
207
208 regulator_bulk_disable(num, s);
209}
210
211static int dsi_phy_regulator_enable(struct msm_dsi_phy *phy)
212{
213 struct regulator_bulk_data *s = phy->supplies;
214 const struct dsi_reg_entry *regs = phy->cfg->reg_cfg.regs;
215 struct device *dev = &phy->pdev->dev;
216 int num = phy->cfg->reg_cfg.num;
217 int ret, i;
218
219 DBG("");
220 for (i = 0; i < num; i++) {
221 if (regs[i].enable_load >= 0) {
222 ret = regulator_set_load(s[i].consumer,
223 regs[i].enable_load);
224 if (ret < 0) {
225 dev_err(dev,
226 "regulator %d set op mode failed, %d\n",
227 i, ret);
228 goto fail;
229 }
230 }
231 }
232
233 ret = regulator_bulk_enable(num, s);
234 if (ret < 0) {
235 dev_err(dev, "regulator enable failed, %d\n", ret);
236 goto fail;
237 }
238
239 return 0;
240
241fail:
242 for (i--; i >= 0; i--)
243 regulator_set_load(s[i].consumer, regs[i].disable_load);
244 return ret;
245}
246
247static int dsi_phy_enable_resource(struct msm_dsi_phy *phy)
248{
249 struct device *dev = &phy->pdev->dev;
250 int ret;
251
252 pm_runtime_get_sync(dev);
253
254 ret = clk_prepare_enable(phy->ahb_clk);
255 if (ret) {
256 dev_err(dev, "%s: can't enable ahb clk, %d\n", __func__, ret);
257 pm_runtime_put_sync(dev);
258 }
259
260 return ret;
261}
262
263static void dsi_phy_disable_resource(struct msm_dsi_phy *phy)
264{
265 clk_disable_unprepare(phy->ahb_clk);
266 pm_runtime_put_sync(&phy->pdev->dev);
267}
268
269static const struct of_device_id dsi_phy_dt_match[] = {
270#ifdef CONFIG_DRM_MSM_DSI_28NM_PHY
271 { .compatible = "qcom,dsi-phy-28nm-hpm",
272 .data = &dsi_phy_28nm_hpm_cfgs },
273 { .compatible = "qcom,dsi-phy-28nm-lp",
274 .data = &dsi_phy_28nm_lp_cfgs },
275#endif
276#ifdef CONFIG_DRM_MSM_DSI_20NM_PHY
277 { .compatible = "qcom,dsi-phy-20nm",
278 .data = &dsi_phy_20nm_cfgs },
279#endif
280#ifdef CONFIG_DRM_MSM_DSI_28NM_8960_PHY
281 { .compatible = "qcom,dsi-phy-28nm-8960",
282 .data = &dsi_phy_28nm_8960_cfgs },
283#endif
284 {}
285};
286
287static int dsi_phy_driver_probe(struct platform_device *pdev)
288{
289 struct msm_dsi_phy *phy;
290 struct device *dev = &pdev->dev;
291 const struct of_device_id *match;
292 int ret;
293
294 phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
295 if (!phy)
296 return -ENOMEM;
297
298 match = of_match_node(dsi_phy_dt_match, dev->of_node);
299 if (!match)
300 return -ENODEV;
301
302 phy->cfg = match->data;
303 phy->pdev = pdev;
304
305 ret = of_property_read_u32(dev->of_node,
306 "qcom,dsi-phy-index", &phy->id);
307 if (ret) {
308 dev_err(dev, "%s: PHY index not specified, %d\n",
309 __func__, ret);
310 goto fail;
311 }
312
313 phy->regulator_ldo_mode = of_property_read_bool(dev->of_node,
314 "qcom,dsi-phy-regulator-ldo-mode");
315
316 phy->base = msm_ioremap(pdev, "dsi_phy", "DSI_PHY");
317 if (IS_ERR(phy->base)) {
318 dev_err(dev, "%s: failed to map phy base\n", __func__);
319 ret = -ENOMEM;
320 goto fail;
321 }
322
323 phy->reg_base = msm_ioremap(pdev, "dsi_phy_regulator",
324 "DSI_PHY_REG");
325 if (IS_ERR(phy->reg_base)) {
326 dev_err(dev, "%s: failed to map phy regulator base\n",
327 __func__);
328 ret = -ENOMEM;
329 goto fail;
330 }
331
332 ret = dsi_phy_regulator_init(phy);
333 if (ret) {
334 dev_err(dev, "%s: failed to init regulator\n", __func__);
335 goto fail;
336 }
337
338 phy->ahb_clk = devm_clk_get(dev, "iface_clk");
339 if (IS_ERR(phy->ahb_clk)) {
340 dev_err(dev, "%s: Unable to get ahb clk\n", __func__);
341 ret = PTR_ERR(phy->ahb_clk);
342 goto fail;
343 }
344
345 /* PLL init will call into clk_register which requires
346 * register access, so we need to enable power and ahb clock.
347 */
348 ret = dsi_phy_enable_resource(phy);
349 if (ret)
350 goto fail;
351
352 phy->pll = msm_dsi_pll_init(pdev, phy->cfg->type, phy->id);
353 if (!phy->pll)
354 dev_info(dev,
355 "%s: pll init failed, need separate pll clk driver\n",
356 __func__);
357
358 dsi_phy_disable_resource(phy);
359
360 platform_set_drvdata(pdev, phy);
361
362 return 0;
363
364fail:
365 return ret;
366}
367
368static int dsi_phy_driver_remove(struct platform_device *pdev)
369{
370 struct msm_dsi_phy *phy = platform_get_drvdata(pdev);
371
372 if (phy && phy->pll) {
373 msm_dsi_pll_destroy(phy->pll);
374 phy->pll = NULL;
375 }
376
377 platform_set_drvdata(pdev, NULL);
378
379 return 0;
380}
381
382static struct platform_driver dsi_phy_platform_driver = {
383 .probe = dsi_phy_driver_probe,
384 .remove = dsi_phy_driver_remove,
385 .driver = {
386 .name = "msm_dsi_phy",
387 .of_match_table = dsi_phy_dt_match,
388 },
389};
390
391void __init msm_dsi_phy_driver_register(void)
392{
393 platform_driver_register(&dsi_phy_platform_driver);
394}
395
396void __exit msm_dsi_phy_driver_unregister(void)
397{
398 platform_driver_unregister(&dsi_phy_platform_driver);
399}
400
401int msm_dsi_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
402 const unsigned long bit_rate, const unsigned long esc_rate)
403{
404 struct device *dev = &phy->pdev->dev;
405 int ret;
406
407 if (!phy || !phy->cfg->ops.enable)
408 return -EINVAL;
409
410 ret = dsi_phy_regulator_enable(phy);
411 if (ret) {
412 dev_err(dev, "%s: regulator enable failed, %d\n",
413 __func__, ret);
414 return ret;
415 }
416
417 ret = phy->cfg->ops.enable(phy, src_pll_id, bit_rate, esc_rate);
418 if (ret) {
419 dev_err(dev, "%s: phy enable failed, %d\n", __func__, ret);
420 dsi_phy_regulator_disable(phy);
421 return ret;
422 }
423
424 return 0;
425}
426
427void msm_dsi_phy_disable(struct msm_dsi_phy *phy)
428{
429 if (!phy || !phy->cfg->ops.disable)
430 return;
431
432 phy->cfg->ops.disable(phy);
433
434 dsi_phy_regulator_disable(phy);
435}
436
437void msm_dsi_phy_get_clk_pre_post(struct msm_dsi_phy *phy,
438 u32 *clk_pre, u32 *clk_post)
439{
440 if (!phy)
441 return;
442
443 if (clk_pre)
444 *clk_pre = phy->timing.clk_pre;
445 if (clk_post)
446 *clk_post = phy->timing.clk_post;
447}
448
449struct msm_dsi_pll *msm_dsi_phy_get_pll(struct msm_dsi_phy *phy)
450{
451 if (!phy)
452 return NULL;
453
454 return phy->pll;
455}
456
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
4 */
5
6#include <linux/platform_device.h>
7
8#include "dsi_phy.h"
9
10#define S_DIV_ROUND_UP(n, d) \
11 (((n) >= 0) ? (((n) + (d) - 1) / (d)) : (((n) - (d) + 1) / (d)))
12
13static inline s32 linear_inter(s32 tmax, s32 tmin, s32 percent,
14 s32 min_result, bool even)
15{
16 s32 v;
17
18 v = (tmax - tmin) * percent;
19 v = S_DIV_ROUND_UP(v, 100) + tmin;
20 if (even && (v & 0x1))
21 return max_t(s32, min_result, v - 1);
22 else
23 return max_t(s32, min_result, v);
24}
25
26static void dsi_dphy_timing_calc_clk_zero(struct msm_dsi_dphy_timing *timing,
27 s32 ui, s32 coeff, s32 pcnt)
28{
29 s32 tmax, tmin, clk_z;
30 s32 temp;
31
32 /* reset */
33 temp = 300 * coeff - ((timing->clk_prepare >> 1) + 1) * 2 * ui;
34 tmin = S_DIV_ROUND_UP(temp, ui) - 2;
35 if (tmin > 255) {
36 tmax = 511;
37 clk_z = linear_inter(2 * tmin, tmin, pcnt, 0, true);
38 } else {
39 tmax = 255;
40 clk_z = linear_inter(tmax, tmin, pcnt, 0, true);
41 }
42
43 /* adjust */
44 temp = (timing->hs_rqst + timing->clk_prepare + clk_z) & 0x7;
45 timing->clk_zero = clk_z + 8 - temp;
46}
47
48int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing *timing,
49 struct msm_dsi_phy_clk_request *clk_req)
50{
51 const unsigned long bit_rate = clk_req->bitclk_rate;
52 const unsigned long esc_rate = clk_req->escclk_rate;
53 s32 ui, lpx;
54 s32 tmax, tmin;
55 s32 pcnt0 = 10;
56 s32 pcnt1 = (bit_rate > 1200000000) ? 15 : 10;
57 s32 pcnt2 = 10;
58 s32 pcnt3 = (bit_rate > 180000000) ? 10 : 40;
59 s32 coeff = 1000; /* Precision, should avoid overflow */
60 s32 temp;
61
62 if (!bit_rate || !esc_rate)
63 return -EINVAL;
64
65 ui = mult_frac(NSEC_PER_MSEC, coeff, bit_rate / 1000);
66 lpx = mult_frac(NSEC_PER_MSEC, coeff, esc_rate / 1000);
67
68 tmax = S_DIV_ROUND_UP(95 * coeff, ui) - 2;
69 tmin = S_DIV_ROUND_UP(38 * coeff, ui) - 2;
70 timing->clk_prepare = linear_inter(tmax, tmin, pcnt0, 0, true);
71
72 temp = lpx / ui;
73 if (temp & 0x1)
74 timing->hs_rqst = temp;
75 else
76 timing->hs_rqst = max_t(s32, 0, temp - 2);
77
78 /* Calculate clk_zero after clk_prepare and hs_rqst */
79 dsi_dphy_timing_calc_clk_zero(timing, ui, coeff, pcnt2);
80
81 temp = 105 * coeff + 12 * ui - 20 * coeff;
82 tmax = S_DIV_ROUND_UP(temp, ui) - 2;
83 tmin = S_DIV_ROUND_UP(60 * coeff, ui) - 2;
84 timing->clk_trail = linear_inter(tmax, tmin, pcnt3, 0, true);
85
86 temp = 85 * coeff + 6 * ui;
87 tmax = S_DIV_ROUND_UP(temp, ui) - 2;
88 temp = 40 * coeff + 4 * ui;
89 tmin = S_DIV_ROUND_UP(temp, ui) - 2;
90 timing->hs_prepare = linear_inter(tmax, tmin, pcnt1, 0, true);
91
92 tmax = 255;
93 temp = ((timing->hs_prepare >> 1) + 1) * 2 * ui + 2 * ui;
94 temp = 145 * coeff + 10 * ui - temp;
95 tmin = S_DIV_ROUND_UP(temp, ui) - 2;
96 timing->hs_zero = linear_inter(tmax, tmin, pcnt2, 24, true);
97
98 temp = 105 * coeff + 12 * ui - 20 * coeff;
99 tmax = S_DIV_ROUND_UP(temp, ui) - 2;
100 temp = 60 * coeff + 4 * ui;
101 tmin = DIV_ROUND_UP(temp, ui) - 2;
102 timing->hs_trail = linear_inter(tmax, tmin, pcnt3, 0, true);
103
104 tmax = 255;
105 tmin = S_DIV_ROUND_UP(100 * coeff, ui) - 2;
106 timing->hs_exit = linear_inter(tmax, tmin, pcnt2, 0, true);
107
108 tmax = 63;
109 temp = ((timing->hs_exit >> 1) + 1) * 2 * ui;
110 temp = 60 * coeff + 52 * ui - 24 * ui - temp;
111 tmin = S_DIV_ROUND_UP(temp, 8 * ui) - 1;
112 timing->shared_timings.clk_post = linear_inter(tmax, tmin, pcnt2, 0,
113 false);
114 tmax = 63;
115 temp = ((timing->clk_prepare >> 1) + 1) * 2 * ui;
116 temp += ((timing->clk_zero >> 1) + 1) * 2 * ui;
117 temp += 8 * ui + lpx;
118 tmin = S_DIV_ROUND_UP(temp, 8 * ui) - 1;
119 if (tmin > tmax) {
120 temp = linear_inter(2 * tmax, tmin, pcnt2, 0, false);
121 timing->shared_timings.clk_pre = temp >> 1;
122 timing->shared_timings.clk_pre_inc_by_2 = true;
123 } else {
124 timing->shared_timings.clk_pre =
125 linear_inter(tmax, tmin, pcnt2, 0, false);
126 timing->shared_timings.clk_pre_inc_by_2 = false;
127 }
128
129 timing->ta_go = 3;
130 timing->ta_sure = 0;
131 timing->ta_get = 4;
132
133 DBG("PHY timings: %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d",
134 timing->shared_timings.clk_pre, timing->shared_timings.clk_post,
135 timing->shared_timings.clk_pre_inc_by_2, timing->clk_zero,
136 timing->clk_trail, timing->clk_prepare, timing->hs_exit,
137 timing->hs_zero, timing->hs_prepare, timing->hs_trail,
138 timing->hs_rqst);
139
140 return 0;
141}
142
143int msm_dsi_dphy_timing_calc_v2(struct msm_dsi_dphy_timing *timing,
144 struct msm_dsi_phy_clk_request *clk_req)
145{
146 const unsigned long bit_rate = clk_req->bitclk_rate;
147 const unsigned long esc_rate = clk_req->escclk_rate;
148 s32 ui, ui_x8;
149 s32 tmax, tmin;
150 s32 pcnt0 = 50;
151 s32 pcnt1 = 50;
152 s32 pcnt2 = 10;
153 s32 pcnt3 = 30;
154 s32 pcnt4 = 10;
155 s32 pcnt5 = 2;
156 s32 coeff = 1000; /* Precision, should avoid overflow */
157 s32 hb_en, hb_en_ckln, pd_ckln, pd;
158 s32 val, val_ckln;
159 s32 temp;
160
161 if (!bit_rate || !esc_rate)
162 return -EINVAL;
163
164 timing->hs_halfbyte_en = 0;
165 hb_en = 0;
166 timing->hs_halfbyte_en_ckln = 0;
167 hb_en_ckln = 0;
168 timing->hs_prep_dly_ckln = (bit_rate > 100000000) ? 0 : 3;
169 pd_ckln = timing->hs_prep_dly_ckln;
170 timing->hs_prep_dly = (bit_rate > 120000000) ? 0 : 1;
171 pd = timing->hs_prep_dly;
172
173 val = (hb_en << 2) + (pd << 1);
174 val_ckln = (hb_en_ckln << 2) + (pd_ckln << 1);
175
176 ui = mult_frac(NSEC_PER_MSEC, coeff, bit_rate / 1000);
177 ui_x8 = ui << 3;
178
179 temp = S_DIV_ROUND_UP(38 * coeff - val_ckln * ui, ui_x8);
180 tmin = max_t(s32, temp, 0);
181 temp = (95 * coeff - val_ckln * ui) / ui_x8;
182 tmax = max_t(s32, temp, 0);
183 timing->clk_prepare = linear_inter(tmax, tmin, pcnt0, 0, false);
184
185 temp = 300 * coeff - ((timing->clk_prepare << 3) + val_ckln) * ui;
186 tmin = S_DIV_ROUND_UP(temp - 11 * ui, ui_x8) - 3;
187 tmax = (tmin > 255) ? 511 : 255;
188 timing->clk_zero = linear_inter(tmax, tmin, pcnt5, 0, false);
189
190 tmin = DIV_ROUND_UP(60 * coeff + 3 * ui, ui_x8);
191 temp = 105 * coeff + 12 * ui - 20 * coeff;
192 tmax = (temp + 3 * ui) / ui_x8;
193 timing->clk_trail = linear_inter(tmax, tmin, pcnt3, 0, false);
194
195 temp = S_DIV_ROUND_UP(40 * coeff + 4 * ui - val * ui, ui_x8);
196 tmin = max_t(s32, temp, 0);
197 temp = (85 * coeff + 6 * ui - val * ui) / ui_x8;
198 tmax = max_t(s32, temp, 0);
199 timing->hs_prepare = linear_inter(tmax, tmin, pcnt1, 0, false);
200
201 temp = 145 * coeff + 10 * ui - ((timing->hs_prepare << 3) + val) * ui;
202 tmin = S_DIV_ROUND_UP(temp - 11 * ui, ui_x8) - 3;
203 tmax = 255;
204 timing->hs_zero = linear_inter(tmax, tmin, pcnt4, 0, false);
205
206 tmin = DIV_ROUND_UP(60 * coeff + 4 * ui + 3 * ui, ui_x8);
207 temp = 105 * coeff + 12 * ui - 20 * coeff;
208 tmax = (temp + 3 * ui) / ui_x8;
209 timing->hs_trail = linear_inter(tmax, tmin, pcnt3, 0, false);
210
211 temp = 50 * coeff + ((hb_en << 2) - 8) * ui;
212 timing->hs_rqst = S_DIV_ROUND_UP(temp, ui_x8);
213
214 tmin = DIV_ROUND_UP(100 * coeff, ui_x8) - 1;
215 tmax = 255;
216 timing->hs_exit = linear_inter(tmax, tmin, pcnt2, 0, false);
217
218 temp = 50 * coeff + ((hb_en_ckln << 2) - 8) * ui;
219 timing->hs_rqst_ckln = S_DIV_ROUND_UP(temp, ui_x8);
220
221 temp = 60 * coeff + 52 * ui - 43 * ui;
222 tmin = DIV_ROUND_UP(temp, ui_x8) - 1;
223 tmax = 63;
224 timing->shared_timings.clk_post =
225 linear_inter(tmax, tmin, pcnt2, 0, false);
226
227 temp = 8 * ui + ((timing->clk_prepare << 3) + val_ckln) * ui;
228 temp += (((timing->clk_zero + 3) << 3) + 11 - (pd_ckln << 1)) * ui;
229 temp += hb_en_ckln ? (((timing->hs_rqst_ckln << 3) + 4) * ui) :
230 (((timing->hs_rqst_ckln << 3) + 8) * ui);
231 tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1;
232 tmax = 63;
233 if (tmin > tmax) {
234 temp = linear_inter(tmax << 1, tmin, pcnt2, 0, false);
235 timing->shared_timings.clk_pre = temp >> 1;
236 timing->shared_timings.clk_pre_inc_by_2 = 1;
237 } else {
238 timing->shared_timings.clk_pre =
239 linear_inter(tmax, tmin, pcnt2, 0, false);
240 timing->shared_timings.clk_pre_inc_by_2 = 0;
241 }
242
243 timing->ta_go = 3;
244 timing->ta_sure = 0;
245 timing->ta_get = 4;
246
247 DBG("%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d",
248 timing->shared_timings.clk_pre, timing->shared_timings.clk_post,
249 timing->shared_timings.clk_pre_inc_by_2, timing->clk_zero,
250 timing->clk_trail, timing->clk_prepare, timing->hs_exit,
251 timing->hs_zero, timing->hs_prepare, timing->hs_trail,
252 timing->hs_rqst, timing->hs_rqst_ckln, timing->hs_halfbyte_en,
253 timing->hs_halfbyte_en_ckln, timing->hs_prep_dly,
254 timing->hs_prep_dly_ckln);
255
256 return 0;
257}
258
259int msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing *timing,
260 struct msm_dsi_phy_clk_request *clk_req)
261{
262 const unsigned long bit_rate = clk_req->bitclk_rate;
263 const unsigned long esc_rate = clk_req->escclk_rate;
264 s32 ui, ui_x8;
265 s32 tmax, tmin;
266 s32 pcnt0 = 50;
267 s32 pcnt1 = 50;
268 s32 pcnt2 = 10;
269 s32 pcnt3 = 30;
270 s32 pcnt4 = 10;
271 s32 pcnt5 = 2;
272 s32 coeff = 1000; /* Precision, should avoid overflow */
273 s32 hb_en, hb_en_ckln;
274 s32 temp;
275
276 if (!bit_rate || !esc_rate)
277 return -EINVAL;
278
279 timing->hs_halfbyte_en = 0;
280 hb_en = 0;
281 timing->hs_halfbyte_en_ckln = 0;
282 hb_en_ckln = 0;
283
284 ui = mult_frac(NSEC_PER_MSEC, coeff, bit_rate / 1000);
285 ui_x8 = ui << 3;
286
287 temp = S_DIV_ROUND_UP(38 * coeff, ui_x8);
288 tmin = max_t(s32, temp, 0);
289 temp = (95 * coeff) / ui_x8;
290 tmax = max_t(s32, temp, 0);
291 timing->clk_prepare = linear_inter(tmax, tmin, pcnt0, 0, false);
292
293 temp = 300 * coeff - (timing->clk_prepare << 3) * ui;
294 tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1;
295 tmax = (tmin > 255) ? 511 : 255;
296 timing->clk_zero = linear_inter(tmax, tmin, pcnt5, 0, false);
297
298 tmin = DIV_ROUND_UP(60 * coeff + 3 * ui, ui_x8);
299 temp = 105 * coeff + 12 * ui - 20 * coeff;
300 tmax = (temp + 3 * ui) / ui_x8;
301 timing->clk_trail = linear_inter(tmax, tmin, pcnt3, 0, false);
302
303 temp = S_DIV_ROUND_UP(40 * coeff + 4 * ui, ui_x8);
304 tmin = max_t(s32, temp, 0);
305 temp = (85 * coeff + 6 * ui) / ui_x8;
306 tmax = max_t(s32, temp, 0);
307 timing->hs_prepare = linear_inter(tmax, tmin, pcnt1, 0, false);
308
309 temp = 145 * coeff + 10 * ui - (timing->hs_prepare << 3) * ui;
310 tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1;
311 tmax = 255;
312 timing->hs_zero = linear_inter(tmax, tmin, pcnt4, 0, false);
313
314 tmin = DIV_ROUND_UP(60 * coeff + 4 * ui, ui_x8) - 1;
315 temp = 105 * coeff + 12 * ui - 20 * coeff;
316 tmax = (temp / ui_x8) - 1;
317 timing->hs_trail = linear_inter(tmax, tmin, pcnt3, 0, false);
318
319 temp = 50 * coeff + ((hb_en << 2) - 8) * ui;
320 timing->hs_rqst = S_DIV_ROUND_UP(temp, ui_x8);
321
322 tmin = DIV_ROUND_UP(100 * coeff, ui_x8) - 1;
323 tmax = 255;
324 timing->hs_exit = linear_inter(tmax, tmin, pcnt2, 0, false);
325
326 temp = 50 * coeff + ((hb_en_ckln << 2) - 8) * ui;
327 timing->hs_rqst_ckln = S_DIV_ROUND_UP(temp, ui_x8);
328
329 temp = 60 * coeff + 52 * ui - 43 * ui;
330 tmin = DIV_ROUND_UP(temp, ui_x8) - 1;
331 tmax = 63;
332 timing->shared_timings.clk_post =
333 linear_inter(tmax, tmin, pcnt2, 0, false);
334
335 temp = 8 * ui + (timing->clk_prepare << 3) * ui;
336 temp += (((timing->clk_zero + 3) << 3) + 11) * ui;
337 temp += hb_en_ckln ? (((timing->hs_rqst_ckln << 3) + 4) * ui) :
338 (((timing->hs_rqst_ckln << 3) + 8) * ui);
339 tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1;
340 tmax = 63;
341 if (tmin > tmax) {
342 temp = linear_inter(tmax << 1, tmin, pcnt2, 0, false);
343 timing->shared_timings.clk_pre = temp >> 1;
344 timing->shared_timings.clk_pre_inc_by_2 = 1;
345 } else {
346 timing->shared_timings.clk_pre =
347 linear_inter(tmax, tmin, pcnt2, 0, false);
348 timing->shared_timings.clk_pre_inc_by_2 = 0;
349 }
350
351 timing->ta_go = 3;
352 timing->ta_sure = 0;
353 timing->ta_get = 4;
354
355 DBG("%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d",
356 timing->shared_timings.clk_pre, timing->shared_timings.clk_post,
357 timing->shared_timings.clk_pre_inc_by_2, timing->clk_zero,
358 timing->clk_trail, timing->clk_prepare, timing->hs_exit,
359 timing->hs_zero, timing->hs_prepare, timing->hs_trail,
360 timing->hs_rqst, timing->hs_rqst_ckln, timing->hs_halfbyte_en,
361 timing->hs_halfbyte_en_ckln, timing->hs_prep_dly,
362 timing->hs_prep_dly_ckln);
363
364 return 0;
365}
366
367void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg,
368 u32 bit_mask)
369{
370 int phy_id = phy->id;
371 u32 val;
372
373 if ((phy_id >= DSI_MAX) || (pll_id >= DSI_MAX))
374 return;
375
376 val = dsi_phy_read(phy->base + reg);
377
378 if (phy->cfg->src_pll_truthtable[phy_id][pll_id])
379 dsi_phy_write(phy->base + reg, val | bit_mask);
380 else
381 dsi_phy_write(phy->base + reg, val & (~bit_mask));
382}
383
384static int dsi_phy_regulator_init(struct msm_dsi_phy *phy)
385{
386 struct regulator_bulk_data *s = phy->supplies;
387 const struct dsi_reg_entry *regs = phy->cfg->reg_cfg.regs;
388 struct device *dev = &phy->pdev->dev;
389 int num = phy->cfg->reg_cfg.num;
390 int i, ret;
391
392 for (i = 0; i < num; i++)
393 s[i].supply = regs[i].name;
394
395 ret = devm_regulator_bulk_get(dev, num, s);
396 if (ret < 0) {
397 if (ret != -EPROBE_DEFER) {
398 DRM_DEV_ERROR(dev,
399 "%s: failed to init regulator, ret=%d\n",
400 __func__, ret);
401 }
402
403 return ret;
404 }
405
406 return 0;
407}
408
409static void dsi_phy_regulator_disable(struct msm_dsi_phy *phy)
410{
411 struct regulator_bulk_data *s = phy->supplies;
412 const struct dsi_reg_entry *regs = phy->cfg->reg_cfg.regs;
413 int num = phy->cfg->reg_cfg.num;
414 int i;
415
416 DBG("");
417 for (i = num - 1; i >= 0; i--)
418 if (regs[i].disable_load >= 0)
419 regulator_set_load(s[i].consumer, regs[i].disable_load);
420
421 regulator_bulk_disable(num, s);
422}
423
424static int dsi_phy_regulator_enable(struct msm_dsi_phy *phy)
425{
426 struct regulator_bulk_data *s = phy->supplies;
427 const struct dsi_reg_entry *regs = phy->cfg->reg_cfg.regs;
428 struct device *dev = &phy->pdev->dev;
429 int num = phy->cfg->reg_cfg.num;
430 int ret, i;
431
432 DBG("");
433 for (i = 0; i < num; i++) {
434 if (regs[i].enable_load >= 0) {
435 ret = regulator_set_load(s[i].consumer,
436 regs[i].enable_load);
437 if (ret < 0) {
438 DRM_DEV_ERROR(dev,
439 "regulator %d set op mode failed, %d\n",
440 i, ret);
441 goto fail;
442 }
443 }
444 }
445
446 ret = regulator_bulk_enable(num, s);
447 if (ret < 0) {
448 DRM_DEV_ERROR(dev, "regulator enable failed, %d\n", ret);
449 goto fail;
450 }
451
452 return 0;
453
454fail:
455 for (i--; i >= 0; i--)
456 regulator_set_load(s[i].consumer, regs[i].disable_load);
457 return ret;
458}
459
460static int dsi_phy_enable_resource(struct msm_dsi_phy *phy)
461{
462 struct device *dev = &phy->pdev->dev;
463 int ret;
464
465 pm_runtime_get_sync(dev);
466
467 ret = clk_prepare_enable(phy->ahb_clk);
468 if (ret) {
469 DRM_DEV_ERROR(dev, "%s: can't enable ahb clk, %d\n", __func__, ret);
470 pm_runtime_put_sync(dev);
471 }
472
473 return ret;
474}
475
476static void dsi_phy_disable_resource(struct msm_dsi_phy *phy)
477{
478 clk_disable_unprepare(phy->ahb_clk);
479 pm_runtime_put_autosuspend(&phy->pdev->dev);
480}
481
482static const struct of_device_id dsi_phy_dt_match[] = {
483#ifdef CONFIG_DRM_MSM_DSI_28NM_PHY
484 { .compatible = "qcom,dsi-phy-28nm-hpm",
485 .data = &dsi_phy_28nm_hpm_cfgs },
486 { .compatible = "qcom,dsi-phy-28nm-hpm-fam-b",
487 .data = &dsi_phy_28nm_hpm_famb_cfgs },
488 { .compatible = "qcom,dsi-phy-28nm-lp",
489 .data = &dsi_phy_28nm_lp_cfgs },
490#endif
491#ifdef CONFIG_DRM_MSM_DSI_20NM_PHY
492 { .compatible = "qcom,dsi-phy-20nm",
493 .data = &dsi_phy_20nm_cfgs },
494#endif
495#ifdef CONFIG_DRM_MSM_DSI_28NM_8960_PHY
496 { .compatible = "qcom,dsi-phy-28nm-8960",
497 .data = &dsi_phy_28nm_8960_cfgs },
498#endif
499#ifdef CONFIG_DRM_MSM_DSI_14NM_PHY
500 { .compatible = "qcom,dsi-phy-14nm",
501 .data = &dsi_phy_14nm_cfgs },
502 { .compatible = "qcom,dsi-phy-14nm-660",
503 .data = &dsi_phy_14nm_660_cfgs },
504#endif
505#ifdef CONFIG_DRM_MSM_DSI_10NM_PHY
506 { .compatible = "qcom,dsi-phy-10nm",
507 .data = &dsi_phy_10nm_cfgs },
508 { .compatible = "qcom,dsi-phy-10nm-8998",
509 .data = &dsi_phy_10nm_8998_cfgs },
510#endif
511 {}
512};
513
514/*
515 * Currently, we only support one SoC for each PHY type. When we have multiple
516 * SoCs for the same PHY, we can try to make the index searching a bit more
517 * clever.
518 */
519static int dsi_phy_get_id(struct msm_dsi_phy *phy)
520{
521 struct platform_device *pdev = phy->pdev;
522 const struct msm_dsi_phy_cfg *cfg = phy->cfg;
523 struct resource *res;
524 int i;
525
526 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dsi_phy");
527 if (!res)
528 return -EINVAL;
529
530 for (i = 0; i < cfg->num_dsi_phy; i++) {
531 if (cfg->io_start[i] == res->start)
532 return i;
533 }
534
535 return -EINVAL;
536}
537
538int msm_dsi_phy_init_common(struct msm_dsi_phy *phy)
539{
540 struct platform_device *pdev = phy->pdev;
541 int ret = 0;
542
543 phy->reg_base = msm_ioremap(pdev, "dsi_phy_regulator",
544 "DSI_PHY_REG");
545 if (IS_ERR(phy->reg_base)) {
546 DRM_DEV_ERROR(&pdev->dev, "%s: failed to map phy regulator base\n",
547 __func__);
548 ret = -ENOMEM;
549 goto fail;
550 }
551
552fail:
553 return ret;
554}
555
556static int dsi_phy_driver_probe(struct platform_device *pdev)
557{
558 struct msm_dsi_phy *phy;
559 struct device *dev = &pdev->dev;
560 const struct of_device_id *match;
561 int ret;
562
563 phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
564 if (!phy)
565 return -ENOMEM;
566
567 match = of_match_node(dsi_phy_dt_match, dev->of_node);
568 if (!match)
569 return -ENODEV;
570
571 phy->cfg = match->data;
572 phy->pdev = pdev;
573
574 phy->id = dsi_phy_get_id(phy);
575 if (phy->id < 0) {
576 ret = phy->id;
577 DRM_DEV_ERROR(dev, "%s: couldn't identify PHY index, %d\n",
578 __func__, ret);
579 goto fail;
580 }
581
582 phy->regulator_ldo_mode = of_property_read_bool(dev->of_node,
583 "qcom,dsi-phy-regulator-ldo-mode");
584
585 phy->base = msm_ioremap(pdev, "dsi_phy", "DSI_PHY");
586 if (IS_ERR(phy->base)) {
587 DRM_DEV_ERROR(dev, "%s: failed to map phy base\n", __func__);
588 ret = -ENOMEM;
589 goto fail;
590 }
591
592 ret = dsi_phy_regulator_init(phy);
593 if (ret)
594 goto fail;
595
596 phy->ahb_clk = msm_clk_get(pdev, "iface");
597 if (IS_ERR(phy->ahb_clk)) {
598 DRM_DEV_ERROR(dev, "%s: Unable to get ahb clk\n", __func__);
599 ret = PTR_ERR(phy->ahb_clk);
600 goto fail;
601 }
602
603 if (phy->cfg->ops.init) {
604 ret = phy->cfg->ops.init(phy);
605 if (ret)
606 goto fail;
607 }
608
609 /* PLL init will call into clk_register which requires
610 * register access, so we need to enable power and ahb clock.
611 */
612 ret = dsi_phy_enable_resource(phy);
613 if (ret)
614 goto fail;
615
616 phy->pll = msm_dsi_pll_init(pdev, phy->cfg->type, phy->id);
617 if (IS_ERR_OR_NULL(phy->pll)) {
618 DRM_DEV_INFO(dev,
619 "%s: pll init failed: %ld, need separate pll clk driver\n",
620 __func__, PTR_ERR(phy->pll));
621 phy->pll = NULL;
622 }
623
624 dsi_phy_disable_resource(phy);
625
626 platform_set_drvdata(pdev, phy);
627
628 return 0;
629
630fail:
631 return ret;
632}
633
634static int dsi_phy_driver_remove(struct platform_device *pdev)
635{
636 struct msm_dsi_phy *phy = platform_get_drvdata(pdev);
637
638 if (phy && phy->pll) {
639 msm_dsi_pll_destroy(phy->pll);
640 phy->pll = NULL;
641 }
642
643 platform_set_drvdata(pdev, NULL);
644
645 return 0;
646}
647
648static struct platform_driver dsi_phy_platform_driver = {
649 .probe = dsi_phy_driver_probe,
650 .remove = dsi_phy_driver_remove,
651 .driver = {
652 .name = "msm_dsi_phy",
653 .of_match_table = dsi_phy_dt_match,
654 },
655};
656
657void __init msm_dsi_phy_driver_register(void)
658{
659 platform_driver_register(&dsi_phy_platform_driver);
660}
661
662void __exit msm_dsi_phy_driver_unregister(void)
663{
664 platform_driver_unregister(&dsi_phy_platform_driver);
665}
666
667int msm_dsi_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
668 struct msm_dsi_phy_clk_request *clk_req)
669{
670 struct device *dev = &phy->pdev->dev;
671 int ret;
672
673 if (!phy || !phy->cfg->ops.enable)
674 return -EINVAL;
675
676 ret = dsi_phy_enable_resource(phy);
677 if (ret) {
678 DRM_DEV_ERROR(dev, "%s: resource enable failed, %d\n",
679 __func__, ret);
680 goto res_en_fail;
681 }
682
683 ret = dsi_phy_regulator_enable(phy);
684 if (ret) {
685 DRM_DEV_ERROR(dev, "%s: regulator enable failed, %d\n",
686 __func__, ret);
687 goto reg_en_fail;
688 }
689
690 ret = phy->cfg->ops.enable(phy, src_pll_id, clk_req);
691 if (ret) {
692 DRM_DEV_ERROR(dev, "%s: phy enable failed, %d\n", __func__, ret);
693 goto phy_en_fail;
694 }
695
696 /*
697 * Resetting DSI PHY silently changes its PLL registers to reset status,
698 * which will confuse clock driver and result in wrong output rate of
699 * link clocks. Restore PLL status if its PLL is being used as clock
700 * source.
701 */
702 if (phy->usecase != MSM_DSI_PHY_SLAVE) {
703 ret = msm_dsi_pll_restore_state(phy->pll);
704 if (ret) {
705 DRM_DEV_ERROR(dev, "%s: failed to restore pll state, %d\n",
706 __func__, ret);
707 goto pll_restor_fail;
708 }
709 }
710
711 return 0;
712
713pll_restor_fail:
714 if (phy->cfg->ops.disable)
715 phy->cfg->ops.disable(phy);
716phy_en_fail:
717 dsi_phy_regulator_disable(phy);
718reg_en_fail:
719 dsi_phy_disable_resource(phy);
720res_en_fail:
721 return ret;
722}
723
724void msm_dsi_phy_disable(struct msm_dsi_phy *phy)
725{
726 if (!phy || !phy->cfg->ops.disable)
727 return;
728
729 phy->cfg->ops.disable(phy);
730
731 dsi_phy_regulator_disable(phy);
732 dsi_phy_disable_resource(phy);
733}
734
735void msm_dsi_phy_get_shared_timings(struct msm_dsi_phy *phy,
736 struct msm_dsi_phy_shared_timings *shared_timings)
737{
738 memcpy(shared_timings, &phy->timing.shared_timings,
739 sizeof(*shared_timings));
740}
741
742struct msm_dsi_pll *msm_dsi_phy_get_pll(struct msm_dsi_phy *phy)
743{
744 if (!phy)
745 return NULL;
746
747 return phy->pll;
748}
749
750void msm_dsi_phy_set_usecase(struct msm_dsi_phy *phy,
751 enum msm_dsi_phy_usecase uc)
752{
753 if (phy)
754 phy->usecase = uc;
755}