1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Copyright (c) 2015-2018 The Linux Foundation. All rights reserved.
  4 */
  5
  6#ifndef __DPU_ENCODER_PHYS_H__
  7#define __DPU_ENCODER_PHYS_H__
  8
  9#include <linux/jiffies.h>
 10
 11#include "dpu_kms.h"
 12#include "dpu_hw_intf.h"
 13#include "dpu_hw_pingpong.h"
 14#include "dpu_hw_ctl.h"
 15#include "dpu_hw_top.h"
 16#include "dpu_encoder.h"
 17#include "dpu_crtc.h"
 18
 19#define DPU_ENCODER_NAME_MAX	16
 20
 21/* wait for at most 2 vsync for lowest refresh rate (24hz) */
 22#define KICKOFF_TIMEOUT_MS		84
 23#define KICKOFF_TIMEOUT_JIFFIES		msecs_to_jiffies(KICKOFF_TIMEOUT_MS)
 24
 25/**
 26 * enum dpu_enc_split_role - Role this physical encoder will play in a
 27 *	split-panel configuration, where one panel is master, and others slaves.
 28 *	Masters have extra responsibilities, like managing the VBLANK IRQ.
 29 * @ENC_ROLE_SOLO:	This is the one and only panel. This encoder is master.
 30 * @ENC_ROLE_MASTER:	This encoder is the master of a split panel config.
 31 * @ENC_ROLE_SLAVE:	This encoder is not the master of a split panel config.
 32 */
 33enum dpu_enc_split_role {
 34	ENC_ROLE_SOLO,
 35	ENC_ROLE_MASTER,
 36	ENC_ROLE_SLAVE,
 37};
 38
 39/**
 40 * enum dpu_enc_enable_state - current enabled state of the physical encoder
 41 * @DPU_ENC_DISABLING:	Encoder transitioning to disable state
 42 *			Events bounding transition are encoder type specific
 43 * @DPU_ENC_DISABLED:	Encoder is disabled
 44 * @DPU_ENC_ENABLING:	Encoder transitioning to enabled
 45 *			Events bounding transition are encoder type specific
 46 * @DPU_ENC_ENABLED:	Encoder is enabled
 47 * @DPU_ENC_ERR_NEEDS_HW_RESET:	Encoder is enabled, but requires a hw_reset
 48 *				to recover from a previous error
 49 */
 50enum dpu_enc_enable_state {
 51	DPU_ENC_DISABLING,
 52	DPU_ENC_DISABLED,
 53	DPU_ENC_ENABLING,
 54	DPU_ENC_ENABLED,
 55	DPU_ENC_ERR_NEEDS_HW_RESET
 56};
 57
 58struct dpu_encoder_phys;
 59
 60/**
 61 * struct dpu_encoder_virt_ops - Interface the containing virtual encoder
 62 *	provides for the physical encoders to use to callback.
 63 * @handle_vblank_virt:	Notify virtual encoder of vblank IRQ reception
 64 *			Note: This is called from IRQ handler context.
 65 * @handle_underrun_virt: Notify virtual encoder of underrun IRQ reception
 66 *			Note: This is called from IRQ handler context.
 67 * @handle_frame_done:	Notify virtual encoder that this phys encoder
 68 *			completes last request frame.
 69 */
 70struct dpu_encoder_virt_ops {
 71	void (*handle_vblank_virt)(struct drm_encoder *,
 72			struct dpu_encoder_phys *phys);
 73	void (*handle_underrun_virt)(struct drm_encoder *,
 74			struct dpu_encoder_phys *phys);
 75	void (*handle_frame_done)(struct drm_encoder *,
 76			struct dpu_encoder_phys *phys, u32 event);
 77};
 78
 79/**
 80 * struct dpu_encoder_phys_ops - Interface the physical encoders provide to
 81 *	the containing virtual encoder.
 82 * @late_register:		DRM Call. Add Userspace interfaces, debugfs.
 83 * @prepare_commit:		MSM Atomic Call, start of atomic commit sequence
 84 * @is_master:			Whether this phys_enc is the current master
 85 *				encoder. Can be switched at enable time. Based
 86 *				on split_role and current mode (CMD/VID).
 87 * @mode_fixup:			DRM Call. Fixup a DRM mode.
 88 * @mode_set:			DRM Call. Set a DRM mode.
 89 *				This likely caches the mode, for use at enable.
 90 * @enable:			DRM Call. Enable a DRM mode.
 91 * @disable:			DRM Call. Disable mode.
 92 * @atomic_check:		DRM Call. Atomic check new DRM state.
 93 * @destroy:			DRM Call. Destroy and release resources.
 94 * @get_hw_resources:		Populate the structure with the hardware
 95 *				resources that this phys_enc is using.
 96 *				Expect no overlap between phys_encs.
 97 * @control_vblank_irq		Register/Deregister for VBLANK IRQ
 98 * @wait_for_commit_done:	Wait for hardware to have flushed the
 99 *				current pending frames to hardware
100 * @wait_for_tx_complete:	Wait for hardware to transfer the pixels
101 *				to the panel
102 * @wait_for_vblank:		Wait for VBLANK, for sub-driver internal use
103 * @prepare_for_kickoff:	Do any work necessary prior to a kickoff
104 *				For CMD encoder, may wait for previous tx done
105 * @handle_post_kickoff:	Do any work necessary post-kickoff work
106 * @trigger_start:		Process start event on physical encoder
107 * @needs_single_flush:		Whether encoder slaves need to be flushed
108 * @irq_control:		Handler to enable/disable all the encoder IRQs
109 * @prepare_idle_pc:		phys encoder can update the vsync_enable status
110 *                              on idle power collapse prepare
111 * @restore:			Restore all the encoder configs.
112 * @get_line_count:		Obtain current vertical line count
113 */
114
115struct dpu_encoder_phys_ops {
116	int (*late_register)(struct dpu_encoder_phys *encoder,
117			struct dentry *debugfs_root);
118	void (*prepare_commit)(struct dpu_encoder_phys *encoder);
119	bool (*is_master)(struct dpu_encoder_phys *encoder);
120	bool (*mode_fixup)(struct dpu_encoder_phys *encoder,
121			const struct drm_display_mode *mode,
122			struct drm_display_mode *adjusted_mode);
123	void (*mode_set)(struct dpu_encoder_phys *encoder,
124			struct drm_display_mode *mode,
125			struct drm_display_mode *adjusted_mode);
126	void (*enable)(struct dpu_encoder_phys *encoder);
127	void (*disable)(struct dpu_encoder_phys *encoder);
128	int (*atomic_check)(struct dpu_encoder_phys *encoder,
129			    struct drm_crtc_state *crtc_state,
130			    struct drm_connector_state *conn_state);
131	void (*destroy)(struct dpu_encoder_phys *encoder);
132	void (*get_hw_resources)(struct dpu_encoder_phys *encoder,
133				 struct dpu_encoder_hw_resources *hw_res);
134	int (*control_vblank_irq)(struct dpu_encoder_phys *enc, bool enable);
135	int (*wait_for_commit_done)(struct dpu_encoder_phys *phys_enc);
136	int (*wait_for_tx_complete)(struct dpu_encoder_phys *phys_enc);
137	int (*wait_for_vblank)(struct dpu_encoder_phys *phys_enc);
138	void (*prepare_for_kickoff)(struct dpu_encoder_phys *phys_enc);
139	void (*handle_post_kickoff)(struct dpu_encoder_phys *phys_enc);
140	void (*trigger_start)(struct dpu_encoder_phys *phys_enc);
141	bool (*needs_single_flush)(struct dpu_encoder_phys *phys_enc);
142	void (*irq_control)(struct dpu_encoder_phys *phys, bool enable);
143	void (*prepare_idle_pc)(struct dpu_encoder_phys *phys_enc);
144	void (*restore)(struct dpu_encoder_phys *phys);
145	int (*get_line_count)(struct dpu_encoder_phys *phys);
146};
147
148/**
149 * enum dpu_intr_idx - dpu encoder interrupt index
150 * @INTR_IDX_VSYNC:    Vsync interrupt for video mode panel
151 * @INTR_IDX_PINGPONG: Pingpong done unterrupt for cmd mode panel
152 * @INTR_IDX_UNDERRUN: Underrun unterrupt for video and cmd mode panel
153 * @INTR_IDX_RDPTR:    Readpointer done unterrupt for cmd mode panel
154 */
155enum dpu_intr_idx {
156	INTR_IDX_VSYNC,
157	INTR_IDX_PINGPONG,
158	INTR_IDX_UNDERRUN,
159	INTR_IDX_CTL_START,
160	INTR_IDX_RDPTR,
161	INTR_IDX_MAX,
162};
163
164/**
165 * dpu_encoder_irq - tracking structure for interrupts
166 * @name:		string name of interrupt
167 * @intr_type:		Encoder interrupt type
168 * @intr_idx:		Encoder interrupt enumeration
169 * @hw_idx:		HW Block ID
170 * @irq_idx:		IRQ interface lookup index from DPU IRQ framework
171 *			will be -EINVAL if IRQ is not registered
172 * @irq_cb:		interrupt callback
173 */
174struct dpu_encoder_irq {
175	const char *name;
176	enum dpu_intr_type intr_type;
177	enum dpu_intr_idx intr_idx;
178	int hw_idx;
179	int irq_idx;
180	struct dpu_irq_callback cb;
181};
182
183/**
184 * struct dpu_encoder_phys - physical encoder that drives a single INTF block
185 *	tied to a specific panel / sub-panel. Abstract type, sub-classed by
186 *	phys_vid or phys_cmd for video mode or command mode encs respectively.
187 * @parent:		Pointer to the containing virtual encoder
188 * @connector:		If a mode is set, cached pointer to the active connector
189 * @ops:		Operations exposed to the virtual encoder
190 * @parent_ops:		Callbacks exposed by the parent to the phys_enc
191 * @hw_mdptop:		Hardware interface to the top registers
192 * @hw_ctl:		Hardware interface to the ctl registers
193 * @hw_pp:		Hardware interface to the ping pong registers
194 * @hw_intf:		Hardware interface to the intf registers
195 * @dpu_kms:		Pointer to the dpu_kms top level
196 * @cached_mode:	DRM mode cached at mode_set time, acted on in enable
197 * @enabled:		Whether the encoder has enabled and running a mode
198 * @split_role:		Role to play in a split-panel configuration
199 * @intf_mode:		Interface mode
200 * @intf_idx:		Interface index on dpu hardware
201 * @enc_spinlock:	Virtual-Encoder-Wide Spin Lock for IRQ purposes
202 * @enable_state:	Enable state tracking
203 * @vblank_refcount:	Reference count of vblank request
204 * @vsync_cnt:		Vsync count for the physical encoder
205 * @underrun_cnt:	Underrun count for the physical encoder
206 * @pending_kickoff_cnt:	Atomic counter tracking the number of kickoffs
207 *				vs. the number of done/vblank irqs. Should hover
208 *				between 0-2 Incremented when a new kickoff is
209 *				scheduled. Decremented in irq handler
210 * @pending_ctlstart_cnt:	Atomic counter tracking the number of ctl start
211 *                              pending.
212 * @pending_kickoff_wq:		Wait queue for blocking until kickoff completes
213 * @irq:			IRQ tracking structures
214 */
215struct dpu_encoder_phys {
216	struct drm_encoder *parent;
217	struct drm_connector *connector;
218	struct dpu_encoder_phys_ops ops;
219	const struct dpu_encoder_virt_ops *parent_ops;
220	struct dpu_hw_mdp *hw_mdptop;
221	struct dpu_hw_ctl *hw_ctl;
222	struct dpu_hw_pingpong *hw_pp;
223	struct dpu_hw_intf *hw_intf;
224	struct dpu_kms *dpu_kms;
225	struct drm_display_mode cached_mode;
226	enum dpu_enc_split_role split_role;
227	enum dpu_intf_mode intf_mode;
228	enum dpu_intf intf_idx;
229	spinlock_t *enc_spinlock;
230	enum dpu_enc_enable_state enable_state;
231	atomic_t vblank_refcount;
232	atomic_t vsync_cnt;
233	atomic_t underrun_cnt;
234	atomic_t pending_ctlstart_cnt;
235	atomic_t pending_kickoff_cnt;
236	wait_queue_head_t pending_kickoff_wq;
237	struct dpu_encoder_irq irq[INTR_IDX_MAX];
238};
239
240static inline int dpu_encoder_phys_inc_pending(struct dpu_encoder_phys *phys)
241{
242	atomic_inc_return(&phys->pending_ctlstart_cnt);
243	return atomic_inc_return(&phys->pending_kickoff_cnt);
244}
245
246/**
247 * struct dpu_encoder_phys_cmd - sub-class of dpu_encoder_phys to handle command
248 *	mode specific operations
249 * @base:	Baseclass physical encoder structure
250 * @intf_idx:	Intf Block index used by this phys encoder
251 * @stream_sel:	Stream selection for multi-stream interfaces
252 * @serialize_wait4pp:	serialize wait4pp feature waits for pp_done interrupt
253 *			after ctl_start instead of before next frame kickoff
254 * @pp_timeout_report_cnt: number of pingpong done irq timeout errors
255 * @pending_vblank_cnt: Atomic counter tracking pending wait for VBLANK
256 * @pending_vblank_wq: Wait queue for blocking until VBLANK received
257 */
258struct dpu_encoder_phys_cmd {
259	struct dpu_encoder_phys base;
260	int stream_sel;
261	bool serialize_wait4pp;
262	int pp_timeout_report_cnt;
263	atomic_t pending_vblank_cnt;
264	wait_queue_head_t pending_vblank_wq;
265};
266
267/**
268 * struct dpu_enc_phys_init_params - initialization parameters for phys encs
269 * @dpu_kms:		Pointer to the dpu_kms top level
270 * @parent:		Pointer to the containing virtual encoder
271 * @parent_ops:		Callbacks exposed by the parent to the phys_enc
272 * @split_role:		Role to play in a split-panel configuration
273 * @intf_idx:		Interface index this phys_enc will control
274 * @enc_spinlock:	Virtual-Encoder-Wide Spin Lock for IRQ purposes
275 */
276struct dpu_enc_phys_init_params {
277	struct dpu_kms *dpu_kms;
278	struct drm_encoder *parent;
279	const struct dpu_encoder_virt_ops *parent_ops;
280	enum dpu_enc_split_role split_role;
281	enum dpu_intf intf_idx;
282	spinlock_t *enc_spinlock;
283};
284
285/**
286 * dpu_encoder_wait_info - container for passing arguments to irq wait functions
287 * @wq: wait queue structure
288 * @atomic_cnt: wait until atomic_cnt equals zero
289 * @timeout_ms: timeout value in milliseconds
290 */
291struct dpu_encoder_wait_info {
292	wait_queue_head_t *wq;
293	atomic_t *atomic_cnt;
294	s64 timeout_ms;
295};
296
297/**
298 * dpu_encoder_phys_vid_init - Construct a new video mode physical encoder
299 * @p:	Pointer to init params structure
300 * Return: Error code or newly allocated encoder
301 */
302struct dpu_encoder_phys *dpu_encoder_phys_vid_init(
303		struct dpu_enc_phys_init_params *p);
304
305/**
306 * dpu_encoder_phys_cmd_init - Construct a new command mode physical encoder
307 * @p:	Pointer to init params structure
308 * Return: Error code or newly allocated encoder
309 */
310struct dpu_encoder_phys *dpu_encoder_phys_cmd_init(
311		struct dpu_enc_phys_init_params *p);
312
313/**
314 * dpu_encoder_helper_trigger_start - control start helper function
315 *	This helper function may be optionally specified by physical
316 *	encoders if they require ctl_start triggering.
317 * @phys_enc: Pointer to physical encoder structure
318 */
319void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc);
320
321static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode(
322		struct dpu_encoder_phys *phys_enc)
323{
324	struct dpu_crtc_state *dpu_cstate;
325
326	if (!phys_enc || phys_enc->enable_state == DPU_ENC_DISABLING)
327		return BLEND_3D_NONE;
328
329	dpu_cstate = to_dpu_crtc_state(phys_enc->parent->crtc->state);
330
331	if (phys_enc->split_role == ENC_ROLE_SOLO &&
332	    dpu_cstate->num_mixers == CRTC_DUAL_MIXERS)
333		return BLEND_3D_H_ROW_INT;
334
335	return BLEND_3D_NONE;
336}
337
338/**
339 * dpu_encoder_helper_split_config - split display configuration helper function
340 *	This helper function may be used by physical encoders to configure
341 *	the split display related registers.
342 * @phys_enc: Pointer to physical encoder structure
343 * @interface: enum dpu_intf setting
344 */
345void dpu_encoder_helper_split_config(
346		struct dpu_encoder_phys *phys_enc,
347		enum dpu_intf interface);
348
349/**
350 * dpu_encoder_helper_report_irq_timeout - utility to report error that irq has
351 *	timed out, including reporting frame error event to crtc and debug dump
352 * @phys_enc: Pointer to physical encoder structure
353 * @intr_idx: Failing interrupt index
354 */
355void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc,
356		enum dpu_intr_idx intr_idx);
357
358/**
359 * dpu_encoder_helper_wait_for_irq - utility to wait on an irq.
360 *	note: will call dpu_encoder_helper_wait_for_irq on timeout
361 * @phys_enc: Pointer to physical encoder structure
362 * @intr_idx: encoder interrupt index
363 * @wait_info: wait info struct
364 * @Return: 0 or -ERROR
365 */
366int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc,
367		enum dpu_intr_idx intr_idx,
368		struct dpu_encoder_wait_info *wait_info);
369
370/**
371 * dpu_encoder_helper_register_irq - register and enable an irq
372 * @phys_enc: Pointer to physical encoder structure
373 * @intr_idx: encoder interrupt index
374 * @Return: 0 or -ERROR
375 */
376int dpu_encoder_helper_register_irq(struct dpu_encoder_phys *phys_enc,
377		enum dpu_intr_idx intr_idx);
378
379/**
380 * dpu_encoder_helper_unregister_irq - unregister and disable an irq
381 * @phys_enc: Pointer to physical encoder structure
382 * @intr_idx: encoder interrupt index
383 * @Return: 0 or -ERROR
384 */
385int dpu_encoder_helper_unregister_irq(struct dpu_encoder_phys *phys_enc,
386		enum dpu_intr_idx intr_idx);
387
388#endif /* __dpu_encoder_phys_H__ */