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1// SPDX-License-Identifier: GPL-2.0
2/* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */
3
4
5#include "msm_gem.h"
6#include "msm_mmu.h"
7#include "msm_gpu_trace.h"
8#include "a6xx_gpu.h"
9#include "a6xx_gmu.xml.h"
10
11#include <linux/devfreq.h>
12
13#define GPU_PAS_ID 13
14
15static inline bool _a6xx_check_idle(struct msm_gpu *gpu)
16{
17 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
18 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
19
20 /* Check that the GMU is idle */
21 if (!a6xx_gmu_isidle(&a6xx_gpu->gmu))
22 return false;
23
24 /* Check tha the CX master is idle */
25 if (gpu_read(gpu, REG_A6XX_RBBM_STATUS) &
26 ~A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER)
27 return false;
28
29 return !(gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS) &
30 A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT);
31}
32
33bool a6xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
34{
35 /* wait for CP to drain ringbuffer: */
36 if (!adreno_idle(gpu, ring))
37 return false;
38
39 if (spin_until(_a6xx_check_idle(gpu))) {
40 DRM_ERROR("%s: %ps: timeout waiting for GPU to idle: status %8.8X irq %8.8X rptr/wptr %d/%d\n",
41 gpu->name, __builtin_return_address(0),
42 gpu_read(gpu, REG_A6XX_RBBM_STATUS),
43 gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS),
44 gpu_read(gpu, REG_A6XX_CP_RB_RPTR),
45 gpu_read(gpu, REG_A6XX_CP_RB_WPTR));
46 return false;
47 }
48
49 return true;
50}
51
52static void a6xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
53{
54 uint32_t wptr;
55 unsigned long flags;
56
57 spin_lock_irqsave(&ring->lock, flags);
58
59 /* Copy the shadow to the actual register */
60 ring->cur = ring->next;
61
62 /* Make sure to wrap wptr if we need to */
63 wptr = get_wptr(ring);
64
65 spin_unlock_irqrestore(&ring->lock, flags);
66
67 /* Make sure everything is posted before making a decision */
68 mb();
69
70 gpu_write(gpu, REG_A6XX_CP_RB_WPTR, wptr);
71}
72
73static void get_stats_counter(struct msm_ringbuffer *ring, u32 counter,
74 u64 iova)
75{
76 OUT_PKT7(ring, CP_REG_TO_MEM, 3);
77 OUT_RING(ring, CP_REG_TO_MEM_0_REG(counter) |
78 CP_REG_TO_MEM_0_CNT(2) |
79 CP_REG_TO_MEM_0_64B);
80 OUT_RING(ring, lower_32_bits(iova));
81 OUT_RING(ring, upper_32_bits(iova));
82}
83
84static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
85 struct msm_file_private *ctx)
86{
87 unsigned int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT;
88 struct msm_drm_private *priv = gpu->dev->dev_private;
89 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
90 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
91 struct msm_ringbuffer *ring = submit->ring;
92 unsigned int i;
93
94 get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP_0_LO,
95 rbmemptr_stats(ring, index, cpcycles_start));
96
97 /*
98 * For PM4 the GMU register offsets are calculated from the base of the
99 * GPU registers so we need to add 0x1a800 to the register value on A630
100 * to get the right value from PM4.
101 */
102 get_stats_counter(ring, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L + 0x1a800,
103 rbmemptr_stats(ring, index, alwayson_start));
104
105 /* Invalidate CCU depth and color */
106 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
107 OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(PC_CCU_INVALIDATE_DEPTH));
108
109 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
110 OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(PC_CCU_INVALIDATE_COLOR));
111
112 /* Submit the commands */
113 for (i = 0; i < submit->nr_cmds; i++) {
114 switch (submit->cmd[i].type) {
115 case MSM_SUBMIT_CMD_IB_TARGET_BUF:
116 break;
117 case MSM_SUBMIT_CMD_CTX_RESTORE_BUF:
118 if (priv->lastctx == ctx)
119 break;
120 fallthrough;
121 case MSM_SUBMIT_CMD_BUF:
122 OUT_PKT7(ring, CP_INDIRECT_BUFFER_PFE, 3);
123 OUT_RING(ring, lower_32_bits(submit->cmd[i].iova));
124 OUT_RING(ring, upper_32_bits(submit->cmd[i].iova));
125 OUT_RING(ring, submit->cmd[i].size);
126 break;
127 }
128 }
129
130 get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP_0_LO,
131 rbmemptr_stats(ring, index, cpcycles_end));
132 get_stats_counter(ring, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L + 0x1a800,
133 rbmemptr_stats(ring, index, alwayson_end));
134
135 /* Write the fence to the scratch register */
136 OUT_PKT4(ring, REG_A6XX_CP_SCRATCH_REG(2), 1);
137 OUT_RING(ring, submit->seqno);
138
139 /*
140 * Execute a CACHE_FLUSH_TS event. This will ensure that the
141 * timestamp is written to the memory and then triggers the interrupt
142 */
143 OUT_PKT7(ring, CP_EVENT_WRITE, 4);
144 OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(CACHE_FLUSH_TS) |
145 CP_EVENT_WRITE_0_IRQ);
146 OUT_RING(ring, lower_32_bits(rbmemptr(ring, fence)));
147 OUT_RING(ring, upper_32_bits(rbmemptr(ring, fence)));
148 OUT_RING(ring, submit->seqno);
149
150 trace_msm_gpu_submit_flush(submit,
151 gmu_read64(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L,
152 REG_A6XX_GMU_ALWAYS_ON_COUNTER_H));
153
154 a6xx_flush(gpu, ring);
155}
156
157const struct adreno_reglist a630_hwcg[] = {
158 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222},
159 {REG_A6XX_RBBM_CLOCK_CNTL_SP1, 0x22222222},
160 {REG_A6XX_RBBM_CLOCK_CNTL_SP2, 0x22222222},
161 {REG_A6XX_RBBM_CLOCK_CNTL_SP3, 0x22222222},
162 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02022220},
163 {REG_A6XX_RBBM_CLOCK_CNTL2_SP1, 0x02022220},
164 {REG_A6XX_RBBM_CLOCK_CNTL2_SP2, 0x02022220},
165 {REG_A6XX_RBBM_CLOCK_CNTL2_SP3, 0x02022220},
166 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
167 {REG_A6XX_RBBM_CLOCK_DELAY_SP1, 0x00000080},
168 {REG_A6XX_RBBM_CLOCK_DELAY_SP2, 0x00000080},
169 {REG_A6XX_RBBM_CLOCK_DELAY_SP3, 0x00000080},
170 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf},
171 {REG_A6XX_RBBM_CLOCK_HYST_SP1, 0x0000f3cf},
172 {REG_A6XX_RBBM_CLOCK_HYST_SP2, 0x0000f3cf},
173 {REG_A6XX_RBBM_CLOCK_HYST_SP3, 0x0000f3cf},
174 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
175 {REG_A6XX_RBBM_CLOCK_CNTL_TP1, 0x02222222},
176 {REG_A6XX_RBBM_CLOCK_CNTL_TP2, 0x02222222},
177 {REG_A6XX_RBBM_CLOCK_CNTL_TP3, 0x02222222},
178 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
179 {REG_A6XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222},
180 {REG_A6XX_RBBM_CLOCK_CNTL2_TP2, 0x22222222},
181 {REG_A6XX_RBBM_CLOCK_CNTL2_TP3, 0x22222222},
182 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
183 {REG_A6XX_RBBM_CLOCK_CNTL3_TP1, 0x22222222},
184 {REG_A6XX_RBBM_CLOCK_CNTL3_TP2, 0x22222222},
185 {REG_A6XX_RBBM_CLOCK_CNTL3_TP3, 0x22222222},
186 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
187 {REG_A6XX_RBBM_CLOCK_CNTL4_TP1, 0x00022222},
188 {REG_A6XX_RBBM_CLOCK_CNTL4_TP2, 0x00022222},
189 {REG_A6XX_RBBM_CLOCK_CNTL4_TP3, 0x00022222},
190 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
191 {REG_A6XX_RBBM_CLOCK_HYST_TP1, 0x77777777},
192 {REG_A6XX_RBBM_CLOCK_HYST_TP2, 0x77777777},
193 {REG_A6XX_RBBM_CLOCK_HYST_TP3, 0x77777777},
194 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
195 {REG_A6XX_RBBM_CLOCK_HYST2_TP1, 0x77777777},
196 {REG_A6XX_RBBM_CLOCK_HYST2_TP2, 0x77777777},
197 {REG_A6XX_RBBM_CLOCK_HYST2_TP3, 0x77777777},
198 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
199 {REG_A6XX_RBBM_CLOCK_HYST3_TP1, 0x77777777},
200 {REG_A6XX_RBBM_CLOCK_HYST3_TP2, 0x77777777},
201 {REG_A6XX_RBBM_CLOCK_HYST3_TP3, 0x77777777},
202 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
203 {REG_A6XX_RBBM_CLOCK_HYST4_TP1, 0x00077777},
204 {REG_A6XX_RBBM_CLOCK_HYST4_TP2, 0x00077777},
205 {REG_A6XX_RBBM_CLOCK_HYST4_TP3, 0x00077777},
206 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
207 {REG_A6XX_RBBM_CLOCK_DELAY_TP1, 0x11111111},
208 {REG_A6XX_RBBM_CLOCK_DELAY_TP2, 0x11111111},
209 {REG_A6XX_RBBM_CLOCK_DELAY_TP3, 0x11111111},
210 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
211 {REG_A6XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111},
212 {REG_A6XX_RBBM_CLOCK_DELAY2_TP2, 0x11111111},
213 {REG_A6XX_RBBM_CLOCK_DELAY2_TP3, 0x11111111},
214 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
215 {REG_A6XX_RBBM_CLOCK_DELAY3_TP1, 0x11111111},
216 {REG_A6XX_RBBM_CLOCK_DELAY3_TP2, 0x11111111},
217 {REG_A6XX_RBBM_CLOCK_DELAY3_TP3, 0x11111111},
218 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
219 {REG_A6XX_RBBM_CLOCK_DELAY4_TP1, 0x00011111},
220 {REG_A6XX_RBBM_CLOCK_DELAY4_TP2, 0x00011111},
221 {REG_A6XX_RBBM_CLOCK_DELAY4_TP3, 0x00011111},
222 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
223 {REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222},
224 {REG_A6XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222},
225 {REG_A6XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222},
226 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
227 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
228 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
229 {REG_A6XX_RBBM_CLOCK_CNTL_RB1, 0x22222222},
230 {REG_A6XX_RBBM_CLOCK_CNTL_RB2, 0x22222222},
231 {REG_A6XX_RBBM_CLOCK_CNTL_RB3, 0x22222222},
232 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x00002222},
233 {REG_A6XX_RBBM_CLOCK_CNTL2_RB1, 0x00002222},
234 {REG_A6XX_RBBM_CLOCK_CNTL2_RB2, 0x00002222},
235 {REG_A6XX_RBBM_CLOCK_CNTL2_RB3, 0x00002222},
236 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
237 {REG_A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00002220},
238 {REG_A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00002220},
239 {REG_A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00002220},
240 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00},
241 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1, 0x00040f00},
242 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2, 0x00040f00},
243 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3, 0x00040f00},
244 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05022022},
245 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
246 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
247 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
248 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
249 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
250 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
251 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
252 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
253 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
254 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
255 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
256 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
257 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
258 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
259 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
260 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
261 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
262 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
263 {},
264};
265
266const struct adreno_reglist a640_hwcg[] = {
267 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
268 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
269 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
270 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
271 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
272 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
273 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
274 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
275 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
276 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
277 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
278 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
279 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
280 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
281 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
282 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
283 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
284 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
285 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
286 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
287 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05222022},
288 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
289 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
290 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
291 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
292 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
293 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
294 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
295 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
296 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
297 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
298 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
299 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
300 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
301 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
302 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
303 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
304 {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
305 {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
306 {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000},
307 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
308 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
309 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
310 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
311 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
312 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
313 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
314 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
315 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
316 {},
317};
318
319const struct adreno_reglist a650_hwcg[] = {
320 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
321 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
322 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
323 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
324 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
325 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
326 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
327 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
328 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
329 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
330 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
331 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
332 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
333 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
334 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
335 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
336 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
337 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
338 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
339 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
340 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},
341 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
342 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
343 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
344 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
345 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
346 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
347 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
348 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
349 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
350 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
351 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
352 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
353 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
354 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
355 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
356 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
357 {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
358 {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
359 {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000777},
360 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
361 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
362 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
363 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
364 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
365 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
366 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
367 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
368 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
369 {},
370};
371
372static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
373{
374 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
375 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
376 struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
377 const struct adreno_reglist *reg;
378 unsigned int i;
379 u32 val, clock_cntl_on;
380
381 if (!adreno_gpu->info->hwcg)
382 return;
383
384 if (adreno_is_a630(adreno_gpu))
385 clock_cntl_on = 0x8aa8aa02;
386 else
387 clock_cntl_on = 0x8aa8aa82;
388
389 val = gpu_read(gpu, REG_A6XX_RBBM_CLOCK_CNTL);
390
391 /* Don't re-program the registers if they are already correct */
392 if ((!state && !val) || (state && (val == clock_cntl_on)))
393 return;
394
395 /* Disable SP clock before programming HWCG registers */
396 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0);
397
398 for (i = 0; (reg = &adreno_gpu->info->hwcg[i], reg->offset); i++)
399 gpu_write(gpu, reg->offset, state ? reg->value : 0);
400
401 /* Enable SP clock */
402 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1);
403
404 gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? clock_cntl_on : 0);
405}
406
407static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
408{
409 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
410 u32 lower_bit = 2;
411 u32 amsbc = 0;
412 u32 rgb565_predicator = 0;
413 u32 uavflagprd_inv = 0;
414
415 /* a618 is using the hw default values */
416 if (adreno_is_a618(adreno_gpu))
417 return;
418
419 if (adreno_is_a640(adreno_gpu))
420 amsbc = 1;
421
422 if (adreno_is_a650(adreno_gpu)) {
423 /* TODO: get ddr type from bootloader and use 2 for LPDDR4 */
424 lower_bit = 3;
425 amsbc = 1;
426 rgb565_predicator = 1;
427 uavflagprd_inv = 2;
428 }
429
430 gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL,
431 rgb565_predicator << 11 | amsbc << 4 | lower_bit << 1);
432 gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, lower_bit << 1);
433 gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL,
434 uavflagprd_inv >> 4 | lower_bit << 1);
435 gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, lower_bit << 21);
436}
437
438static int a6xx_cp_init(struct msm_gpu *gpu)
439{
440 struct msm_ringbuffer *ring = gpu->rb[0];
441
442 OUT_PKT7(ring, CP_ME_INIT, 8);
443
444 OUT_RING(ring, 0x0000002f);
445
446 /* Enable multiple hardware contexts */
447 OUT_RING(ring, 0x00000003);
448
449 /* Enable error detection */
450 OUT_RING(ring, 0x20000000);
451
452 /* Don't enable header dump */
453 OUT_RING(ring, 0x00000000);
454 OUT_RING(ring, 0x00000000);
455
456 /* No workarounds enabled */
457 OUT_RING(ring, 0x00000000);
458
459 /* Pad rest of the cmds with 0's */
460 OUT_RING(ring, 0x00000000);
461 OUT_RING(ring, 0x00000000);
462
463 a6xx_flush(gpu, ring);
464 return a6xx_idle(gpu, ring) ? 0 : -EINVAL;
465}
466
467static int a6xx_ucode_init(struct msm_gpu *gpu)
468{
469 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
470 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
471
472 if (!a6xx_gpu->sqe_bo) {
473 a6xx_gpu->sqe_bo = adreno_fw_create_bo(gpu,
474 adreno_gpu->fw[ADRENO_FW_SQE], &a6xx_gpu->sqe_iova);
475
476 if (IS_ERR(a6xx_gpu->sqe_bo)) {
477 int ret = PTR_ERR(a6xx_gpu->sqe_bo);
478
479 a6xx_gpu->sqe_bo = NULL;
480 DRM_DEV_ERROR(&gpu->pdev->dev,
481 "Could not allocate SQE ucode: %d\n", ret);
482
483 return ret;
484 }
485
486 msm_gem_object_set_name(a6xx_gpu->sqe_bo, "sqefw");
487 }
488
489 gpu_write64(gpu, REG_A6XX_CP_SQE_INSTR_BASE_LO,
490 REG_A6XX_CP_SQE_INSTR_BASE_HI, a6xx_gpu->sqe_iova);
491
492 return 0;
493}
494
495static int a6xx_zap_shader_init(struct msm_gpu *gpu)
496{
497 static bool loaded;
498 int ret;
499
500 if (loaded)
501 return 0;
502
503 ret = adreno_zap_shader_load(gpu, GPU_PAS_ID);
504
505 loaded = !ret;
506 return ret;
507}
508
509#define A6XX_INT_MASK (A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR | \
510 A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW | \
511 A6XX_RBBM_INT_0_MASK_CP_HW_ERROR | \
512 A6XX_RBBM_INT_0_MASK_CP_IB2 | \
513 A6XX_RBBM_INT_0_MASK_CP_IB1 | \
514 A6XX_RBBM_INT_0_MASK_CP_RB | \
515 A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS | \
516 A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW | \
517 A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \
518 A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \
519 A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR)
520
521static int a6xx_hw_init(struct msm_gpu *gpu)
522{
523 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
524 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
525 int ret;
526
527 /* Make sure the GMU keeps the GPU on while we set it up */
528 a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET);
529
530 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0);
531
532 /*
533 * Disable the trusted memory range - we don't actually supported secure
534 * memory rendering at this point in time and we don't want to block off
535 * part of the virtual memory space.
536 */
537 gpu_write64(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO,
538 REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI, 0x00000000);
539 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x00000000);
540
541 /* Turn on 64 bit addressing for all blocks */
542 gpu_write(gpu, REG_A6XX_CP_ADDR_MODE_CNTL, 0x1);
543 gpu_write(gpu, REG_A6XX_VSC_ADDR_MODE_CNTL, 0x1);
544 gpu_write(gpu, REG_A6XX_GRAS_ADDR_MODE_CNTL, 0x1);
545 gpu_write(gpu, REG_A6XX_RB_ADDR_MODE_CNTL, 0x1);
546 gpu_write(gpu, REG_A6XX_PC_ADDR_MODE_CNTL, 0x1);
547 gpu_write(gpu, REG_A6XX_HLSQ_ADDR_MODE_CNTL, 0x1);
548 gpu_write(gpu, REG_A6XX_VFD_ADDR_MODE_CNTL, 0x1);
549 gpu_write(gpu, REG_A6XX_VPC_ADDR_MODE_CNTL, 0x1);
550 gpu_write(gpu, REG_A6XX_UCHE_ADDR_MODE_CNTL, 0x1);
551 gpu_write(gpu, REG_A6XX_SP_ADDR_MODE_CNTL, 0x1);
552 gpu_write(gpu, REG_A6XX_TPL1_ADDR_MODE_CNTL, 0x1);
553 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1);
554
555 /* enable hardware clockgating */
556 a6xx_set_hwcg(gpu, true);
557
558 /* VBIF/GBIF start*/
559 if (adreno_is_a640(adreno_gpu) || adreno_is_a650(adreno_gpu)) {
560 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE0, 0x00071620);
561 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE1, 0x00071620);
562 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE2, 0x00071620);
563 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620);
564 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620);
565 gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x3);
566 } else {
567 gpu_write(gpu, REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3);
568 }
569
570 if (adreno_is_a630(adreno_gpu))
571 gpu_write(gpu, REG_A6XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009);
572
573 /* Make all blocks contribute to the GPU BUSY perf counter */
574 gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xffffffff);
575
576 /* Disable L2 bypass in the UCHE */
577 gpu_write(gpu, REG_A6XX_UCHE_WRITE_RANGE_MAX_LO, 0xffffffc0);
578 gpu_write(gpu, REG_A6XX_UCHE_WRITE_RANGE_MAX_HI, 0x0001ffff);
579 gpu_write(gpu, REG_A6XX_UCHE_TRAP_BASE_LO, 0xfffff000);
580 gpu_write(gpu, REG_A6XX_UCHE_TRAP_BASE_HI, 0x0001ffff);
581 gpu_write(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_LO, 0xfffff000);
582 gpu_write(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_HI, 0x0001ffff);
583
584 if (!adreno_is_a650(adreno_gpu)) {
585 /* Set the GMEM VA range [0x100000:0x100000 + gpu->gmem - 1] */
586 gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MIN_LO,
587 REG_A6XX_UCHE_GMEM_RANGE_MIN_HI, 0x00100000);
588
589 gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MAX_LO,
590 REG_A6XX_UCHE_GMEM_RANGE_MAX_HI,
591 0x00100000 + adreno_gpu->gmem - 1);
592 }
593
594 gpu_write(gpu, REG_A6XX_UCHE_FILTER_CNTL, 0x804);
595 gpu_write(gpu, REG_A6XX_UCHE_CACHE_WAYS, 0x4);
596
597 if (adreno_is_a640(adreno_gpu) || adreno_is_a650(adreno_gpu))
598 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140);
599 else
600 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x010000c0);
601 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c);
602
603 /* Setting the mem pool size */
604 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128);
605
606 /* Setting the primFifo thresholds default values */
607 if (adreno_is_a650(adreno_gpu))
608 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300000);
609 else if (adreno_is_a640(adreno_gpu))
610 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200000);
611 else
612 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, (0x300 << 11));
613
614 /* Set the AHB default slave response to "ERROR" */
615 gpu_write(gpu, REG_A6XX_CP_AHB_CNTL, 0x1);
616
617 /* Turn on performance counters */
618 gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_CNTL, 0x1);
619
620 /* Select CP0 to always count cycles */
621 gpu_write(gpu, REG_A6XX_CP_PERFCTR_CP_SEL_0, PERF_CP_ALWAYS_COUNT);
622
623 a6xx_set_ubwc_config(gpu);
624
625 /* Enable fault detection */
626 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL,
627 (1 << 30) | 0x1fffff);
628
629 gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, 1);
630
631 /* Set weights for bicubic filtering */
632 if (adreno_is_a650(adreno_gpu)) {
633 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0, 0);
634 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1,
635 0x3fe05ff4);
636 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2,
637 0x3fa0ebee);
638 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3,
639 0x3f5193ed);
640 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4,
641 0x3f0243f0);
642 }
643
644 /* Protect registers from the CP */
645 gpu_write(gpu, REG_A6XX_CP_PROTECT_CNTL, 0x00000003);
646
647 gpu_write(gpu, REG_A6XX_CP_PROTECT(0),
648 A6XX_PROTECT_RDONLY(0x600, 0x51));
649 gpu_write(gpu, REG_A6XX_CP_PROTECT(1), A6XX_PROTECT_RW(0xae50, 0x2));
650 gpu_write(gpu, REG_A6XX_CP_PROTECT(2), A6XX_PROTECT_RW(0x9624, 0x13));
651 gpu_write(gpu, REG_A6XX_CP_PROTECT(3), A6XX_PROTECT_RW(0x8630, 0x8));
652 gpu_write(gpu, REG_A6XX_CP_PROTECT(4), A6XX_PROTECT_RW(0x9e70, 0x1));
653 gpu_write(gpu, REG_A6XX_CP_PROTECT(5), A6XX_PROTECT_RW(0x9e78, 0x187));
654 gpu_write(gpu, REG_A6XX_CP_PROTECT(6), A6XX_PROTECT_RW(0xf000, 0x810));
655 gpu_write(gpu, REG_A6XX_CP_PROTECT(7),
656 A6XX_PROTECT_RDONLY(0xfc00, 0x3));
657 gpu_write(gpu, REG_A6XX_CP_PROTECT(8), A6XX_PROTECT_RW(0x50e, 0x0));
658 gpu_write(gpu, REG_A6XX_CP_PROTECT(9), A6XX_PROTECT_RDONLY(0x50f, 0x0));
659 gpu_write(gpu, REG_A6XX_CP_PROTECT(10), A6XX_PROTECT_RW(0x510, 0x0));
660 gpu_write(gpu, REG_A6XX_CP_PROTECT(11),
661 A6XX_PROTECT_RDONLY(0x0, 0x4f9));
662 gpu_write(gpu, REG_A6XX_CP_PROTECT(12),
663 A6XX_PROTECT_RDONLY(0x501, 0xa));
664 gpu_write(gpu, REG_A6XX_CP_PROTECT(13),
665 A6XX_PROTECT_RDONLY(0x511, 0x44));
666 gpu_write(gpu, REG_A6XX_CP_PROTECT(14), A6XX_PROTECT_RW(0xe00, 0xe));
667 gpu_write(gpu, REG_A6XX_CP_PROTECT(15), A6XX_PROTECT_RW(0x8e00, 0x0));
668 gpu_write(gpu, REG_A6XX_CP_PROTECT(16), A6XX_PROTECT_RW(0x8e50, 0xf));
669 gpu_write(gpu, REG_A6XX_CP_PROTECT(17), A6XX_PROTECT_RW(0xbe02, 0x0));
670 gpu_write(gpu, REG_A6XX_CP_PROTECT(18),
671 A6XX_PROTECT_RW(0xbe20, 0x11f3));
672 gpu_write(gpu, REG_A6XX_CP_PROTECT(19), A6XX_PROTECT_RW(0x800, 0x82));
673 gpu_write(gpu, REG_A6XX_CP_PROTECT(20), A6XX_PROTECT_RW(0x8a0, 0x8));
674 gpu_write(gpu, REG_A6XX_CP_PROTECT(21), A6XX_PROTECT_RW(0x8ab, 0x19));
675 gpu_write(gpu, REG_A6XX_CP_PROTECT(22), A6XX_PROTECT_RW(0x900, 0x4d));
676 gpu_write(gpu, REG_A6XX_CP_PROTECT(23), A6XX_PROTECT_RW(0x98d, 0x76));
677 gpu_write(gpu, REG_A6XX_CP_PROTECT(24),
678 A6XX_PROTECT_RDONLY(0x980, 0x4));
679 gpu_write(gpu, REG_A6XX_CP_PROTECT(25), A6XX_PROTECT_RW(0xa630, 0x0));
680
681 /* Enable expanded apriv for targets that support it */
682 if (gpu->hw_apriv) {
683 gpu_write(gpu, REG_A6XX_CP_APRIV_CNTL,
684 (1 << 6) | (1 << 5) | (1 << 3) | (1 << 2) | (1 << 1));
685 }
686
687 /* Enable interrupts */
688 gpu_write(gpu, REG_A6XX_RBBM_INT_0_MASK, A6XX_INT_MASK);
689
690 ret = adreno_hw_init(gpu);
691 if (ret)
692 goto out;
693
694 ret = a6xx_ucode_init(gpu);
695 if (ret)
696 goto out;
697
698 /* Set the ringbuffer address */
699 gpu_write64(gpu, REG_A6XX_CP_RB_BASE, REG_A6XX_CP_RB_BASE_HI,
700 gpu->rb[0]->iova);
701
702 gpu_write(gpu, REG_A6XX_CP_RB_CNTL,
703 MSM_GPU_RB_CNTL_DEFAULT | AXXX_CP_RB_CNTL_NO_UPDATE);
704
705 /* Always come up on rb 0 */
706 a6xx_gpu->cur_ring = gpu->rb[0];
707
708 /* Enable the SQE_to start the CP engine */
709 gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 1);
710
711 ret = a6xx_cp_init(gpu);
712 if (ret)
713 goto out;
714
715 /*
716 * Try to load a zap shader into the secure world. If successful
717 * we can use the CP to switch out of secure mode. If not then we
718 * have no resource but to try to switch ourselves out manually. If we
719 * guessed wrong then access to the RBBM_SECVID_TRUST_CNTL register will
720 * be blocked and a permissions violation will soon follow.
721 */
722 ret = a6xx_zap_shader_init(gpu);
723 if (!ret) {
724 OUT_PKT7(gpu->rb[0], CP_SET_SECURE_MODE, 1);
725 OUT_RING(gpu->rb[0], 0x00000000);
726
727 a6xx_flush(gpu, gpu->rb[0]);
728 if (!a6xx_idle(gpu, gpu->rb[0]))
729 return -EINVAL;
730 } else if (ret == -ENODEV) {
731 /*
732 * This device does not use zap shader (but print a warning
733 * just in case someone got their dt wrong.. hopefully they
734 * have a debug UART to realize the error of their ways...
735 * if you mess this up you are about to crash horribly)
736 */
737 dev_warn_once(gpu->dev->dev,
738 "Zap shader not enabled - using SECVID_TRUST_CNTL instead\n");
739 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TRUST_CNTL, 0x0);
740 ret = 0;
741 } else {
742 return ret;
743 }
744
745out:
746 /*
747 * Tell the GMU that we are done touching the GPU and it can start power
748 * management
749 */
750 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET);
751
752 if (a6xx_gpu->gmu.legacy) {
753 /* Take the GMU out of its special boot mode */
754 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_BOOT_SLUMBER);
755 }
756
757 return ret;
758}
759
760static void a6xx_dump(struct msm_gpu *gpu)
761{
762 DRM_DEV_INFO(&gpu->pdev->dev, "status: %08x\n",
763 gpu_read(gpu, REG_A6XX_RBBM_STATUS));
764 adreno_dump(gpu);
765}
766
767#define VBIF_RESET_ACK_TIMEOUT 100
768#define VBIF_RESET_ACK_MASK 0x00f0
769
770static void a6xx_recover(struct msm_gpu *gpu)
771{
772 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
773 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
774 int i;
775
776 adreno_dump_info(gpu);
777
778 for (i = 0; i < 8; i++)
779 DRM_DEV_INFO(&gpu->pdev->dev, "CP_SCRATCH_REG%d: %u\n", i,
780 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(i)));
781
782 if (hang_debug)
783 a6xx_dump(gpu);
784
785 /*
786 * Turn off keep alive that might have been enabled by the hang
787 * interrupt
788 */
789 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 0);
790
791 gpu->funcs->pm_suspend(gpu);
792 gpu->funcs->pm_resume(gpu);
793
794 msm_gpu_hw_init(gpu);
795}
796
797static int a6xx_fault_handler(void *arg, unsigned long iova, int flags)
798{
799 struct msm_gpu *gpu = arg;
800
801 pr_warn_ratelimited("*** gpu fault: iova=%08lx, flags=%d (%u,%u,%u,%u)\n",
802 iova, flags,
803 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(4)),
804 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(5)),
805 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(6)),
806 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(7)));
807
808 return -EFAULT;
809}
810
811static void a6xx_cp_hw_err_irq(struct msm_gpu *gpu)
812{
813 u32 status = gpu_read(gpu, REG_A6XX_CP_INTERRUPT_STATUS);
814
815 if (status & A6XX_CP_INT_CP_OPCODE_ERROR) {
816 u32 val;
817
818 gpu_write(gpu, REG_A6XX_CP_SQE_STAT_ADDR, 1);
819 val = gpu_read(gpu, REG_A6XX_CP_SQE_STAT_DATA);
820 dev_err_ratelimited(&gpu->pdev->dev,
821 "CP | opcode error | possible opcode=0x%8.8X\n",
822 val);
823 }
824
825 if (status & A6XX_CP_INT_CP_UCODE_ERROR)
826 dev_err_ratelimited(&gpu->pdev->dev,
827 "CP ucode error interrupt\n");
828
829 if (status & A6XX_CP_INT_CP_HW_FAULT_ERROR)
830 dev_err_ratelimited(&gpu->pdev->dev, "CP | HW fault | status=0x%8.8X\n",
831 gpu_read(gpu, REG_A6XX_CP_HW_FAULT));
832
833 if (status & A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR) {
834 u32 val = gpu_read(gpu, REG_A6XX_CP_PROTECT_STATUS);
835
836 dev_err_ratelimited(&gpu->pdev->dev,
837 "CP | protected mode error | %s | addr=0x%8.8X | status=0x%8.8X\n",
838 val & (1 << 20) ? "READ" : "WRITE",
839 (val & 0x3ffff), val);
840 }
841
842 if (status & A6XX_CP_INT_CP_AHB_ERROR)
843 dev_err_ratelimited(&gpu->pdev->dev, "CP AHB error interrupt\n");
844
845 if (status & A6XX_CP_INT_CP_VSD_PARITY_ERROR)
846 dev_err_ratelimited(&gpu->pdev->dev, "CP VSD decoder parity error\n");
847
848 if (status & A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR)
849 dev_err_ratelimited(&gpu->pdev->dev, "CP illegal instruction error\n");
850
851}
852
853static void a6xx_fault_detect_irq(struct msm_gpu *gpu)
854{
855 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
856 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
857 struct drm_device *dev = gpu->dev;
858 struct msm_drm_private *priv = dev->dev_private;
859 struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu);
860
861 /*
862 * Force the GPU to stay on until after we finish
863 * collecting information
864 */
865 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 1);
866
867 DRM_DEV_ERROR(&gpu->pdev->dev,
868 "gpu fault ring %d fence %x status %8.8X rb %4.4x/%4.4x ib1 %16.16llX/%4.4x ib2 %16.16llX/%4.4x\n",
869 ring ? ring->id : -1, ring ? ring->seqno : 0,
870 gpu_read(gpu, REG_A6XX_RBBM_STATUS),
871 gpu_read(gpu, REG_A6XX_CP_RB_RPTR),
872 gpu_read(gpu, REG_A6XX_CP_RB_WPTR),
873 gpu_read64(gpu, REG_A6XX_CP_IB1_BASE, REG_A6XX_CP_IB1_BASE_HI),
874 gpu_read(gpu, REG_A6XX_CP_IB1_REM_SIZE),
875 gpu_read64(gpu, REG_A6XX_CP_IB2_BASE, REG_A6XX_CP_IB2_BASE_HI),
876 gpu_read(gpu, REG_A6XX_CP_IB2_REM_SIZE));
877
878 /* Turn off the hangcheck timer to keep it from bothering us */
879 del_timer(&gpu->hangcheck_timer);
880
881 queue_work(priv->wq, &gpu->recover_work);
882}
883
884static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
885{
886 u32 status = gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS);
887
888 gpu_write(gpu, REG_A6XX_RBBM_INT_CLEAR_CMD, status);
889
890 if (status & A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT)
891 a6xx_fault_detect_irq(gpu);
892
893 if (status & A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR)
894 dev_err_ratelimited(&gpu->pdev->dev, "CP | AHB bus error\n");
895
896 if (status & A6XX_RBBM_INT_0_MASK_CP_HW_ERROR)
897 a6xx_cp_hw_err_irq(gpu);
898
899 if (status & A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW)
900 dev_err_ratelimited(&gpu->pdev->dev, "RBBM | ATB ASYNC overflow\n");
901
902 if (status & A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW)
903 dev_err_ratelimited(&gpu->pdev->dev, "RBBM | ATB bus overflow\n");
904
905 if (status & A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS)
906 dev_err_ratelimited(&gpu->pdev->dev, "UCHE | Out of bounds access\n");
907
908 if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS)
909 msm_gpu_retire(gpu);
910
911 return IRQ_HANDLED;
912}
913
914static const u32 a6xx_register_offsets[REG_ADRENO_REGISTER_MAX] = {
915 REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_BASE, REG_A6XX_CP_RB_BASE),
916 REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_BASE_HI, REG_A6XX_CP_RB_BASE_HI),
917 REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR_ADDR,
918 REG_A6XX_CP_RB_RPTR_ADDR_LO),
919 REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR_ADDR_HI,
920 REG_A6XX_CP_RB_RPTR_ADDR_HI),
921 REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR, REG_A6XX_CP_RB_RPTR),
922 REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_WPTR, REG_A6XX_CP_RB_WPTR),
923 REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_CNTL, REG_A6XX_CP_RB_CNTL),
924};
925
926static int a6xx_pm_resume(struct msm_gpu *gpu)
927{
928 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
929 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
930 int ret;
931
932 gpu->needs_hw_init = true;
933
934 ret = a6xx_gmu_resume(a6xx_gpu);
935 if (ret)
936 return ret;
937
938 msm_gpu_resume_devfreq(gpu);
939
940 return 0;
941}
942
943static int a6xx_pm_suspend(struct msm_gpu *gpu)
944{
945 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
946 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
947
948 devfreq_suspend_device(gpu->devfreq.devfreq);
949
950 return a6xx_gmu_stop(a6xx_gpu);
951}
952
953static int a6xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value)
954{
955 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
956 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
957
958 /* Force the GPU power on so we can read this register */
959 a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET);
960
961 *value = gpu_read64(gpu, REG_A6XX_RBBM_PERFCTR_CP_0_LO,
962 REG_A6XX_RBBM_PERFCTR_CP_0_HI);
963
964 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET);
965 return 0;
966}
967
968static struct msm_ringbuffer *a6xx_active_ring(struct msm_gpu *gpu)
969{
970 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
971 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
972
973 return a6xx_gpu->cur_ring;
974}
975
976static void a6xx_destroy(struct msm_gpu *gpu)
977{
978 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
979 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
980
981 if (a6xx_gpu->sqe_bo) {
982 msm_gem_unpin_iova(a6xx_gpu->sqe_bo, gpu->aspace);
983 drm_gem_object_put(a6xx_gpu->sqe_bo);
984 }
985
986 a6xx_gmu_remove(a6xx_gpu);
987
988 adreno_gpu_cleanup(adreno_gpu);
989 kfree(a6xx_gpu);
990}
991
992static unsigned long a6xx_gpu_busy(struct msm_gpu *gpu)
993{
994 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
995 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
996 u64 busy_cycles, busy_time;
997
998
999 /* Only read the gpu busy if the hardware is already active */
1000 if (pm_runtime_get_if_in_use(a6xx_gpu->gmu.dev) == 0)
1001 return 0;
1002
1003 busy_cycles = gmu_read64(&a6xx_gpu->gmu,
1004 REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L,
1005 REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H);
1006
1007 busy_time = (busy_cycles - gpu->devfreq.busy_cycles) * 10;
1008 do_div(busy_time, 192);
1009
1010 gpu->devfreq.busy_cycles = busy_cycles;
1011
1012 pm_runtime_put(a6xx_gpu->gmu.dev);
1013
1014 if (WARN_ON(busy_time > ~0LU))
1015 return ~0LU;
1016
1017 return (unsigned long)busy_time;
1018}
1019
1020static const struct adreno_gpu_funcs funcs = {
1021 .base = {
1022 .get_param = adreno_get_param,
1023 .hw_init = a6xx_hw_init,
1024 .pm_suspend = a6xx_pm_suspend,
1025 .pm_resume = a6xx_pm_resume,
1026 .recover = a6xx_recover,
1027 .submit = a6xx_submit,
1028 .flush = a6xx_flush,
1029 .active_ring = a6xx_active_ring,
1030 .irq = a6xx_irq,
1031 .destroy = a6xx_destroy,
1032#if defined(CONFIG_DRM_MSM_GPU_STATE)
1033 .show = a6xx_show,
1034#endif
1035 .gpu_busy = a6xx_gpu_busy,
1036 .gpu_get_freq = a6xx_gmu_get_freq,
1037 .gpu_set_freq = a6xx_gmu_set_freq,
1038#if defined(CONFIG_DRM_MSM_GPU_STATE)
1039 .gpu_state_get = a6xx_gpu_state_get,
1040 .gpu_state_put = a6xx_gpu_state_put,
1041#endif
1042 .create_address_space = adreno_iommu_create_address_space,
1043 },
1044 .get_timestamp = a6xx_get_timestamp,
1045};
1046
1047struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
1048{
1049 struct msm_drm_private *priv = dev->dev_private;
1050 struct platform_device *pdev = priv->gpu_pdev;
1051 struct device_node *node;
1052 struct a6xx_gpu *a6xx_gpu;
1053 struct adreno_gpu *adreno_gpu;
1054 struct msm_gpu *gpu;
1055 int ret;
1056
1057 a6xx_gpu = kzalloc(sizeof(*a6xx_gpu), GFP_KERNEL);
1058 if (!a6xx_gpu)
1059 return ERR_PTR(-ENOMEM);
1060
1061 adreno_gpu = &a6xx_gpu->base;
1062 gpu = &adreno_gpu->base;
1063
1064 adreno_gpu->registers = NULL;
1065 adreno_gpu->reg_offsets = a6xx_register_offsets;
1066
1067 if (adreno_is_a650(adreno_gpu))
1068 adreno_gpu->base.hw_apriv = true;
1069
1070 ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1);
1071 if (ret) {
1072 a6xx_destroy(&(a6xx_gpu->base.base));
1073 return ERR_PTR(ret);
1074 }
1075
1076 /* Check if there is a GMU phandle and set it up */
1077 node = of_parse_phandle(pdev->dev.of_node, "qcom,gmu", 0);
1078
1079 /* FIXME: How do we gracefully handle this? */
1080 BUG_ON(!node);
1081
1082 ret = a6xx_gmu_init(a6xx_gpu, node);
1083 if (ret) {
1084 a6xx_destroy(&(a6xx_gpu->base.base));
1085 return ERR_PTR(ret);
1086 }
1087
1088 if (gpu->aspace)
1089 msm_mmu_set_fault_handler(gpu->aspace->mmu, gpu,
1090 a6xx_fault_handler);
1091
1092 return gpu;
1093}