1/* SPDX-License-Identifier: GPL-2.0 */
 2/*
 3 * Copyright (c) 2019 MediaTek Inc.
 4 * Author: Jitao Shi <jitao.shi@mediatek.com>
 5 */
 6
 7#ifndef _MTK_MIPI_TX_H
 8#define _MTK_MIPI_TX_H
 9
10#include <linux/clk.h>
11#include <linux/clk-provider.h>
12#include <linux/delay.h>
13#include <linux/io.h>
14#include <linux/module.h>
15#include <linux/nvmem-consumer.h>
16#include <linux/of_device.h>
17#include <linux/platform_device.h>
18#include <linux/phy/phy.h>
19#include <linux/slab.h>
20
21struct mtk_mipitx_data {
22	const u32 mppll_preserve;
23	const struct clk_ops *mipi_tx_clk_ops;
24	void (*mipi_tx_enable_signal)(struct phy *phy);
25	void (*mipi_tx_disable_signal)(struct phy *phy);
26};
27
28struct mtk_mipi_tx {
29	struct device *dev;
30	void __iomem *regs;
31	u32 data_rate;
32	u32 mipitx_drive;
33	u32 rt_code[5];
34	const struct mtk_mipitx_data *driver_data;
35	struct clk_hw pll_hw;
36	struct clk *pll;
37};
38
39struct mtk_mipi_tx *mtk_mipi_tx_from_clk_hw(struct clk_hw *hw);
40void mtk_mipi_tx_clear_bits(struct mtk_mipi_tx *mipi_tx, u32 offset, u32 bits);
41void mtk_mipi_tx_set_bits(struct mtk_mipi_tx *mipi_tx, u32 offset, u32 bits);
42void mtk_mipi_tx_update_bits(struct mtk_mipi_tx *mipi_tx, u32 offset, u32 mask,
43			     u32 data);
44int mtk_mipi_tx_pll_set_rate(struct clk_hw *hw, unsigned long rate,
45			     unsigned long parent_rate);
46unsigned long mtk_mipi_tx_pll_recalc_rate(struct clk_hw *hw,
47					  unsigned long parent_rate);
48
49extern const struct mtk_mipitx_data mt2701_mipitx_data;
50extern const struct mtk_mipitx_data mt8173_mipitx_data;
51extern const struct mtk_mipitx_data mt8183_mipitx_data;
52
53#endif