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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2015 MediaTek Inc.
4 */
5
6#include <linux/clk.h>
7#include <linux/component.h>
8#include <linux/module.h>
9#include <linux/of_device.h>
10#include <linux/of_irq.h>
11#include <linux/platform_device.h>
12#include <linux/soc/mediatek/mtk-cmdq.h>
13
14#include "mtk_drm_crtc.h"
15#include "mtk_drm_ddp_comp.h"
16
17#define DISP_REG_RDMA_INT_ENABLE 0x0000
18#define DISP_REG_RDMA_INT_STATUS 0x0004
19#define RDMA_TARGET_LINE_INT BIT(5)
20#define RDMA_FIFO_UNDERFLOW_INT BIT(4)
21#define RDMA_EOF_ABNORMAL_INT BIT(3)
22#define RDMA_FRAME_END_INT BIT(2)
23#define RDMA_FRAME_START_INT BIT(1)
24#define RDMA_REG_UPDATE_INT BIT(0)
25#define DISP_REG_RDMA_GLOBAL_CON 0x0010
26#define RDMA_ENGINE_EN BIT(0)
27#define RDMA_MODE_MEMORY BIT(1)
28#define DISP_REG_RDMA_SIZE_CON_0 0x0014
29#define RDMA_MATRIX_ENABLE BIT(17)
30#define RDMA_MATRIX_INT_MTX_SEL GENMASK(23, 20)
31#define RDMA_MATRIX_INT_MTX_BT601_to_RGB (6 << 20)
32#define DISP_REG_RDMA_SIZE_CON_1 0x0018
33#define DISP_REG_RDMA_TARGET_LINE 0x001c
34#define DISP_RDMA_MEM_CON 0x0024
35#define MEM_MODE_INPUT_FORMAT_RGB565 (0x000 << 4)
36#define MEM_MODE_INPUT_FORMAT_RGB888 (0x001 << 4)
37#define MEM_MODE_INPUT_FORMAT_RGBA8888 (0x002 << 4)
38#define MEM_MODE_INPUT_FORMAT_ARGB8888 (0x003 << 4)
39#define MEM_MODE_INPUT_FORMAT_UYVY (0x004 << 4)
40#define MEM_MODE_INPUT_FORMAT_YUYV (0x005 << 4)
41#define MEM_MODE_INPUT_SWAP BIT(8)
42#define DISP_RDMA_MEM_SRC_PITCH 0x002c
43#define DISP_RDMA_MEM_GMC_SETTING_0 0x0030
44#define DISP_REG_RDMA_FIFO_CON 0x0040
45#define RDMA_FIFO_UNDERFLOW_EN BIT(31)
46#define RDMA_FIFO_PSEUDO_SIZE(bytes) (((bytes) / 16) << 16)
47#define RDMA_OUTPUT_VALID_FIFO_THRESHOLD(bytes) ((bytes) / 16)
48#define RDMA_FIFO_SIZE(rdma) ((rdma)->data->fifo_size)
49#define DISP_RDMA_MEM_START_ADDR 0x0f00
50
51#define RDMA_MEM_GMC 0x40402020
52
53struct mtk_disp_rdma_data {
54 unsigned int fifo_size;
55};
56
57/**
58 * struct mtk_disp_rdma - DISP_RDMA driver structure
59 * @ddp_comp - structure containing type enum and hardware resources
60 * @crtc - associated crtc to report irq events to
61 */
62struct mtk_disp_rdma {
63 struct mtk_ddp_comp ddp_comp;
64 struct drm_crtc *crtc;
65 const struct mtk_disp_rdma_data *data;
66};
67
68static inline struct mtk_disp_rdma *comp_to_rdma(struct mtk_ddp_comp *comp)
69{
70 return container_of(comp, struct mtk_disp_rdma, ddp_comp);
71}
72
73static irqreturn_t mtk_disp_rdma_irq_handler(int irq, void *dev_id)
74{
75 struct mtk_disp_rdma *priv = dev_id;
76 struct mtk_ddp_comp *rdma = &priv->ddp_comp;
77
78 /* Clear frame completion interrupt */
79 writel(0x0, rdma->regs + DISP_REG_RDMA_INT_STATUS);
80
81 if (!priv->crtc)
82 return IRQ_NONE;
83
84 mtk_crtc_ddp_irq(priv->crtc, rdma);
85
86 return IRQ_HANDLED;
87}
88
89static void rdma_update_bits(struct mtk_ddp_comp *comp, unsigned int reg,
90 unsigned int mask, unsigned int val)
91{
92 unsigned int tmp = readl(comp->regs + reg);
93
94 tmp = (tmp & ~mask) | (val & mask);
95 writel(tmp, comp->regs + reg);
96}
97
98static void mtk_rdma_enable_vblank(struct mtk_ddp_comp *comp,
99 struct drm_crtc *crtc)
100{
101 struct mtk_disp_rdma *rdma = comp_to_rdma(comp);
102
103 rdma->crtc = crtc;
104 rdma_update_bits(comp, DISP_REG_RDMA_INT_ENABLE, RDMA_FRAME_END_INT,
105 RDMA_FRAME_END_INT);
106}
107
108static void mtk_rdma_disable_vblank(struct mtk_ddp_comp *comp)
109{
110 struct mtk_disp_rdma *rdma = comp_to_rdma(comp);
111
112 rdma->crtc = NULL;
113 rdma_update_bits(comp, DISP_REG_RDMA_INT_ENABLE, RDMA_FRAME_END_INT, 0);
114}
115
116static void mtk_rdma_start(struct mtk_ddp_comp *comp)
117{
118 rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN,
119 RDMA_ENGINE_EN);
120}
121
122static void mtk_rdma_stop(struct mtk_ddp_comp *comp)
123{
124 rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN, 0);
125}
126
127static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,
128 unsigned int height, unsigned int vrefresh,
129 unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
130{
131 unsigned int threshold;
132 unsigned int reg;
133 struct mtk_disp_rdma *rdma = comp_to_rdma(comp);
134
135 mtk_ddp_write_mask(cmdq_pkt, width, comp,
136 DISP_REG_RDMA_SIZE_CON_0, 0xfff);
137 mtk_ddp_write_mask(cmdq_pkt, height, comp,
138 DISP_REG_RDMA_SIZE_CON_1, 0xfffff);
139
140 /*
141 * Enable FIFO underflow since DSI and DPI can't be blocked.
142 * Keep the FIFO pseudo size reset default of 8 KiB. Set the
143 * output threshold to 6 microseconds with 7/6 overhead to
144 * account for blanking, and with a pixel depth of 4 bytes:
145 */
146 threshold = width * height * vrefresh * 4 * 7 / 1000000;
147 reg = RDMA_FIFO_UNDERFLOW_EN |
148 RDMA_FIFO_PSEUDO_SIZE(RDMA_FIFO_SIZE(rdma)) |
149 RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold);
150 mtk_ddp_write(cmdq_pkt, reg, comp, DISP_REG_RDMA_FIFO_CON);
151}
152
153static unsigned int rdma_fmt_convert(struct mtk_disp_rdma *rdma,
154 unsigned int fmt)
155{
156 /* The return value in switch "MEM_MODE_INPUT_FORMAT_XXX"
157 * is defined in mediatek HW data sheet.
158 * The alphabet order in XXX is no relation to data
159 * arrangement in memory.
160 */
161 switch (fmt) {
162 default:
163 case DRM_FORMAT_RGB565:
164 return MEM_MODE_INPUT_FORMAT_RGB565;
165 case DRM_FORMAT_BGR565:
166 return MEM_MODE_INPUT_FORMAT_RGB565 | MEM_MODE_INPUT_SWAP;
167 case DRM_FORMAT_RGB888:
168 return MEM_MODE_INPUT_FORMAT_RGB888;
169 case DRM_FORMAT_BGR888:
170 return MEM_MODE_INPUT_FORMAT_RGB888 | MEM_MODE_INPUT_SWAP;
171 case DRM_FORMAT_RGBX8888:
172 case DRM_FORMAT_RGBA8888:
173 return MEM_MODE_INPUT_FORMAT_ARGB8888;
174 case DRM_FORMAT_BGRX8888:
175 case DRM_FORMAT_BGRA8888:
176 return MEM_MODE_INPUT_FORMAT_ARGB8888 | MEM_MODE_INPUT_SWAP;
177 case DRM_FORMAT_XRGB8888:
178 case DRM_FORMAT_ARGB8888:
179 return MEM_MODE_INPUT_FORMAT_RGBA8888;
180 case DRM_FORMAT_XBGR8888:
181 case DRM_FORMAT_ABGR8888:
182 return MEM_MODE_INPUT_FORMAT_RGBA8888 | MEM_MODE_INPUT_SWAP;
183 case DRM_FORMAT_UYVY:
184 return MEM_MODE_INPUT_FORMAT_UYVY;
185 case DRM_FORMAT_YUYV:
186 return MEM_MODE_INPUT_FORMAT_YUYV;
187 }
188}
189
190static unsigned int mtk_rdma_layer_nr(struct mtk_ddp_comp *comp)
191{
192 return 1;
193}
194
195static void mtk_rdma_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
196 struct mtk_plane_state *state,
197 struct cmdq_pkt *cmdq_pkt)
198{
199 struct mtk_disp_rdma *rdma = comp_to_rdma(comp);
200 struct mtk_plane_pending_state *pending = &state->pending;
201 unsigned int addr = pending->addr;
202 unsigned int pitch = pending->pitch & 0xffff;
203 unsigned int fmt = pending->format;
204 unsigned int con;
205
206 con = rdma_fmt_convert(rdma, fmt);
207 mtk_ddp_write_relaxed(cmdq_pkt, con, comp, DISP_RDMA_MEM_CON);
208
209 if (fmt == DRM_FORMAT_UYVY || fmt == DRM_FORMAT_YUYV) {
210 mtk_ddp_write_mask(cmdq_pkt, RDMA_MATRIX_ENABLE, comp,
211 DISP_REG_RDMA_SIZE_CON_0,
212 RDMA_MATRIX_ENABLE);
213 mtk_ddp_write_mask(cmdq_pkt, RDMA_MATRIX_INT_MTX_BT601_to_RGB,
214 comp, DISP_REG_RDMA_SIZE_CON_0,
215 RDMA_MATRIX_INT_MTX_SEL);
216 } else {
217 mtk_ddp_write_mask(cmdq_pkt, 0, comp,
218 DISP_REG_RDMA_SIZE_CON_0,
219 RDMA_MATRIX_ENABLE);
220 }
221 mtk_ddp_write_relaxed(cmdq_pkt, addr, comp, DISP_RDMA_MEM_START_ADDR);
222 mtk_ddp_write_relaxed(cmdq_pkt, pitch, comp, DISP_RDMA_MEM_SRC_PITCH);
223 mtk_ddp_write(cmdq_pkt, RDMA_MEM_GMC, comp,
224 DISP_RDMA_MEM_GMC_SETTING_0);
225 mtk_ddp_write_mask(cmdq_pkt, RDMA_MODE_MEMORY, comp,
226 DISP_REG_RDMA_GLOBAL_CON, RDMA_MODE_MEMORY);
227
228}
229
230static const struct mtk_ddp_comp_funcs mtk_disp_rdma_funcs = {
231 .config = mtk_rdma_config,
232 .start = mtk_rdma_start,
233 .stop = mtk_rdma_stop,
234 .enable_vblank = mtk_rdma_enable_vblank,
235 .disable_vblank = mtk_rdma_disable_vblank,
236 .layer_nr = mtk_rdma_layer_nr,
237 .layer_config = mtk_rdma_layer_config,
238};
239
240static int mtk_disp_rdma_bind(struct device *dev, struct device *master,
241 void *data)
242{
243 struct mtk_disp_rdma *priv = dev_get_drvdata(dev);
244 struct drm_device *drm_dev = data;
245 int ret;
246
247 ret = mtk_ddp_comp_register(drm_dev, &priv->ddp_comp);
248 if (ret < 0) {
249 dev_err(dev, "Failed to register component %pOF: %d\n",
250 dev->of_node, ret);
251 return ret;
252 }
253
254 return 0;
255
256}
257
258static void mtk_disp_rdma_unbind(struct device *dev, struct device *master,
259 void *data)
260{
261 struct mtk_disp_rdma *priv = dev_get_drvdata(dev);
262 struct drm_device *drm_dev = data;
263
264 mtk_ddp_comp_unregister(drm_dev, &priv->ddp_comp);
265}
266
267static const struct component_ops mtk_disp_rdma_component_ops = {
268 .bind = mtk_disp_rdma_bind,
269 .unbind = mtk_disp_rdma_unbind,
270};
271
272static int mtk_disp_rdma_probe(struct platform_device *pdev)
273{
274 struct device *dev = &pdev->dev;
275 struct mtk_disp_rdma *priv;
276 int comp_id;
277 int irq;
278 int ret;
279
280 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
281 if (!priv)
282 return -ENOMEM;
283
284 irq = platform_get_irq(pdev, 0);
285 if (irq < 0)
286 return irq;
287
288 comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DISP_RDMA);
289 if (comp_id < 0) {
290 dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
291 return comp_id;
292 }
293
294 ret = mtk_ddp_comp_init(dev, dev->of_node, &priv->ddp_comp, comp_id,
295 &mtk_disp_rdma_funcs);
296 if (ret) {
297 if (ret != -EPROBE_DEFER)
298 dev_err(dev, "Failed to initialize component: %d\n",
299 ret);
300
301 return ret;
302 }
303
304 /* Disable and clear pending interrupts */
305 writel(0x0, priv->ddp_comp.regs + DISP_REG_RDMA_INT_ENABLE);
306 writel(0x0, priv->ddp_comp.regs + DISP_REG_RDMA_INT_STATUS);
307
308 ret = devm_request_irq(dev, irq, mtk_disp_rdma_irq_handler,
309 IRQF_TRIGGER_NONE, dev_name(dev), priv);
310 if (ret < 0) {
311 dev_err(dev, "Failed to request irq %d: %d\n", irq, ret);
312 return ret;
313 }
314
315 priv->data = of_device_get_match_data(dev);
316
317 platform_set_drvdata(pdev, priv);
318
319 ret = component_add(dev, &mtk_disp_rdma_component_ops);
320 if (ret)
321 dev_err(dev, "Failed to add component: %d\n", ret);
322
323 return ret;
324}
325
326static int mtk_disp_rdma_remove(struct platform_device *pdev)
327{
328 component_del(&pdev->dev, &mtk_disp_rdma_component_ops);
329
330 return 0;
331}
332
333static const struct mtk_disp_rdma_data mt2701_rdma_driver_data = {
334 .fifo_size = SZ_4K,
335};
336
337static const struct mtk_disp_rdma_data mt8173_rdma_driver_data = {
338 .fifo_size = SZ_8K,
339};
340
341static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
342 { .compatible = "mediatek,mt2701-disp-rdma",
343 .data = &mt2701_rdma_driver_data},
344 { .compatible = "mediatek,mt8173-disp-rdma",
345 .data = &mt8173_rdma_driver_data},
346 {},
347};
348MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
349
350struct platform_driver mtk_disp_rdma_driver = {
351 .probe = mtk_disp_rdma_probe,
352 .remove = mtk_disp_rdma_remove,
353 .driver = {
354 .name = "mediatek-disp-rdma",
355 .owner = THIS_MODULE,
356 .of_match_table = mtk_disp_rdma_driver_dt_match,
357 },
358};